A method, device and electronic device for estimating energy consumption limit of digital circuit

Abstract

The present invention discloses a method, device and electronic device for estimating the energy consumption limit of a digital circuit, wherein the digital circuit includes at least one logic gate. The present invention calculates the energy consumption limit of the logic gate based on the crossover theory mentioned above and by analyzing the probability distribution of the input state and output state of the logic gate. Furthermore, the digital circuit is composed of logic gates, and therefore, the energy consumption limit of the digital circuit can be estimated by calculating the energy consumption limit of each logic gate. By implementing the present invention, the energy consumption limit of the digital circuit is estimated, and the estimation process is simple and easy, and is not affected by factors such as the process and materials of the digital circuit itself.

Description

Technical Field

[0001] The present invention relates to the technical field of digital circuits, and in particular to a method, a device and an electronic device for estimating the energy consumption limit of a digital circuit. Background Art

[0002] As the gate size of transistors gradually approaches the mesoscopic or even quantum scale, quantum effects such as quantum tunneling will cause the transistor to lose control of classical bits. The latest research shows that the energy consumption limit of the actual computing process has nothing to do with the process and materials of the logic gates and circuits. It is the lower limit of energy dissipation to complete the corresponding logic function under the constraints of random thermodynamic theory. As the random chip process is further shortened, the number of electrons contained is further reduced, and the power supply voltage is further reduced, its energy consumption gradually approaches the physical limit. Estimating the energy consumption limit of digital circuits is of great significance in guiding the design and manufacture of digital circuits. However, no estimation method for the energy consumption limit of digital circuits has been proposed in the prior art. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a method, device and electronic device for estimating the energy consumption limit of a digital circuit to solve the technical problem that no estimation method for the energy consumption limit of a digital circuit has been proposed in the prior art.

[0004] The technical solution proposed by the present invention is as follows:

[0005] In a first aspect, an embodiment of the present invention provides a method for estimating the energy consumption limit of a digital circuit, wherein the digital circuit includes at least one logic gate; the method for estimating the energy consumption limit of a digital circuit includes: obtaining a first input probability distribution and a first output probability distribution of a computing unit in each of the logic gates in the digital circuit to be estimated; determining a second input probability distribution and a second output probability distribution of the computing unit in each of the logic gates based on the first input probability distribution and a preset condition; determining the energy consumption limit of each of the logic gates based on the first input probability distribution, the first output probability distribution, the second input probability distribution and the second output probability distribution through the introduction cross theory; estimating the energy consumption limit of the digital circuit to be estimated based on the energy consumption limit of each of the logic gates to obtain an energy consumption limit estimation result of the digital circuit to be estimated.

[0006] In combination with the first aspect, in a possible implementation of the first aspect, obtaining the first input probability distribution of the computing unit in each of the logic gates in the digital circuit to be estimated includes: obtaining the first input probability corresponding to each input state of the computing unit in each of the logic gates in the digital circuit to be estimated; and determining the first input probability distribution of the computing unit in each of the logic gates based on each of the first input probabilities.

[0007] In combination with the first aspect, in another possible implementation of the first aspect, obtaining the first output probability distribution of the computing unit in each of the logic gates in the digital circuit to be estimated includes: based on each of the first input probabilities, obtaining the first output probability corresponding to each of the first input probabilities through the computing unit; and determining the first output probability distribution of the computing unit in each of the logic gates based on each of the first output probabilities.

[0008] In combination with the first aspect, in another possible implementation of the first aspect, based on the first input probability distribution and preset conditions, the second input probability distribution and the second output probability distribution of the computing unit in each of the logic gates are determined, including: adjusting the first input probability distribution of the computing unit in each of the logic gates until the adjusted first input probability distribution meets the preset conditions, thereby obtaining the second input probability distribution of the computing unit in each of the logic gates; and determining the second output probability distribution of the computing unit in each of the logic gates based on each of the second input probability distributions.

[0009] In combination with the first aspect, in another possible implementation of the first aspect, the preamble intersection theory includes the Landauer principle and the mismatch principle; based on the first input probability distribution, the first output probability distribution, the second input probability distribution and the second output probability distribution, the energy consumption limit of each of the logic gates is determined through the preamble intersection theory, including: based on the first input probability distribution and the first output probability distribution, the first energy consumption of each of the logic gates is determined through the Landauer principle; based on each of the second input probability distribution and each of the second output probability distribution, the second energy consumption of each of the logic gates is determined through the mismatch principle; based on the first energy consumption of each of the logic gates and the second energy consumption of each of the logic gates, the energy consumption limit of each of the logic gates is determined.

[0010] In a second aspect, an embodiment of the present invention provides a digital circuit energy consumption limit estimation device, wherein the digital circuit includes at least one logic gate; the digital circuit energy consumption limit estimation device includes: an acquisition module, used to acquire a first input probability distribution and a first output probability distribution of a computing unit in each of the logic gates in the digital circuit to be estimated; a first determination module, used to determine a second input probability distribution and a second output probability distribution of the computing unit in each of the logic gates based on the first input probability distribution and a preset condition; a second determination module, used to determine the energy consumption limit of each of the logic gates based on the first input probability distribution, the first output probability distribution, the second input probability distribution and the second output probability distribution through the introduction cross theory; an estimation module, used to estimate the energy consumption limit of the digital circuit to be estimated based on the energy consumption limit of each of the logic gates, and obtain an energy consumption limit estimation result of the digital circuit to be estimated.

[0011] In combination with the second aspect, in a possible implementation of the second aspect, the acquisition module includes: an acquisition submodule, used to obtain the first input probability corresponding to each input state of the computing unit in each of the logic gates in the digital circuit to be estimated; and a first determination submodule, used to determine the first input probability distribution of the computing unit in each of the logic gates based on each of the first input probabilities.

[0012] In combination with the second aspect, in another possible implementation of the second aspect, the acquisition module also includes: a processing submodule, used to obtain the first output probability corresponding to each first input probability through the calculation unit based on each first input probability; a second determination submodule, used to determine the first output probability distribution of the calculation unit in each of the logic gates based on each first output probability.

[0013] In a third aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is used to enable the computer to execute the digital circuit energy consumption limit estimation method as described in the first aspect of the embodiment of the present invention and any one of the first aspects.

[0014] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing a computer program, and the processor executing the digital circuit energy consumption limit estimation method as described in the first aspect of the embodiment of the present invention and any one of the first aspects by executing the computer program.

[0015] The technical solution provided by the present invention has the following effects:

[0016] The method for estimating the energy consumption limit of a digital circuit provided by the embodiment of the present invention calculates the energy consumption limit of a logic gate based on the crossover theory mentioned above and by analyzing the probability distribution of the input state and output state of the logic gate. Furthermore, a digital circuit is composed of logic gates, and therefore, the energy consumption limit of the digital circuit can be estimated by calculating the energy consumption limit of each logic gate. By implementing the present invention, the energy consumption limit of a digital circuit is estimated, and the estimation process is simple and easy, and is not affected by factors such as the process and materials of the digital circuit itself. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a flow chart of a method for estimating energy consumption limit of a digital circuit provided in an embodiment of the present invention;

[0019] Figure 2A is a schematic diagram of an irreversible process of AND gate logic provided according to an embodiment of the present invention;

[0020] Figure 2B is a schematic diagram of an irreversible process of XOR gate logic provided according to an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of a mismatch principle provided in an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of a three-input phase AND circuit provided according to an embodiment of the present invention;

[0023] Figure 5 is a structural block diagram of a digital circuit energy consumption limit estimation device provided according to an embodiment of the present invention;

[0024] Figure 6 is a schematic diagram of the structure of a computer-readable storage medium provided according to an embodiment of the present invention;

[0025] Figure 7 It is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] The embodiment of the present invention provides a method for estimating the energy consumption limit of a digital circuit. Figure 1 As shown, the method comprises the following steps:

[0029] Step 101: Obtain a first input probability distribution and a first output probability distribution of a computing unit in each logic gate in a digital circuit to be estimated.

[0030] Among them, the digital circuit is composed of at least one logic gate (such as an AND gate and an XOR gate).

[0031] The computing unit is used to complete the logical operations of the logic gates.

[0032] First, a first input probability distribution corresponding to the input state of the computing unit in each logic gate in the digital circuit to be estimated is obtained; further, a first output probability distribution corresponding to the output state of the computing unit in each logic gate can be obtained based on the first input probability distribution.

[0033] Step 102: Based on the first input probability distribution and a preset condition, determine a second input probability distribution and a second output probability distribution of the computing unit in each of the logic gates.

[0034] Among them, the second input probability distribution represents the optimal input probability distribution, that is, under the current probability distribution, the energy consumption of the logic gate is minimal; the second output probability distribution represents the optimal output probability distribution.

[0035] Specifically, the first input probability distribution is optimized based on a preset condition, and a second input probability distribution is obtained.

[0036] Further, a corresponding second output probability distribution is determined based on the second input probability distribution.

[0037] Step 103: Based on the first input probability distribution, the first output probability distribution, the second input probability distribution and the second output probability distribution, the energy consumption limit of each logic gate is determined through the introduction crossover theory.

[0038] Among them, the introductory crossover theory includes Landauer's principle and the mismatch principle.

[0039] Specifically, according to the Landauer principle, any logically irreversible computing process will lead to energy consumption. Among them, logical irreversibility means that the mapping between the input and output states of the input logic gate does not satisfy bijection, that is, the output state cannot determine the unique input state. Figure 2A and 2B As shown, the logic operation process completed by the AND gate and the XOR gate is a logically irreversible process.

[0040] According to the mismatch principle, incorrect priors will lead to additional computational energy consumption. Figure 3 As shown in the figure, for a given computing unit (logic gate), when it is "tuned" to a certain input probability distribution, its energy consumption is minimal, and this input probability distribution is regarded as the optimal input probability distribution. At the same time, the output probability distribution when the input is the optimal input probability distribution is regarded as the optimal output probability distribution. Since the actual input probability distribution is not necessarily equal to the optimal input probability distribution, the actual output probability distribution is not necessarily equal to the optimal output probability distribution. The mismatch between probability distributions will lead to energy consumption.

[0041] Therefore, the energy consumption limit of each logic gate includes the energy consumption caused by the irreversible process of logic and the energy consumption caused by the mismatch between the probability distribution.

[0042] Furthermore, since both energy consumptions are affected by the probability distribution of the input and output states of the logic gate, the energy consumption limit of each logic gate can be determined based on the obtained first input probability distribution, first output probability distribution, second input probability distribution and second output probability distribution.

[0043] Step 104: based on the energy consumption limit of each of the logic gates, the energy consumption limit of the digital circuit to be estimated is estimated to obtain an estimation result of the energy consumption limit of the digital circuit to be estimated.

[0044] Specifically, the energy consumption limit of each logic gate is summed up, and the energy consumption limit of the digital circuit to be estimated can be estimated, as shown in the following relation (1):

[0045]

[0046] Where: represents the estimated energy consumption limit of the digital circuit to be estimated; represents the energy consumption limit of the i-th logic gate in the digital circuit to be estimated; n represents the number of logic gates in the digital circuit to be estimated.

[0047] The method for estimating the energy consumption limit of a digital circuit provided by the embodiment of the present invention calculates the energy consumption limit of a logic gate based on the crossover theory mentioned above and by analyzing the probability distribution of the input state and output state of the logic gate. Furthermore, a digital circuit is composed of logic gates, and therefore, the energy consumption limit of the digital circuit can be estimated by calculating the energy consumption limit of each logic gate. By implementing the present invention, the energy consumption limit of a digital circuit is estimated, and the estimation process is simple and easy, and is not affected by factors such as the process and materials of the digital circuit itself.

[0048] As an optional implementation manner of an embodiment of the present invention, obtaining the first input probability distribution of the computing unit in each of the logic gates in the digital circuit to be estimated includes: obtaining the first input probability corresponding to each input state of the computing unit in each of the logic gates in the digital circuit to be estimated; and determining the first input probability distribution of the computing unit in each of the logic gates based on each of the first input probabilities.

[0049] The first input probability distribution reflects the probability distribution characteristics of different input states of the logic gate.

[0050] Specifically, a first input probability corresponding to each input state of each logic gate is obtained, and a probability distribution feature of different input states of each logic gate, ie, a first input probability distribution, is determined based on each first input probability.

[0051] As an optional implementation manner of an embodiment of the present invention, obtaining the first output probability distribution of the computing unit in each of the logic gates in the digital circuit to be estimated includes: based on each of the first input probabilities, obtaining the first output probability corresponding to each of the first input probabilities through the computing unit; and determining the first output probability distribution of the computing unit in each of the logic gates based on each of the first output probabilities.

[0052] Specifically, after each input state passes through the calculation unit, the corresponding output state will be output.

[0053] Therefore, based on the first input probability of each input state, the first output probability of the output state corresponding to each input state can be obtained.

[0054] Further, based on the first output probability of each output state, the probability distribution characteristics of different output states of each logic gate, ie, the first output probability distribution, can be determined.

[0055] As an optional implementation of an embodiment of the present invention, step 102 includes: adjusting the first input probability distribution of the computing unit in each of the logic gates until the adjusted first input probability distribution meets a preset condition, thereby obtaining the second input probability distribution of the computing unit in each of the logic gates; and determining the second output probability distribution of the computing unit in each of the logic gates based on each of the second input probability distributions.

[0056] Specifically, under ideal conditions, the optimal input distribution is a uniform distribution. The actual optimal distribution is affected by factors such as the physical structure, materials, process, and design of the device (logic gate). It is necessary to measure the energy consumption of the device under different input distributions to determine the optimal input distribution of the device (that is, the input distribution with the lowest energy consumption).

[0057] Specifically, according to the description in step 103, when the first input probability distribution is adjusted to the second input probability distribution, the energy consumption of the logic gate is minimal, that is, the second input probability distribution is used as the optimal probability distribution.

[0058] Further, according to the description in step 102, a corresponding second output probability distribution is determined based on the second input probability distribution.

[0059] As an optional implementation of the embodiment of the present invention, step 103 includes: based on the first input probability distribution and the first output probability distribution, determining the first energy consumption of each of the logic gates through the Landauer principle; based on each of the second input probability distribution and each of the second output probability distribution, determining the second energy consumption of each of the logic gates through the mismatch principle; based on the first energy consumption of each of the logic gates and the second energy consumption of each of the logic gates, determining the energy consumption limit of each of the logic gates.

[0060] Specifically, the first energy consumption represents the energy consumption caused by the logical irreversible process, as shown in the following equation (2):

[0061] W LC =S(P in )-S(P out ) (2)

[0062] Where: P in represents the probability distribution of the computing unit input, that is, the first input probability distribution; P out Represents the probability distribution of the computing unit output, that is, the first output probability distribution.

[0063] Furthermore, S(P) is the information entropy expression, as shown in the following equation (3):

[0064]

[0065] Where: P(x) represents the probability when the actual input / output is x.

[0066] Furthermore, according to P(x), we can get P in and P out .

[0067] The second energy consumption represents the energy consumption caused by the mismatch between probability distributions, as shown in the following equation (3):

[0068] W MC =D(P in Q in )-D(P out Q out ) (4)

[0069] Where: Q in represents the optimal input probability distribution of the computing unit, that is, the second input probability distribution; Q out represents the optimal output probability distribution of the computing unit, that is, the second output probability distribution.

[0070] Furthermore, D(P||Q) is the relative entropy expression, as shown in the following equation (5):

[0071]

[0072] Where: Q(x) represents the probability when the input / output is x when the distribution is optimal.

[0073] Furthermore, according to Q(x), we can get Q in and Q out .

[0074] From the above equations (4) and (5), it can be known that the second energy consumption depends only on the input-output probability distribution and the optimal probability distribution, and has nothing to do with the details of the calculation process.

[0075] Then, based on the first energy consumption and the second energy consumption, the energy consumption limit of the logic gate is determined, as shown in the following relation (6):

[0076]

[0077] in,

[0078] Finally, the energy consumption limit of each logic gate calculated by equation (6) is Substituting into the above relation (1), the energy consumption limit of the digital circuit to be estimated can be estimated.

[0079] In an example, an AND gate is taken as an example to illustrate the method for estimating the energy consumption limit of a digital circuit provided by an embodiment of the present invention.

[0080] Specifically, P represents the actual probability distribution, P(x) represents the actual probability of the state; Q represents the optimal probability distribution, Q(x) represents the optimal probability of the state, the superscripts in and out represent input and output respectively, and the subscripts "AND" and "2-AND" represent the corresponding logic gates and circuits.

[0081] First, according to the above relationship (2), the energy consumption of the AND gate caused by the logical irreversible process, that is, the first energy consumption It can be expressed as the following relation (7):

[0082]

[0083] in, is the information entropy, when the actual input probability distribution of the AND gate is When the uniform distribution is followed, the first energy consumption of the AND gate is expressed as follows:

[0084]

[0085] Where K is the Boltzmann constant and T is the Kelvin temperature of the environment.

[0086] Secondly, according to the above relationship (4), the energy consumption caused by the mismatch between the input and output probability distribution of the AND gate is the second energy consumption It can be expressed as the following relation (9):

[0087]

[0088] in, is the relative entropy.

[0089] If the optimal input probability distribution of the AND gate is It obeys uniform distribution. From the result of “AND” operation, we can know that the optimal output probability distribution of AND gate is for:

[0090] Furthermore, assume that all AND gates in the digital circuit and All satisfy the above distributions.

[0091] Furthermore, the optimal output probability distribution of a logic gate is determined by the optimal input probability distribution, and the optimal output probability distribution is not necessarily the same as the optimal input probability distribution. and After that, the above relationship (9) can be expressed as the following relationship (10):

[0092]

[0093] Finally, based on the above relations (9) and (10), we can get the energy consumption limit of the AND gate: The following relationship (11):

[0094]

[0095] From the above relationship (11), it can be seen that the energy consumption limit of the AND gate is proportional to the probability that the output is 0.

[0096] Further, consider Figure 4 According to the above relationship (11), the energy consumption limit of the three-input phase AND circuit can be obtained as follows: The following relationship (12):

[0097]

[0098] The embodiment of the present invention also provides a digital circuit energy consumption limit estimation device, such as Figure 5 As shown, the device comprises:

[0099] The acquisition module 501 is used to obtain the first input probability distribution and the first output probability distribution of the computing unit in each logic gate in the digital circuit to be estimated; for details, please refer to the relevant description of step 101 in the above method embodiment.

[0100] The first determination module 502 is used to determine the second input probability distribution and the second output probability distribution of the computing unit in each of the logic gates based on the first input probability distribution and a preset condition; for details, see the relevant description of step 102 in the above method embodiment.

[0101] The second determination module 503 is used to determine the energy consumption limit of each of the logic gates based on the first input probability distribution, the first output probability distribution, the second input probability distribution and the second output probability distribution through the introduction cross theory; for details, please refer to the relevant description of step 103 in the above method embodiment.

[0102] The estimation module 504 is used to estimate the energy consumption limit of the digital circuit to be estimated based on the energy consumption limit of each logic gate, and obtain the energy consumption limit estimation result of the digital circuit to be estimated; for details, please refer to the relevant description of step 104 in the above method embodiment.

[0103] The digital circuit energy consumption limit estimation device provided by the embodiment of the present invention calculates the energy consumption limit of the logic gate according to the crossover theory mentioned in the introduction and by analyzing the probability distribution of the input state and output state of the logic gate. Furthermore, the digital circuit is composed of logic gates, so the energy consumption limit of each logic gate obtained by calculation can be used to estimate the energy consumption limit of the digital circuit. By implementing the present invention, the energy consumption limit of the digital circuit is estimated, and the estimation process is simple and easy, and is not affected by factors such as the process and materials of the digital circuit itself.

[0104] As an optional implementation manner of an embodiment of the present invention, the acquisition module includes: an acquisition submodule, used to obtain the first input probability corresponding to each input state of the computing unit in each of the logic gates in the digital circuit to be estimated; and a first determination submodule, used to determine the first input probability distribution of the computing unit in each of the logic gates based on each of the first input probabilities.

[0105] As an optional implementation of an embodiment of the present invention, the acquisition module also includes: a processing submodule, used to obtain the first output probability corresponding to each first input probability through the calculation unit based on each first input probability; a second determination submodule, used to determine the first output probability distribution of the calculation unit in each of the logic gates based on each first output probability.

[0106] As an optional implementation manner of an embodiment of the present invention, the first determination module includes: an adjustment submodule, used to adjust the first input probability distribution of the calculation unit in each of the logic gates until the adjusted first input probability distribution meets a preset condition, thereby obtaining the second input probability distribution of the calculation unit in each of the logic gates; and a third determination submodule, used to determine the second output probability distribution of the calculation unit in each of the logic gates based on each of the second input probability distributions.

[0107] As an optional implementation manner of an embodiment of the present invention, the foreword crossover theory includes the Landauer principle and the mismatch principle; the second determination module includes: a fourth determination submodule, used to determine the first energy consumption of each of the logic gates based on the first input probability distribution and the first output probability distribution, through the Landauer principle; a fifth determination submodule, used to determine the second energy consumption of each of the logic gates based on each of the second input probability distribution and each of the second output probability distribution, through the mismatch principle; a sixth determination submodule, used to determine the energy consumption limit of each of the logic gates based on the first energy consumption of each of the logic gates and the second energy consumption of each of the logic gates.

[0108] For detailed description of the function of the digital circuit energy consumption limit estimation device provided in the embodiment of the present invention, please refer to the description of the digital circuit energy consumption limit estimation method in the above embodiment.

[0109] The embodiment of the present invention also provides a storage medium, such as Figure 6 As shown, a computer program 601 is stored thereon, and when the program is executed by the processor, the steps of the method for estimating the energy consumption limit of a digital circuit in the above embodiment are implemented. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk (HDD) or a solid-state drive (SSD), etc.; the storage medium may also include a combination of the above-mentioned types of memory.

[0110] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk (HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0111] The embodiment of the present invention further provides an electronic device, such as Figure 7 As shown, the electronic device may include a processor 71 and a memory 72, wherein the processor 71 and the memory 72 may be connected via a bus or other means. Figure 7 The example of connecting through bus is taken in the following.

[0112] The processor 71 may be a central processing unit (CPU). The processor 71 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips.

[0113] The memory 72 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as the corresponding program instructions / modules in the embodiment of the present invention. The processor 71 executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory 72, that is, the digital circuit energy consumption limit estimation method in the above method embodiment is implemented.

[0114] The memory 72 may include a program storage area and a data storage area, wherein the program storage area may store an application required for operating the device and at least one function; the data storage area may store data created by the processor 71, etc. In addition, the memory 72 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 72 may optionally include a memory remotely arranged relative to the processor 71, and these remote memories may be connected to the processor 71 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0115] The one or more modules are stored in the memory 72 and when executed by the processor 71, perform the following steps: Figure 1-4 A method for estimating energy consumption limit of a digital circuit in the illustrated embodiment.

[0116] For details of the above electronic equipment, please refer to Figures 1 to 4 The corresponding related descriptions and effects in the illustrated embodiments can be understood and will not be repeated here.

[0117] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for estimating energy consumption limit of a digital circuit, characterized in that: The digital circuit comprises at least one logic gate; the method comprises: Obtaining a first input probability distribution and a first output probability distribution of a computing unit in each of the logic gates in the digital circuit to be estimated; Based on the first input probability distribution and a preset condition, determining a second input probability distribution and a second output probability distribution of the computing unit in each of the logic gates; Based on the first input probability distribution, the first output probability distribution, the second input probability distribution and the second output probability distribution, the energy consumption limit of each logic gate is determined through the preamble crossover theory, wherein the preamble crossover theory includes the Landauer principle and the mismatch principle; Based on the energy consumption limit of each of the logic gates, the energy consumption limit of the digital circuit to be estimated is estimated to obtain an energy consumption limit estimation result of the digital circuit to be estimated; Wherein, based on the first input probability distribution, the first output probability distribution, the second input probability distribution and the second output probability distribution, the energy consumption limit of each logic gate is determined through the introduction crossover theory, including: Based on the first input probability distribution and the first output probability distribution, determining a first energy consumption of each of the logic gates through the Landauer principle; Based on each of the second input probability distributions and each of the second output probability distributions, and through a mismatch principle, determining a second energy consumption of each of the logic gates; determining the energy consumption limit of each of the logic gates based on the first energy consumption of each of the logic gates and the second energy consumption of each of the logic gates; The first energy consumption represents the energy consumption caused by the logical irreversible process, which is expressed as the following relational expression: W LC =S(P in )-S(P out ) Where: W LC Represents the first energy consumption; P in represents the first input probability distribution; P out represents the first output probability distribution; S(P) is the information entropy expression, which is expressed as the following relationship: Where: P(x) represents the probability when the actual input / output is x; The second energy consumption represents the energy consumption caused by the mismatch between probability distributions, which is expressed as the following relation: W MC =D(P in Q in )-D(P out Q out ) Where: W MC Indicates the second energy consumption; Q in represents the second input probability distribution; Q out represents the second output probability distribution; D(PQ) is the relative entropy expression, which is expressed as the following relationship: Where: Q(x) represents the probability when the input / output is x when the optimal distribution is obtained; The energy consumption limit is expressed as the following relationship: in, Indicates the energy consumption limit; 2. The method according to claim 1, characterized in that Obtaining a first input probability distribution of a computing unit in each logic gate in the digital circuit to be estimated comprises: Obtaining a first input probability corresponding to each input state of the computing unit in each of the logic gates in the digital circuit to be estimated; The first input probability distribution of the computing unit in each of the logic gates is determined based on each of the first input probabilities.

3. The method according to claim 2, characterized in that Obtaining a first output probability distribution of a computing unit in each of the logic gates in the digital circuit to be estimated, comprising: Based on each of the first input probabilities, through the calculation unit, a first output probability corresponding to each of the first input probabilities is obtained; The first output probability distribution of the computing unit in each of the logic gates is determined based on each of the first output probabilities.

4. The method according to claim 1, characterized in that: Determining a second input probability distribution and a second output probability distribution of the computing unit in each of the logic gates based on the first input probability distribution and a preset condition includes: Adjusting the first input probability distribution of the computing unit in each of the logic gates until the adjusted first input probability distribution meets a preset condition, thereby obtaining the second input probability distribution of the computing unit in each of the logic gates; Based on each of the second input probability distributions, the second output probability distribution of the computing unit in each of the logic gates is determined.

5. A digital circuit energy consumption limit estimation device, characterized in that: The digital circuit comprises at least one logic gate; the device comprises: An acquisition module, used for acquiring a first input probability distribution and a first output probability distribution of a computing unit in each of the logic gates in the digital circuit to be estimated; A first determination module, configured to determine a second input probability distribution and a second output probability distribution of the computing unit in each of the logic gates based on the first input probability distribution and a preset condition; A second determination module is used to determine the energy consumption limit of each logic gate based on the first input probability distribution, the first output probability distribution, the second input probability distribution and the second output probability distribution through a preamble crossover theory, wherein the preamble crossover theory includes a Landauer principle and a mismatch principle; An estimation module, configured to estimate the energy consumption limit of the digital circuit to be estimated based on the energy consumption limit of each of the logic gates, and obtain an estimation result of the energy consumption limit of the digital circuit to be estimated; Wherein, the second determining module includes: a fourth determination submodule, configured to determine a first energy consumption of each of the logic gates based on the first input probability distribution and the first output probability distribution and by using the Landauer principle; a fifth determination submodule, configured to determine the second energy consumption of each of the logic gates based on each of the second input probability distributions and each of the second output probability distributions and through a mismatch principle; a sixth determining submodule, configured to determine the energy consumption limit of each of the logic gates based on the first energy consumption of each of the logic gates and the second energy consumption of each of the logic gates; The first energy consumption represents the energy consumption caused by the logical irreversible process, which is expressed as the following relational expression: W LC =S(P in )-S(P out ) Where: W LC Represents the first energy consumption; P in represents the first input probability distribution; P out represents the first output probability distribution; S(P) is the information entropy expression, which is expressed as the following relationship: Where: P(x) represents the probability when the actual input / output is x; The second energy consumption represents the energy consumption caused by the mismatch between probability distributions, which is expressed as the following relation: W MC =D(P in Q in )-D(P out Q out ) Where: W MC Indicates the second energy consumption; Q in represents the second input probability distribution; Q out represents the second output probability distribution; D(PQ) is the relative entropy expression, which is expressed as the following relationship: Where: Q(x) represents the probability when the input / output is x when the optimal distribution is obtained; The energy consumption limit is expressed as the following relationship: in, Indicates the energy consumption limit; 6. The device according to claim 5, characterized in that The acquisition module comprises: An acquisition submodule, used for acquiring a first input probability corresponding to each input state of the computing unit in each of the logic gates in the digital circuit to be estimated; The first determining submodule is used to determine the first input probability distribution of the computing unit in each of the logic gates based on each of the first input probabilities.

7. The device according to claim 6, characterized in that The acquisition module further includes: a processing submodule, configured to obtain, based on each of the first input probabilities, a first output probability corresponding to each of the first input probabilities through the calculation unit; The second determining submodule is used to determine the first output probability distribution of the computing unit in each of the logic gates based on each of the first output probabilities.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is used to enable the computer to execute the digital circuit energy consumption limit estimation method according to any one of claims 1 to 4.

9. An electronic device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores a computer program, and the processor executes the digital circuit energy consumption limit estimation method according to any one of claims 1 to 4 by executing the computer program.

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