Encapsulation Substrate and Method for Manufacturing the Same

Abstract

An encapsulation substrate and a manufacturing method thereof, including embedding a circuit layer and alignment parts in an insulating layer, and then forming blind vias at positions corresponding to the alignment parts in the insulating layer to form conductors in the blind vias. Therefore, through the design of the alignment parts, the blind vias can be formed at predetermined positions.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, and more particularly to a packaging substrate with embedded traces and a manufacturing method thereof. Background Art

[0002] With the vigorous development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in form, and are developed towards high performance, high functionality and high speed in terms of functions. Therefore, in order to meet the requirements of high integration and miniaturization of semiconductor devices, packaging substrates with high-density and fine-pitch lines are often used in the packaging process.

[0003] As Figure 1 shown, a conventional packaging substrate 1 includes a core layer 10 having a plurality of conductive posts 100, a plurality of dielectric layers 11 respectively disposed on opposite sides of the core layer 10, and a circuit layer 12 disposed on each of the dielectric layers 11, so as to electrically connect the circuit layers 12 located on opposite sides of the core layer 10 through the plurality of conductive posts 100. Among them, the circuit layer 12 is electrically connected to the conductive post 100 through a conductor 120.

[0004] However, in the conventional packaging substrate 1, the conductor 120 is fabricated by first forming blind holes in the dielectric layer 11 by means of laser, drilling or etching, and then filling the blind holes with a conductive material. Therefore, during the process of forming the blind holes, misalignment often occurs due to working errors, resulting in the blind holes not being aligned with the conductive posts 100, so that the conductor 120 cannot effectively connect to the conductive posts 100, causing a problem of poor electrical connection of the packaging substrate 1.

[0005] Therefore, how to overcome the above-mentioned problems of the prior art has actually become an urgent issue to be solved currently. Summary of the Invention

[0006] In view of the above-mentioned deficiencies of the prior art, the present invention provides a packaging substrate and a manufacturing method thereof, which can at least partially solve the above-mentioned problems of the prior art.

[0007] The packaging substrate of the present invention includes: an insulating layer having opposite sides, and blind holes are formed in at least one side of the insulating layer; a circuit layer embedded in the insulating layer and exposed on the surface of at least one side of the opposite sides of the insulating layer; an alignment portion embedded in the insulating layer and exposed on the surface of at least one side of the opposite sides of the insulating layer to correspond to the blind holes in the insulating layer; and a conductor formed in the blind holes.

[0008] The present invention also provides a method for manufacturing a packaging substrate, comprising: providing an insulating layer having opposite sides; pressing a circuit layer and an alignment portion into at least one of the opposite sides of the insulating layer, such that the circuit layer and the alignment portion are embedded in the insulating layer; forming blind vias at least at one of the opposite sides of the insulating layer corresponding to the alignment portion; and forming a conductor in the blind vias.

[0009] In the foregoing packaging substrate and its manufacturing method, the alignment portion is a ring body.

[0010] In the foregoing packaging substrate and its manufacturing method, the insulating layer is formed on opposite surfaces of a core layer, such that conductors are formed on both opposite surfaces of the core layer, and conductive posts are provided in the core layer, so that the conductors on both opposite surfaces of the core layer are electrically connected to the conductive posts.

[0011] In the foregoing packaging substrate and its manufacturing method, alignment portions are respectively formed on opposite sides of the insulating layer, such that blind vias are formed at positions corresponding to the alignment portions, so that the blind vias on opposite sides of the insulating layer communicate with each other. For example, conductive posts connected to each other are formed in the blind vias on opposite sides of the insulating layer to serve as the conductors.

[0012] In the foregoing packaging substrate and its manufacturing method, it further includes providing a core layer having conductive posts and build-up structures bonded to opposite sides of the core layer, such that the insulating layer is formed on at least one of the build-up structures, conductors are disposed on the build-up structures, and the build-up structures have wiring layers electrically connecting the conductive posts and the conductors.

[0013] As can be seen from the above, in the packaging substrate and its manufacturing method of the present invention, mainly through the design of the alignment portion, during the process of forming the blind vias, only by aligning the alignment portion for hole forming operation, the problem of deviation due to working errors can be avoided. Therefore, compared with the prior art, the blind vias of the present invention can effectively align with the conductive posts in the core layer, enabling the conductors to effectively connect to the conductive posts, thus avoiding the problem of poor electrical connection of the packaging substrate. Description of the Drawings

[0014] Figure 1 It is a schematic cross-sectional view of a conventional packaging substrate.

[0015] Figures 2A to 2F It is a schematic cross-sectional view of the first embodiment of the method for manufacturing the packaging substrate of the present invention.

[0016] Figures 3A to 3D It is a schematic cross-sectional view of the second embodiment of the method for manufacturing the packaging substrate of the present invention.

[0017] Figures 4A to 4F It is a schematic cross-sectional view of the third embodiment of the method for manufacturing the packaging substrate of the present invention.

[0018] Among them, the description of the reference numerals is as follows:

[0019] 1, 2, 3, 4: Encapsulation substrate

[0020] 10, 23: Core layer

[0021] 100, 230: Conductive pillar

[0022] 11: Dielectric layer

[0023] 12, 21: Circuit layer

[0024] 120, 25, 35, 45: Conductor

[0025] 20: Carrier

[0026] 200: Metal layer

[0027] 21a, 22a, 23a, 23b, 24a, 34a: Surface

[0028] 22: Alignment part

[0029] 231: Insulating filler

[0030] 232: Inner layer circuit

[0031] 24, 34: Insulating layer

[0032] 240, 440: Blind hole

[0033] 25a: Metal material

[0034] 340: Through hole

[0035] 341: First blind hole

[0036] 342: Second blind hole

[0037] 35a: First conductive pillar

[0038] 35b: Second conductive pillar

[0039] 4a: Substrate body

[0040] 40: Build-up structure

[0041] 400: Dielectric

[0042] 401: Wiring layer

[0043] 41: Hard layer

[0044] 45a: Seed layer

[0045] S: Interface. Detailed implementation manners

[0046] The following uses specific embodiments to illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0047] It should be noted that the structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear narration and are not used to limit the scope for the implementation of the present invention. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope within which the present invention can be implemented.

[0048] Figures 2A to 2F It is a cross-sectional schematic diagram of the first embodiment of the manufacturing method of the encapsulation substrate 2 of the present invention. In this embodiment, the encapsulation substrate 2 is in a form with a core layer.

[0049] As Figure 2A shown, a circuit layer 21 and a positioning portion 22 are formed on a carrier 20.

[0050] In this embodiment, the carrier 20 has a metal layer 200 to form a carrier structure such as a copper foil substrate. For example, the circuit layer 21 and the positioning portion 22 can be formed by electroplating copper on the metal layer 200, and the positioning portion 22 is a metal ring.

[0051] As Figure 2B shown, on the opposite two surfaces 23a, 23b of a core layer 23 made of an insulating material, an insulating layer 24 with opposite sides is respectively formed, so that one side of the insulating layer 24 is combined with the core layer 23. Then, the carrier 20 with the circuit layer 21 and the positioning portion 22 thereon is combined with the other side of the insulating layer 24.

[0052] In this embodiment, at least one conductive post 230 is formed in the core layer 23, and an inner layer circuit 232 electrically connected to the conductive post 230 can be formed on the core layer 23 as required. For example, the conductive post 230 can be a hollow copper post filled with an insulating filler 231 inside. It should be understood that the conductive post 230 can also be a solid copper post without filling the insulating filler 231.

[0053] Furthermore, the material for forming the insulating layer 24 is a dielectric material such as prepreg (PP for short) or other suitable materials.

[0054] In addition, both of the two carrier members 20 press-fit the circuit layer 21 and the alignment portion 22 into the other side of the insulating layer 24, so that the circuit layer 21 and the alignment portion 22 are embedded in the insulating layer 24.

[0055] As Figure 2C shown, the carrier member 20 is removed by a peeling or etching method, while the metal layer 200 is retained.

[0056] As Figure 2D shown, a blind hole 240 is formed at the position of the insulating layer 24 corresponding to the alignment portion 22, so that the conductive post 230 is exposed from the blind hole 240.

[0057] In this embodiment, the blind hole 240 is formed by a laser method. For example, the laser is aligned with the center of the ring of the alignment portion 22, and the insulating layer 24 within the ring is burned until the end face of the conductive post 230 is exposed.

[0058] As Figure 2E shown, a metal material 25a is formed on the insulating layer 24, and the metal material 25a is filled into the blind hole 240 to contact the conductive post 230.

[0059] In this embodiment, the metal material 25a can be formed by electroplating copper material through the metal layer 200.

[0060] As Figure 2F shown, the metal material 25a on the insulating layer 24 and the metal layer 200 are removed, and only the metal material 25a in the blind hole 240 is retained to serve as the conductor 25.

[0061] In this embodiment, the circuit layer 21 and the alignment portion 22 are exposed on the surface 24a of the insulating layer 24. For example, the surface 21a of the circuit layer 21 is flush with (or slightly lower than) the surface 24a of the insulating layer 24 as well as the surface 22a of the alignment portion 22.

[0062] Furthermore, the conductor 25 is conical, and it is connected to the conductive post 230 with its narrower end face, and the conductor 25 is exposed on the surface 24a of the insulating layer 24. For example, the wider end face of the conductor 25 is flush with (or slightly lower than) the surface 24a of the insulating layer 24.

[0063] Therefore, by pressing the alignment portion 22 into the insulating layer 24, during the process of forming the blind hole 240 in the encapsulation substrate 2 of the present invention, it is only necessary to align the laser with the alignment portion 22, and the blind hole 240 can be accurately formed at the predetermined position. Thus, the problem of deviation caused by working errors can be avoided. Therefore, compared with the prior art, the blind hole 240 of the present invention can effectively align with the conductive post 230, enabling each conductive body 25 to effectively connect to the conductive post 230, and thus the problem of poor electrical connection of the encapsulation substrate 2 can be avoided.

[0064] Figures 3A to 3D It is a cross-sectional schematic view of the second embodiment of the manufacturing method of the encapsulation substrate 3 of the present invention. The difference between this embodiment and the first embodiment is that the encapsulation substrate 3 is in a coreless state, so the same parts will not be described in detail below.

[0065] As Figure 3A shown, an insulating layer 34 is provided, which has opposite sides. Then, the two carriers 20 are bonded to the opposite sides of the insulating layer 34 with the circuit layers 21 and the alignment portions 22 thereon.

[0066] In this embodiment, the material for forming the insulating layer 34 is a dielectric material such as prepreg (PP) or other suitable materials.

[0067] Furthermore, the carriers 20 press the circuit layer 21 and the alignment portion 22 into the opposite sides of the insulating layer 34 in a lamination manner, so that the circuit layer 21 and the alignment portion 22 are embedded in the insulating layer 34.

[0068] As Figure 3B shown, after removing the carriers 20 and retaining the metal layer 200, a first blind hole 341 and a second blind hole 342 are formed in the insulating layer 34 corresponding to the alignment portion 22, so that the first blind hole 341 communicates with the second blind hole 342 to form a through hole 340 penetrating the insulating layer 34.

[0069] In this embodiment, the first blind hole 341 and the second blind hole 342 are formed by a laser method. For example, the laser is aligned with the ring of the alignment portion 22 to burn the insulating layer 34 within the ring until the first blind hole 341 communicates with the second blind hole 342.

[0070] As Figure 3C shown, a metal material 25a is formed on the insulating layer 34, and the metal material 25a is filled into the first blind hole 341 and the second blind hole 342 to serve as a first conductive post 35a and a second conductive post 35b.

[0071] In this embodiment, the metal material 25a can be formed by electroplating copper on the metal layer 200, and the first conductive post 35a is connected to the second conductive post 35b.

[0072] As Figure 3D shown, the metal material 25a and the metal layer 200 on the insulating layer 34 are removed, and only the metal material 25a in the through hole 340 (i.e., the first conductive pillar 35a and the second conductive pillar 35b) is retained to serve as the columnar conductor 35.

[0073] In this embodiment, both the first conductive pillar 35a and the second conductive pillar 35b are conical, and the two are butt-jointed with their narrower end faces, as Figure 3D shown by the interface S.

[0074] Furthermore, the first conductive pillar 35a and the second conductive pillar 35b are exposed on the surface 34a of the insulating layer 34. For example, the wider end face of the first conductive pillar 35a is flush with (or slightly lower than) the surface 34a of the insulating layer 34.

[0075] In addition, the circuit layer 21 and the alignment portion 22 are exposed on the surface 34a of the insulating layer 34. For example, the surface 21a of the circuit layer 21 is flush with (or slightly lower than) the surface 34a of the insulating layer 34.

[0076] In other embodiments, a circuit build-up structure (not shown) can be formed on the insulating layer 34 to electrically connect the conductor 35 and the circuit layer 21.

[0077] Therefore, by pressing the alignment portion 22 into the insulating layer 34, the packaging substrate 3 of the present invention only needs to align the laser with the alignment portion 22 during the formation of the first blind hole 341 and the second blind hole 342, so that the first blind hole 341 and the second blind hole 342 can be accurately formed at the predetermined positions, thus avoiding the misalignment problem caused by working errors. Therefore, when the packaging substrate 3 of the present invention is applied in the coreless form, the first blind hole 341 and the second blind hole 342 can also be effectively aligned with each other, so that the first conductive pillar 35a and the second conductive pillar 35b can still be effectively butt-jointed, thus avoiding the problem of poor electrical connection of the packaging substrate 3.

[0078] Figures 4A to 4F It is a cross-sectional schematic view of the third embodiment of the manufacturing method of the packaging substrate 4 of the present invention. In this embodiment, the packaging substrate 4 is in a form with a core layer and a build-up structure.

[0079] As Figure 4A shown, a substrate body 4a is provided, which has the core layer 23 and the build-up structures 40 disposed on opposite sides of the core layer 23.

[0080] In this embodiment, a plurality of the conductive posts 230 are formed in the core layer 23, and an inner layer circuit 232 electrically connected to the conductive posts 230 can be formed on the core layer 23 as required. For example, the conductive post 230 can be a hollow copper post, and an insulating filler 231 is filled therein. It should be understood that the conductive post 230 can also be a solid copper post without filling the insulating filler 231.

[0081] Furthermore, the build-up structure 40 has a dielectric body 400 composed of a plurality of dielectric layers and a wiring layer 401 formed on each of the dielectric layers.

[0082] As Figure 4B shown, the carrier 20 is provided, and the circuit layer 21 and the alignment portion 22 are formed thereon.

[0083] In this embodiment, a metal layer 200 is provided on the carrier 20 to form a carrier structure such as a copper foil substrate.

[0084] As Figure 4C shown, the carrier 20 is bonded to one of the build-up structures 40 of the core layer 23 through the insulating layer 24, so that the circuit layer 21 and the alignment portion 22 on the carrier 20 are embedded in the insulating layer 24. Then, the carrier 20 is removed by peeling or etching, and the metal layer 200 is retained.

[0085] In this embodiment, the carrier 20 is bonded to the core layer 23 by a lamination method. For example, it is bonded to another build-up structure 40 of the core layer 23 through a hard layer 41 such as a metal material and another insulating layer 24. It should be understood that another carrier 20 having a circuit layer 21 and the alignment portion 22 can also be bonded to another build-up structure 40 of the core layer 23.

[0086] As Figure 4D shown, blind vias 240 are formed at positions of the insulating layers 24 corresponding to the alignment portion 22, so that a partial surface of the wiring layer 401 of the build-up structure 40 is exposed in the blind vias 240. Then, the carrier 20 is removed.

[0087] In this embodiment, the blind vias 240 are formed by a laser method. For example, the laser is aligned with the loop of the alignment portion 22 to burn the insulating layer 24 within the loop until a partial surface of the wiring layer 401 is exposed.

[0088] Furthermore, blind vias 440 can also be formed on the hard layer 41 and another build-up structure 40 of the core layer 23 by a laser method, so that a partial surface of the wiring layer 401 of the build-up structure 40 is exposed in the blind vias 440.

[0089] As Figure 4EAs shown, a patterning process is carried out to form a seed layer 45a on the metal layer 200 on the insulating layer 24, on the hard layer 41, and in the blind holes 240. Then, a metal material 25a is electroplated through the seed layer 45a, and the metal material 25a fills the blind holes 240. Next, the metal material 25a and the seed layer 45a on the metal layer 200 and the hard layer 41 are removed, and only the metal material 25a and the seed layer 45a at the blind holes 240 are retained. After that, the exposed metal layer 200 and the hard layer 41 are etched away to form a patterned circuit for use as the conductor 45.

[0090] In this embodiment, more circuit layers 21 can be formed on the build-up structure 40 by lamination, as Figure 4F shown.

[0091] Therefore, in the package substrate 4 of the present invention, by pressing the alignment portion 22 into the insulating layer 24, during the process of forming the blind holes 240, only by aligning the laser with the alignment portion 22, the blind holes 240 can be accurately formed at the predetermined positions. Thus, the problem of deviation caused by working errors can be avoided. Therefore, the blind holes 240 of the present invention can be effectively formed at the predetermined positions, enabling each of the conductors 25 to effectively connect to the wiring layer 401, and thus the problem of poor electrical connection of the package substrate 4 can be avoided.

[0092] The present invention provides a package substrate 2, 3, 4, comprising: an insulating layer 24, 34 having opposite sides, a circuit layer 21 embedded in the insulating layer 24, 34, at least one alignment portion 22 embedded in the insulating layer 24, 34, and at least one conductor 25, 35, 45 embedded in the insulating layer 24, 34 corresponding to the alignment portion 22.

[0093] The circuit layer 21 is exposed on at least one surface 24a, 34a of at least one of the opposite sides of the insulating layer 24, 34.

[0094] The alignment portion 22 is exposed on at least one surface 24a, 34a of at least one of the opposite sides of the insulating layer 24, 34, so as to form blind holes 240 (the first blind hole 341 and the second blind hole 342) at the positions of the insulating layer 24, 34 corresponding to the alignment portion 22.

[0095] The conductors 25, 35, 45 are formed in the blind holes 240 (the first blind hole 341 and the second blind hole 342).

[0096] In one embodiment, the encapsulation substrate 2 further includes a core layer 23, such that the insulating layer 24 is formed on opposite surfaces 23a, 23b of the core layer 23, conductors 25 are disposed on opposite surfaces 23a, 23b of the core layer 23, and conductive posts 230 are provided in the core layer 23, such that the conductors 25 on opposite surfaces 23a, 23b of the core layer 23 are electrically connected to the conductive posts 230.

[0097] In one embodiment, alignment portions 22 are respectively formed on opposite sides of the insulating layer 34, such that a first blind hole 341 and a second blind hole 342 are formed at positions corresponding to the alignment portions 22, and the first blind hole 341 and the second blind hole 342 on opposite sides of the insulating layer 34 communicate with each other. For example, a first conductive post 35a and a second conductive post 35b that are connected to each other are formed in the first blind hole 341 and the second blind hole 342 on opposite sides of the insulating layer 34 to serve as the conductor 35.

[0098] In one embodiment, the encapsulation substrate 4 further includes a core layer 23 and build-up structures 40 bonded to opposite sides of the core layer 23, such that the insulating layer 24 is formed on at least one of the build-up structures 40, conductors 45 are disposed on the build-up structures 40, conductive posts 230 are provided in the core layer 23, and the build-up structures 40 have wiring layers 401 that electrically connect the conductive posts 230 and the conductors 45.

[0099] In summary, for the encapsulation substrate and its manufacturing method of the present invention, through the design of the alignment portion, during the process of forming the blind hole, only by aligning the alignment portion for hole forming operation, the problem of deviation due to working error can be avoided. Therefore, the encapsulation substrate of the present invention can ensure normal electrical connection.

[0100] The above embodiments are only used to illustrate the principles and effects of the present invention by way of example, and are not used to limit the present invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the rights protection of the present invention shall be as set forth in the claims.

Claims

1. An encapsulation substrate, comprising: A core layer having conductive posts; An insulating layer having opposite sides and formed on opposite surfaces of the core layer, and blind vias are formed in at least one side of the insulating layer; A circuit layer embedded in the insulating layer and exposed on the surface of at least one side of the opposite sides of the insulating layer; An alignment portion embedded in the insulating layer and exposed on the surface of at least one side of the opposite sides of the insulating layer to correspond to the blind vias in the insulating layer; And A conductor formed in the blind vias, and the conductor in the blind vias is electrically connected to the conductive posts in the core layer, Wherein, the surfaces of the circuit layer, the alignment portion, and the conductor are lower than the surface of at least one side of the insulating layer in which the circuit layer and the alignment portion are embedded, Wherein, the alignment portion effectively aligns the conductive posts so that the blind vias effectively align with the conductive posts.

2. The packaged substrate according to claim 1, wherein The alignment portion is a ring body.

3. The encapsulation substrate according to claim 1, wherein Conductors are disposed on opposite surfaces of the core layer so that the conductors on opposite surfaces of the core layer are both electrically connected to the conductive posts.

4. The encapsulated substrate according to claim 1, wherein, The alignment portion and the blind vias corresponding to the alignment portion are respectively formed on opposite sides of the insulating layer.

5. The encapsulated substrate according to claim 1, wherein, The encapsulation substrate further includes build-up structures bonded to opposite sides of the core layer so that the insulating layer is formed on at least one of the build-up structures, a conductor is disposed on the build-up structure, and the build-up structure has a wiring layer electrically connecting the conductive posts and the conductor.

6. A method for manufacturing an encapsulation substrate, comprising: Providing an insulating layer having opposite sides, wherein the insulating layer is formed on opposite surfaces of a core layer, and the core layer has conductive posts; Pressing a circuit layer and an alignment portion into at least one side of the opposite sides of the insulating layer so that the circuit layer and the alignment portion are embedded in the insulating layer; Forming blind vias at least on one side of the opposite sides of the insulating layer corresponding to the alignment portion; and Forming a conductor in the blind vias so that the conductor in the blind vias is electrically connected to the conductive posts in the core layer; Wherein, the surfaces of the circuit layer, the alignment portion, and the conductor are lower than the surface of at least one side of the insulating layer into which the circuit layer and the alignment portion are pressed, Wherein, the alignment portion effectively aligns the conductive posts so that the blind vias effectively align with the conductive posts.

7. The manufacturing method of the encapsulated substrate according to claim 6, wherein, The alignment portion is a ring body.

8. The manufacturing method of the encapsulated substrate as described in claim 6, wherein, Conductors are formed on opposite surfaces of the core layer so that the conductors on opposite surfaces of the core layer are both electrically connected to the conductive posts.

9. The manufacturing method of the encapsulation substrate according to claim 6, wherein, The alignment portion is respectively formed on opposite sides of the insulating layer to form the blind vias at positions corresponding to the alignment portion.

10. The manufacturing method of the encapsulated substrate according to claim 6, wherein, The method further includes providing build-up structures bonded to opposite sides of the core layer so that the insulating layer is formed on at least one of the build-up structures, a conductor is disposed on the build-up structure, and the build-up structure has a wiring layer electrically connecting the conductive posts and the conductor.

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