Semiconductor structure and method for preparing semiconductor structure

Abstract

The embodiment of the present application provides a semiconductor structure and a method for preparing the semiconductor structure, the semiconductor structure comprising: a substrate, the substrate comprising a first active region, a second active region and an isolation structure; wherein the first active region and the second active region are isolated by the isolation structure; the first active region comprises a first doping region and a second doping region; the second active region comprises a third doping region and a fourth doping region; the semiconductor structure further comprises a gate structure, and the gate structure is arranged above the second doping region and the third doping region, and the gate structure is connected to the second doping region and the third doping region. In this way, the semiconductor structure of the embodiment of the present application can improve the device integration and improve the electrical performance of the semiconductor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Art

[0002] The existing dynamic random access memory (DRAM) includes storage units and peripheral control devices. With the advancement of semiconductor manufacturing technology, the key dimensions defined in the semiconductor component design specifications are getting smaller and smaller, which increases the difficulty of manufacturing peripheral control devices. Summary of the invention

[0003] The present application provides a semiconductor structure and a method for preparing the semiconductor structure, which can increase the integration of transistors and improve the electrical performance of transistors.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor structure, including:

[0005] A substrate, comprising a first active region, a second active region and an isolation structure; wherein the first active region and the second active region are isolated by the isolation structure;

[0006] The first active region includes a first doping region and a second doping region; the second active region includes a third doping region and a fourth doping region;

[0007] The semiconductor structure further includes a gate structure, and the gate structure is disposed above the second doping region and the third doping region, and the gate structure is connected to the second doping region and the third doping region.

[0008] In some embodiments, the second doping region and the third doping region have the same doping type.

[0009] In some embodiments, the first doping region and the fourth doping region have opposite doping types.

[0010] In some embodiments, the third doping region and the fourth doping region have the same doping type, and the third doping region and the fourth doping region have different doping concentrations.

[0011] In some embodiments, the doping type of the first doping region is N-type doping; the doping types of the second doping region, the third doping region and the fourth doping region are P-type doping; and the doping concentration of the fourth doping region is higher than the doping concentration of the third doping region.

[0012] In some embodiments, the first active region and / or the second active region includes a fin structure.

[0013] In some embodiments, the second doped region is located at an end of the first active region close to the second active region, and the third doped region is located at an end of the second active region close to the first active region.

[0014] In some embodiments, the second doped region includes a first connection region connecting at least two fin structures of the first active region together.

[0015] In some embodiments, the third doped region includes a second connection region connecting at least two fin structures of the second active region together.

[0016] In a second aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising:

[0017] providing a substrate;

[0018] Forming a first active region, a second active region and an isolation structure on a substrate; wherein the first active region and the second active region are isolated by the isolation structure;

[0019] A first doping region and a second doping region are formed at two ends of the first active region respectively; a third doping region and a fourth doping region are formed at two ends of the second active region respectively;

[0020] A gate structure is formed above the second doping region and the third doping region, and the gate structure is connected to the second doping region and the third doping region.

[0021] In some embodiments, forming the first active region, the second active region and the isolation structure on the substrate includes:

[0022] A covering layer is formed on a substrate, and a patterned mask is formed on the covering layer; a pattern transfer process is performed on the substrate through the patterned mask, and the patterned mask and the covering layer are removed to obtain a first active area and a second active area; an insulating material is filled between the first active area and the second active area to obtain an isolation structure.

[0023] In some embodiments, forming a patterned mask on the cover layer includes:

[0024] An initial pattern is formed on the cover layer; the initial pattern is cut to obtain a first pattern and a second pattern; a first dielectric layer is deposited on the sidewalls of the first pattern and the second pattern, and the first pattern and the second pattern are removed, and the first dielectric layer is retained to obtain a patterned mask.

[0025] In some embodiments, the method further comprises:

[0026] A first mask layer is formed on the first active region and the second active region, and the first mask layer covers part of the first active region and part of the second active region, exposing an end of the first active region away from the second active region and an end of the second active region away from the first active region; a first doping process is performed on an end of the first active region away from the second active region to obtain a first doping region; and a second doping process is performed on an end of the second active region away from the first active region to obtain a fourth doping region; the first mask layer is removed to form a second mask layer, and the second mask layer covers the first doping region and the fourth doping region, and the second mask layer does not cover an end of the first active region close to the second active region and an end of the second active region close to the first active region; a third doping process is performed on an end of the first active region close to the second active region and an end of the second active region close to the first active region to obtain a second doping region and a third doping region; the second mask layer is removed, and gate structures are formed on the second doping region and the third doping region.

[0027] In some embodiments, the method further comprises:

[0028] forming a third mask layer on the first active region and the second active region, wherein the third mask layer covers a portion of the first active region and a portion of the second active region, exposing an end of the first active region close to the second active region and an end of the second active region close to the first active region; performing a third doping process on an end of the first active region close to the second active region and an end of the second active region close to the first active region, to obtain a second doping region and a third doping region;

[0029] The third mask layer is removed to form a gate structure on the second doping region and the third doping region; a first doping process is performed on an end of the first active region away from the second active region to obtain a first doping region; and a second doping process is performed on an end of the second active region away from the first active region to obtain a fourth doping region.

[0030] In some embodiments, the doping types of the first doping process and the third doping process are opposite, the doping types of the second doping process and the third doping process are the same, and the doping concentration of the second doping process is different from the doping concentration of the third doping process.

[0031] In some embodiments, the doping type of the first doping region is N-type doping; the doping types of the second doping region, the third doping region and the fourth doping region are P-type doping; and the doping concentration of the fourth doping region is higher than the doping concentration of the third doping region.

[0032] The embodiment of the present application provides a semiconductor structure and a method for preparing the semiconductor structure, wherein the semiconductor structure comprises: a substrate, wherein the substrate comprises a first active region, a second active region and an isolation structure; wherein the first active region and the second active region are isolated by the isolation structure; the first active region comprises a first doping region and a second doping region; the second active region comprises a third doping region and a fourth doping region; the semiconductor structure further comprises a gate structure, and the gate structure is arranged above the second doping region and the third doping region, and the gate structure is connected to the second doping region and the third doping region. In this way, the gate structure is arranged on the second doping region in the first active region and the third doping region in the second active region, and the states of the two active regions can be controlled by one gate structure, thereby improving the device integration and the electrical performance of the semiconductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of another semiconductor structure provided in an embodiment of the present application;

[0036] Figure 4 A circuit diagram of a semiconductor structure provided in an embodiment of the present application;

[0037] Figure 5 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present application;

[0038] Fig. 6A A schematic diagram of a semiconductor structure preparation process provided in an embodiment of the present application Figure 1 ;

[0039] Figure 6B A schematic diagram of a semiconductor structure preparation process provided in an embodiment of the present application Figure 2 ;

[0040] Fig. 7A A schematic diagram of a semiconductor structure preparation process provided in an embodiment of the present application Figure 3 ;

[0041] Figure 7B A schematic diagram of a semiconductor structure preparation process provided in an embodiment of the present application Figure 4 ;

[0042] Fig. 8A A schematic diagram of a semiconductor structure preparation process provided in an embodiment of the present application Figure 5 ;

[0043] Figure 8B Schematic diagram 6 of a semiconductor structure preparation process provided in an embodiment of the present application;

[0044] Fig. 9A Schematic diagram 7 of a semiconductor structure preparation process provided in an embodiment of the present application;

[0045] Fig. 9B Schematic diagram 8 of a semiconductor structure preparation process provided in an embodiment of the present application;

[0046] Fig. 10A Schematic diagram 9 of a semiconductor structure preparation process provided in an embodiment of the present application;

[0047] Fig. 10B Schematic diagram 10 of a semiconductor structure preparation process provided in an embodiment of the present application;

[0048] Fig.11A 11 is a schematic diagram of a semiconductor structure preparation process provided in an embodiment of the present application;

[0049] Fig. 11B Schematic diagram 12 of a semiconductor structure preparation process provided in an embodiment of the present application;

[0050] Fig. 12A A schematic front view of another semiconductor structure provided in an embodiment of the present application;

[0051] Fig. 12B A schematic diagram of a top view of another semiconductor structure provided in an embodiment of the present application;

[0052] Fig.13 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It is understood that the specific embodiments described herein are only used to explain the related applications, rather than to limit the applications. It should also be noted that, for ease of description, only the parts related to the related applications are shown in the accompanying drawings.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0055] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0056] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0057] Explain the English abbreviations involved in this application.

[0058] MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide Semiconductor Field-Effect Transistor;

[0059] NMOS: N-type MOS tube, a semiconductor that mainly conducts electricity through electrons;

[0060] PMOS: P-type MOS tube, a semiconductor mainly based on hole conduction;

[0061] FinFET (FinField Effect Transistor): fin field effect transistor.

[0062] The existing dynamic random access memory (DRAM) includes storage units and peripheral control devices. With the advancement of semiconductor manufacturing technology, the key dimensions defined in the semiconductor component design specifications are getting smaller and smaller, which increases the difficulty of manufacturing peripheral control devices.

[0063] The embodiment of the present application provides a semiconductor structure, which includes a substrate, and the substrate includes a first active region, a second active region and an isolation structure; wherein the first active region and the second active region are isolated by the isolation structure; the first active region includes a first doping region and a second doping region; the second active region includes a third doping region and a fourth doping region; the semiconductor structure also includes a gate structure, and the gate structure is arranged above the second doping region and the third doping region, and the gate structure is connected to the second doping region and the third doping region. In this way, the gate structure is arranged on the second doping region in the first active region and the third doping region in the second active region, and the states of the two active regions can be controlled by one gate structure, thereby improving the device integration and improving the electrical performance of the semiconductor.

[0064] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0065] In one embodiment of the present application, see Figure 1 , which shows a schematic diagram of the structure of a semiconductor structure 10 provided in an embodiment of the present application. Figure 1 As shown, the semiconductor structure 10 may include:

[0066] The substrate includes a first active region 101, a second active region 102 and an isolation structure 103. That is, the isolation structure 103 defines a plurality of active regions on the substrate, the first active region 101 and the second active region 102 are isolated by the isolation structure 103, and the interior of the first active region 101 (or the interior of the second active region 102) is also isolated by the isolation structure 103.

[0067] The first active region 101 includes a first doping region 1011 and a second doping region 1012 ; the second active region 102 includes a third doping region 1021 and a fourth doping region 1022 ;

[0068] The semiconductor structure 10 further includes a gate structure, and the gate structure is disposed above the second doping region 1012 and the third doping region 1021 , and the gate structure is connected to the second doping region 1012 and the third doping region 1021 .

[0069] It should be noted that the isolation structure 103 may be a shallow trench isolation (STI) structure.

[0070] It should be noted that Figure 1 is a top view of the semiconductor structure 10, and Figure 1 The surface of the substrate is covered by the isolation structure or active area, so Figure 1 The substrate is not shown. It should be understood that the substrate is below the isolation structure and the active area.

[0071] In addition, since the gate structure actually covers the second doping region 1012 and the third doping region 1021, in order to more clearly describe the relative position relationship, Figure 1 The second doping region 1012 and the third doping region 1021 are shown in FIG. Figure 2 , which shows a schematic structural diagram of another semiconductor structure 10 provided in an embodiment of the present application. In particular, Figure 2 is along Figure 1 The cross-section is taken along the A-A' direction, and the cross-section is perpendicular to the substrate. Figure 2 As shown, the gate structure 103 is disposed above the second doping region 1012 and the third doping region 1021 .

[0072] In some embodiments, the second doping region 1012 and the third doping region 1021 have the same doping type.

[0073] It should be noted that the doping type includes hole doping (P type) and electron doping (N type). Since the second doping region 1012 and the third doping region 1021 are both regions below the gate structure, the same doping type is used.

[0074] For example, the second doping region 1012 and the third doping region 1021 are both P-type doped, or the second doping region 1012 and the third doping region 1021 are both N-type doped.

[0075] In some embodiments, the first doping region 1011 and the fourth doping region 1022 have opposite doping types.

[0076] For example, the first doping region 1011 is N-type doped, and the fourth doping region is P-type doped; or, the first doping region 1011 is P-type doped, and the fourth doping region is N-type doped.

[0077] In some embodiments, the first doping region 1011 and the second doping region 1012 have opposite doping types.

[0078] For example, when the second doping region 1012 and the third doping region 1021 are both P-type doped, the first doping region 1011 is N-type doped; when the second doping region 1012 and the third doping region 1021 are both N-type doped, the first doping region 1011 is P-type doped.

[0079] In some embodiments, the third doping region 1021 and the fourth doping region 1022 have the same doping type, and the third doping region 1021 and the fourth doping region 1022 have different doping concentrations.

[0080] For example, when the second doping region 1012 and the third doping region 1021 are both P-type doped, the fourth doping region 1022 is high-concentration P (P+) type doped; when the second doping region 1012 and the third doping region 1021 are both N-type doped, the fourth doping region 1022 is high-concentration N (N+) type doped.

[0081] In a specific embodiment, the doping type of the first doping region 1011 is N-type doping; the doping types of the second doping region 1012 , the third doping region 1021 and the fourth doping region 1022 are P-type doping; and the doping concentration of the fourth doping region 1022 is higher than the doping concentration of the third doping region 1021 .

[0082] In another specific embodiment, the doping type of the first doping region 1011 is P-type doping; the doping types of the second doping region 1012 , the third doping region 1021 and the fourth doping region 1022 are N-type doping; and the doping concentration of the fourth doping region 1022 is higher than the doping concentration of the third doping region 1021 .

[0083] In some embodiments, Figure 1 and Figure 2 As shown, the second doping region 1012 is located at one end of the first active region 101 close to the second active region 102 , and the third doping region 1021 is located at one end of the second active region 102 close to the first active region 101 .

[0084] In this way, the gate structure 104 can be conveniently formed on the second doping region 1012 and the third doping region 1021 , so that the first active region and the second active region can be controlled by one gate structure, thereby increasing device integration and improving the electrical performance of the semiconductor.

[0085] In one application scenario, the semiconductor structure 20 provided in the embodiment of the present application can be used to form a fin field effect transistor FinFET, which can significantly reduce leakage current and shorten the length of the gate structure of the transistor, further improving electrical performance. Figure 3 , which shows a schematic diagram of the structure of another semiconductor structure provided by an embodiment of the present application. Figure 3 As shown,

[0086] The first active region 101 and / or the second active region 102 includes a fin-shaped structure. The fin-shaped structure is specifically as follows: Figure 3 As shown in a in .

[0087] In some embodiments, the second doped region 1012 includes a first connection region connecting at least two fin structures of the first active region 101. In some embodiments, the third doped region 1021 includes a second connection region connecting at least two fin structures of the second active region 102.

[0088] It should be noted that at least two fin structures are connected together through the first connection region so as to form a channel of a transistor in the first active region 101. At least two fin structures are connected together through the second connection region so as to form a channel of a transistor in the second active region 102. The first connection region and the second connection region are specifically as follows: Figure 3 As shown in b.

[0089] Here, the specific patterns of the fin structure and the first connection area / second connection area may include a variety of situations, which can be set according to actual needs. For example, the first connection area / second connection area may be located at the end or middle of the corresponding active area fin structure.

[0090] It should be noted that since the gate structure 103 is arranged above the first connection area and the second connection area, the working state of the first connection area and the second connection area is controlled by the gate structure 103, that is, the gate structure 103 can simultaneously control the working state of the first active area 101 and the second active area 102.

[0091] The following is a specific description using an example in which the first doping region 1011 is N-type doped, the second doping region 1012 and the third doping region 1021 are P-type doped, and the fourth doping region 1022 is P+ type doped.

[0092] When the gate structure is in a low potential state, the first connection area and the second connection area are both P-type. At this time, the first active area forms an NPN channel and is in a disconnected state, and the second active area forms a P+PP+ channel and is in a connected state; when the gate structure is in a high potential state, the first connection area and the second connection area are inverted to N-type. At this time, the first active area forms an NNN channel and is in a connected state, and the second active area forms a P+NP+ channel and is in a disconnected state.

[0093] In other words, for the semiconductor structure provided in the embodiment of the present application, by applying different potentials to the gate structure, it is possible to control the first active area to form an effective conductive channel or control the second active area to form an effective conductive channel. In this way, it is achieved that the states of the two active areas are controlled by one gate structure, thereby improving the device integration and improving the electrical performance of the semiconductor. In addition, the semiconductor structure provided in the embodiment of the present application can be used for the preparation of a variety of electrical devices, such as NMOS devices, PMOS devices, complementary transistor CMOS devices, bipolar transistors (Bipolar Junction Transistor, BJT), etc., which are not limited by the embodiment of the present application.

[0094] The embodiment of the present application provides a semiconductor structure, which includes a substrate, and the substrate includes a first active region, a second active region and an isolation structure; wherein the first active region and the second active region are isolated by the isolation structure; the first active region includes a first doping region and a second doping region; the second active region includes a third doping region and a fourth doping region; the semiconductor structure also includes a gate structure, and the gate structure is arranged above the second doping region and the third doping region, and the gate structure is connected to the second doping region and the third doping region. In this way, the gate structure is arranged on the second doping region in the first active region and the third doping region in the second active region, and the states of the two active regions can be controlled by one gate structure, thereby improving the device integration and improving the electrical performance of the semiconductor.

[0095] In another embodiment of the present application, continue to refer to Figure 3 , taking a transistor as an application scenario, the semiconductor structure 10 is further described.

[0096] The embodiment of the present application provides a semiconductor structure 10, in which a plurality of active regions are defined on a substrate by an isolation structure, and a pattern having a U-shaped cross-section (hereinafter referred to as a U-shaped pattern) exists in each active region. A group of adjacent active regions is referred to as a first active region 101 and a second active region 102.

[0097] From the doping perspective, the first active region 101 includes a first doping region and a second doping region, and the second active region 102 includes a third doping region and a fourth doping region. The second doping region and the third doping region have the same doping type. In the embodiment of the present application, the first doping region is N-type doped, the second doping region and the third doping region are P-type doped, and the fourth doping region is P+ type doped. This does not constitute a relevant limitation.

[0098] From a structural perspective, Figure 3 As shown, in the first active area 101, there are a first fin structure (at a), a second fin structure (at a) and a first connection area (at b), and the two endpoints of the first connection area are respectively connected to the endpoints of the first fin structure and the endpoints of the second fin structure, so that the cross-sectional shapes of the first fin structure, the second fin structure and the first connection area are U-shaped. In addition, the first fin structure and the second fin structure are both located in the first doped area (N-type doping), and the first connection area is located in the second doped area (P-type doping). At this time, the first active area 101 can be used to form a junction-type NMOS, and the first connection area can be used as a conductive channel of the NMOS.

[0099] In the second active area 102, there are a third fin structure (at a), a fourth fin structure (at a), and a second connection area (at b), and the two endpoints of the second connection area are respectively connected to the endpoints of the third fin structure and the endpoints of the fourth fin structure, so that the cross-sectional shape of the third fin structure, the fourth fin structure, and the second connection area is U-shaped. The third fin structure and the fourth fin structure are both located in the fourth doping area (P+ type doping), and the second connection area is located in the third doping area (P type doping). At this time, the second active area 102 can be used to form a junctionless PMOS, and the second connection area can be used as a conductive channel of the PMOS.

[0100] In addition, a gate structure 104 is provided on the upper side of the first connection area and the second connection area, and the gate structure 104 serves as the gate of the NMOS and the gate of the PMOS at the same time. Specifically, when the gate structure 104 is externally connected to a low potential, the first connection area and the second connection area are in a P-doped state, and the channel of the NMOS in the first active area 101 is in an NPN state, that is, a disconnected state; the channel of the PMOS in the second active area 102 is in a P+PP+ state, that is, a conductive state; when the gate structure is externally connected to a high potential, the first connection area and the second connection area are inverted to an N-doped state, and the channel of the NMOS in the first active area 101 is in an NNN state, that is, a conductive state; the channel of the PMOS in the second active area 102 is in a P+NP+ state, that is, a disconnected state.

[0101] In a specific circuit scenario, see Figure 4 , which shows a circuit diagram of a semiconductor structure provided by an embodiment of the present application. Figure 4 As shown, the PMOS external power supply voltage (V DD ), NMOS external ground voltage (V ss ), if a high voltage is applied to the gate, PMOS is turned off and NMOS is turned on. At this time, the output ground voltage (V ss ); If a low voltage is applied to the gate, NMOS is turned off and PMOS is turned on. At this time, the output power supply voltage (V DD ). In summary, the embodiments of the present application provide a semiconductor structure with a shared gate structure, which can increase the integration of field effect transistors and improve the electrical performance and speed of the device.

[0102] The embodiment of the present application provides a semiconductor structure, which includes a substrate, and the substrate includes a first active region, a second active region and an isolation structure; wherein the first active region and the second active region are isolated by the isolation structure; the first active region includes a first doping region and a second doping region; the second active region includes a third doping region and a fourth doping region; the semiconductor structure also includes a gate structure, and the gate structure is arranged above the second doping region and the third doping region, and the gate structure is connected to the second doping region and the third doping region. In this way, the gate structure is arranged on the second doping region in the first active region and the third doping region in the second active region, and the states of the two active regions can be controlled by one gate structure, thereby improving the device integration and improving the electrical performance of the semiconductor.

[0103] In another embodiment of the present application, see Figure 5 , which shows a schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application. Figure 5 As shown, the method may include:

[0104] S201: providing a substrate.

[0105] It should be noted that the preparation method provided in the embodiment of the present application is mainly used to prepare the aforementioned semiconductor structure 10 .

[0106] S202: forming a first active region, a second active region and an isolation structure on a substrate; wherein the first active region and the second active region are isolated by the isolation structure.

[0107] It should be noted that the isolation structure may be a shallow trench isolation structure. Here, the interior of the first active region or the interior of the second active region is also isolated by the isolation structure.

[0108] In some embodiments, forming the first active region, the second active region and the isolation structure on the substrate may include:

[0109] forming a capping layer on the substrate, and forming a patterned mask on the capping layer;

[0110] Performing pattern transfer processing on the substrate through a patterned mask, and removing the patterned mask and the cover layer to obtain a first active area and a second active area;

[0111] An insulating material is filled between the first active region and the second active region to obtain an isolation structure.

[0112] It should be noted that when preparing the active area and the isolation structure, the substrate is first protected by a cover layer, and then a patterned mask is formed on the cover layer, and the patterned mask is transferred to the substrate to obtain a substrate with multiple grooves. At this time, the grooves are filled with insulating materials to form an isolation structure, and the non-groove area on the substrate surface forms an active area.

[0113] In addition, the shape and size of the patterned mask need to be designed and determined according to the required active area. The pattern transfer process can be a forward pattern transfer process or a reverse pattern transfer process.

[0114] In some embodiments, forming a patterned mask on the cover layer may include:

[0115] forming an initial pattern on the cover layer;

[0116] Performing a cutting process on the initial pattern to obtain a first pattern and a second pattern;

[0117] A first dielectric layer is deposited on the sidewalls of the first pattern and the second pattern, and the first pattern and the second pattern are removed, and the first dielectric layer is retained to obtain a patterned mask.

[0118] It should be noted that in the embodiment of the present application, the active areas need to appear in pairs. Therefore, after the initial pattern is formed on the cover layer, the initial pattern can be cut into a first pattern and a second pattern; then the first dielectric layer is deposited on the sidewall of the first pattern, and the second dielectric layer is deposited on the sidewall of the second pattern. In this way, the shapes of the first dielectric layer and the second dielectric layer are patterned masks, and the first dielectric layer can assist in forming the first active area, and the second dielectric layer can assist in forming the second active area.

[0119] Here, the cross-sectional shape of the active region may be in various shapes, such as U-shape, H-shape, V-shape, etc. The following takes the cross-sectional shape of the active region as U-shape as an example to provide a specific preparation process.

[0120] It should be noted that see Figures 6A to 11B , which shows a schematic diagram of a semiconductor structure preparation process provided by an embodiment of the present application. Figures 6A to 11B As shown, the active region and the isolation structure between the active regions can be prepared by the following steps:

[0121] (1) Step 1: Fig. 6A and Figure 6B As shown, a cover layer 301 is formed on a substrate 100, and an initial pattern 302 is formed on the cover layer 301. The cover layer 301 may include a silicon nitride layer and a silicon oxide layer from top to bottom, and the material of the initial pattern 302 may be polysilicon. The initial pattern 302 includes a plurality of cubic structures arranged at intervals along the x direction, and different cubic structures are parallel to each other.

[0122] In particular, Fig. 6A is a schematic diagram of the semiconductor structure in the xz direction after the first step. Figure 6B It is a schematic diagram of the semiconductor structure in the xy direction after the first step.

[0123] (2) Step 2: Fig. 7A and Figure 7B As shown, the middle of the initial pattern 302 is cut in the y direction, and the shape of the initial pattern 302 in the xz plane does not change. At this time, each initial pattern 302 is divided into two symmetrical cubic structures. For the convenience of description, the cubic structure obtained after cutting is called the pattern to be processed 303.

[0124] In particular, Fig. 7A is a schematic diagram of the semiconductor structure in the xz direction after the second step. Figure 7B It is a schematic diagram of the semiconductor structure in the xy direction after the second step.

[0125] (3) Step 3: Fig. 8A and Figure 8B As shown, a first dielectric layer 304 is deposited on the side of the pattern to be processed 303. The material of the first dielectric layer 304 may be silicon oxide. In this way, the first dielectric layer 304 forms a plurality of patterns with a U-shaped cross-section (hereinafter referred to as U-shaped patterns).

[0126] In particular, Fig. 8A This is a schematic diagram of the semiconductor structure in the xz direction after the third step. Figure 8B Schematic diagram of the semiconductor structure in the xy direction after the third step.

[0127] (4) Step 4: Fig. 9A and Fig. 9B As shown, the pattern to be processed 303 is removed, and only the first dielectric layer 304 is retained. At this time, only a plurality of U-shaped patterns, namely the patterned mask 305, remain on the cover layer 301.

[0128] In particular, Fig. 9A This is a schematic diagram of the semiconductor structure in the xz direction after the fourth step. Fig. 9B It is a schematic diagram of the semiconductor structure in the xy direction after the fourth step.

[0129] (5) Step 5: Fig. 10A and Fig. 10B As shown, the portion not covered by the patterned mask 305 is etched downward until it reaches deep into the substrate 100 .

[0130] In particular, Fig. 10A This is a schematic diagram of the semiconductor structure in the xz direction after the fifth step. Fig. 10B It is a schematic diagram of the semiconductor structure in the xy direction after the fifth step.

[0131] (6) Step 6: Fig.11A and Fig. 11BAs shown, the patterned mask 305 and the remaining cover layer 301 are removed to form a plurality of trenches on the substrate 100. Then, an insulating material is filled into the trenches on the substrate 100. At this time, the filled insulating material forms an isolation structure 103, and the portion of the upper surface of the substrate 100 where no trench is formed forms an active area. Fig. 11B In the figure, the upper active region can be called the first active region 101, the lower active region can be called the second active region 102, and the remaining white part is the isolation structure 103.

[0132] In particular, Fig.11A This is a schematic diagram of the semiconductor structure in the xz direction after the sixth step. Fig. 11B Schematic diagram of the semiconductor structure in the xy direction after the sixth step.

[0133] In this way, through the above steps, a first active area, a second active area and a doping structure are formed on the substrate.

[0134] S203: forming a first doping region and a second doping region at two ends of the first active region respectively; forming a third doping region and a fourth doping region at two ends of the second active region respectively.

[0135] S204: forming a gate structure above the second doping region and the third doping region, wherein the gate structure is connected to the second doping region and the third doping region.

[0136] It should be noted that the first doping region and the second doping region are formed at both ends of the first active region, the third doping region and the fourth doping region are formed at both ends of the second active region, and a gate structure needs to be constructed above the second doping region and the third doping region. In this way, the gate structure is arranged on the second doping region and the third doping region, and the states of the two active regions can be controlled by one gate structure, thereby improving the device integration and the electrical performance of the semiconductor.

[0137] Since the shapes of the active regions are various, here, the two ends of the first active region refer to: one end of the first active region close to the second active region and one end of the first active region far from the second active region; the two ends of the second active region refer to: one end of the second active region close to the first active region and one end of the first active region far from the second active region.

[0138] It should be noted that the first doped region is formed at an end of the first active region away from the second active region, the second doped region is formed at an end of the first active region close to the second active region, the third doped region is formed at an end of the second active region close to the first active region, and the fourth doped region is formed at an end of the second active region close to the first active region.

[0139] It should also be noted that step S303 and step S304 do not have a specific order, that is, the doping step can be completed first and then the gate forming step, or the gate forming step can be completed first and then the doping step, or part of the doping step can be completed first, then the gate forming step, and finally the remaining doping steps can be completed.

[0140] Two feasible doping methods are given below.

[0141] In a specific embodiment, the first doping region and the fourth doping region may be formed first, and then the second doping region and the third doping region may be formed, and finally the gate structure may be formed. Therefore, the method may further include:

[0142] Forming a first mask layer on the first active region and the second active region, wherein the first mask layer covers a portion of the first active region and a portion of the second active region, exposing an end of the first active region away from the second active region and an end of the second active region away from the first active region;

[0143] Performing a first doping process on an end of the first active region away from the second active region to obtain a first doped region; and performing a second doping process on an end of the second active region away from the first active region to obtain a fourth doped region;

[0144] The first mask layer is removed to form a second mask layer, wherein the second mask layer covers the first doped region and the fourth doped region, and the second mask layer does not cover an end of the first active region close to the second active region and an end of the second active region close to the first active region;

[0145] Performing a third doping process on one end of the first active region close to the second active region and one end of the second active region close to the first active region to obtain a second doping region and a third doping region;

[0146] The second mask layer is removed, and a gate structure is formed on the second doping region and the third doping region.

[0147] It should be noted that, first, the portion reserved for the second doping region and the third doping region is covered, the first active region is doped to form the first doping region, and the second active region is doped to form the fourth doping region. It should be understood that if the doping elements of the first doping region and the fourth doping region are different, when forming the first active region, part of the fourth doping region may also be covered; when forming the fourth doping region, part of the first doping region may also be covered. Secondly, after forming the first doping region and the fourth doping region, the first mask layer covering the second doping region and the third doping region is removed, and the first doping region and the fourth doping region are covered by the second mask, and then the first active region and the second active region are doped to form the second doping region and the third doping region. Here, the doping process of the second doping region and the third doping region is the same, and they can be processed together. Finally, the second mask layer is removed, and a gate structure is formed on the second doping region and the third doping region.

[0148] In another specific embodiment, the second doping region and the third doping region may be formed first, then the gate structure may be formed, and finally the first doping region and the fourth doping region may be formed. Therefore, the method may further include:

[0149] forming a third mask layer on the first active region and the second active region, wherein the third mask layer covers a portion of the first active region and a portion of the second active region, exposing an end of the first active region close to the second active region and an end of the second active region close to the first active region;

[0150] Performing a third doping process on one end of the first active region close to the second active region and one end of the second active region close to the first active region to obtain a second doping region and a third doping region;

[0151] removing the third mask layer, and forming a gate structure on the second doping region and the third doping region;

[0152] A first doping process is performed on an end of the first active region away from the second active region to obtain a first doping region; and a second doping process is performed on an end of the second active region away from the first active region to obtain a fourth doping region.

[0153] It should be noted that, first, the third mask layer is used to cover the portion reserved for the first doping region and the fourth doping region, and the first active region and the second edge region are doped to form the second doping region and the third doping region. Secondly, a gate structure is established above the second doping region and the third doping region. Finally, since the gate structure is higher than the second doping region and the third doping region, it can act as a mask, and there is no need to form a mask again. The remaining portion of the first active region is directly doped to form the first doping region, and the remaining portion of the second active region is doped to form the fourth active region.

[0154] In some embodiments, the doping types of the first doping process and the third doping process are opposite, the doping types of the second doping process and the third doping process are the same, and the doping concentration of the second doping process is different from the doping concentration of the third doping process.

[0155] Exemplarily, the doping type of the first doping region is N-type doping; the doping types of the second doping region, the third doping region and the fourth doping region are P-type doping; and the doping concentration of the fourth doping region is higher than the doping concentration of the third doping region.

[0156] Alternatively, in other embodiments, the doping type of the first doping region is P-type doping; the doping types of the second doping region, the third doping region and the fourth doping region are N-type doping; and the doping concentration of the fourth doping region is higher than the doping concentration of the third doping region.

[0157] See also Fig. 12A, which shows a front view schematic diagram of another semiconductor structure provided by an embodiment of the present application. Fig. 12B , which shows a schematic diagram of a top view of another semiconductor structure provided by an embodiment of the present application. For the convenience of explanation, the gate structure 104 is shown with a semi-transparent pattern.

[0158] like Fig. 12A and Fig. 12B As shown, the first active region 101 and the second active region 102 are both composed of a plurality of U-shaped patterns. Fig. 12A As shown, a gate structure 104 is formed above the active region; Fig. 12B As shown, the gate structure 104 covers the second doping region in the first active region 101 and the third doping region in the second active region 102 .

[0159] The embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising providing a substrate; forming a first active region, a second active region and an isolation structure on the substrate; wherein the first active region and the second active region are isolated by the isolation structure; forming a first doping region and a second doping region at both ends of the first active region; forming a third doping region and a fourth doping region at both ends of the second active region; forming a gate structure above the second doping region and the third doping region, and the gate structure is connected to the second doping region and the third doping region. In this way, the gate structure is arranged on the second doping region in the first active region and the third doping region in the second active region, and the states of the two active regions can be controlled by one gate structure, thereby improving the device integration and improving the electrical performance of the semiconductor.

[0160] In another embodiment of the present application, see Fig.13 , which shows a schematic diagram of the structure of an electronic device 40 provided in an embodiment of the present application. Fig.13 As shown, the electronic device 40 includes the aforementioned semiconductor structure 10 .

[0161] For the electronic device 40, since it includes a semiconductor structure 10, and the gate structure in the semiconductor structure 10 is arranged on the second doped region in the first active region and the third doped region in the second active region, the states of the two active regions can be controlled by one gate structure, thereby improving the device integration and improving the electrical performance of the semiconductor.

[0162] The above are only preferred embodiments of the present application and are not intended to limit the protection scope of the present application.

[0163] It should be noted that, in this application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0164] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0165] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0166] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0167] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0168] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a first active region, a second active region and an isolation structure; wherein the first active region and the second active region are isolated by the isolation structure; The first active region includes a first doping region and a second doping region; the second active region includes a third doping region and a fourth doping region; The semiconductor structure further includes a gate structure, and the gate structure is disposed above the second doping region and the third doping region, and the gate structure is connected to the second doping region and the third doping region; The first active region and / or the second active region comprises a fin-shaped structure; The second doped region is located at one end of the first active region close to the second active region, and the third doped region is located at one end of the second active region close to the first active region; The second doped region includes a first connection region connecting at least two fin structures of the first active region together.

2. The semiconductor structure according to claim 1, characterized in that: The second doping region and the third doping region have the same doping type.

3. The semiconductor structure according to claim 2, characterized in that: The first doping region and the fourth doping region have opposite doping types.

4. The semiconductor structure according to claim 3, characterized in that: The third doping region and the fourth doping region have the same doping type, and the third doping region and the fourth doping region have different doping concentrations.

5. The semiconductor structure according to claim 4, characterized in that: The doping type of the first doping region is N-type doping; the doping types of the second doping region, the third doping region and the fourth doping region are P-type doping; and the doping concentration of the fourth doping region is higher than the doping concentration of the third doping region.

6. The semiconductor structure according to claim 1, characterized in that The third doped region includes a second connection region, and the second connection region connects at least two fin structures of the second active region together.

7. A method for preparing a semiconductor structure, characterized in that: The method comprises: providing a substrate; forming a first active region, a second active region and an isolation structure on the substrate; wherein the first active region and the second active region are isolated by the isolation structure; A first doping region and a second doping region are formed at two ends of the first active region respectively; a third doping region and a fourth doping region are formed at two ends of the second active region respectively; forming a gate structure above the second doping region and the third doping region, wherein the gate structure is connected to the second doping region and the third doping region; The first active region and / or the second active region comprises a fin-shaped structure; The second doped region is located at one end of the first active region close to the second active region, and the third doped region is located at one end of the second active region close to the first active region; The second doped region includes a first connection region connecting at least two fin structures of the first active region together.

8. The preparation method according to claim 7, characterized in that: The forming of the first active region, the second active region and the isolation structure on the substrate comprises: forming a covering layer on the substrate, and forming a patterned mask on the covering layer; Performing a pattern transfer process on the substrate through the patterned mask, and removing the patterned mask and the cover layer to obtain the first active area and the second active area; An insulating material is filled between the first active region and the second active region to obtain the isolation structure.

9. The preparation method according to claim 8, characterized in that: The forming of a patterned mask on the cover layer comprises: forming an initial pattern on the cover layer; Performing a cutting process on the initial pattern to obtain a first pattern and a second pattern; A first dielectric layer is deposited on the sidewalls of the first pattern and the second pattern, and the first pattern and the second pattern are removed, and the first dielectric layer is retained to obtain the patterned mask.

10. The preparation method according to claim 7, characterized in that: The method further comprises: forming a first mask layer on the first active region and the second active region, wherein the first mask layer covers a portion of the first active region and a portion of the second active region, exposing an end of the first active region away from the second active region and an end of the second active region away from the first active region; Performing a first doping process on an end of the first active region away from the second active region to obtain the first doped region; and performing a second doping process on an end of the second active region away from the first active region to obtain the fourth doped region; removing the first mask layer to form a second mask layer, wherein the second mask layer covers the first doped region and the fourth doped region, and the second mask layer does not cover an end of the first active region close to the second active region and an end of the second active region close to the first active region; Performing a third doping process on one end of the first active region close to the second active region and one end of the second active region close to the first active region to obtain the second doping region and the third doping region; The second mask layer is removed, and the gate structure is formed on the second doping region and the third doping region.

11. The preparation method according to claim 7, characterized in that: The method further comprises: forming a third mask layer on the first active region and the second active region, wherein the third mask layer covers a portion of the first active region and a portion of the second active region, and exposes an end of the first active region close to the second active region and an end of the second active region close to the first active region; Performing a third doping process on one end of the first active region close to the second active region and one end of the second active region close to the first active region to obtain the second doping region and the third doping region; removing the third mask layer, and forming the gate structure on the second doping region and the third doping region; A first doping process is performed on an end of the first active region away from the second active region to obtain the first doping region; and a second doping process is performed on an end of the second active region away from the first active region to obtain the fourth doping region.

12. The preparation method according to claim 10 or 11, characterized in that: The doping types of the first doping process and the third doping process are opposite, the doping types of the second doping process and the third doping process are the same, and the doping concentration of the second doping process is different from the doping concentration of the third doping process.

13. The preparation method according to claim 12, characterized in that: The doping type of the first doping region is N-type doping; the doping types of the second doping region, the third doping region and the fourth doping region are P-type doping; and the doping concentration of the fourth doping region is higher than the doping concentration of the third doping region.

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