Wide bandgap semiconductor corner trench MOSFET device structure and manufacturing method thereof

Abstract

The present invention provides a wide bandgap semiconductor angled trench MOSFET device structure and a manufacturing method thereof. The wide bandgap semiconductor angled trench MOSFET device structure comprises: a substrate, a P-well region, an N-pillar group, a source P+ region, a source N+ region, a gate, a source, and a drain. The P-well region is disposed on the upper surface of the substrate, the N-pillar group penetrates the P-well region along a first direction, and the lower end of the N-pillar group is connected to the upper surface of the substrate. The bottom of the gate is connected to the upper end of the N-pillar group, and the gate is embedded in the P-well region along the first direction. The source P+ region and the source N+ region are both disposed on the upper surface of the P-well region, with multiple source P+ regions and multiple source N+ regions arranged in sequence. The source is disposed on the upper surface of the source P+ region and the source N+ region, and the drain is disposed at the bottom of the substrate. The device structure can construct a P-well region deeper than the trench, so that the P-well region wraps around the trench corner, thereby reducing the electric field at the trench corner. The N-pillar group can also suppress surge current, thereby improving the stability and reliability of device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a wide bandgap semiconductor angle trench MOSFET device structure and a manufacturing method thereof. Background Art

[0002] Currently, ultra-wide bandgap semiconductor materials with band gaps greater than those of silicon carbide (SiC) and gallium nitride (GaN) primarily include gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN). With their superior optical and electrical properties, they are considered an exciting and challenging new research area. Larger band gaps enable device applications in many extremely harsh environments: higher drilling speeds and lower failure rates are possible in geothermal energy production and oil and gas extraction, while high temperatures allow electronic sensors in aluminum and steel mills, as well as coal- and gas-fired power plants, to operate at higher temperatures, thereby improving the energy efficiency of these industrial processes.

[0003] Silicon carbide devices can achieve P-type doping through ion implantation or epitaxial growth. However, it is more difficult to achieve P-type doping through ion implantation for materials with larger band gaps than silicon carbide, such as gallium nitride, gallium oxide, diamond, and aluminum nitride (AlN). P-type is generally achieved through special processes such as epitaxial growth or oxide growth.

[0004] There are several problems in the actual process manufacturing and application of trench MOSFETs made of wide bandgap semiconductor materials:

[0005] 1. The high electric field in the drift region of the material leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the trench corners, causing the gate dielectric layer to quickly break down under high drain voltages. The device has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit.

[0006] 2. Since wide bandgap semiconductor power MOSFETs are mainly used in high-voltage, high-frequency, and high-current applications, parasitic parameters in the circuit can cause overshoot and other spikes during high-frequency switching, resulting in instantaneous overvoltage in the device current path and increased switching losses. Changes in power load and other factors can also cause large surge voltages.

[0007] 3. The limited depth of ion implantation makes it difficult to implement many targeted trench gate protection structures and surge protection designs from a technological perspective.

[0008] In summary, existing MOSFET devices do not have the ability to self-suppress surge voltage and overvoltage protection. The external matching suppression and overvoltage protection circuits often have time delays. The high-frequency peak voltage surges in the actual switching process are still borne by the device itself, which sometimes leads to breakdown failure of the device channel region and gradual failure of the gate structure and electrode ohmic contact area, causing device reliability problems. Therefore, it is necessary to design a new wide-bandgap semiconductor MOSFET device structure as a more ideal semiconductor material. Summary of the Invention

[0009] Based on the above description, the present invention provides a wide bandgap semiconductor angled trench MOSFET device structure and a manufacturing method thereof, so as to optimize the surge voltage resistance and overvoltage protection of the existing MOSFET device structure and improve the reliability of the device.

[0010] The technical solution of the present invention to solve the above technical problems is as follows:

[0011] In a first aspect, the present invention provides a wide bandgap semiconductor angled trench MOSFET device structure, comprising: a substrate, a P-well region, an N-column group, a source P+ region, a source N+ region, a gate, a source, and a drain;

[0012] The P-well region is provided on the upper surface of the substrate, the N-pillar group is provided through the P-well region along a first direction, and the lower end of the N-pillar group is connected to the upper surface of the substrate;

[0013] The bottom of the gate is connected to the upper end of the N column group, and the gate is embedded in the P well region along the first direction;

[0014] The source P+ region and the source N+ region are both provided on the upper surface of the P-well region, and a plurality of the source P+ regions and a plurality of the source N+ regions are arranged in sequence and spaced apart from each other;

[0015] The source is arranged on the upper surfaces of the source P+ region and the source N+ region, and the drain is arranged on the bottom of the substrate.

[0016] On the basis of the above technical solution, the present invention can also be improved as follows.

[0017] Furthermore, the gate includes a gate dielectric layer, gate silicon and a gate trench;

[0018] The gate trench is U-shaped and extends along the first direction;

[0019] The gate dielectric layer is arranged on the inner wall side of the gate trench; the gate silicon is filled in the middle of the gate trench and is in contact with the gate dielectric layer.

[0020] Furthermore, the wide bandgap semiconductor angled trench MOSFET device structure further includes an interlayer dielectric layer;

[0021] The interlayer dielectric layer covers the opening of the gate trench, and the middle portion thereof contacts the gate dielectric layer and the upper end surface of the gate silicon, and the two ends thereof contact the source N+ region.

[0022] Further, the N-pillar group includes a first N-pillar and a second N-pillar;

[0023] The first N pillars and the second N pillars are spaced apart along a second direction;

[0024] Wherein, the second direction is arranged perpendicular to the first direction.

[0025] Furthermore, each of the first N pillars and the second N pillars includes a plurality of N pillar segments, and the plurality of N pillar segments are arranged at intervals.

[0026] Furthermore, there are a plurality of N column groups; the plurality of N column groups are spaced apart and arranged in the P well region along the second direction;

[0027] The number of the gates and the interlayer dielectric layers is the same as the number of the N column groups, and the gates and the interlayer dielectric layers are arranged corresponding to the N column groups.

[0028] Furthermore, the wide bandgap semiconductor corner trench MOSFET device structure further includes a guide layer;

[0029] The guide layer is provided between the gate trench and the N column group;

[0030] The width of the guide layer along the second direction is smaller than the width of the gate trench; or the width of the guide layer along the second direction is larger than the width of the gate trench.

[0031] Furthermore, the substrate includes an N+ substrate layer and an N- epitaxial layer;

[0032] The N- epitaxial layer is provided on the N+ substrate layer;

[0033] The P-well region is arranged on the upper surface of the N- epitaxial layer, and the drain is arranged on the lower surface of the N+ substrate layer.

[0034] In a second aspect, the present invention further provides a method for manufacturing a wide bandgap semiconductor angle trench MOSFET device structure as described in any one of the first aspects, comprising:

[0035] forming a P-type oxide on the substrate to obtain a P-well region;

[0036] Fabricating a source P+ region and a source N+ region on the P-well region;

[0037] Performing dry etching on the P-well region, the source P+ region, and the source N+ region to obtain a gate trench;

[0038] An N column group is obtained by performing ion implantation on the P-well region at the bottom of the gate trench;

[0039] performing gate dielectric growth, gate silicon growth, and interlayer dielectric deposition in sequence on the gate trench to obtain a gate;

[0040] A metal is deposited on the upper surface of the source P+ region and the source N+ region to form a source electrode; and a metal is deposited on the lower surface of the substrate to form a drain electrode.

[0041] On the basis of the above technical solution, the present invention can also be improved as follows.

[0042] Furthermore, before forming the P-type oxide on the substrate layer, the method further includes:

[0043] An N-epitaxial layer is grown on an N+ substrate layer to obtain the base.

[0044] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0045] The wide bandgap semiconductor corner trench MOSFET device structure provided by the present invention is provided with a substrate, a P-well region, an N-pillar group, a source P+ region, a source N+ region, a gate, a source and a drain, wherein the P-well region is provided on the upper surface of the substrate, the N-pillar group is penetrated in the P-well region along a first direction, the lower end of the N-pillar group is connected to the upper surface of the substrate, the bottom of the gate is connected to the upper end of the N-pillar group, and the gate is embedded in the P-well region along the first direction, and a P-pillar can be formed in the middle of the N-pillar group. With this arrangement, a P-well region deeper than the gate trench can be constructed, so that the P-well region wraps around the trench corner of the gate trench, and a conductive channel is formed through the N-pillar group at the bottom of the gate, so that the P-pillars are interconnected through the P-well region and thus grounded.

[0046] Compared with the existing technology, the wide bandgap semiconductor corner trench MOSFET device structure has the following advantages:

[0047] First, the high electric field in the drift region of the wide-bandgap semiconductor material leads to a very high electric field on the gate dielectric layer. This problem is exacerbated at the trench corners, causing the gate dielectric layer to quickly breakdown under high drain voltage. Constructing a P-well region deeper than the trench so that the P-well region covers the trench corners can effectively reduce the electric field at the trench corners.

[0048] Second, existing MOSFET devices themselves do not have the ability to self-suppress surge voltage and overvoltage protection. When a surge voltage occurs, the N-column group provided by the present invention will completely deplete the region to increase the on-resistance and suppress the surge current.

[0049] Third, when charge balance is achieved between the N-pillar group and the P-well / P-pillar, a superjunction effect occurs, and the electric field in the N-pillar group can be evenly distributed, thereby increasing the breakdown voltage and reducing the on-resistance.

[0050] In summary, the wide bandgap semiconductor angled trench MOSFET device structure provided by the present invention can effectively improve the stability and reliability of device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A schematic diagram of the three-dimensional structure of a wide bandgap semiconductor angled trench MOSFET device structure provided in the first embodiment of the present invention;

[0052] Figure 2 A schematic cross-sectional view of a wide bandgap semiconductor angled trench MOSFET device structure at section A provided in the first embodiment of the present invention;

[0053] Figure 3 A schematic diagram of charge balance of a wide bandgap semiconductor angled trench MOSFET device structure provided in the first embodiment of the present invention;

[0054] Figure 4 A schematic diagram of the three-dimensional structure of a wide bandgap semiconductor angled trench MOSFET device structure provided in the second embodiment of the present invention;

[0055] Figure 5 A schematic cross-sectional structure diagram of a wide bandgap semiconductor angled trench MOSFET device structure at section A provided in the second embodiment of the present invention;

[0056] Figure 6 This is a schematic diagram of a connection structure of N pillars in different sections provided in the second embodiment of the present invention;

[0057] Figure 7 The second schematic diagram of the N-pillar connection structure in different sections provided by the second embodiment of the present invention;

[0058] Figure 8 The third schematic diagram of the N-pillar connection structure in different sections provided in the second embodiment of the present invention;

[0059] Figure 9 The fourth schematic diagram of the N-pillar connection structure in different sections provided in the second embodiment of the present invention;

[0060] Figure 10 The fifth schematic diagram of the N-pillar connection structure in different sections provided in the second embodiment of the present invention;

[0061] Figure 11 The sixth schematic diagram of the N-pillar connection structure of different sections provided in the second embodiment of the present invention;

[0062] Figure 12 A schematic diagram of the three-dimensional structure of a wide bandgap semiconductor angled trench MOSFET device structure provided in the third embodiment of the present invention;

[0063] Figure 13 A schematic cross-sectional structure diagram of a wide bandgap semiconductor angled trench MOSFET device structure at section A provided in the third embodiment of the present invention;

[0064] Figure 14 This is one of the schematic diagrams of the N-pillar connection structure in different sections provided in the third embodiment of the present invention;

[0065] Figure 15 This is the second schematic diagram of the N-pillar connection structure in different sections provided by the third embodiment of the present invention;

[0066] Figure 16 The third schematic diagram of the N-pillar connection structure in different sections provided by the third embodiment of the present invention;

[0067] Figure 17 This is a fourth schematic diagram of a connection structure of N pillars in different sections provided in the third embodiment of the present invention;

[0068] Figure 18 This is the fifth schematic diagram of the N-pillar connection structure of different sections provided in the third embodiment of the present invention;

[0069] Figure 19 This is a sixth schematic diagram of the N-pillar connection structure of different sections provided in the third embodiment of the present invention;

[0070] Figure 20 A schematic diagram of a method for manufacturing a wide bandgap semiconductor angled trench MOSFET device structure provided in a fourth embodiment of the present invention;

[0071] Reference numerals:

[0072] 1. Substrate; 101. N+ substrate layer; 102. N- epitaxial layer

[0073] 2. P-well region; 201. P-pillar;

[0074] 3. N-pillar group; 301. first N-pillar; 302. second N-pillar;

[0075] 4. Source P+ region;

[0076] 5. Source N+ region;

[0077] 6. Gate; 601. Gate dielectric layer; 602. Gate silicon; 603. Gate trench;

[0078] 7. Source;

[0079] 8. Drain;

[0080] 9. Interlayer dielectric layer;

[0081] 10. Diversion layer. DETAILED DESCRIPTION

[0082] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0083] SiC and GaN are third-generation wide-bandgap semiconductor materials. They have more advantages than Si in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. The power devices prepared from them, such as diodes, transistors, and power modules, have better electrical properties. They can overcome the defects of silicon-based materials that cannot meet the application requirements of high power, high voltage, high frequency, and high temperature. They are also one of the breakthrough paths that can surpass Moore's Law. Therefore, they are widely used in new energy fields (photovoltaic, energy storage, charging piles, electric vehicles, etc.).

[0084] Ultra-wide bandgap semiconductor materials with bandgap widths greater than those of SiC and GaN mainly include gallium oxide (Ga2O3), diamond (C), aluminum nitride (AlN), etc. Due to their superior optical and electrical properties, they have been considered an exciting and challenging new research field.

[0085] In power switch applications, Baliga's figure-of-merit (BFOM) is an indicator used to indicate the suitability of semiconductor materials for power electronics. It is expressed as: BFOM = εμE 3 , where ε is the dielectric constant, μ is the mobility, and E is the breakdown field strength of the semiconductor. The BFOM value is roughly positively correlated with the sixth power of the bandgap width Eg. Therefore, a larger bandgap width means that wide-bandgap semiconductors have lower power loss and higher conversion efficiency in power device applications, thus realizing more excellent and ideal power electronics applications.

[0086] Among wide-bandgap semiconductor materials, Ga2O3 boasts a bandgap of 4.8eV, an ideal breakdown electric field strength of 8MV / cm, and a BFOM value of 3400, approximately four times that of GaN and ten times that of SiC. Therefore, in today's power electronics applications, which demand higher power density and lower power consumption, Ga2O3 materials hold significant research significance and offer a broad market application prospect.

[0087] Among them, the ability to self-suppress surge voltage and overvoltage protection are important indicators for measuring the performance of MOSFET devices. However, trench MOSFETs made of wide-bandgap semiconductor materials do not themselves have the ability to self-suppress surge voltage and overvoltage protection. In practical applications, it is often necessary to design complex buffer circuits, surge voltage suppression circuits, and overvoltage protection circuits.

[0088] However, the external matching suppression and overvoltage protection circuits mentioned above often have time delays. The high-frequency spike voltage surges during the actual switching process are still borne by the device itself, which sometimes leads to breakdown failure in the device channel region and gradual failure of the gate structure and electrode ohmic contact area, causing device reliability problems.

[0089] The present invention provides a wide bandgap semiconductor angled trench MOSFET device structure that can effectively solve the above-mentioned problems. The embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0090] Example 1

[0091] like Figure 1 and Figure 2 As shown, the wide bandgap semiconductor angled trench MOSFET device structure provided in this embodiment consists of a substrate 1, a P-well region 2, an N-column group 3, a source P+ region 4, a source N+ region 5, a gate 6, a source 7 and a drain 8.

[0092] The substrate 1 includes an N+ substrate layer 101 and an N− epitaxial layer 102 ; the N− epitaxial layer 102 is disposed on the N+ substrate layer 101 .

[0093] The P-well region 2 is provided on the upper surface of the N- epitaxial layer 102 , and the drain 8 is provided on the lower surface of the N+ substrate layer 101 .

[0094] The P-well region 2 is provided on the upper surface of the substrate 1 . The N-column group 3 is provided through the P-well region 2 along a first direction. The lower end of the N-column group 3 is connected to the upper surface of the substrate 1 .

[0095] The bottom of the gate 6 is connected to the upper end of the N column group 3, and the gate 6 is embedded in the P well region 2 along the first direction. Figure 1 The width direction of the middle structure is the first direction.

[0096] The N-pillar group 3 includes a first N-pillar 301 and a second N-pillar 302 ; the first N-pillar 301 and the second N-pillar 302 are arranged at intervals along the second direction.

[0097] The second direction is perpendicular to the first direction. Figure 1 The length direction of the middle structure is the second direction.

[0098] The first N pillar 301 and the second N pillar 302 each include a plurality of N pillar segments, and the plurality of N pillar segments are arranged at intervals. Figure 1 As shown, in an optional example, the number of N-column segments can be 2, and the two N-column segments are separated by a certain distance. The distance between the two is not limited here and can be set according to actual needs.

[0099] Further, if Figure 1 As shown, both the source P+ region 4 and the source N+ region 5 are disposed on the upper surface of the P-well region 2, and multiple source P+ regions 4 and multiple source N+ regions 5 are sequentially spaced apart. The specific number and spacing of the source P+ regions 4 and source N+ regions 5 are not specifically limited herein and can be set according to actual needs. Various arrangements that can meet the functions of the present invention are within the scope of protection of the present invention.

[0100] The source 7 is provided on the upper surfaces of the source P+ region 4 and the source N+ region 5 , and the drain 8 is provided on the bottom of the substrate 1 .

[0101] Further, if Figure 1 As shown, the gate 6 includes a gate dielectric layer 601 , gate silicon 602 and a gate trench 603 .

[0102] like Figure 2 As shown, the gate trench 603 is U-shaped and extends along the first direction.

[0103] The gate dielectric layer 601 is disposed on the inner wall of the gate trench 603 ; the gate silicon 602 is filled in the middle of the gate trench 603 and is in contact with the gate dielectric layer 601 .

[0104] On the basis of the above embodiment, further, as Figure 1 As shown, the wide bandgap semiconductor angled trench MOSFET device structure also includes an interlayer dielectric layer 9, which covers the open opening of the gate trench 603, and the middle part of the interlayer dielectric layer 9 contacts the upper end surface of the gate dielectric layer 601 and the gate silicon 602, and the two ends thereof contact the source N+ region 5.

[0105] like Figure 1 As shown, there are multiple N-pillar groups 3; multiple N-pillar groups 3 are arranged in the P-well region 2 at intervals along the second direction; here, three N-pillar groups 3 are used as an example. Each N-pillar group 3 includes two N-pillars, and a P-pillar 201 is formed between the two N-pillars.

[0106] Correspondingly, the number of gates 6 and interlayer dielectric layers 9 is the same as the number of N column groups 3 , which is also 3, and they are all arranged in a one-to-one correspondence with the N column groups 3 .

[0107] The wide bandgap semiconductor angled trench MOSFET device structure provided by an embodiment of the present invention is provided with a substrate 1, a P-well region 2, an N-column group 3, a source P+ region 4, a source N+ region 5, a gate 6, a source 7 and a drain 8, wherein the P-well region 2 is provided on the upper surface of the substrate 1, the N-column group 3 is provided in the P-well region 2 along a first direction, the lower end of the N-column group 3 is connected to the upper surface of the substrate 1, the bottom of the gate 6 is connected to the upper end of the N-column group 3, and the gate 6 is embedded in the P-well region 2 along the first direction, and a P-column 201 can be formed in the middle of the N-column group 3. With such a setting, a P-well region 2 deeper than the gate trench 603 can be constructed, so that the P-well region 2 wraps the trench corner of the gate trench 603, and a conductive channel is formed through the N-column group 3 at the bottom of the gate 6, so that the P-column 201 is interconnected through the P-well region 2 and thus grounded.

[0108] Compared with existing technologies, Figure 3 The charge balance diagram of the wide bandgap semiconductor corner trench MOSFET device structure shown in FIG. The wide bandgap semiconductor corner trench MOSFET device structure has the following advantages:

[0109] First, the high electric field in the drift region of the wide-bandgap semiconductor material leads to a very high electric field on the gate dielectric layer. This problem is exacerbated at the trench corners, causing the gate dielectric layer to quickly break down under high drain voltages. Constructing a P-well region 2 deeper than the trench so that the P-well region 2 covers the trench corners can effectively reduce the electric field at the trench corners.

[0110] Second, existing MOSFET devices themselves do not have the ability to self-suppress surge voltage and overvoltage protection. When a surge voltage occurs, the N column group 3 provided in the embodiment of the present invention will completely deplete the region to increase the on-resistance and suppress the surge current.

[0111] Third, when charge balance is achieved between the N-pillar group 3 and the P-well / P-pillar 201 , a superjunction effect occurs, and the electric field in the N-pillar group 3 can be evenly distributed, thereby increasing the breakdown voltage and reducing the on-resistance.

[0112] In summary, the wide bandgap semiconductor angled trench MOSFET device structure provided by the embodiments of the present invention can effectively improve the stability and reliability of device performance.

[0113] Example 2

[0114] Based on the above embodiment 1, Figure 4 and Figure 5 As shown, the wide bandgap semiconductor angle trench MOSFET device structure further includes a guide layer 10 ; the guide layer 10 is provided between the gate trench 603 and the N column group 3 , and the width of the guide layer 10 along the second direction is smaller than the width of the gate trench 603 .

[0115] In a specific example, an N conductive layer 10 is added between the N pillars at the bottom of the trench. The N conductive layer 10 allows the conductive channels of the two N pillars to communicate with each other, further reducing the on-resistance. The trench width is defined as W1, and the conductive layer 10 width is defined as W2. When W1 is greater than W2, the structure is as follows: Figure 4 shown.

[0116] Based on the above structure, the arrangement of the N pillars, the guide layer 10, and the gate trench 603 can be as follows:

[0117] 1. A section of N pillars along the extending direction (first direction) of the gate trench 603 may have one or more guide layers 10, such as Figure 6 As shown, for example, two guide layers 10 are provided on any N column segment.

[0118] 2. Along the extending direction of the gate trench 603, the N pillars may be separated by a segment of N pillars or multiple segments of N pillars before the guide layer 10 is formed. Figure 7 As shown, there are three N-column sections, wherein the middle N-column section is not provided with the guide layer 10 , while the other two sections are provided with the guide layer 10 .

[0119] 3. N columns in different sections can also be connected through the guide layer 10, such as Figure 8 As shown, only the adjacent N column segments on one side are connected by the guide layer 10; Figure 9 As shown, the adjacent N column segments on both sides are connected by the guide layer 10; Figure 10 As shown, the N column segment on the left (upper position) is connected to the N column segment on the right (lower position) through the guide layer 10; Figure 11 As shown, the N column segments on the left are connected in an alternating manner with the N column segments on the right through the guide layer 10 .

[0120] Example 3

[0121] Based on the above embodiment 1, Figure 12 and Figure 13 As shown, the wide bandgap semiconductor corner trench MOSFET device structure further includes a guide layer 10; the guide layer 10 is disposed between the gate trench 603 and the N column group 3, and the width of the guide layer 10 along the second direction is greater than the width of the gate trench 603. The corners of the trench where the guide layer 10 is located are opened, which can further reduce the on-resistance.

[0122] In a specific example, an N conductive layer 10 is added between the N pillars at the bottom of the trench. The N conductive layer 10 allows the conductive channels of the two N pillars to communicate with each other, further reducing the on-resistance. The trench width is defined as W1, and the conductive layer 10 width is defined as W2. When W1 is smaller than W2, the structure is as follows: Figure 12 shown.

[0123] Based on the above structure, the arrangement of the N pillars, the guide layer 10, and the gate trench 603 can be as follows: (same as the arrangement in the above embodiment 2, only briefly described here, no further details are given)

[0124] 1. A section of N pillars along the extending direction (first direction) of the gate trench 603 may have one or more guide layers 10, such as Figure 14 shown.

[0125] 2. Along the extending direction of the gate trench 603, the N pillars may be separated by a segment of N pillars or multiple segments of N pillars before the guide layer 10 is formed. Figure 15 shown.

[0126] 3. N columns in different sections can also be connected through the guide layer 10, such as Figures 16-19 shown.

[0127] Example 4

[0128] The embodiment of the present invention also provides a method for manufacturing a wide bandgap semiconductor corner trench MOSFET device structure, such as Figure 20 As shown, including:

[0129] Step S1: growing an N- epitaxial layer on an N+ substrate layer to obtain a base.

[0130] Step S2: forming a P-type oxide on the N-epitaxial layer to obtain a P-well region.

[0131] Step S3: forming a source P+ region and a source N+ region on the P-well region.

[0132] Step S4: dry etching is performed on the P-well region, the source P+ region and the source N+ region to obtain a gate trench.

[0133] Step S5: performing ion implantation on the P-well region at the bottom of the gate trench to obtain an N-column group.

[0134] Step S6: gate dielectric growth, gate silicon growth and interlayer dielectric deposition are sequentially performed on the gate trench to obtain a gate.

[0135] Step S7: depositing metal on the upper surfaces of the source P+ region and the source N+ region to form a source; and depositing metal on the lower surface of the N+ substrate layer to form a drain.

[0136] Since this manufacturing method is used to manufacture a wide bandgap semiconductor angled trench MOSFET device structure, the beneficial effects of the wide bandgap semiconductor angled trench MOSFET device structure are also applicable to this manufacturing method. For its beneficial effects, please refer to Example 1 and will not be described in detail here.

[0137] Throughout this specification, reference to terms such as "specific examples" or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and integrate different embodiments or examples, and features of different embodiments or examples, described in this specification, unless otherwise mutually incompatible.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A wide bandgap semiconductor angle trench MOSFET device structure, characterized in that: include: substrate, P-well region, N-pillar group, source P+ region, source N+ region, gate, source and drain; The P-well region is provided on the upper surface of the substrate, the N-pillar group is provided through the P-well region along a first direction, and the lower end of the N-pillar group is connected to the upper surface of the substrate; the width direction of the device structure is defined as the first direction; The bottom of the gate is connected to the upper end of the N column group, and the gate is embedded in the P well region along the first direction; The source P+ region and the source N+ region are both provided on the upper surface of the P-well region, and the source P+ region and the source N+ region are arranged in sequence and spaced apart; The source is provided on the upper surface of the source P+ region and the source N+ region, and the drain is provided on the bottom of the substrate; The gate comprises a gate dielectric layer, gate silicon and a gate trench; The gate trench is U-shaped and extends along the first direction; The gate dielectric layer is provided on the inner wall side of the gate trench; the gate silicon is filled in the middle of the gate trench and contacts the gate dielectric layer; The wide bandgap semiconductor corner trench MOSFET device structure further includes an interlayer dielectric layer; The interlayer dielectric layer is covered at the opening of the gate trench, and its middle portion contacts the gate dielectric layer and the upper end surface of the gate silicon, and its two ends contact the source N+ region; The N-pillar group includes a first N-pillar and a second N-pillar; The first N pillars and the second N pillars are spaced apart along a second direction, and a P-well region is formed between the first N pillars and the second N pillars; a length direction of the device structure is defined as the second direction; wherein the second direction is arranged perpendicular to the first direction; The first N pillars and the second N pillars each include a plurality of N pillar segments, and the plurality of N pillar segments are arranged at intervals; There are a plurality of N column groups; the plurality of N column groups are spaced apart in the P well region along the second direction; The number of the gates and the interlayer dielectric layers is the same as the number of the N column groups, and the gates and the interlayer dielectric layers are arranged corresponding to the N column groups.

2. The wide bandgap semiconductor angle trench MOSFET device structure according to claim 1, characterized in that: The wide bandgap semiconductor angled trench MOSFET device structure further includes a guide layer; the guide layer is provided between the gate trench and the N column group; The width of the guide layer along the second direction is smaller than the width of the gate trench; or the width of the guide layer along the second direction is larger than the width of the gate trench.

3. The wide bandgap semiconductor angle trench MOSFET device structure according to claim 1, characterized in that: The substrate includes an N+ substrate layer and an N- epitaxial layer; The N- epitaxial layer is provided on the N+ substrate layer; The P-well region is arranged on the upper surface of the N- epitaxial layer, and the drain is arranged on the lower surface of the N+ substrate layer.

4. A method for manufacturing a wide bandgap semiconductor angle trench MOSFET device structure according to any one of claims 1 to 3, characterized in that: include: forming a P-type oxide on the substrate to obtain a P-well region; Fabricating a source P+ region and a source N+ region on the P-well region; Performing dry etching on the P-well region, the source P+ region, and the source N+ region to obtain a gate trench; An N column group is obtained by performing ion implantation on the P-well region at the bottom of the gate trench; performing gate dielectric growth, gate silicon growth, and interlayer dielectric deposition in sequence on the gate trench to obtain a gate; A metal is deposited on the upper surface of the source P+ region and the source N+ region to form a source electrode; and a metal is deposited on the lower surface of the substrate to form a drain electrode.

5. The production method according to claim 4, characterized in that: Before making P-type oxide on the substrate, it also includes: An N-epitaxial layer is grown on an N+ substrate layer to obtain the base.

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