A topcon cell structure with double poly-silicon layers and a preparation method thereof
By employing a double polycrystalline silicon layer structure and selective epitaxial growth technology on the back of the TOPCon cell, the problems of recombination current in the metal contact area and photoparasitic absorption in the non-metallic area were solved, achieving low recombination current and high efficiency cell performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHUZHOU JIETAI NEW ENERGY TECH CO LTD
- Filing Date
- 2023-05-29
- Publication Date
- 2026-06-02
AI Technical Summary
In existing TOPCon batteries, it is difficult to balance the thickness and concentration of the polycrystalline silicon doped layer in the metal contact area, which leads to damage to the interface oxide layer, high recombination current, and high contact resistance. At the same time, severe photoparasitic absorption in the non-metallic area affects the battery efficiency.
A dual polycrystalline silicon layer structure is adopted, with a first doped polycrystalline silicon layer on the back and a second doped polycrystalline silicon layer located between the metal electrode and the first doped polycrystalline silicon layer. By combining laser film opening and chemical vapor deposition technology, the second doped polycrystalline silicon layer is locally selectively epitaxially grown to ensure low recombination current in the metal region and low photoparasitic absorption in the non-metal region.
It effectively shields against slurry penetration, reduces the risk of interface oxide layer damage, decreases recombination current and contact resistance, improves battery open-circuit voltage and short-circuit current, and enhances battery efficiency.
Smart Images
Figure CN116504858B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of battery processing technology, specifically to a TOPCon battery structure with two polycrystalline silicon layers and its preparation method. Background Technology
[0002] Existing TOPCon (tunneling oxide passivated contact) solar cells typically consist of a 1-2 nm ultrathin tunneling oxide layer fabricated on the back side of a silicon wafer, followed by the deposition of an 80-200 nm thick doped polycrystalline silicon layer on the oxide layer surface, and finally, silicon nitride deposited on the doped polycrystalline silicon layer. This structure provides excellent surface and field passivation for the back side of the silicon wafer. The ultrathin oxide layer allows electrons to tunnel into the polycrystalline silicon layer while blocking hole transport, reducing recombination current. The lateral transport characteristics of the doped polycrystalline silicon layer reduce series resistance. These two characteristics together improve the cell's open-circuit voltage, fill factor, and conversion efficiency.
[0003] TOPCon cells typically use Ag paste to burn through SiN on the back. x The dielectric film forms an ohmic contact with the doped polysilicon. During the sintering process, metallic Ag grains may penetrate the doped polysilicon film, disrupting the passivation effect of the interface oxide layer. To reduce the recombination current density in the metal contact region, a sufficient thickness of doped polysilicon is required, typically 100-150 nm. To ensure good field passivation and low ohmic contact, the doped polysilicon needs a sufficient doping concentration, typically >1e20 cm⁻¹. -3 On the other hand, excessively thick or concentrated doped polysilicon films can lead to short-circuit current losses in TOPCon cells due to free carrier absorption (FCA) of long-wavelength light. Simultaneously, parasitic absorption of back-incident light by doped polysilicon reduces the cell's bifaciality. Balancing polysilicon film thickness and doping concentration with recombination, resistive losses, and optical losses is typically difficult. Currently, efforts are mainly focused on minimizing the polysilicon film thickness while ensuring the metal electrode paste does not burn through the tunneling oxide layer and that good ohmic contact is formed between the metal electrode and the polysilicon film, thus reducing parasitic absorption of photons within the highly doped polysilicon layer. Alternatively, the aforementioned passivation structure can be used only in the metal electrode region of the cell, but this approach struggles to balance light absorption and passivation effects. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention provides a TOPCon battery structure with a double polycrystalline silicon layer and its fabrication method. This structure can ensure the thickness of the doped polycrystalline silicon in the metal contact area, prevent the tunneling oxide layer from being damaged during the slurry sintering process, and reduce recombination current and contact resistance. At the same time, it can reduce photoparasitic absorption in the non-metallic region, especially the absorption of free carriers.
[0005] To achieve the above objectives, the technical solution of the present invention is implemented through the following technical solution:
[0006] A TOPCon solar cell structure with two polycrystalline silicon layers includes a monocrystalline silicon wafer, a diffusion layer, a passivation layer, a front antireflection layer, and a front metal electrode sequentially disposed on the front side of the monocrystalline silicon wafer, and a tunneling layer, a doped polycrystalline silicon layer, a back antireflection layer, and a back metal electrode sequentially disposed on the back side of the monocrystalline silicon wafer. The doped polycrystalline silicon layer includes a first doped polycrystalline silicon layer located on the back side and a second doped polycrystalline silicon layer located between the first doped polycrystalline silicon layer and the back metal electrode; the first doped polycrystalline silicon layer is a phosphorus-doped polycrystalline silicon layer with a thickness of 30-80 nm and a doping concentration not exceeding 1e20 cm⁻¹. -3 The second doped polycrystalline silicon layer is a phosphorus-doped polycrystalline silicon layer with a thickness of 50-150 nm and a doping concentration of 1e20 to 1e21 cm⁻¹. -3 Its concentration is higher than that of the first doped polycrystalline silicon layer.
[0007] Preferably, the single-crystal silicon wafer is a phosphorus-doped N-type single-crystal silicon wafer with a resistivity of 0.1-10 Ω·cm and a thickness of 100-200 μm.
[0008] Preferably, the diffusion layer is a boron-doped P-type layer with a sheet resistance of 100-300 Ω / □.
[0009] Preferably, the passivation layer is aluminum oxide with a thickness of 2-6 nm.
[0010] Preferably, the front antireflection layer and the back antireflection layer are composite films composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.1.
[0011] Preferably, the front metal electrode is an Ag / Al gate electrode, and the back metal electrode is an Ag gate electrode.
[0012] Preferably, the tunneling layer is silicon oxide with a thickness of 1-3 nm.
[0013] The fabrication method of TOPCon batteries includes the following steps:
[0014] S1. Texturing: Using acid and alkali chemicals, organic contaminants and metallic impurities on the surface of silicon wafers are removed, and a surface texture is formed on the surface of silicon wafers to increase the absorption of sunlight and reduce reflection.
[0015] S2, Boron diffusion: forms a front-side PN junction;
[0016] S3, BSG: Single-sided HF etching to remove BSG on the back side;
[0017] S4. Backside etching: Removes the PN junction formed by parasitic diffusion on the backside to prevent edge leakage;
[0018] S5, LPCVD: In-situ oxidation to generate a tunneling oxide layer and deposit an intrinsic amorphous silicon layer;
[0019] S6, Phosphorus diffusion: Phosphorus diffusion doping is performed on the back amorphous silicon and amorphous silicon oxide, and they are transformed from the amorphous state to the crystalline state to form the first doped polycrystalline silicon layer;
[0020] S7, PSG: Single-sided HF etching to remove PSG on the front side of the polysilicon surface after diffusion;
[0021] S8. Front etching: The polysilicon layer is removed by etching with an alkaline solution, and the BSG on the front side and the PSG on the back side are removed by cleaning with hydrofluoric acid.
[0022] S9, CVD mask: A layer of SiN is grown on the back side using chemical vapor deposition. X Masking; SiH4 and NH3 are introduced to form a solid film with a thickness of 10-25 nm on the sample surface;
[0023] S10, LCO: SiN under the back metal area is exposed using laser film cutting. X The mask barrier layer is etched to create grooves, leaving a thin silicon oxide layer on the surface of the first doped polysilicon at the groove location;
[0024] S11, HF cleaning: HF cleaning is used to remove the silicon oxide layer on the surface of the first doped polysilicon at the groove.
[0025] S12, Selective Poly Epitaxial Deposition on the Back Side: A second doped polysilicon layer is selectively grown on the first doped polysilicon surface at the SiNx trench using chemical vapor deposition; S13, Mask Removal and Cleaning: The SiNx mask layer on the silicon wafer surface is removed using wet chemical methods, and the silicon wafer surface is cleaned.
[0026] S14. A dense AlO layer is deposited on the front side of the substrate using ALD atomic layer deposition. x film;
[0027] S15, Front-side PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the front side of the substrate by PECVD;
[0028] S16, Backside PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the backside of a substrate by PECVD;
[0029] S17, Printing / Sintering / Photoinjection: The front side is printed with negative electrode Ag / Al paste, and the back side is printed with electrode Ag paste; co-sintering is performed to form good ohmic contact; photoinjection is used to repair defects in the cell body and on the surface.
[0030] Preferably, the chemical vapor deposition process in step S12 is carried out under conditions of pressure <100 Torr and temperature 850-950℃. During the deposition process, H2 is used as the carrier gas and SiH2Cl2 is used as the silicon precursor. PH3 gas is introduced to perform in-situ doping of the epitaxial second polycrystalline silicon layer. The HCl formed during the reaction can etch the silicon on the PECVD SiOx surface to maintain selective epitaxy. Additional HCl can also be introduced during the reaction as an etching source. The specific process includes: ① heating to the epitaxial deposition temperature; ② H2 baking; ③ selective silicon deposition; ④ cooling.
[0031] H2 baking is a critical process step that must be kept at the same temperature as subsequent deposition. This allows the natural oxide layer on the silicon surface to be effectively removed through H2 reduction, ensuring the quality of epitaxial layer growth.
[0032] This invention provides a TOPCon cell structure with two polycrystalline silicon layers and its fabrication method, which has the following advantages compared with the prior art:
[0033] (1) In this invention, a first doped polycrystalline silicon layer and a second doped polycrystalline silicon layer located between the metal electrode and the first doped polycrystalline silicon layer are used on the back side of the N-type monocrystalline silicon wafer to form a composite polycrystalline silicon layer in the metal region. The thickness of the composite polycrystalline silicon layer is greater than that of the first doped polycrystalline silicon layer in the non-metal region. This can effectively shield the penetration of the slurry during sintering and prevent the interface tunneling oxide layer from being damaged, thereby ensuring that the metal contact area has a low composite current. Since the second doped polycrystalline silicon has a high doping concentration, it can ensure that the metal contact area has a low contact resistance. The non-metal region only has the first doped polycrystalline silicon layer, which is thin and has a low concentration. This can reduce the photoparasitic absorption of the doped polycrystalline silicon layer in the non-metal region and improve the short-circuit current of the battery. Therefore, the battery efficiency can be effectively improved.
[0034] (2) This invention uses laser film-opening method to open the SiN back metal area. X The mask barrier layer is etched and grooved to open the SiN. X A mask layer is used to expose polycrystalline silicon, and then local selective epitaxial growth of the doped polycrystalline silicon layer is achieved by chemical vapor deposition (CVD). The preparation method is simple and easy to implement. Attached image description:
[0035] Figure 1 This is a flowchart of the TOPCon battery manufacturing process of the present invention;
[0036] Figure 2This is a structural diagram of the TOPCon battery of the present invention;
[0037] Figure 3 Here is a diagram of the existing TOPCon battery structure;
[0038] In the figure: 1. Monocrystalline silicon wafer; 2. Diffusion layer; 3. Passivation layer; 4. Front antireflection layer; 5. Front metal electrode; 6. Tunneling layer; 7. Doped polycrystalline silicon layer; 7-1. First doped polycrystalline silicon layer; 7-2. Second doped polycrystalline silicon layer; 8. Back antireflection layer; 9. Back metal electrode. Detailed Implementation
[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0040] Example 1:
[0041] Fabrication of a TOPCon battery:
[0042] S1. Texturing: Select phosphorus-doped N-type single crystal silicon wafers with a resistivity of 1.0 Ωcm and a thickness of 160 μm; use acid and alkali chemicals to remove organic contaminants and metallic impurities from the silicon wafer surface, forming a surface texture on the silicon wafer surface to increase the absorption of sunlight and reduce reflection.
[0043] S2, Boron diffusion: A front-side PN junction is formed by low-pressure diffusion of BCl3, with a diffusion temperature of 1000℃ and a sheet resistance of 200Ω / □.
[0044] S3, BSG: Single-sided HF etching to remove BSG on the back side;
[0045] S4. Backside etching: Alkaline solution is used for etching to remove the PN junction formed by parasitic diffusion on the backside and prevent edge leakage.
[0046] S5, LPCVD: In-situ oxidation using LPCVD is employed to generate a tunneling oxide layer at a temperature of 600℃ and a thickness of 1.5nm, and an intrinsic amorphous silicon layer with a thickness of 50nm is deposited.
[0047] S6. Phosphorus Diffusion: Using POCl3 as the diffusion source, phosphorus diffusion doping is performed on the back-side amorphous silicon at a diffusion temperature of 850℃, transforming it from an amorphous state to a crystalline state to form the first doped polycrystalline silicon layer, with a doping concentration of 1e20cm⁻¹. -3 ;
[0048] S7, PSG: Single-sided HF etching to remove PSG on the front side of the polysilicon surface after diffusion;
[0049] S8. Front etching: The polysilicon layer is removed by etching with an alkaline solution, and the BSG on the front side and the PSG on the back side are removed by cleaning with hydrofluoric acid.
[0050] S9, CVD mask: A layer of SiN is grown on the back side using chemical vapor deposition (CVD). X Masking; introducing appropriate amounts of SiH4 and NH3, and through a series of chemical and plasma reactions, forming a solid film (SiNx) on the sample surface; its thickness is 20 nm, preparing for subsequent backside poly selective epitaxial deposition;
[0051] S10, LCO: SiN under the back metal area is exposed using laser film cutting. X The purpose of etching grooves into the mask barrier layer is to open up the SiN. X The mask layer exposes the polysilicon, preparing it for the subsequent growth of the silicon epitaxial layer;
[0052] S11, HF Cleaning: Because step S10 uses laser film opening to open the SiN... X The mask layer leaves a thin silicon oxide layer on the surface of the first doped polysilicon layer below the back metal region of the trench; the silicon oxide layer on the surface of the first doped polysilicon layer below the back metal region is removed by HF cleaning.
[0053] S12. Backside Poly Selective Epitaxial Deposition: Silicon epitaxial growth was achieved in a single-wafer batch reactor via chemical vapor deposition (CVD). The process was carried out under reduced pressure (100 Torr) and at a temperature of 900°C, using dichlorosilane (SiH2Cl2) as the silicon source and hydrogen (H2) as the carrier gas. PH3 was used as the doping gas, and the growth layer was a phosphorus-doped second-doped polycrystalline silicon layer with a doping concentration of 1e21cm. -3 The thickness is 100 nm; the epitaxial growth of silicon on the crystalline material is influenced by the surface chemical potential, therefore the second doped polycrystalline silicon layer only grows in the bare silicon region, and the interface is covered by SiN. X No epitaxial deposition occurred on the back surface "covered" by the mask layer.
[0054] S13, Mask Removal and Cleaning: Due to the presence of a layer of SiN in the back metal area. X The SiNx mask layer is removed from the silicon wafer surface using a wet chemical method, and the silicon wafer surface is then cleaned.
[0055] S14, ALD: A dense AlO layer is deposited on the front side of the substrate using ALD atomic layer deposition. x film;
[0056] S15, Front-side PECVD: Deposit a silicon oxynitride stacked film on the front side of the substrate using PECVD;
[0057] S16, Backside PECVD: Deposit a silicon oxynitride stacked film on the backside of the substrate using PECVD;
[0058] S17, Printing / Sintering / Photoinjection: The front side is printed with negative electrode Ag / Al paste, and the back side is printed with electrode Ag paste; co-sintering is performed to form good ohmic contact; photoinjection is used to repair defects in the cell body and on the surface.
[0059] The specific TOPCon battery structure is as follows: Figure 2 As shown: It includes a monocrystalline silicon wafer 1, a diffusion layer 2, a passivation layer 3, a front antireflection layer 4 and a front metal electrode 5 sequentially disposed on the front side of the monocrystalline silicon wafer 1, and a tunneling layer 6, a doped polycrystalline silicon layer 7, a back antireflection layer 8 and a back metal electrode 9 sequentially disposed on the back side of the monocrystalline silicon wafer 1; the doped polycrystalline silicon layer 7 includes a first doped polycrystalline silicon layer 7-1 located on the back side of the silicon wafer and a second doped polycrystalline silicon layer 7-2 located between the first doped polycrystalline silicon layer 7-1 and the back metal electrode 9.
[0060] Comparative Example 1:
[0061] As a comparative example of the TOPCon battery, see attached Figure 3 As shown, compared with Example 1, the difference is that the back side of the silicon wafer uses single-doped polycrystalline silicon with a thickness of 130 nm and a doping concentration of 2-3e20cm. -3 .
[0062] Detection:
[0063] The electrical performance parameters of the TOPCon batteries in Example 1 and Comparative Example 1 are shown in the table below:
[0064]
[0065] Comparing the TOPCon cells prepared in Example 1 and Comparative Example 1, it can be seen that Example 1 uses the cell structure and preparation method provided in this application. By using a first doped polycrystalline silicon layer 7-1 and a second doped polycrystalline silicon layer 7-2 located between the metal electrode and the first doped polycrystalline silicon layer 7-1 on the back of the N-type monocrystalline silicon wafer, a composite polycrystalline silicon layer is formed in the metal region. Its thickness is greater than that of the first doped polycrystalline silicon layer 7-1 in the non-metal region. This can effectively shield the penetration of slurry during sintering and prevent the interface tunneling oxide layer from being damaged, thereby ensuring that the metal contact area has a lower recombination current and obtaining a higher open-circuit voltage of the cell. Since the second doped polycrystalline silicon layer 7-2 has a high doping concentration, it can ensure that the metal contact area has a lower contact resistance and obtain a larger fill factor. The non-metal region only has the first doped polycrystalline silicon layer 7-1, which is thinner and has a lower concentration. This can reduce the photoparasitic absorption of the doped polycrystalline silicon layer in the non-metal region and improve the short-circuit current of the cell.
[0066] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0067] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A TOPCon cell structure with two polycrystalline silicon layers, comprising a monocrystalline silicon wafer (1), a diffusion layer (2), a passivation layer (3), a front antireflection layer (4), and a front metal electrode (5) sequentially disposed on the front side of the monocrystalline silicon wafer (1), and a tunneling layer (6), a doped polycrystalline silicon layer (7), a back antireflection layer (8), and a back metal electrode (9) sequentially disposed on the back side of the monocrystalline silicon wafer (1), characterized in that, The doped polysilicon layer (7) includes a first doped polysilicon layer (7-1) located on the back side and a second doped polysilicon layer (7-2) located between the first doped polysilicon layer (7-1) and the back metal electrode (9). The first doped polycrystalline silicon layer (7-1) is a phosphorus-doped polycrystalline silicon layer with a thickness of 30-80 nm and a doping concentration not exceeding 1e20 cm⁻¹. -3 The second doped polycrystalline silicon layer (7-2) is a phosphorus-doped polycrystalline silicon layer with a thickness of 50-150 nm and a doping concentration of 1e20~1e21 cm⁻¹. -3 Its concentration is higher than that of the first doped polysilicon layer (7-1). The method for fabricating the TOPCon solar cell with dual polycrystalline silicon layers includes the following steps: S1. Texturing: Using acid and alkali chemicals, organic contaminants and metallic impurities on the surface of silicon wafers are removed, and a surface texture is formed on the surface of silicon wafers to increase the absorption of sunlight and reduce reflection. S2, Boron diffusion: forms a front-side PN junction; S3, BSG: Single-sided HF etching to remove BSG on the back side; S4. Backside etching: Removes the PN junction formed by parasitic diffusion on the backside to prevent edge leakage; S5, LPCVD: In-situ oxidation to generate a tunneling oxide layer and deposit an intrinsic amorphous silicon layer; S6, Phosphorus diffusion: Phosphorus diffusion doping is performed on the back amorphous silicon and amorphous silicon oxide to transform them from an amorphous state to a crystalline state; S7, PSG: Single-sided HF etching to remove PSG on the front side of the polysilicon surface after diffusion; S8. Front etching: The polysilicon layer is removed by etching with an alkaline solution, and the BSG on the front side and the PSG on the back side are removed by cleaning with hydrofluoric acid. S9, CVD mask: A SiNX mask is grown on the back side using chemical vapor deposition; SiH4 and NH3 are introduced to form a solid film with a thickness of 10-25nm on the sample surface; S10, LCO: The SiNX mask barrier layer under the back metal area is etched and grooved using laser etching, leaving a thin silicon oxide layer under the grooved back metal area. S11, HF cleaning: HF cleaning is used to remove the silicon oxide layer under the metal area on the back side; S12, Backside Poly Selective Epitaxial Deposition: A second doped polysilicon layer is selectively epitaxially grown on the first doped polysilicon surface at the SiNx trench using chemical vapor deposition. S13. Mask Removal and Cleaning: The SiNx mask layer on the surface of the silicon wafer is removed using a wet chemical method, and the surface of the silicon wafer is then cleaned. S14. A dense AlOx film is deposited on the front side of the substrate using ALD atomic layer deposition. S15, Front-side PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the front side of the substrate by PECVD; S16, Backside PECVD: Depositing one or more stacked films of silicon nitride and silicon oxynitride on the backside of a substrate by PECVD; S17, Printing / Sintering / Photoinjection: Front side is printed with negative electrode Ag / Al paste, back side is printed with electrode Ag paste; co-sintering is performed to form good ohmic contact; photoinjection is used to repair defects in the cell body and surface. The chemical vapor deposition method described in step S12 is carried out under conditions of pressure <100 Torr and temperature 850-950℃. During the deposition process, H2 is used as the carrier gas and SiH2Cl2 is used as the silicon precursor. PH3 doping gas is introduced, and HCl formed during the reaction is used as the etching gas. The specific process includes: ① heating to the epitaxial deposition temperature; ② H2 baking; ③ selective silicon deposition; ④ cooling.
2. The TOPCon cell structure with two polycrystalline silicon layers according to claim 1, characterized in that: The single-crystal silicon wafer (1) is a phosphorus-doped N-type single-crystal silicon wafer with a resistivity of 0.1-10Ω▪cm and a thickness of 100-200um.
3. The TOPCon cell structure with two polycrystalline silicon layers according to claim 1, characterized in that: The diffusion layer (2) is a boron-doped P-type doped layer with a sheet resistance of 100-300Ω / □.
4. The TOPCon cell structure with two polycrystalline silicon layers according to claim 1, characterized in that: The passivation layer (3) is aluminum oxide with a thickness of 2-6 nm.
5. The TOPCon cell structure with two polycrystalline silicon layers according to claim 1, characterized in that: The front antireflective layer (4) and the back antireflective layer (8) are both composite films composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a total thickness of 70-120 nm and a comprehensive refractive index of 1.9-2.
1.
6. The TOPCon cell structure with two polycrystalline silicon layers according to claim 1, characterized in that: The front metal electrode (5) is an Ag / Al gate electrode, and the back metal electrode (9) is an Ag gate electrode.
7. The TOPCon cell structure with two polycrystalline silicon layers according to claim 1, characterized in that: The tunneling layer (6) is silicon oxide with a thickness of 1-3 nm.