Identify uncorrectable errors using error pattern analysis

Abstract

Techniques are described for identifying patterns of memory cells in a memory array that are indicative of uncorrectable errors ("corruption patterns"). The techniques described herein identify patterns of cell errors that may generate errors that cannot be corrected by error correction codes (ECC). Identification of uncorrectable cells is accomplished by identifying patterns of cell errors that store bit values ​​that deviate from corresponding expected values. These patterns of memory cells and various combinations of cells in the pattern are compared to patterns of cells that are known to be correctable using ECC. If one or more of the error patterns or combinations of cells in the pattern that have errors do not correlate with patterns that can be corrected via ECC, then the error pattern is identified as indicative of errors that may be uncorrectable.

Description

Technical Field

[0001] The present disclosure relates to detecting errors in memory devices. In particular, the present disclosure relates to pattern-based identification of uncorrectable memory errors in memory devices. Background Art

[0002] Dynamic random access memory (DRAM) is generally composed of a regular array of memory cells (e.g., deep trench capacitors), each of which stores a charge state indicating that a single data bit is either "1" or "0." A single DRAM device (i.e., an integrated circuit die of an electronic package) may include millions or billions of individual cells. The individual cells within each device may be arranged in a hierarchy of cell blocks.

[0003] In some cases, the charge state stored in the memory cell is inadvertently switched from the stored (written) state to an erroneous state different from the stored state, thereby inadvertently generating an erroneous bit value in the cell. These so-called "soft errors" can be caused by the encounter between the memory cell and the cosmic origin particles, the natural radiation generated by the decay of the materials used in the manufacture of the electronic device, and the like. A processor communicating with the memory device can execute an error correction code (ECC) algorithm that uses metadata stored in the memory device to identify errors in the corresponding stored data. For example, an ECC algorithm can identify a cell in a memory area that stores a bit value different from the bit value originally written to the cell. Some errors are correctable because various techniques can be used to restore the written value to the memory cell. Other errors are uncorrectable.

[0004] The approaches described in this section are approaches that could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their inclusion in this section. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In the figures of the accompanying drawings, embodiments are illustrated by way of example and not by way of limitation. It should be noted that reference to "one" or "an" embodiment in the present disclosure does not necessarily refer to the same embodiment, but to at least one. In the drawings:

[0006] Figure 1A illustrates a system according to one or more embodiments;

[0007] Figure 1B illustrates an example memory region including a memory block comprised of an array of individual memory cells according to one or more embodiments;

[0008] Figure 2illustrates an example set of operations for detecting uncorrectable memory errors by comparing a subset of erroneous memory cells to a pattern of correctable memory errors in accordance with one or more embodiments;

[0009] Figure 3 illustrates a relationship between a set of combinations of potential corruption modes and a set of correctable error modes that satisfy a vulnerability criterion for a memory region in accordance with one or more embodiments;

[0010] Figure 4 illustrates an example set of operations for detecting uncorrectable memory errors by comparing a subset of erroneous memory cells to a pattern of uncorrectable memory errors in accordance with one or more embodiments;

[0011] Figure 5 illustrates a minimum overlap between a set of combinations of potential corruption modes and a set of uncorrectable error modes required to satisfy a vulnerability criterion for a memory region in accordance with one or more embodiments;

[0012] Figure 6 illustrates an example region of a memory in which individual memory cells are marked to indicate whether their corresponding stored bit values ​​deviate from expected values ​​or are correct in accordance with one or more embodiments;

[0013] Figure 7 The present invention is based on one or more embodiments. Figure 6 A subset of combinations of individually faulty memory cells of the error pattern of the memory area shown in (latent damage pattern);

[0014] Fig. 8A The diagram shows Figure 6 an uncorrectable error pattern associated with the memory region shown in , as determined by analysis of a corresponding error correction code;

[0015] Figure 8B The present invention illustrates a method according to one or more embodiments. Figure 7 The subset of potential error modes shown in Fig. 8A The similarity criterion for the uncorrectable error patterns shown in ; and

[0016] Fig. 9 A block diagram illustrating a computer system in accordance with one or more embodiments is shown. DETAILED DESCRIPTION

[0017] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding. One or more embodiments may be practiced without these specific details. Features described in one embodiment may be combined with features described in different embodiments. In some examples, well-known structures and devices are described with reference to block diagram form to avoid unnecessary confusion of the present invention.

[0018] 1. General Overview

[0019] 2. System architecture

[0020] 3. Memory device structure and error correction code

[0021] 4. Use error pattern analysis to predict uncorrectable errors

[0022] 4.1 Comparison of Predicting Uncorrectable Errors Using Correctable Corruption Patterns

[0023] 4.2 Predicting Uncorrectable Errors Using Uncorrectable Corruption Pattern Comparison

[0024] 5. Example Embodiments

[0025] 6. Computer Networks and Cloud Networks

[0026] 7. Other Matters; Extension

[0027] 8. Hardware Overview

[0028] 1. General Overview

[0029] One or more embodiments include techniques for identifying patterns of memory cells associated with uncorrectable errors in a memory array. While conventional techniques use a total memory cell error count or an error count rate to identify uncorrectable errors, the techniques described herein instead identify patterns of memory cell errors (i.e., a group of one or more memory cells storing bit values ​​that deviate from the expected or written bit values) that are unlikely to be corrected (e.g., using an error correction code (ECC)) or that are correctable but associated with a pattern that may generate uncorrectable errors in the future. The system first identifies an initial pattern of memory cells with errors in a memory region. The system generates additional patterns formed by various combinations of cells included in the initial pattern. The initial pattern and the additional pattern are collectively referred to as potential damage patterns. The system compares potential damage patterns with cell patterns known to be correctable using ECC. If all potential damage patterns (equivalent term "error patterns") are determined to be correctable using ECC, no further action is required except for performing ECC to correct the erroneous bits. However, if one or more of the combinations of erroneous cells associated with the corruption pattern are not associated with an ECC correctable pattern, then the system determines that the memory array (or region of memory having erroneous cells) meets the vulnerability criteria for data corruption associated with an uncorrectable error pattern.

[0030] One or more embodiments described in this specification and / or set forth in the claims may not be included in this general summary section.

[0031] 2. System architecture

[0032] Figure 1A A memory management system 100 is illustrated in accordance with one or more embodiments. In the illustrated embodiment, the memory management system 100 includes a memory module 102, a memory management engine 128, and a data repository 164. In one or more embodiments, the system 100 may include a memory module 102, a memory management engine 128, and a data repository 164. Figure 1A There are more components than shown in the . Figure 1A The components shown in FIG. 1 may be local or remote from other components used by system 100 . Figure 1A The components shown in the figure can be implemented in software and / or hardware and can be distributed on one or more applications and / or machines. Figure 1A The operations described by the components shown in FIG. 1 may be performed alternatively by one or more other components.

[0033] The memory module 102 may include any type of memory type, whether DRAM, SRAM, or magnetic memory type. The examples described below are presented in the context of DRAM memory, but the embodiments described herein are applicable to any other memory type that may use error correction codes. The memory module 102 may include one or more memory regions, which are described below. Figure 1B 102 is described in the context of . In some examples, the memory module 102 includes a plurality of interconnected memory devices. For example, the memory module 102 may include a plurality of DRAM devices mounted on a substrate (i.e., DRAM dies of an electronic package). Common configurations of memory modules are single in-line memory modules (SIMMs) or dual in-line memory modules (DIMMs). Although the memory module 102 is used in the following explanation, it will be appreciated that these techniques are applicable to memory areas of any size or configuration, whether a single memory group (e.g., a region within a DRAM die), an entire DRAM die, some or all of a DRAM SIMM or DIMM, or a group of many SIMMs or DIMMs. The term "region" as used herein applies to any of these memory component levels.

[0034] The memory management engine 128 may identify one or more memory cells in the memory module 102 that store bit values ​​that deviate from expected bit values ​​(i.e., erroneous memory cells). The memory management engine 128 may also determine whether the erroneous cells form a pattern that can be corrected using error correction code (ECC).

[0035] The memory management engine 128 includes a memory cell error detector 132 , a potential error pattern generator 136 , a processor 140 , an error correction code repository 144 , a pattern comparison engine 156 , and a remediation engine 160 .

[0036] The memory cell error detector 132 may use metadata stored in the memory module 102 along with the error correction codes stored in the error correction code repository 144 to detect erroneous memory cells in the memory module 102. Once detected, the memory cell error detector 132 may pass the erroneous cell address and / or the correct cell address to the potential error pattern generator 136.

[0037] The potential error pattern generator 136 generates mathematical combinations of memory cells in which errors have been detected (using only the cells with errors once in each combination), thereby generating a plurality of potential error patterns. As described below, the potential error patterns are generated in preparation for comparison with patterns that are known to be uncorrectable using ECC. Because the memory cells are assumed to operate independently of each other and because memory cells that exhibit current errors are assumed to be more likely to exhibit errors in the future, the generation of these patterns predicts possible future error patterns.

[0038] The processor 140 can communicate with an error correction code memory 144 storing one or more error correction codes. The processor 140 can communicate with the error correction code storage library 144 and use the stored error correction code to generate a representation of one or both of a correctable cell pattern and an uncorrectable cell pattern. In some embodiments, the representation of one or both of a correctable cell pattern and an uncorrectable cell pattern can be generated by analyzing the characteristics associated with the stored error correction code to efficiently generate an approximate representation of one or both of the above-mentioned patterns (e.g., using a probabilistic data structure with high computational efficiency, such as using a Bloom filter to search for patterns). Although it is computationally efficient to generate cell patterns using code characteristics, this process generates a set of correctable or uncorrectable error patterns that over-represent or under-represent the actual set of (one or more) correctable and / or uncorrectable error patterns. When compared with the actual error pattern, these over- or under-included sets can result in false positive or false negative analysis results. Therefore, in other embodiments, the processor 140 can communicate with the error correction code storage library 144 to perform various ECCs to generate accurate mappings of some or all of the correctable and / or uncorrectable error patterns. Regardless of the technique, processor 140 may compare patterns of correctable memory cells and / or patterns of uncorrectable memory cells as described herein. These generated patterns are stored in correctable error pattern store 148 and uncorrectable error pattern store 152, respectively.

[0039] The storage repositories 148, 152 are memory areas within or in communication with the processor 140. The storage repositories 148, 152 can store their associated patterns, which are generated according to the techniques described herein. Although shown as elements of the processor 140, in another embodiment, these memory areas can be stored in the data repository 164. Optional additional and / or alternative storage locations are represented in FIG. 1 using dashed lines to outline the storage repositories 148, 152 in the data repository 164.

[0040] In one or more embodiments, the various repositories (e.g., the correctable error pattern repository 148, the uncorrectable error pattern repository 152, the error correction code repository 144) and the data repository 164 may be any type of storage unit and / or device for storing data (e.g., a file system, a database, a collection of tables, or any other storage mechanism). In addition, these repositories and data repositories may include multiple different memory units and / or devices. The multiple different storage units and / or devices may or may not be of the same type or located in the same physical location. In addition, these repositories may be implemented or executed on the same computing system as the memory management engine 128 and / or the system 100. In another embodiment, the data repository may be implemented or executed on a computing system separate from the memory management engine 128 and / or the system 100. The data repository may be communicatively coupled to the system 100 and / or the memory management engine 128 via a direct connection or via a network.

[0041] Although not shown in FIG. 1 , the data repository may also store potential corruption patterns, executable code for implementing the techniques described herein, and other aspects.

[0042] The pattern comparison engine 156 may compare one or both of the patterns stored in the correctable error pattern repository 148 and the uncorrectable error pattern repository 152 with the corresponding (erroneous cell or correct cell) patterns stored in the potential error pattern generator 136 .

[0043] The detection of an uncorrectable error is sent to the remediation engine 160. The remediation engine 160 may send a notification of a remediation action to be performed or may initiate a remediation action itself.

[0044] Information describing techniques for identifying uncorrectable errors using error pattern analysis may be implemented across any component within system 100. However, for purposes of clarity and explanation, FIG1 illustrates a memory management engine 128 implementing an embodiment of error pattern analysis.

[0045] In one or more embodiments, the memory management engine 128 refers to hardware and / or software configured to perform the operations described herein for identifying uncorrectable errors using error pattern analysis. Figure 2 and Figure 4 An example of operations for identifying uncorrectable errors using error pattern analysis is described.

[0046] In an embodiment, the memory management engine 128 is implemented on one or more digital devices. The term "digital device" generally refers to any hardware device including a processor. A digital device may refer to a physical device that executes an application or a virtual machine. Examples of digital devices include computers, tablet computers, laptop computers, desktop computers, netbooks, servers, web servers, network policy servers, proxy servers, general-purpose machines, function-specific hardware devices, hardware routers, hardware switches, hardware firewalls, hardware firewalls, hardware network address translators (NATs), hardware load balancers, mainframes, televisions, content receivers, set-top boxes, printers, mobile phones, smart phones, personal digital assistants ("PDAs"), wireless receivers and / or transmitters, base stations, communication management devices, routers, switches, controllers, access points, and / or client devices.

[0047] In one or more embodiments, the memory management engine 128 includes one or more interfaces (e.g., generated by the remediation engine 160), whether hardware and / or software configured to facilitate communication between a user and the memory management engine 128. Such interfaces render user interface elements and receive input via the user interface elements. Examples of interfaces include graphical user interfaces (GUIs), command line interfaces (CLIs), tactile interfaces, and voice command interfaces. Examples of user interface elements include check boxes, radio buttons, drop-down lists, list boxes, buttons, switches, text fields, date and time selectors, command lines, sliders, pages, and forms.

[0048] In an embodiment, different components of an interface are specified in different languages. The behavior of a user interface element is specified in a dynamic programming language (such as JavaScript). The content of a user interface element is specified in a markup language (such as Hypertext Markup Language (HTML) or XML User Interface Language (XUL)). The layout of a user interface element is specified in a style sheet language (such as Cascading Style Sheets (CSS)). Alternatively, an interface can be specified in one or more other languages ​​(such as Java, C or C++).

[0049] 3. Memory device structure and error correction code

[0050] Figure 1B 1 illustrates a more detailed view of the memory module 102 according to one or more embodiments. Figure 1B As shown in FIG. 1 , the memory module 102 is a 32-bit DRAM memory region. The memory module 102 includes two memory blocks 104 and 108 (sometimes equivalently referred to as "memory groups" or "memory regions"). Each of the memory blocks 104, 108 is formed by an array of 16 memory cells. Figure 1BAs shown in FIG, memory block 104 includes cells 112A-112H arranged in a first column 110 and memory cells 116A-116H arranged in a second column 114. Memory block 108 includes cells 120A-120H arranged in a first column 118 and memory cells 124A-124H arranged in a second column 122. Because each memory cell of the example memory module 102 is capable of storing a single bit (e.g., as a high or low charge state in a capacitor), each of the blocks 104, 108 can store 16 bits.

[0051] In some embodiments, each column 110, 114, 118, 122 is associated with a corresponding input / output (I / O) pin of a DRAM device (not shown) of an electronic package of which memory module 102 is a component. In some embodiments, each row of memory cells (e.g., 112A, 116A, 120A, 124A) can be read and / or written during a single clock cycle of a computer system of which memory module 102 is a component.

[0052] Memory regions and devices may have a hierarchical organization, where the size of a memory block is based on the number of rows and columns of memory cells in the memory block. The rows and columns of a block are generally accessible via bit lines (columns of read and write memory cells) and word lines (rows of read and write memory cells). A memory region may be formed of multiple blocks, which may be accessed via a bus or other interconnects made between the blocks.

[0053] In one or more embodiments, the memory module 102 may include Figure 1B More or fewer components than those shown in the Figure 1B For convenience and clarity of explanation. For example, a single DRAM die (ie, a patterned and functional silicon chip) may have millions, billions, or trillions of individual memory cells.

[0054] The technology described herein involves using error correction codes (ECC) to determine whether a pattern of cells in which one or more errors are detected is correctable or uncorrectable. Error correction codes are algorithms that can use metadata, for example, that is stored with bit values ​​to determine whether a bit value stored in a memory cell (e.g., a high or low charge state in a DRAM capacitor) is an expected value. Bit values ​​stored in a cell that are unexpected or inconsistent with the values ​​predicted by the ECC are identified as errors. In some examples, the execution of the ECC can correct the erroneous bit values ​​in the cell and restore them to the expected (i.e., written) values.

[0055] The degree to which ECC can correct errors can vary depending on the algorithm itself (e.g., Golay, multidimensional parity check, Hamming), the microprocessor used in the computing system, and other factors. In some cases, certain types of error patterns are commonly corrected by many different ECC algorithms. For example, many different ECC algorithms are designed to correct erroneous bit values ​​in cells associated with a common I / O pin. Figure 1B In the context of the example shown in , an example error pattern associated with a shared I / O pin would include one or more cells in cell column 110 having an error (or equivalently, errors in only any one of columns 114, 118, or 122). Many other error patterns are correctable when executing an ECC algorithm.

[0056] The technology of the present disclosure uses ECC to generate known correctable patterns, and then compares the patterns formed by the combination of cells with errors in the memory area with these known correctable patterns. If any error pattern (i.e., a group of one or more memory cells storing bit values ​​that deviate from the expected or written bit values) exhibited in the area of ​​memory (or any subset thereof) is different from the correctable error pattern, then the system identifies the memory area as vulnerable. In some examples, the error pattern can be correctable but includes one or more cells associated with uncorrectable errors. In response, the system can generate a notification recommending a remedial action or can directly perform a remedial action.

[0057] Compared with the traditional technology for identifying vulnerable memory areas, using error pattern analysis to identify the collection of memory cells that are susceptible to the generation of uncorrectable memory cell error patterns, as described herein, has many benefits. To some extent, traditional technology may incorrectly identify some memory areas as being susceptible to permanent memory failures ("false positives"), and may also incorrectly identify some memory areas as being not susceptible to permanent memory failures ("false negatives"). False positive and false negative error identifications can be generated by traditional technology, which relies on simple error counting schemes to identify vulnerable memory areas. For example, if the number of errors in a particular area exceeds a threshold count, the system identifies the particular area as being susceptible to permanent memory failures. If a high error count is associated with a pattern that can be corrected using ECC, the traditional error counting scheme can therefore generate a false positive. Similarly, if the errors generated by the memory area that cannot be corrected using ECC do not exceed the threshold, the traditional error counting scheme can generate a false negative result.

[0058] 4. Use error pattern analysis to predict uncorrectable errors

[0059] Two examples of techniques for identifying uncorrectable errors in memory regions are described below. The first technique (described in Section 4.1) compares the error pattern in the memory region and various combinations of cells with errors in the pattern with patterns of memory cells that are known to be correctable when ECC is applied. If the memory region damage pattern or any combination of cells in the pattern (generated by the system as part of the techniques herein) deviates from the known correctable pattern, then the system assumes that the memory region is prone to uncorrectable errors in the future. The second technique (described in Section 4.2) applies the inverse of the first technique. The system compares the error pattern in the memory region (i.e., a set of potential damage patterns) and various combinations of cells with errors in the pattern (generated by the system) with known uncorrectable error patterns based on ECC analysis. If the memory region error pattern or any combination thereof generated by the system matches any known uncorrectable error pattern, then the system assumes that the memory region is prone to uncorrectable errors in the future.

[0060] 4.1 Predicting Uncorrectable Errors Using Correctable Corruption Pattern Comparison

[0061] Figure 2 An example set of operations in accordance with one or more embodiments is illustrated as a method 200 for identifying memory regions that include uncorrectable errors and that may require remediation. Figure 2 One or more of the operations shown in may be modified, rearranged, or omitted entirely. Figure 2 The particular order of operations shown in the drawings should not be construed as limiting the scope of one or more embodiments.

[0062] Method 200 may begin with the system identifying memory cells in a memory region that are associated with at least one error (operation 204). The system may use ECC to identify a memory region that includes at least one error to determine whether a bit value (e.g., a low or high charge state of a capacitor in a DRAM device) associated with a particular memory cell in the memory region matches an expected value. If the stored bit value is different from the expected bit value for the particular memory cell, the system identifies the particular memory cell as storing an incorrect bit value (i.e., associating the cell with an error). The system may analyze cells in a particular region of memory to identify a pattern of memory cells in the region storing bit values, some of which store correct bit values ​​and others of which store erroneous bit values.

[0063] The pattern of correct and / or erroneous bit values ​​corresponding to the memory region may correspond to a "transient" pattern generated as a snapshot when performing operation 204. The pattern may be used to generate an error vector representing an erroneous cell. In some examples, the system may repeatedly perform operation 204 over a period of time and accumulate (or "aggregate") the pattern of correct and erroneous memory cells in the memory region (operation 208). The system may generate an error vector in which erroneous memory cells are accumulated over time. The error vector may accumulate memory cell identifiers associated with errors over time by joining a set of erroneous cells generated by repeated operations 204 (e.g., using an "OR" operation). In other examples, errors are accumulated in one or more error vectors (e.g., each error vector is associated with a region or set of memory cells, or is associated with a single region at a specific detection time or within a specific detection time). In various examples, an error vector is a representation of each memory cell associated with an error during a measurement period. The error vectors may then be connected to form a connected error vector. In some examples, a connected set may be referred to as a "superset". Similarly, a connected error vector may be used to generate a superset of a potential damage pattern. This superset may then be analyzed to determine similarity to correctable or uncorrectable error patterns, as described herein.

[0064] The aforementioned embodiments of the error vector can associate an error with a cell after detecting an erroneous bit value once. Use a single error occurrence in a cell to identify an erroneous assumption that a memory cell that exhibits an error at one point in time is more likely to exhibit an error in the future. Other embodiments of the error vector can also operate on the additional assumption that some errors are random events (e.g., from cosmic particles), which do not necessarily predict future failures of the cell. Assuming a random event error model can mean that some example error vectors can use a filter to accumulate errors, which does not identify it as having an error until a minimum threshold number of errors has been identified for the cell (operation 212). In one embodiment, the total number of errors can be accumulated toward a threshold during a measurement period. In another embodiment, a removal rate per unit time (e.g., a "leaky bucket" counter) can be used to accumulate and simultaneously decrement errors during a measurement period.

[0065] In some examples, the error vectors associated with the separate memory regions can be stored separately in a table of error vectors. Entries in the error vector table (e.g., corresponding to the separate memory regions and / or corresponding error vectors) can be identified with a unique identifier. This enables the system to access any stored error vectors associated with a particular memory region.

[0066] Regardless of the error accounting technique used, once the system identifies a memory cell in a memory area as having an error, the system generates multiple subsets of cells associated with the error. In some embodiments, each subset is a different combination of memory cells (or their corresponding identifiers) that are erroneous (operation 216). These different combinations describe potential damage patterns. That is, because it is assumed that the cells operate independently of each other, any combination of cells associated with the error is identified as a possible future damage pattern, even if the identified damage pattern itself is correctable. In some embodiments, each of the different combinations of memory cells that have errors can be represented as one or more error vectors. Error patterns and potential damage patterns as representations of error vectors facilitate similarity analysis, as described below. Subsets of different combinations of memory cells that have errors can include a set consisting of individual cells or groups of cells. In one example, the subset includes all memory cells that have errors.

[0067] The system then identifies a pattern of erroneous memory cells that are known to be correctable via the ECC algorithm used by the system (operation 220). These techniques are described above in the context of FIG.

[0068] The system then compares the various potential damage patterns to the patterns of correctable memory cells generated via the ECC algorithm to determine whether at least one potential damage pattern does not meet a similarity threshold with any correctable error pattern (operation 224). The system can perform the comparison by performing a similarity comparison (e.g., cosine similarity) between the vector representation of each potential damage pattern (e.g., using the corresponding error vector) and the vector representation of each correctable error pattern.

[0069] If at least one potential corruption pattern does not meet a similarity threshold with any correctable error pattern (operation 224), then the memory region is determined to be capable of generating uncorrectable errors (operation 228). A vulnerability threshold is met and remedial action other than ECC may be recommended (operation 230). The system may optionally correct any errors that are capable of being corrected (operation 238).

[0070] However, if the pattern does meet the similarity threshold to a correctable error pattern (operation 224), then the error is determined to be correctable (operation 234) and can optionally be corrected by applying ECC (operation 238). In other words, if the set of potentially corrupted patterns forms a subset of the set of correctable patterns, then the error is assumed to be correctable. The vulnerability threshold is not met and the error can be corrected using ECC (operation 232). The system can optionally continue to monitor for errors by resuming method 200 at operation 204.

[0071] In some examples, remedial actions consume more significant resources than simply performing ECC. Examples of remedial actions include reassigning data to different memory areas, duplicating regions of memory in different memory areas or different memory devices, or even physically replacing memory areas (e.g., DIMMs or SIMMs). All of these remedial actions consume computing and / or financial resources, and some of these remedial actions may only be deployed a fixed number of times before more significant actions are taken. The improved accuracy of the techniques described herein improves the operation of a computing device by avoiding the use of remedial actions when they are not actually needed.

[0072] Figure 3 300, which graphically illustrates the relationship between a set of correctable damage patterns 304 and a set of latent damage patterns 308. As shown, the set of correctable damage patterns 304 encompasses most, but not all, of the set of latent damage patterns 308. Instead, a portion of the set of latent damage patterns 308 (indicated by shading) is outside the set of correctable damage patterns 304. The shaded portion indicates a subset of the latent damage patterns 312 that does not satisfy the similarity criterion with any pattern in the set of correctable damage patterns 304. For clarity, the portion of the diagram 300 representing the subset 312 has been exaggerated. In some examples, only a single latent damage pattern (or even a single memory cell within a single latent damage pattern) needs to be different from the set of correctable damage patterns 304 to exceed the vulnerability criterion.

[0073] 4.2 Predicting Uncorrectable Errors Using Uncorrectable Corruption Pattern Comparison

[0074] Figure 4 A method 400 is illustrated that is similar to the method 200 shown in FIG. 2 , except that in the method 400 , the vulnerability criterion is satisfied when the latent corruption satisfies a similarity criterion of an error pattern corresponding to an uncorrectable error.

[0075] Method 400 begins with operations similar to those used by method 200. The system identifies memory cells in a memory region that are associated with at least one error (operation 404). The system can use ECC to identify memory cells with errors to determine whether a bit value (e.g., a low or high charge state of a capacitor in a DRAM device) associated with a particular memory cell in the memory region matches an expected value. If the stored bit value is different from the expected bit value for the particular memory cell, the system identifies the particular memory cell as storing an incorrect bit value (i.e., associates the cell with an error). The system can identify cells with errors in a particular region of memory, thereby identifying a pattern of memory cells in the region storing bit values, where some cells store correct bit values ​​and others store erroneous bit values.

[0076] As with method 200, method 400 may also accumulate erroneous memory cells into an error vector over time (operation 408) and / or filter errors using a threshold error count and / or decrement rate (operation 412). These techniques are described above in the context of operations 408 and 412.

[0077] Regardless of the error interpretation technique used, once the system identifies a memory cell in a memory region as having an error, the system generates a plurality of subsets of cells associated with the error to identify potential damage patterns (operation 416). In some embodiments, each subset is a different combination of memory cells (or their corresponding cell identifiers) that have an error. As described above, the system generates these potential damage patterns based on the assumption that any cell associated with an error during the measurement period is more likely to be associated with another error in the future. Each potential damage pattern therefore represents a combination of cells that can generate future errors, assuming that the currently erroneous cell can be associated with future errors. In some embodiments, each of the different combinations of erroneous memory cells can be represented as an error vector to facilitate the performance of similarity analysis.

[0078] The system then identifies patterns of erroneous memory cells that are known to be uncorrectable via the ECC algorithm used by the system (operation 420). The techniques used for operation 420 are similar to those described above in the context of operation 220.

[0079] The system then compares the various potential damage patterns to the patterns of uncorrectable memory cells generated via the ECC algorithm (operation 424). The system can perform the comparison of operation 424 by performing a similarity comparison (e.g., cosine similarity) between the vector representation of each potential damage pattern (i.e., the error vector of each potential damage pattern) and the vector representation of each correctable error pattern.

[0080] If at least one potential corruption pattern satisfies a similarity threshold with any uncorrectable error pattern (operation 424), then the memory region is determined to be capable of generating uncorrectable errors (operation 428). Based on operation 428, the system determines that the vulnerability criteria are met (operation 430). The system may optionally identify uncorrectable errors and / or recommended remedial actions. The system may optionally correct any errors that are capable of being corrected (operation 438).

[0081] Alternatively, if no potential corruption pattern is similar to the uncorrectable error pattern, the system determines that the memory region does not meet the vulnerability criteria (operation 434). The ECC may optionally be used to correct the errors (operation 438) and the system may resume monitoring (operation 404).

[0082] Figure 5 5 is a Venn diagram 500 that graphically illustrates an example relationship between a set 504 of uncorrectable damage patterns and a set 508 of potential damage patterns. As shown, the uncorrectable damage pattern 504 may be tangent to the set 508 of potential damage patterns. Tangent point 512 indicates that only one potential damage pattern 508 needs to satisfy the similarity criterion with the set 504 of uncorrectable damage patterns to satisfy the vulnerability criterion. A single tangent point 512 between patterns 504 and 508 represents a minimum condition for satisfying the vulnerability criterion.

[0083] 5. Example Embodiments

[0084] For the sake of clarity, a detailed example is described below. The components and / or operations described below should be understood as a specific example that may not be applicable to certain embodiments. Thus, the components and / or operations described below should not be interpreted as limiting the scope of any claim.

[0085] Figure 6 , 7 , 8A and 8B illustrate the various stages of the above-described technique in the context of a particular memory region.

[0086] Figure 6 Memory region 604 is illustrated, which includes memory cells 612A, 612B, 612C, 612D in a first column 610 and memory cells 616A, 616B, 616C, 616D in a second column 614. Memory region 604 may be part of a larger memory array. For ease and clarity of explanation, Figure 6 The finite size of memory area 604 is presented in FIG.

[0087] Each of the memory cells 612A-612D, 616A-616D is labeled with a corresponding error state 628. The memory cells 612A, 612D, 616A, 616B, and 616C each store bits that match corresponding bit values ​​checked using an ECC algorithm executed by a computing device (e.g., a processor) in communication with the memory region 604.

[0088] Memory cells 612B, 612C, and 616D are marked with an error state 628 indicating that the bit values ​​stored in these cells deviate from the expected bit values. The error state 628 of these memory cells is a "threshold number of errors" to reflect the optional use of the above-mentioned filters and / or thresholds. That is, in some embodiments, memory cells 612B, 612C, and 616D are not associated with errors until a minimum number of deviations from the expected bit value is detected within the measurement period. Once identified as being associated with an erroneous bit value, the set of memory cells 612B, 612C, and 616D constitutes a first damage mode.

[0089] Figure 7 Pictured Figure 6 There are many different combinations of cells with errors as shown in . That is, Figure 7 Potential damage modes 704, 708, 712, 716, 720, 724, 728 are illustrated, each of which is Figure 6 6. Potential damage patterns 704, 708, and 712 each illustrate a potential damage pattern having only one of cells 612B, 612C, and 616D with an error. Potential damage patterns 716, 720, and 724 include potential damage patterns that are each a subset of cells with two errors. Potential damage pattern 728 is a subset of all three cells with errors.

[0090] As explained above, each of the potential damage patterns 704, 708, 712, 716, 720, 724, and 728 is generated based on the assumption that any memory cell currently storing an erroneous bit value may generate an error in the future.

[0091] Fig. 8A Illustrated is an uncorrectable corruption pattern 804, as determined from analysis of the error correction code associated with memory region 604. Uncorrectable corruption pattern 804 is characterized by errors present in both memory cells 612B and 626D.

[0092] Figure 8B The diagram shows Figure 6 804. In one embodiment, the memory region 604 is associated with a potential damage pattern associated with a different combination of cells with errors in the memory region 604 that matches the uncorrectable error pattern 804. That is, the potential damage pattern 716 includes the same cells 612B and 616D that are present in the uncorrectable damage pattern 804. Because the potential damage pattern 716 matches the uncorrectable error pattern 804 (or more generally, satisfies the similarity criterion with the uncorrectable error pattern 804), the memory region 604 satisfies the vulnerability criterion. The system can then take remedial action or generate a notification recommending a remedial action.

[0093] 6. Computer Networks and Cloud Networks

[0094] In one or more embodiments, a computer network provides connectivity between a collection of nodes. The nodes may be local to each other and / or remote from each other. The nodes are connected by a collection of links. Examples of links include coaxial cables, unshielded twisted pairs, copper cables, optical fibers, and virtual links.

[0095] A subset of nodes implements a computer network. Examples of such nodes include switches, routers, firewalls, and network address translators (NATs). Another subset of nodes uses a computer network. Such nodes (also referred to as "hosts") can execute client processes and / or server processes. A client process makes a request for a computing service (such as the execution of a particular application and / or the storage of a particular amount of data). The server process responds by performing the requested service and / or returning corresponding data.

[0096] A computer network may be a physical network, comprising physical nodes connected by physical links. A physical node is any digital device. A physical node may be a function-specific hardware device, such as a hardware switch, a hardware router, a hardware firewall, and a hardware NAT. Additionally or alternatively, a physical node may be a general-purpose machine configured to execute various virtual machines and / or applications that execute corresponding functions. A physical link is a physical medium that connects two or more physical nodes. Examples of links include coaxial cables, unshielded twisted cables, copper cables, and optical fibers.

[0097] A computer network may be an overlay network. An overlay network is a logical network implemented on top of another network (such as a physical network). Each node in the overlay network corresponds to a corresponding node in the underlying network. Therefore, each node in the overlay network is associated with both an overlay address (addressing the overlay node) and an underlying address (addressing the underlying node that implements the overlay node). An overlay node may be a digital device and / or a software process (such as a virtual machine, an application instance, or a thread). The link connecting the overlay nodes is implemented as a tunnel through the underlying network. The overlay nodes at either end of the tunnel treat the underlying multi-hop path between them as a single logical link. Tunneling is performed by encapsulation and decapsulation.

[0098] In an embodiment, the client may be located locally and / or remote from the computer network. The client may access the computer network through other computer networks, such as a private network or the Internet. The client may transmit the request to the computer network using a communication protocol, such as a hypertext transfer protocol (HTTP). The request is transmitted through an interface, such as a client interface, such as a web browser, a program interface, or an application programming interface (API).

[0099] In an embodiment, a computer network provides a connection between a client and a network resource. The network resource includes hardware and / or software configured to execute a server process. Examples of network resources include processors, data storage devices, virtual machines, containers, and / or software applications. Network resources are shared between multiple clients. Clients request computing services from a computer network independently of each other. Network resources are dynamically allocated to requests and / or clients on demand. The network resources allocated to each request and / or client can be expanded or reduced based on, for example, (a) computing services requested by a specific client, (b) aggregate computing services requested by a specific tenant, and / or (c) the requested aggregate computing services of the computer network. Such a computer network may be referred to as a "cloud network."

[0100] In an embodiment, a service provider provides a cloud network to one or more end users. The cloud network can implement various service models, including but not limited to software as a service (SaaS), platform as a service (PaaS), and infrastructure as a service (IaaS). In SaaS, a service provider provides the end user with the ability to use the service provider's applications that are being executed on network resources. In PaaS, a service provider provides the end user with the ability to deploy customized applications on network resources. Customized applications can be created using programming languages, libraries, services, and tools supported by the service provider. In IaaS, a service provider provides the end user with the ability to supply processing, storage, network, and other basic computing resources provided by network resources. Any arbitrary application, including an operating system, can be deployed on network resources.

[0101] In an embodiment, a computer network can implement various deployment models, including but not limited to private cloud, public cloud and hybrid cloud. In a private cloud, network resources are supplied to a specific group of one or more entities for exclusive use (the term "entity" as used herein refers to an enterprise, organization, individual or other entity). Network resources can be local to and / or away from the premises of a specific entity group. In a public cloud, cloud resources are supplied to multiple entities (also referred to as "tenants" or "customers") that are independent of each other. A computer network and its network resources are accessed by clients corresponding to different tenants. Such a computer network may be referred to as a "multi-tenant computer network". Several tenants may use the same specific network resources at different times and / or at the same time. Network resources may be local to and / or away from the premises of a tenant. In a hybrid cloud, a computer network includes a private cloud and a public cloud. The interface between a private cloud and a public cloud allows portability of data and applications. Data stored at a private cloud and data stored at a public cloud can be exchanged through an interface. Applications implemented at a private cloud and applications implemented at a public cloud may have dependencies on each other. Calls from an application at the private cloud to an application at the public cloud (and vice versa) may be performed through the interface.

[0102] In an embodiment, the tenants of a multi-tenant computer network are independent of each other. For example, the business or operation of one tenant can be separated from the business or operation of another tenant. Different tenants may have different network requirements for the computer network. Examples of network requirements include processing speed, data storage capacity, security requirements, performance requirements, throughput requirements, latency requirements, elasticity requirements, quality of service (QoS) requirements, tenant isolation and / or consistency. The same computer network may need to implement different network requirements required by different tenants.

[0103] In one or more embodiments, in a multi-tenant computer network, tenant isolation is implemented to ensure that applications and / or data of different tenants are not shared with each other. Various tenant isolation methods can be used.

[0104] In an embodiment, each tenant is associated with a tenant ID. Each network resource of the multi-tenant computer network is marked with a tenant ID. Only when the tenant and the specific network resource are associated with the same tenant ID, the tenant is allowed to access the specific network resource.

[0105] In an embodiment, each tenant is associated with a tenant ID. Each application implemented by the computer network is tagged with the tenant ID. Additionally or alternatively, each data structure and / or data set stored by the computer network is tagged with the tenant ID. A tenant is allowed to access a specific application, data structure, and / or data set only if the tenant and the specific application, data structure, and / or data set are associated with the same tenant ID.

[0106] As an example, each database implemented by a multi-tenant computer network can be marked with a tenant ID. Only the tenant associated with the corresponding tenant ID can access the data of a particular database. As another example, each entry in a database implemented by a multi-tenant computer network can be marked with a tenant ID. Only the tenant associated with the corresponding tenant ID can access the data of a particular entry. However, a database can be shared by multiple tenants.

[0107] In an embodiment, the subscription list indicates which tenants have access to which applications. For each application, a list of tenant IDs of tenants authorized to access the application is stored. Only when the tenant ID of a tenant is included in the subscription list corresponding to a specific application, the tenant is allowed to access the specific application.

[0108] In an embodiment, network resources corresponding to different tenants (such as digital devices, virtual machines, application instances, and threads) are isolated to tenant-specific overlay networks maintained by a multi-tenant computer network. As an example, a data packet from any source device in a tenant overlay network can be sent only to other devices within the same tenant overlay network. The encapsulation tunnel is used to prohibit any transmission from a source device on a tenant overlay network to devices in other tenant overlay networks. Specifically, a data packet received from a source device is encapsulated in an outer data packet. The outer data packet is sent from a first encapsulation tunnel endpoint (communicating with a source device in a tenant overlay network) to a second encapsulation tunnel endpoint (communicating with a destination device in a tenant overlay network). The second encapsulation tunnel endpoint decapsulates the outer data packet to obtain the original data packet sent by the source device. The original data packet is sent from the second encapsulation tunnel endpoint to a destination device in the same specific overlay network.

[0109] 7. Other Matters; Extension

[0110] Embodiments are directed to a system having one or more devices comprising a hardware processor and configured to perform any of the operations described herein and / or in any of the following claims.

[0111] In an embodiment, a non-transitory computer-readable storage medium comprises instructions that, when executed by one or more hardware processors, cause performance of any of the operations described herein and / or any of the claims.

[0112] According to one or more embodiments, any combination of the features and functions described herein may be used. In the foregoing description, embodiments have been described with reference to many specific details that vary depending on the implementation. Therefore, the description and drawings should be considered illustrative rather than restrictive. The sole and exclusive indicator of the scope of the present invention and what the applicant intends to be the scope of the present invention is the literal and equivalent range of the set of claims issued from this application, in the specific form in which such claims are issued, including any subsequent corrections.

[0113] 8. Hardware Overview

[0114] According to one embodiment, the technology described herein is implemented by one or more special-purpose computing devices. The special-purpose computing device can be hard-wired to perform the present technology, or can include a digital electronic device that is permanently programmed to perform the present technology, such as one or more application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or network processing units (NPUs), or can include one or more general-purpose hardware processors that are programmed to perform the present technology according to program instructions in firmware, memory, other storage devices, or combinations. Such special-purpose computing devices can also combine customized hard-wired logic, ASICs, FPGAs, or NPUs with customized programming to implement the present technology. The special-purpose computing device can be a desktop computer system, a portable computer system, a handheld device, a networking device, or any other device that combines hard-wiring and / or program logic to implement the technology.

[0115] For example, Fig. 9 900 is a block diagram illustrating a computer system 900 upon which embodiments of the present invention may be implemented. Computer system 900 includes a bus 902 or other communication mechanism for communicating information and a hardware processor 904 coupled with bus 902 for processing information. Hardware processor 904 may be, for example, a general purpose microprocessor.

[0116] The computer system 900 also includes a main memory 906, such as a random access memory (RAM) or other dynamic storage device, coupled to the bus 902 for storing information and instructions to be executed by the processor 904. The main memory 906 may also be used to store temporary variables or other intermediate information during execution of instructions to be executed by the processor 904. When such instructions are stored in a non-transitory storage medium accessible to the processor 904, such instructions cause the computer system 900 to become a special-purpose machine customized to perform the operations specified in the instructions.

[0117] Computer system 900 also includes a read only memory (ROM) 908 or other static storage device coupled to bus 902 for storing static information and instructions for processor 904. A storage device 910, such as a magnetic or optical disk, is provided and coupled to bus 902 for storing information and instructions.

[0118] The computer system 900 may be coupled via the bus 902 to a display 912, such as a cathode ray tube (CRT), for displaying information to a computer user. An input device 914, including alphanumeric and other keys, is coupled to the bus 902 for communicating information and command selections to the processor 904. Another type of user input device is a cursor control 916, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to the processor 904 and for controlling cursor movement on the display 912. Such input devices typically have two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), to allow the device to specify a position in a plane.

[0119] The computer system 900 may implement the techniques described herein using custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic that, in combination with the computer system, makes the computer system 900 a special purpose machine or programs the computer system 900 to be a special purpose machine. According to one embodiment, the techniques herein are performed by the computer system 900 in response to the processor 904 executing one or more sequences of one or more instructions contained in the main memory 906. These instructions may be read into the main memory 906 from another storage medium, such as the storage device 910. Execution of the sequences of instructions contained in the main memory 906 causes the processor 904 to perform the process steps described herein. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions.

[0120] The term "storage medium" as used herein refers to any non-transitory medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such storage media may include non-volatile media and / or volatile media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 910. Volatile media include dynamic memory, such as main memory 906. Common forms of storage media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, tapes or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with hole patterns, RAM, PROM and EPROM, FLASH-EPROM, NVRAM, any other memory chip or cassette, content addressable memory (CAM) and ternary content addressable memory (TCAM).

[0121] Storage media are distinct from but may be used in conjunction with transmission media. Transmission media participate in the transfer of information between storage media. For example, transmission media include coaxial cables, copper wire, and optical fiber, including the wires that comprise bus 902. Transmission media may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0122] Various forms of media may be involved in carrying one or more sequences of one or more instructions to processor 904 for execution. For example, the instructions may initially be carried on a disk or solid-state drive of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to the computer system 900 can receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal. An infrared detector can receive the data carried in the infrared signal and appropriate circuitry can place the data on bus 902. Bus 902 carries the data to main memory 906, from which processor 904 retrieves and executes the instructions. The instructions received by main memory 906 may optionally be stored on storage device 910 before or after execution by processor 904.

[0123] Computer system 900 also includes a communication interface 918 coupled to bus 902. Communication interface 918 provides a two-way data communication coupled to a network link 920, wherein network link 920 is connected to a local network 922. For example, communication interface 918 can be an integrated services digital network (ISDN) card, a cable modem, a satellite modem, or a modem that provides a data communication connection to a telephone line of a corresponding type. As another example, communication interface 918 can be a LAN card that provides a data communication connection to a compatible local area network (LAN). Wireless links can also be implemented. In any such implementation, communication interface 918 sends and receives electrical signals, electromagnetic signals, or optical signals that carry digital data streams representing various types of information.

[0124] The network link 920 typically provides data communication to other data devices through one or more networks. For example, the network link 920 can provide a connection to a host computer 924 or to data equipment operated by an Internet Service Provider (ISP) 926 through a local network 922. The ISP 926, in turn, provides data communication services through a global packet data communication network now commonly referred to as the "Internet" 928. Both the local network 922 and the Internet 928 use electrical, electromagnetic, or optical signals that carry digital data streams. The signals through the various networks and the signals on the network link 920 and through the communication interface 918 are example forms of transmission media that carry digital data to or from the computer system 900.

[0125] Computer system 900 can send messages and receive data, including program code, through the network(s), network link 920, and communication interface 918. In the Internet example, server 930 can transmit the requested code for an application program through Internet 928, ISP 926, local network 922, and communication interface 918.

[0126] The received code may be executed by processor 904 as it is received, and / or stored in storage device 910 or other non-volatile storage for later execution.

[0127] In the foregoing specification, embodiments of the present invention have been described with reference to numerous specific details that may vary from implementation to implementation. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive. The sole and exclusive indicator of the scope of the invention, and what the applicants intend as the scope of the invention, is the literal and equivalent scope of the set of claims issuing from this application in the specific form in which such claims are issued, including any subsequent corrections.

Claims

1. One or more non-transitory computer-readable media storing instructions that, when executed by one or more hardware processors, cause operations to be performed, including: identifying a first plurality of memory cells in a region of the memory that are respectively associated with at least one error by reading values ​​stored in the memory; generating a first plurality of potential damage patterns comprising different combinations of the first plurality of memory cells, wherein the different combinations comprise subsets of the first plurality of memory cells; identifying a plurality of correctable corruption patterns corresponding to correctable errors associated with memory cells of the region of memory; comparing the first plurality of potential damage patterns to the plurality of correctable damage patterns; determining, based on the comparing operation, that at least one potential damage pattern in the first plurality of potential damage patterns does not satisfy a similarity criterion with at least one correctable damage pattern in the plurality of correctable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable error pattern.

2. The medium of claim 1, wherein the operations further comprise: identifying a second plurality of memory cells stored in a region of the memory that are respectively associated with at least one error; generating a plurality of combinations corresponding to subsets of the second plurality of memory cells as a second plurality of potential damage patterns; concatenating the first plurality of potential damage modes and the second plurality of potential damage modes to form a superset of potential damage modes; determining that at least one potential damage pattern of the plurality of potential damage patterns in the superset of potential damage patterns does not satisfy a similarity criterion with any correctable damage pattern of the plurality of correctable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable corruption pattern.

3. The medium of claim 1, further comprising establishing a minimum error threshold corresponding to a memory cell in the first plurality of memory cells, wherein when the minimum error threshold is exceeded, a cell is identified as a member of the first plurality of memory cells associated with at least one error.

4. The medium of claim 1, wherein the first plurality of memory cells are identified by: identifying, within a time period, the first plurality of memory cells in a region of the memory that are associated with respective errors; aggregating each memory cell of the first plurality of memory cells identified during the time period; generating error vectors and indications of errors corresponding to the first plurality of memory cells; as well as Error vectors are stored in an error vector table indexed by addresses corresponding to cells associated with memory cells in the region of memory.

5. The medium of claim 4, wherein the operations further comprise: identifying a second plurality of memory cells stored in a region of the memory that are respectively associated with at least one error; generating additional error vectors and indications of errors corresponding to said second plurality of memory cells; concatenating error vectors corresponding to the first plurality of memory cells and additional error vectors corresponding to the second plurality of memory cells to form a concatenated error vector; Generate a superset of potential corruption patterns using the concatenated error vectors; determining that at least one potential damage pattern of the plurality of potential damage patterns in the superset of potential damage patterns does not satisfy a similarity criterion with any correctable damage pattern of the plurality of correctable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable corruption pattern.

6. The medium of claim 4, wherein determining that at least one potential corruption pattern does not satisfy a similarity criterion comprises: generating a vector corresponding to a pattern of the plurality of correctable corruption patterns; as well as A vector comparison is performed that compares error vectors corresponding to memory cells of the first plurality of memory cells with vectors corresponding to the plurality of correctable corruption patterns.

7. The medium of claim 1, further comprising: applying a minimum error threshold to a memory cell in said first plurality of memory cells; measuring a number of errors for each memory cell of the first plurality of memory cells; as well as Wherein associating a memory cell of the first plurality of memory cells with at least one error comprises associating the error with a particular memory cell when a number of errors of the particular memory cell exceeds a minimum error threshold.

8. The medium of claim 7, further comprising: defining a measurement period during which a number of errors of respective memory cells of the first plurality of memory cells is measured; identifying an error time associated with identification of errors associated with the first plurality of memory cells; as well as A threshold time period is defined within the measurement period after which errors associated with the first plurality of memory cells are removed.

9. One or more non-transitory computer-readable media storing instructions that, when executed by one or more hardware processors, cause operations to be performed, including: identifying a first plurality of memory cells in a region of the memory that are respectively associated with at least one error by reading values ​​stored in the memory; generating a plurality of combinations corresponding to subsets of the first plurality of memory cells as a first plurality of potential damage patterns; identifying a plurality of uncorrectable corruption patterns corresponding to uncorrectable errors associated with memory cells of the region of memory; determining that at least one potential damage pattern of the first plurality of potential damage patterns satisfies a similarity criterion with at least one uncorrectable damage pattern of the plurality of uncorrectable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable corruption pattern.

10. The medium of claim 9, wherein the operations further comprise: identifying a second plurality of memory cells stored in a region of the memory that are respectively associated with at least one error; generating a plurality of combinations corresponding to subsets of the second plurality of memory cells as a second plurality of potential damage patterns; concatenating the first plurality of potential damage modes and the second plurality of potential damage modes to form a superset of potential damage modes; determining that at least one potential damage pattern of the plurality of potential damage patterns in the superset of potential damage patterns satisfies a similarity criterion with any uncorrectable damage pattern of the plurality of uncorrectable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable error pattern.

11. The medium of claim 9, further comprising establishing a minimum error threshold corresponding to a memory cell in the first plurality of memory cells, wherein when the minimum error threshold is exceeded, a cell is identified as a member of the first plurality of memory cells that is associated with at least one error.

12. The medium of claim 9, wherein the first plurality of memory cells are identified by: identifying, within a time period, the first plurality of memory cells in a region of the memory that are associated with respective errors; aggregating each memory cell of the first plurality of memory cells identified during the time period; as well as generating error vectors and indications of errors corresponding to the first plurality of memory cells; as well as Error vectors are stored in an error vector table indexed by addresses corresponding to cells associated with memory cells in the region of memory.

13. The medium of claim 12, wherein the operations further comprise: identifying a second plurality of memory cells stored in a region of the memory that are respectively associated with at least one error; generating additional error vectors and indications of errors corresponding to said second plurality of memory cells; concatenating error vectors corresponding to the first plurality of memory cells and additional error vectors corresponding to the second plurality of memory cells to form a concatenated error vector; Generate a superset of potential corruption patterns using the concatenated error vectors; determining that at least one potential damage pattern of the plurality of potential damage patterns in the superset of potential damage patterns does satisfy a similarity criterion with any one of the plurality of correctable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable corruption pattern.

14. The medium of claim 12, wherein determining that at least one potential corruption pattern satisfies a similarity criterion comprises: generating a vector corresponding to a pattern of the plurality of uncorrectable corruption patterns; as well as A vector comparison is performed that compares error vectors corresponding to memory cells of the first plurality of memory cells with vectors corresponding to the plurality of uncorrectable corruption patterns.

15. The medium of claim 9, further comprising: applying a minimum error threshold to a memory cell in said first plurality of memory cells; measuring a number of errors for each memory cell of the first plurality of memory cells; as well as Wherein associating a memory cell of the first plurality of memory cells with at least one error comprises associating the error with a particular memory cell when a number of errors of the particular memory cell exceeds a minimum error threshold.

16. The medium of claim 15, further comprising: defining a measurement period during which a number of errors of respective memory cells of the first plurality of memory cells is measured; identifying an error time associated with identification of errors associated with the first plurality of memory cells; as well as A threshold time period is defined within the measurement period after which errors associated with the first plurality of memory cells are removed.

17. A system comprising: at least one device including a hardware processor; The system is configured to perform operations including: identifying a first plurality of memory cells in a region of the memory that are respectively associated with at least one error by reading values ​​stored in the memory; generating a first plurality of potential damage patterns comprising different combinations of the first plurality of memory cells, wherein the different combinations comprise subsets of the first plurality of memory cells; identifying a plurality of correctable corruption patterns corresponding to correctable errors associated with memory cells of the region of memory; comparing the first plurality of potential damage patterns to the plurality of correctable damage patterns; determining, based on the comparing operation, that at least one potential damage pattern in the first plurality of potential damage patterns does not satisfy a similarity criterion with at least one correctable damage pattern in the plurality of correctable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable error pattern.

18. The system of claim 17, wherein the operations further comprise: identifying a second plurality of memory cells stored in a region of the memory that are respectively associated with at least one error; generating a plurality of combinations corresponding to subsets of the second plurality of memory cells as a second plurality of potential damage patterns; concatenating the first plurality of potential damage modes and the second plurality of potential damage modes to form a superset of potential damage modes; determining that at least one potential damage pattern of the plurality of potential damage patterns in the superset of potential damage patterns does not satisfy a similarity criterion with any correctable damage pattern of the plurality of correctable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable corruption pattern.

19. The system of claim 17, further comprising establishing a minimum error threshold corresponding to a memory cell in the first plurality of memory cells, wherein when the minimum error threshold is exceeded, a cell is identified as a member of the first plurality of memory cells associated with at least one error.

20. The system of claim 17, wherein the first plurality of memory cells are identified by: identifying, within a time period, the first plurality of memory cells in a region of the memory that are associated with respective errors; aggregating each memory cell of the first plurality of memory cells identified during the time period; generating error vectors and indications of errors corresponding to the first plurality of memory cells; as well as Error vectors are stored in an error vector table indexed by addresses corresponding to cells associated with memory cells in the region of memory.

21. The system of claim 20, wherein the operations further comprise: identifying a second plurality of memory cells stored in a region of the memory that are respectively associated with at least one error; generating additional error vectors and indications of errors corresponding to said second plurality of memory cells; concatenating error vectors corresponding to the first plurality of memory cells and additional error vectors corresponding to the second plurality of memory cells to form a concatenated error vector; Generate a superset of potential corruption patterns using the concatenated error vectors; determining that at least one potential damage pattern of the plurality of potential damage patterns in the superset of potential damage patterns does not satisfy a similarity criterion with any correctable damage pattern of the plurality of correctable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable corruption pattern.

22. The system of claim 20, wherein determining that at least one potential corruption pattern does not satisfy a similarity criterion comprises: generating a vector corresponding to a pattern of the plurality of correctable corruption patterns; as well as A vector comparison is performed comparing error vectors of the first plurality of memory cells to vectors corresponding to the plurality of correctable corruption patterns.

23. The system of claim 17, further comprising: applying a minimum error threshold to a memory cell in said first plurality of memory cells; measuring a number of errors for each memory cell of the first plurality of memory cells; as well as Wherein associating a memory cell of the first plurality of memory cells with at least one error comprises associating the error with a particular memory cell when a number of errors of the particular memory cell exceeds a minimum error threshold.

24. A method comprising: identifying a first plurality of memory cells in a region of the memory that are respectively associated with at least one error by reading values ​​stored in the memory; generating a first plurality of potential damage patterns comprising different combinations of the first plurality of memory cells, wherein the different combinations comprise subsets of the first plurality of memory cells; identifying a plurality of correctable corruption patterns corresponding to correctable errors associated with memory cells of the region of memory; comparing the first plurality of potential damage patterns to the plurality of correctable damage patterns; determining, based on the comparing operation, that at least one potential damage pattern in the first plurality of potential damage patterns does not satisfy a similarity criterion with at least one correctable damage pattern in the plurality of correctable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable error pattern.

25. A method comprising: identifying a first plurality of memory cells in a region of the memory that are respectively associated with at least one error by reading values ​​stored in the memory; generating a plurality of combinations corresponding to subsets of the first plurality of memory cells as a first plurality of potential damage patterns; identifying a plurality of uncorrectable corruption patterns corresponding to uncorrectable errors associated with memory cells of the region of memory; determining that at least one potential damage pattern of the first plurality of potential damage patterns satisfies a similarity criterion with at least one uncorrectable damage pattern of the plurality of uncorrectable damage patterns; and In response to the OK operation: A region of the memory is determined to satisfy a vulnerability criterion for data corruption associated with an uncorrectable corruption pattern.

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