A sensing and calculating integrated laser radar detection chip

Abstract

The application relates to a laser radar detection chip integrating sensing and calculation, characterized by comprising a detection front end, a pixel array and an analog-digital conversion and readout circuit connected in sequence, wherein the pixel array comprises multiple pixel columns, a first bus and a second bus corresponding to each column, and a first differential calculation capacitor and a second differential calculation capacitor corresponding to each column; the first bus is connected with the first differential calculation capacitor; the second bus is connected with the second differential calculation capacitor; a first transmission gate switch is connected between the first buses of adjacent columns; a second transmission gate switch is connected between the second buses of adjacent columns; a pixel in the pixel array comprises an in-pixel detection circuit and an in-pixel multiplication circuit; the in-pixel multiplication circuit is connected with the in-pixel detection circuit and the corresponding first bus and second bus. Compared with the prior art, the application greatly improves the energy efficiency of the detection system, reduces the calculation delay, and reduces the bandwidth consumption and power consumption caused by the movement of redundant data.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of laser radar detection, in particular to a sensing and computing integrated laser radar detection chip. BACKGROUND

[0002] Laser radar can detect the depth direction information of the target. Compared with the two-dimensional image imaging array constructed by charge coupled device or complementary metal oxide semiconductor array, the three-dimensional image imaging array composed of Geiger avalanche detector array can obtain the information of the depth direction of the target, and has wide application in the fields of space detection and intelligent driving. After the laser radar array detects the target information, the data needs to be transmitted to an external chip for separate data processing, and finally the tasks such as target detection, classification and segmentation can be completed. In this process, the large amount of redundant detection data and the high delay and low energy efficiency caused by data transfer cannot be ignored.

[0003] In order to improve the energy efficiency, reduce the delay and reduce the bus bandwidth pressure, an AI vision chip appears. The traditional AI vision chip is mostly based on two-dimensional image sensing, and the sensing end and the computing end are not fused, and the delay and energy consumption caused by data transfer from the detection end to the computing end are not solved by optimizing the computing path, quantization and sparsification of the computing end. A sensing and computing integrated laser radar detection system with high energy efficiency, low delay and low power consumption is urgently needed in the fields of autonomous driving, aerospace and other fields, and has great research value. SUMMARY

[0004] The purpose of the present application is to provide a sensing and computing integrated laser radar detection chip, which greatly improves the energy efficiency of the detection system, reduces the delay of the calculation, and reduces the bandwidth consumption and power consumption caused by the movement of redundant data.

[0005] The purpose of the present application can be realized by the following technical solutions:

[0006] A sensing and computing integrated laser radar detection chip, characterized in that it comprises a detection front end, a pixel array and an analog-to-digital conversion and readout circuit connected in sequence, the pixel array comprises a plurality of pixel columns, a first bus and a second bus corresponding to each column, and a first differential calculation capacitor and a second differential calculation capacitor corresponding to each column, the first bus is connected to the first differential calculation capacitor, the second bus is connected to the second differential calculation capacitor, and a first transmission gate switch is connected between the first buses of adjacent columns, and a second transmission gate switch is connected between the second buses of adjacent columns, the pixels in the pixel array include an in-pixel detection circuit and an in-pixel multiplication circuit, and the in-pixel multiplication circuit is connected to the in-pixel detection circuit and the corresponding first bus and second bus.

[0007] The in-pixel detection circuit comprises:

[0008] The Geiger avalanche detector and the quenching circuit convert the light pulse into a short-time voltage pulse after receiving the light pulse.

[0009] The pulse modulation signal digital circuit converts the short-time voltage pulse into a pulse width modulation signal.

[0010] The in-pixel multiplication circuit comprises a weight selector, a first D flip-flop, a first gate signal generator, a second gate signal generator, a third gate signal generator, a first current source group and a second current source group, the current sources in the first current source group are connected to a first bus, the current sources in the second current source group are connected to a second bus, and a gate switch module is arranged between each current source and the bus, one input end of the weight selector is connected to a second output end of the first D flip-flop of the in-pixel multiplication circuit of a pixel in a same row in a same column, the other input end is connected to a first output end of the first D flip-flop of the in-pixel multiplication circuit of a pixel in the same row in the previous column, and the output end is connected to an input end of the first D flip-flop, an input end of the first gate signal generator, an input end of the second gate signal generator and an output end of the third gate signal generator respectively, the other input end of the first gate signal generator is connected to an output end of the corresponding in-pixel detection circuit, and the output end is connected to all the gate switch modules, the output end of the second gate signal generator is connected to the gate switch module corresponding to the first current source group, and the output end of the third gate signal generator is connected to the gate switch module corresponding to the second current source group.

[0011] The weight of the output of the weight selector is a binary sequence, comprising a 1-bit sign bit and a plurality of non-sign bits.

[0012] The first gate signal generator is configured to sum all the non-sign bits, and generate a first gate signal based on the sum result.

[0013] The second gate signal generator is configured to read the sign bit, and generate a second gate signal based on the sign bit.

[0014] The third gate signal generator is configured to invert the sign bit, and generate a third gate signal based on the inversion result of the sign bit, and the second gate signal and the third gate signal are in opposite phases.

[0015] The first gate signal generator is an AND gate circuit.

[0016] The gate switch module comprises two gate switches, one of which is connected to the first gate signal generator, the other of which is connected to the second gate switch generator corresponding to the current source in the first current source group, and the other of which is connected to the third gate signal generator corresponding to the current source in the second current source group.

[0017] The first current source group and the second current source group each have 7 current sources, and the non-sign bit of the weight has 3 bits.

[0018] The detection front end comprises a laser.

[0019] The analog-to-digital conversion and readout circuit comprises an analog-to-digital converter, a readout selector and a second D flip-flop, the input end of the analog-to-digital converter is connected to the differential calculation capacitor, the output end is connected to the readout selector, and the readout selector is connected to the second D flip-flop.

[0020] Compared with the prior art, the present application has the following beneficial effects: by fusing the convolution calculation circuit in the traditional laser radar detection circuit, the integration design of detection and calculation is completed. Compared with the traditional separation design of sensing end and calculation end, the present application greatly improves the energy efficiency of the detection system, reduces the delay of calculation, reduces the bandwidth consumption and power consumption caused by the movement of redundant data. At the same time, the present application uses laser radar as the sensing end, which has a wide application significance and a deep research significance compared with the traditional two-dimensional image detection as the sensing end. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a structure block diagram of a laser radar detection system integrating sensing and calculation.

[0022] Figure 2 It is a whole schematic diagram of a laser radar detection front end.

[0023] Figure 3 It is a schematic diagram of a pixel-in detection circuit in a laser radar detection front end.

[0024] Figure 4 It is a schematic diagram of a pixel-in multiplication circuit

[0025] Figure 5 It is a schematic diagram of a pixel array accumulation circuit.

[0026] Figure 6 It is a schematic diagram of a multi-column charge fusion circuit working mode in a pixel array accumulation circuit.

[0027] Figure 7 It is a schematic diagram of an analog-to-digital conversion and readout circuit. DETAILED DESCRIPTION

[0028] The application will be described in detail below with reference to the drawings and specific embodiments. The embodiments are implemented on the premise of the technical solutions of the application, and detailed implementation modes and specific operation processes are given, but the protection scope of the application is not limited to the following embodiments.

[0029] Figure 1 Figure 1 is a structural block diagram of a laser radar detection system integrated with sensing and computing for an embodiment. The detection system is used to realize three-dimensional spatial information detection of a target and processing of original detection data. The detection target can be a static target or a dynamic target; the processing of the original data supports spatially related convolution operation on the original data. Referring to Figure 1, the laser radar detection system 10 integrated with sensing and computing includes a laser radar detection front end 100, an in-pixel multiplication circuit 200, a pixel array accumulation circuit 300, and a convolution result analog-digital conversion and readout circuit 400. Figure 1

[0030] Figure 2 Figure 2 is a schematic diagram of the laser radar detection front end 100 as a whole for an embodiment. The laser 110 emits a laser pulse at T start , and the reflected pulse from the target reaches the pixel array 120 at T signal . In this process, each pixel corresponds to a different field of view, and the received reflected pulse time is different, forming a series of original input light pulses 130. After the original input light pulses 130 pass through the in-pixel sensing circuit 140, they are converted into a series of pulse width modulation signals 144.

[0031] The in-pixel detection circuit 140 in the laser radar detection front end is as described in Figure 3 . After receiving the light pulse, it can be converted into a short-time voltage pulse 142, and after passing through the pulse modulation signal digital circuit 143, it can be converted into a pulse width modulation signal 144 used for in-pixel convolution input.

[0032] Figure 4 Figure 3 is a schematic diagram of the in-pixel multiplication circuit 200 for an embodiment. 211, 212, 213, 214, 215, and 216 constitute a data path for weight shifting and storage. The 4-bit weight 211 from the left pixel and the 4-bit weight 212 from the upper pixel are input to the weight selector 213, which selects the weight used in the current detection frame. The D flip-flop 214 is used to register the weight of the current detection frame, generating the weight output 215 to the right pixel and the weight output 216 to the lower pixel. The pulse width modulation signal 144 from the laser radar detection front end 140 is used as the signal input 220 of the current detection frame. The signal input 220 of the current detection frame and each bit of the weight output by the weight selector 213 except the highest bit pass through the AND gate logic, generating the time-gated signal 231, i.e., the first time-gated signal, which includes T​B0 to T B2 The highest bit weight output by the weight selector 213 generates another set of gate signals 232 and 233 through inverters, which are the second and third gate signals. The in-pixel multiplication circuit 200 includes two sets of sub-threshold current sources 234, each of which includes 7 branches of the same branch. The time gate signal 231 (including T B0 , T B1 , T B2 ) controls the 1st, 2nd and 4th branches in the two sets of current sources, respectively, corresponding to the proportional coefficients in the weights. The gate signals 232 and 233 generated by the highest bit of the weights control the conduction of the unilateral current sources. The two sets of current sources are connected to two buses 241 and 242, i.e., the first bus and the second bus. At the beginning of the calculation, the proportional current generated according to the proportional coefficients of the weights and the integral time generated by the time gate signal 231 linearly discharge one of the buses 241 and 242. The voltage difference between the two buses 241 and 242 is the in-pixel multiplication result.

[0033] Figure 5 Fig. 10 is a schematic diagram of a pixel array accumulation circuit 300. The pixel array accumulation circuit 300 includes a complete pixel 310 array composed of the in-pixel detection circuit 140 and the in-pixel multiplication circuit 200 in the front end; a set of differential calculation capacitors 321 and 322 connected to the two buses 241 and 242 in the array, serving as devices for charge accumulation and discharge; in an embodiment, a plurality of rows of pixels are convolved, and the multiplication results of each column are accumulated in the differential calculation capacitors 321 and 322 to complete the partial product summation of a single column of the convolution kernel. In this embodiment, the pixel array accumulation circuit 300 further includes a plurality of column charge fusion circuits 330 to complete the summation of the partial sums of multiple columns and obtain the final analog domain convolution result.

[0034] Figure 6 Fig. 11 is a schematic diagram of the working mode of the column charge fusion circuit 330 in the pixel array accumulation circuit. The bottom of each column of pixels includes a set of differential calculation capacitors 331, in which different calculation polarity capacitors 332 and 334 in different columns need to be summed up. The 336 control logic generates a series of control signals according to the size of the convolution kernel and the step state of the current calculation frame to control the transmission gate switch 335 between the differential calculation capacitors 321 and 322. When the transmission gate is turned on, voltage transformation is completed according to the principle of charge redistribution. In an embodiment, the size of the convolution kernel is 3x3, and the partial sums of three columns need to be accumulated. Assuming that the voltage values of the three columns of positive polarity capacitors 321 are V1 + , V2 + , V3 + , after the transmission gate is turned on, the summed voltage value V + =(V1 + +V2+ +V-3 + ) / 3, and V - , and finally V + -V - , which is the convolution result of the current kernel in the analog domain.

[0035] Figure 7 Fig. 4 is a schematic diagram of the analog-to-digital conversion and readout circuit 400. After the analog domain convolution result is obtained by the multi-column charge fusion circuit 330, the voltages on the last group of different calculation polarity capacitors 332 and 334 in each group of three columns are taken as the differential input terminals 411 and 412 of the 8-bit successive approximation analog-to-digital converter 420; the readout logic includes a readout selector 430 and a D flip-flop 440, and in the figure, ADCLK controls the working mode of the readout logic, and the input end of the gated D flip-flop 440 is connected to the output of the 8-bit successive approximation analog-to-digital converter 420 (register mode) or the previous stage D flip-flop 440 (readout mode); RDCLK is the working clock of the D flip-flop 440, and in the readout mode, the 8-bit convolution result 450 in the form of a group of digital signals converted in the array is output in series, and the final convolution calculation is completed.

Claims

1. A sensing and computing integrated lidar detection chip, characterized in that, The pixel array includes a plurality of columns of pixels, a first bus and a second bus corresponding to each column, and a first differential calculation capacitor and a second differential calculation capacitor corresponding to each column, the first bus is connected to the first differential calculation capacitor, the second bus is connected to the second differential calculation capacitor, and a first transfer gate switch is connected between the first buses of adjacent columns, and a second transfer gate switch is connected between the second buses of adjacent columns.

2. The sensing and computing integrated lidar detection chip of claim 1, wherein, The in-pixel detection circuit includes: A Geiger avalanche detector and a quenching circuit, which converts a light pulse into a short-time voltage pulse after receiving the light pulse; A pulse modulation signal digital circuit, which converts the short-time voltage pulse into a pulse width modulation signal.

3. The sensing and computing integrated lidar detection chip of claim 1, wherein, The in-pixel multiplication circuit includes a weight selector, a first D flip-flop, a first gate signal generator, a second gate signal generator, a third gate signal generator, a first current source group, and a second current source group, the current sources in the first current source group are connected to the first bus, the current sources in the second current source group are connected to the second bus, and a gate switch module is provided between each current source and the bus, one input end of the weight selector is connected to the second output end of the first D flip-flop of the in-pixel multiplication circuit of the pixel in the same column in the previous row, the other input end is connected to the first output end of the first D flip-flop of the in-pixel multiplication circuit of the pixel in the same row in the previous column, and the output end is connected to the input end of the first D flip-flop, one input end of the first gate signal generator, the input end of the second gate signal generator, and the output end of the third gate signal generator, respectively, the other input end of the first gate signal generator is connected to the output end of the corresponding in-pixel detection circuit, and the output end is connected to all gate switch modules, the output end of the second gate signal generator is connected to the gate switch module corresponding to the first current source group, and the output end of the third gate signal generator is connected to the gate switch module corresponding to the second current source group.

4. The sensing and computing integrated lidar detection chip of claim 3, wherein, The weight of the output of the weight selector is a binary sequence, including a 1-bit sign bit and a plurality of non-significant bits. The first gate signal generator is configured to sum all non-significant bits, and generate a first gate signal based on the sum result. The second gate signal generator is configured to read the sign bit, and generate a second gate signal based on the sign bit. The third gate signal generator is configured to invert the sign bit, and generate a third gate signal based on the inverted sign bit, and the second gate signal and the third gate signal are in opposite phases.

5. The sensing and computing integrated lidar detection chip of claim 4, wherein, The first gate signal generator is an AND gate circuit.

6. The sensing and computing integrated lidar detection chip of claim 3, wherein, The gate switch module includes two gate switches, one of which is connected to a first gate signal generator, another of which is connected to a second gate switch generator corresponding to a current source in the first current source group, and another of which is connected to a third gate signal generator corresponding to a current source in the second current source group.

7. The sensing and computing integrated lidar detection chip of claim 4, wherein, The first current source group and the second current source group each have 7 current sources, and the non-sign bits of the weight have a total of 3 bits.

8. The sensing and computing integrated lidar detection chip of claim 1, wherein, The detection front end includes a laser.

9. The sensing and computing integrated lidar detection chip of claim 3, wherein, The analog-to-digital conversion and readout circuit includes an analog-to-digital converter, a readout selector, and a second D flip-flop, the input end of the analog-to-digital converter is connected to a differential calculation capacitor, the output end is connected to the readout selector, and the readout selector is connected to the second D flip-flop.

10. The sensing and computing integrated lidar detection chip of claim 9, wherein, The analog-to-digital converter is an 8-bit successive approximation type analog-to-digital converter.

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