Display substrate, display panel and display device

Abstract

This invention discloses a display substrate, a display panel, and a display device. The display substrate includes a display area and a fan-out area, and the fan-out area includes multiple fan-out sub-areas. Each fan-out sub-area includes a first group of pins and a second group of pins. The first group of pins includes m first pins, and the second group of pins includes m second pins, where m > 1. In a first direction, the first pins and second pins are alternately arranged in the nth fan-out sub-area, and the second pins and first pins are alternately arranged in the (n+1)th fan-out sub-area, where n is a positive odd number. The first pins are connected to a first adapter pin disposed on the same layer as the second pins, and the second pins are connected to a second adapter pin disposed on the same layer as the first pins. In the nth fan-out sub-area, the first pins are led out to the display area through a first lead, and the second pins are led out to the display area through a second lead. In the (n+1)th fan-out sub-area, the second pins are led out to the display area through a first lead, and the first pins are led out to the display area through a second lead.

Description

Technical Field

[0001] This invention relates to the field of display technology. More specifically, it relates to a display substrate, a display panel, and a display device. Background Technology

[0002] With the development of information technology, electronic devices are widely used in people's daily lives, and display technology is developing rapidly.

[0003] In traditional panel designs, most panels have multiple fan-out sub-regions within their fan-out area. The pins of each sub-region are arranged in double rows. Furthermore, to eliminate display defects caused by electrostatic discharge, the first and second rows of pins are placed in different metal layers. Additionally, because the start and end positions of the pins are determined by the IC channel, the pin cycle order of adjacent fan-out sub-regions on the display panel is inconsistent. The adjacent pins of left and right fan-out sub-regions are located in the same metal layer, causing a split-screen phenomenon when displaying specific images. Summary of the Invention

[0004] The purpose of this invention is to provide a display substrate, a display panel, and a display device to solve at least one of the problems existing in the related technologies.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] The first aspect of the present invention provides a display substrate, including a display area and a fan-out area located on one side of the display area, the fan-out area including a plurality of fan-out sub-regions arranged along a first direction;

[0007] The fan-out sub-region includes a first group of pins and a second group of pins arranged along a second direction, the second direction being orthogonal to the first direction. The first group of pins includes m first pins arranged along the first direction, and the second group of pins includes m second pins arranged along the first direction, where m > 1. In the first direction, the first pins and second pins are alternately arranged in the nth fan-out sub-region, and the second pins and first pins are alternately arranged in the (n+1)th fan-out sub-region, where n is a positive odd number.

[0008] Wherein, the first pin is connected to a first adapter pin that is set on the same layer as the second pin, and the second pin is connected to a second adapter pin that is set on the same layer as the first pin;

[0009] In the nth fan-out sub-region, the first pin is led out to the display area through the first lead and the second pin is led out to the display area through the second lead; in the (n+1)th fan-out sub-region, the second pin is led out to the display area through the first lead and the first pin is led out to the display area through the second lead.

[0010] The first lead is disposed on the same layer as one of the first pin and the second pin, and the second lead is disposed on the same layer as the other of the first pin and the second pin.

[0011] Optionally, the display area includes an array of thin-film transistors, the source and drain of which are formed in a source-drain metal layer;

[0012] One of the first pin and the second pin is disposed in the same layer as the gate of the thin-film transistor, and the other is disposed in the same layer as the source and drain metal layers.

[0013] Optionally, the first adapter pin is located on the side of the first pin closer to the display area, and the second adapter pin is located on the side of the second pin closer to the display area.

[0014] Optionally, multiple first leads may have the same line width, and multiple second leads may have the same line width.

[0015] Optionally, the first pin is connected to a first adapter pin disposed on the same layer as the second pin via a first via.

[0016] The second pin is connected to a second adapter pin located on the same layer as the first pin via a second via.

[0017] Optionally, the display substrate further includes an insulating layer, which comprises a first insulating layer and a second insulating layer.

[0018] The first insulating layer is located between the first pin and the second pin;

[0019] The second insulating layer is located on the side of the second pin opposite to the first pin;

[0020] The first via includes a third via exposing the first pin and a fourth via exposing the first adapter pin; the second via includes a fifth via exposing the second pin and a sixth via exposing the second adapter pin.

[0021] The fan-out sub-region also includes a first transfer electrode and a second transfer electrode.

[0022] The first adapter electrode is electrically connected to the first pin through the third via and electrically connected to the first adapter pin corresponding to the first pin through the fourth via;

[0023] The second adapter electrode is electrically connected to the second pin through the fifth via and to the second adapter pin corresponding to the second pin through the sixth via.

[0024] Optionally, the first and second transfer electrodes are indium tin oxide electrodes.

[0025] A second aspect of the present invention provides a display panel comprising the display substrate provided in the first aspect of the present invention.

[0026] Optionally, the display panel further includes:

[0027] The opposing substrate is disposed opposite to the display substrate;

[0028] A liquid crystal layer is located between the display substrate and the opposing substrate.

[0029] A third aspect of the present invention provides a display device including the display panel provided in the second aspect of the present invention.

[0030] The beneficial effects of this invention are as follows:

[0031] An embodiment of the present invention provides a display substrate having a first group of pins and a second group of pins arranged in a second direction. The first group of pins and the second group of pins are led out to the display area through alternately arranged first leads and second leads, and are provided with adapter pins. The first pin in the first group of pins is connected to a first adapter pin that is arranged on the same layer as the second pin in the second group of pins; the second pin in the second group of pins is connected to a second adapter pin that is arranged on the same layer as the first pin in the first group of pins. This allows the pins to be connected to the display area in the same order regardless of the IC channel selection, so that there will be no situation where two adjacent leads are arranged on the same layer in the fan-out area. Thus, under a specific screen, the driving order of different fan-out sub-areas is consistent, and there is no significant difference in brightness, solving the screen splitting problem of the display substrate. Attached Figure Description

[0032] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0033] Figure 1 A schematic diagram of the structure of a fan-out region in the prior art is shown.

[0034] Figure 2 A schematic diagram of the structure of a display substrate in the prior art is shown.

[0035] Figure 3 An embodiment of the prior art is presented. Figure 1 Cross-sectional view of R-R'.

[0036] Figure 4 A schematic diagram of the structure of a display substrate according to an embodiment of the prior art is shown.

[0037] Figure 5 A schematic diagram of a display substrate proposed in an embodiment of the prior art is shown.

[0038] Figure 6 A schematic diagram of the structure of a display substrate proposed in one embodiment of the present invention is shown.

[0039] Figure 7 A schematic diagram of the structure of the fan-out region proposed in one embodiment of the present invention is shown.

[0040] Figure 8 A schematic diagram of the structure of a display substrate according to an embodiment of the present invention is shown.

[0041] Figure 9 A schematic diagram of a display substrate according to an embodiment of the present invention is shown.

[0042] Figure 10-13 A schematic diagram of the fan-out region proposed in one embodiment of the present invention is shown. Detailed Implementation

[0043] To more clearly illustrate the present invention, the following description, in conjunction with embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.

[0044] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, this does not indicate any order, quantity, or importance, but is merely used to distinguish different components. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Words such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0046] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0047] In the description of the embodiments of this disclosure, the technical terms such as "center" and "edge" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this disclosure.

[0048] In traditional panel design, when designing the display substrate on the glass side, the integrated circuit output pads in the fan-out area typically employ a dual-row design. In a specific example, such as... Figure 1 As shown, the fan-out region includes fan-out sub-regions P and Q located on the left and right sides. Since power lines C need to be placed below the integrated circuit output pins, and the impedance of power lines C is required to be very low, the power lines need to be designed to be very wide. Furthermore, to avoid electrostatic discharge issues, the distance D between the power line C, fabricated on the same layer as the gate, and the output pin A, also fabricated on the same layer as the gate, cannot be too small; the distance D between the power line C and the output pin A, fabricated on the same layer as the gate, needs to be greater than or equal to 50 micrometers. Based on the above considerations, the first row of the fan-out region integrated circuit consists of first-type output pins A, fabricated on the same layer as the gate; the second row consists of second-type output pins B, fabricated on the same layer as the source and drain; the third row contains power lines C, and the fan-out traces connected to the output pins are fabricated on the same layer as their corresponding output pins.

[0049] like Figure 2 As shown, the output pins on the right side of the fan-out sub-region P end with the second type of output pin B, while the output pins on the left side of the fan-out sub-region Q also start with the second type of output pin B, resulting in the corresponding two adjacent fan-out traces being on the same metal layer, and the looping patterns of the fan-out sub-regions P and Q being inconsistent.

[0050] Specifically, the first fan-out sub-region corresponds to the sequentially arranged output pins 1 to 720, cycling starting with the first type of output pins; the second fan-out sub-region corresponds to the sequentially arranged output pins 721 to 1440, cycling starting with the second type of output pins; both output pins 720 and 721 are second type output pins, and the cycling patterns of the first and second fan-out sub-regions are different. The first fan-out sub-region cycles through first type output pins A and second type output pins B, i.e., AB alternates; the second fan-out sub-region cycles through second type output pins B and first type output pins A, i.e., BA alternates. Correspondingly, as... Figure 3 The figure shows a cross-sectional view obtained along the R-R' section line, in which the first lead 103 connected to the first type of output pin and the second lead 203 connected to the second type of output pin are respectively disposed on different film layers.

[0051] In a specific example, such as Figure 4 As shown, the fan-out area includes fan-out sub-areas P, Q, W, and U arranged from left to right, and their display effect under a specific screen is as follows. Figure 5 As shown, a clear split-screen phenomenon can be observed, with a significant difference in brightness between two adjacent fan-out sub-regions.

[0052] The inventors' analysis revealed that the main reason for this phenomenon is that, in the actual production process, the first type of output pins and the second type of output pins are located on different layers, prepared at different times using different deposition processes, and even prepared using different equipment and in different factories. This results in differences in the width and film thickness of the first type of output pins and the second type of output pins. This difference is amplified when charging is insufficient, leading to… Figure 5 The screen splitting phenomenon shown exhibits significant brightness differences.

[0053] Specifically, actual resistance measurements revealed that the trace resistance in brighter areas was lower than that in darker areas, indicating a thicker film layer. The specific relationship is as follows: thicker film layer / wider line width results in lower resistance, higher charging rate, and brighter display brightness.

[0054] Based on the above considerations, one embodiment of the present invention provides a display substrate, such as... Figure 6 , Figure 7 , Figure 8 , Figure 9 As shown, the display substrate includes a display area (Active Area, AA) and a fan-out area located on one side of the display area. The fan-out area includes a plurality of fan-out sub-areas arranged along a first direction x.

[0055] The fan-out sub-region includes a first group of pins 10 and a second group of pins 20 arranged along the second direction y, the second direction y being orthogonal to the first direction x. The first group of pins 10 includes m first pins 101 arranged along the first direction x, and the second group of pins 20 includes m second pins 201 arranged along the first direction x, where m > 1. In the first direction, the first pins and second pins are alternately arranged in the nth fan-out sub-region, and the second pins and first pins are alternately arranged in the (n+1)th fan-out sub-region, where n is a positive odd number.

[0056] Wherein, the first pin 101 is connected to the first adapter pin 102 which is arranged on the same layer as the second pin 201, and the second pin 201 is connected to the second adapter pin 202 which is arranged on the same layer as the first pin 101;

[0057] In the nth fan-out sub-region, the first pin 101 is led out to the display area through the first lead 103 and the second pin 201 is led out to the display area through the second lead 203; in the (n+1)th fan-out sub-region, the second pin 201 is led out to the display area through the first lead 103 and the first pin 101 is led out to the display area through the second lead 203.

[0058] The first lead 103 is disposed on the same layer as one of the first pin 101 and the second pin 201, and the second lead 203 is disposed on the same layer as the other of the first pin 101 and the second pin 201.

[0059] This embodiment features a first group of pins 10 and a second group of pins 20 arranged in a second direction. The first group of pins 10 and the second group of pins 20 are led out to the display area via alternately arranged first leads 103 and second leads 203, and adapter pins are provided. The first pin 101 of the first group of pins 10 is connected to a first adapter pin 102 disposed on the same layer as the second pin 201 of the second group of pins 20; the second pin 201 of the second group of pins 20 is connected to a second adapter pin 202 disposed on the same layer as the first pin 101 of the first group of pins 10. This ensures that regardless of the IC channel selection, the pins can be connected to the display area via leads in the same order, preventing adjacent leads from being disposed on the same layer in the fan-out area. Therefore, under a specific screen display, the driving sequence of different fan-out sub-areas is consistent, eliminating significant brightness differences and solving the screen splitting problem of the display substrate. Figure 9 As shown, this is the actual display effect of the display substrate in this disclosure. The display brightness is uniform and there is no screen splitting phenomenon.

[0060] In one specific example, the display substrate further includes multiple scan lines and data lines disposed in the display area. The multiple scan lines and data lines are arranged intersectingly, and the multiple scan lines and data lines divide the display area into multiple sub-pixels. Each sub-pixel includes a thin-film transistor and a pixel electrode.

[0061] In one specific example, the display area includes an array of thin-film transistors, the sources and drains of which are formed in a source-drain metal layer.

[0062] One of the first pin 101 and the second pin 201 is disposed in the same layer as the gate of the thin-film transistor, and the other is disposed in the same layer as the source and drain metal layers.

[0063] The gate of the thin-film transistor is disposed on the same layer as the scan line and the corresponding lead and is electrically connected. The source and drain of the thin-film transistor are disposed on the same layer as the data line and the lead of the corresponding fan-out region. The source of the thin-film transistor is electrically connected to the data line, and the drain of the thin-film transistor is electrically connected to the pixel electrode.

[0064] Specifically, the thin-film transistor can be a top-gate structure or a bottom-gate structure. In the top-gate structure, the active layer is located between the gate and the substrate, while in the bottom-gate structure, the active layer is located between the gate and the drain and source.

[0065] In a specific example, with Figure 6 The following is a detailed description using the illustrated display substrate as an example: The fan-out area includes a first fan-out sub-area K and a second fan-out sub-area L, whose pins are connected to the data lines of the display area via leads. The first fan-out sub-area K corresponds to the first data line D1 to the 720th data line D720, and the second fan-out sub-area L corresponds to the 721st data line D721 to the 1440th data line D1440.

[0066] Each fan-out sub-region includes a first group of pins 10 and a second group of pins 20 arranged in the second direction y. The first group of pins 10 of the first fan-out sub-region K includes 360 first pins 101 arranged in the first direction x, and the second group of pins 20 of the first fan-out sub-region K includes 360 second pins 201 arranged in the first direction x. The first group of pins 10 of the second fan-out sub-region L includes 360 first pins 101 arranged in the first direction x, and the second group of pins 20 of the second fan-out sub-region L includes 360 second pins 201 arranged in the first direction x.

[0067] Specifically, each first pin 101 in the first group of pins 10 of the first fan-out sub-region K is led out to the display area through a first lead 103, that is, connected to the data signal line of the display area through the first lead 103; each second pin 201 in the second group of pins 20 of the first fan-out sub-region K is led out to the display area through a second lead 203, that is, connected to the data signal line of the display area through the second lead 203.

[0068] In contrast to the first fan-out sub-region K, each first pin 101 in the first group of pins 10 of the second fan-out sub-region L is led out to the display area through the second lead 203, that is, connected to the data signal line of the display area through the second lead 203; each second pin 201 in the second group of pins 20 of the second fan-out sub-region L is led out to the display area through the first lead 103, that is, connected to the data signal line of the display area through the first lead 103.

[0069] Specifically, the present invention is provided with an adapter pin, which can be electrically connected to the lead regardless of whether the pin is set on the same layer as the lead. In this example, the lead, i.e. the fan-out line of the fan-out area, is arranged alternately, and the cyclic order of the fan-out lines of each fan-out sub-region is consistent. The adjacent fan-out lines of two adjacent fan-out sub-regions, such as the first fan-out sub-region K and the second fan-out sub-region L, are located on different film layers, which avoids the situation that the two adjacent traces of two adjacent fan-out sub-regions are set on the same layer. Through the design, the leads connecting adjacent pins between different fan-out areas are not on the same layer.

[0070] It should be noted that the accompanying drawings in this invention are only for illustrating the structure of the substrate. Some parts are drawn in an exaggerated manner to facilitate understanding. The dimensions and proportions in the drawings do not represent the actual dimensions and proportions.

[0071] In addition, for areas where the fan-out line and the output pin are on the same layer, it is not necessary to set an adapter pin. The output pin can be directly led out to the display area through the fan-out line on the same layer.

[0072] In one specific embodiment, the display substrate includes two driving chips, such as... Figure 8 As shown, the first driving chip is led out to the display area of ​​the display substrate through the first fan-out sub-region and the second fan-out sub-region, and the second driving chip is led out to the display area of ​​the display substrate through the third fan-out sub-region and the fourth fan-out sub-region.

[0073] It should be noted that the number of driving chips corresponding to the display substrate can be 1, 2 or 3, which can be set according to the specific situation, and no specific limitation is made here.

[0074] In an optional embodiment, the first lead is disposed on the same layer as the first pin, that is, on the same layer as the gate of the display area, and the second lead is disposed on the same layer as the second pin, that is, on the same layer as the source and drain metal layers of the display area. The first lead and the second lead can be straight or broken.

[0075] In another alternative embodiment, the first lead and the second pin are disposed on the same layer, that is, on the same layer as the source and drain metal layer of the display area, and the second lead and the first pin are disposed on the same layer, that is, on the same layer as the gate of the display area.

[0076] In a specific embodiment, such as Figure 8 As shown, the first adapter pin is located on the side of the first pin closer to the display area, and the second adapter pin is located on the side of the second pin closer to the display area. The first lead and the second lead can be straight or broken.

[0077] In this embodiment, an adapter pin electrically connected to the output pin is added. The adapter pin and the corresponding output pin are located on different film layers. Regardless of whether the pin is set on the same layer as the lead wire, it can be electrically connected to it. The wiring design of the fan-out area can be carried out in a unified order. The order will not be swapped in the interval of the fan-out sub-area. By adopting the above-mentioned design, the problem of large difference between brightness and darkness and screen splitting is solved.

[0078] In one specific embodiment, multiple first leads 103 have the same line width, and multiple second leads 203 have the same line width.

[0079] This embodiment sets the line width of multiple first leads to be the same, and the line width of multiple second leads to be the same, so that the line width of the first leads, the second leads, and the multiple data lines on the corresponding display substrate are also consistent. This makes the resistance and charging rate of the multiple leads consistent, and the brightness of the corresponding display substrate is also consistent, further solving the problem of display splitting.

[0080] In one specific embodiment, the film thickness of the multiple first leads is the same, and the film thickness of the multiple second leads is the same.

[0081] This embodiment sets the film thickness of multiple first leads to be the same, and the film thickness of multiple second leads to be the same, so that the film thickness of the first leads, second leads and multiple data lines on the corresponding display substrate are consistent, thereby making the charging rate of multiple leads consistent and the brightness of the corresponding display substrate consistent, further solving the problem of display splitting.

[0082] In one specific embodiment, the first pin 101 is connected to the first adapter pin 102, which is disposed on the same layer as the second pin 201, through a first via.

[0083] The second pin 201 is connected to the second adapter pin 202, which is disposed on the same layer as the first pin 101, through the second via.

[0084] In a specific example, such as Figure 10 As shown, along Figure 7 The cross-sectional view obtained by cutting along the d-d' section line shows that the display substrate includes a first insulating layer 301 and a second insulating layer 302. The first pin 101 located in the first fan-out sub-region K is disposed on the same layer as the first lead 103. The first pin 101 and the first lead 103 are disposed between the first insulating layer 301 and the second insulating layer 302. A first via is provided on the first insulating layer, penetrating to the first pin 101. The first adapter pin 102 is electrically connected to the first pin 101 through the first via.

[0085] In a specific example, such as Figure 11 As shown, along Figure 7 The cross-sectional view obtained by cutting along line e-e' shows that the display substrate includes a first insulating layer 301 and a second insulating layer 302. The second pin 201 and the second lead 203 located in the first fan-out sub-region K are disposed on the same layer. The second pin 201 and the second lead 203 are disposed on the first insulating layer 301 and are electrically connected to the second adapter pin 202 through a second through hole disposed on the first insulating layer.

[0086] It should be noted that the present invention does not specifically limit whether the orthogonal projection of the adapter pin on the substrate or the orthogonal projection of the pin on the substrate covers each other.

[0087] In one specific embodiment, the display substrate further includes an insulating layer, which comprises a first insulating layer 301 and a second insulating layer 302.

[0088] The first insulating layer 301 is located between the first pin 101 and the second pin 201;

[0089] The second insulating layer 302 is located on the side of the second pin 201 opposite to the first pin 101.

[0090] In one specific embodiment, the first via includes a third via exposing the first pin 101 and a fourth via exposing the first adapter pin 102, and the second via includes a fifth via exposing the second pin 201 and a sixth via exposing the second adapter pin 202.

[0091] The fan-out sub-region also includes a transfer electrode 303, comprising a first transfer electrode and a second transfer electrode.

[0092] The first adapter electrode is electrically connected to the first pin through the third via and electrically connected to the first adapter pin corresponding to the first pin through the fourth via;

[0093] The second adapter electrode is electrically connected to the second pin through the fifth via and to the second adapter pin corresponding to the second pin through the sixth via.

[0094] Specifically, such as Figure 12 As shown, along Figure 7The cross-sectional view taken along section line b-b' shows that the first pin 101 and the second adapter pin 202 located in the second fan-out sub-region L are on different film layers; the third via penetrates through the second insulating layer 302 to the first pin 101 to expose the first pin 101, and the fourth via penetrates through the second insulating layer to the first adapter pin 102, which is disposed on the same layer as the second pin, to expose the first adapter pin 102. After the third and fourth vias are fabricated, conductive material is laid on them to form the first adapter electrode.

[0095] Specifically, such as Figure 13 As shown, along Figure 7 The cross-section line c-c' shows that the second pin 201 and the second adapter pin 202 in the second fan-out sub-region L are located in different film layers. The fifth via penetrates the second insulating layer 302 to expose the second pin 201. The sixth via penetrates the first insulating layer 301 and the second insulating layer 302 to expose the second adapter pin 202. After forming the fifth and sixth vias, a transparent conductive material such as indium tin oxide is laid on them to achieve the electrical connection between the second pin 201 and the second adapter pin 202.

[0096] In one specific embodiment, the first and second transfer electrodes are indium tin oxide electrodes.

[0097] One embodiment of the present invention provides a display panel, including the display substrate provided in the embodiment of the present invention.

[0098] The display panel in this embodiment includes a display substrate, whose fan-out area is provided with adapter pins corresponding to the pins. The first pin in the first group of pins is connected to the first adapter pin that is set on the same layer as the second pin in the second group of pins; the second pin in the second group of pins is connected to the second adapter pin that is set on the same layer as the first pin in the first group of pins. This allows the pins to be connected to the display area in the same order regardless of how the IC channel is selected. This prevents two adjacent wires from being set on the same layer in the fan-out area. As a result, the driving order of different fan-out sub-areas is consistent under a specific screen, and there is no significant difference in brightness, thus solving the split-screen problem.

[0099] Taking a liquid crystal display panel as an example, the display panel further includes:

[0100] The opposing substrate is disposed opposite to the display substrate;

[0101] A liquid crystal layer is located between the display substrate and the opposing substrate.

[0102] Specifically, the display substrate, the opposing substrate, and the liquid crystal layer are fixed together by a sealant.

[0103] It should be noted that the display panel is not limited to a liquid crystal display panel, but can also be an organic light-emitting diode display.

[0104] In one specific embodiment, the opposing substrate includes a color filter and a black matrix. The orthographic projection of the black matrix onto the substrate covers the orthographic projection of the scan lines and data lines onto the substrate. Therefore, the opening area of ​​the black matrix corresponds to the light-emitting area of ​​the sub-pixel.

[0105] The color filter includes filters corresponding to the colors of the sub-pixels. The sub-pixels include red sub-pixels, blue sub-pixels, and green sub-pixels. Accordingly, the color filter includes red filters, blue filters, and green filters.

[0106] One embodiment of the present invention provides a display device, the display device including the display panel provided in the embodiment of the present invention.

[0107] In one specific embodiment, the display device further includes a driver chip, which is connected to the data lines in the display panel via a first set of pins and a second set of pins in the fan-out sub-region.

[0108] Specifically, the driver chip includes a first driver chip and a second driver chip, each driver chip corresponding to two fan-out sub-regions. It should be noted that the number of driver chips can be set according to requirements and is not specifically limited here.

[0109] In one specific embodiment, the display device further includes a backlight module, and the display panel is located on the light-emitting side of the backlight module.

[0110] The display device provided in this embodiment of the invention includes any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0111] In the accompanying drawings, the size, proportion, or area of ​​the constituent elements are sometimes exaggerated for clarity. Therefore, embodiments of this disclosure are not necessarily limited to these dimensions, and the shape and size of each component in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate some examples, and embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0112] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A display substrate, characterized by, The display substrate comprises a display area and a fan-out area located on one side of the display area, the fan-out area comprises a plurality of fan-out sub-areas arranged along a first direction; The fan-out sub-area comprises a first group of pins and a second group of pins arranged along a second direction, the second direction is orthogonal to the first direction, the first group of pins comprises m first pins arranged along the first direction, the second group of pins comprises m second pins arranged along the first direction, m>1, in the first direction, the first pins and the second pins in the nth fan-out sub-area are arranged alternately, the second pins and the first pins in the n+1th fan-out sub-area are arranged alternately, n is a positive odd number; The first pins are connected to first adapter pins arranged in the same layer as the second pins, and the second pins are connected to second adapter pins arranged in the same layer as the first pins; The first pins in the nth fan-out sub-area are led out to the display area through first lead lines, and the second pins are led out to the display area through second lead lines, the second pins in the n+1th fan-out sub-area are led out to the display area through first lead lines, and the first pins are led out to the display area through second lead lines; The first lead lines are arranged in the same layer as one of the first pins and the second pins, and the second lead lines are arranged in the same layer as the other one of the first pins and the second pins; The first pins and the second pins are arranged in different layers.

2. The display substrate of claim 1, wherein The display area comprises a plurality of thin film transistors arranged in an array, the source and drain electrodes of the thin film transistors are formed in a source-drain metal layer; One of the first pins and the second pins is arranged in the same layer as the gate electrode of the thin film transistor, and the other one is arranged in the same layer as the source-drain metal layer.

3. The display substrate of claim 1, wherein The first adapter pins are located on the side of the first pins close to the display area, and the second adapter pins are located on the side of the second pins close to the display area.

4. The display substrate of claim 1, wherein The line widths of the plurality of first lead lines are the same, and the line widths of the plurality of second lead lines are the same.

5. The display substrate of claim 1, wherein The first pins are connected to the first adapter pins arranged in the same layer as the second pins through first vias; The second pins are connected to the second adapter pins arranged in the same layer as the first pins through second vias.

6. The display substrate of claim 5, wherein The display substrate further comprises an insulating layer, the insulating layer comprises a first insulating layer and a second insulating layer, The first insulating layer is located between the first pins and the second pins; The second insulating layer is located on the side of the second pins away from the first pins; The first via comprises a third via exposing the first pins and a fourth via exposing the first adapter pins, and the second via comprises a fifth via exposing the second pins and a sixth via exposing the second adapter pins; The fan-out sub-area further comprises a first adapter electrode and a second adapter electrode, The first transition electrode is electrically connected with the first pin through the third via hole and is electrically connected with a first transition pin corresponding to the first pin through the fourth via hole. The second transition electrode is electrically connected with the second pin through the fifth via hole and is electrically connected with a second transition pin corresponding to the second pin through the sixth via hole.

7. The display substrate of claim 6, wherein: The first transition electrode and the second transition electrode are indium tin oxide electrodes.

8. A display panel, characterized by, A display substrate according to any one of claims 1-7.

9. The display panel of claim 8, wherein: The display panel further comprises: A counter substrate disposed opposite to the display substrate; A liquid crystal layer between the display substrate and the counter substrate.

10. A display device, characterized by comprising: A display panel according to claim 9 and a driving chip, wherein the driving chip is connected with the data lines in the display panel through the first group of pins and the second group of pins of the fan-out sub-area.

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