FC network clock synchronization method and system

Abstract

The present invention discloses a FC network clock synchronization method and system, the method comprising: a switch of the FC network receives a standard clock sent by a source node of the FC network, and obtains a clock frequency difference and a clock phase difference according to the standard clock and the local clock of the switch; the switch corrects the local clock of the switch according to the clock frequency difference and the clock phase difference, obtains the corrected local clock of the switch and sends it to each node of the FC network connected to the switch, so that the local clock of each node corresponding to the switch is synchronized with the standard clock. The present invention obtains data sent by the source node based on a high-precision clock source, so that the node and the switch extract the clock from the received data and complete the clock synchronization of the entire FC network, thereby improving the accuracy of the FC network clock synchronization.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization, and in particular to a FC network clock synchronization method and system. Background Art

[0002] The application of Fibre Channel (FC) technology in the aerospace field at home and abroad, along with the increase in the size of spacecraft and the number of various application payloads, the time synchronization of payloads is also facing challenges. On the one hand, the increase in the number of payloads expands the network topology, increases the uncertainty of network time synchronization and the complexity of implementation; on the other hand, the requirements of payloads for time accuracy are constantly increasing. High-precision time synchronization is of great significance to the coordinated operation of various systems on spacecraft, task scheduling and execution, fault finding and accident analysis.

[0003] The existing clock synchronization method can achieve nanosecond accuracy and does not require the installation of special GPS equipment, so the investment cost is low. However, this method uses an algorithm to calculate the timestamp to complete clock frequency synchronization, with an accuracy of nanoseconds, and no clock phase synchronization scheme is designed, so it is impossible to achieve sub-nanosecond synchronization.

[0004] The existing Ethernet solution can complete frequency transmission through the existing physical layer PHY of Ethernet, and because the clock transmitted in the network is extracted and recovered from the physical layer line code stream, it is not affected by the business load flow and the quality of clock transmission is guaranteed. However, the disadvantage is that it relies on the Ethernet-specific physical layer PHY, is not suitable for other protocols, and no clock phase synchronization solution is designed.

[0005] Therefore, it is urgent to provide a technical solution to solve the above problems. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a FC network clock synchronization method and system.

[0007] The technical solution of a FC network clock synchronization method of the present invention is as follows:

[0008] The switch of the FC network receives the standard clock sent by the source node of the FC network, and obtains a clock frequency difference and a clock phase difference according to the standard clock and the local clock of the switch;

[0009] The switch corrects the local clock of the switch according to the clock frequency difference and the clock phase difference, obtains the corrected local clock of the switch and sends it to each node of the FC network connected to the switch, so that the local clock of each node corresponding to the switch is synchronized with the standard clock.

[0010] The beneficial effects of the FC network clock synchronization method of the present invention are as follows:

[0011] The method of the present invention obtains data sent by a source node based on a high-precision clock source, so that the node and the switch extract the clock from the received data and complete the clock synchronization of the entire FC network, thereby improving the accuracy of the FC network clock synchronization.

[0012] Based on the above solution, the FC network clock synchronization method of the present invention can also be improved as follows.

[0013] Furthermore, the switch includes: an FPGA; and the process of obtaining the clock frequency difference and the clock phase difference by the switch includes:

[0014] The FPGA receives the standard clock sent by the source node, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch.

[0015] Furthermore, the switch further comprises: a digital-to-analog converter, a voltage-controlled oscillator and a phase-locked loop; the switch corrects the local clock of the switch according to the clock frequency difference and the clock phase difference to obtain the corrected local clock of the switch, comprising:

[0016] The digital-to-analog converter receives the clock frequency difference in digital form sent by the FPGA and performs digital-to-analog conversion to obtain the clock frequency difference in analog form and sends it to the voltage-controlled oscillator;

[0017] The voltage-controlled oscillator corrects the frequency of the local clock of the switch according to the clock frequency difference in the analog form, obtains and sends the corrected local clock frequency to the phase-locked loop;

[0018] The phase-locked loop receives and corrects the phase of the local clock of the switch according to the clock phase difference sent by the FPGA to obtain a corrected local clock phase, and obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency.

[0019] Further, the FPGA includes: a data receiving module, a data sending module, a frequency detector, a phase detector, a DAC control module and a PLL control module; the FPGA receives the standard clock sent by the source node, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch, including:

[0020] The data receiving module receives the standard clock sent by the source node, and sends the clock frequency of the standard clock to the frequency detector, and sends the clock phase of the standard clock to the phase detector;

[0021] The frequency detector compares the clock frequency of the standard clock with the clock frequency of the local clock of the switch, obtains a frequency compensation value and sends it to the DAC control module, so that the DAC control module obtains the clock frequency difference according to the frequency compensation value;

[0022] The phase detector compares the clock phase of the standard clock with the clock phase of the local clock of the switch, obtains a phase compensation value and sends it to the PLL control module, so that the PLL control module obtains the clock phase difference value according to the phase compensation value.

[0023] Further, the phase-locked loop includes: a reference clock input interface, a serial deserializer reference clock interface and a control interface;

[0024] The phase-locked loop receives and corrects the phase of the local clock of the switch according to the clock phase difference sent by the FPGA to obtain a corrected local clock phase, and obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency, comprising:

[0025] The phase-locked loop receives the clock phase difference sent by the PLL control module through the control interface, and corrects the phase of the local clock of the switch according to the clock phase difference to obtain a corrected local clock phase;

[0026] The phase-locked loop receives the corrected local clock frequency sent by the voltage-controlled oscillator through the reference clock input interface, obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency, and sends the corrected local clock of the switch through the serial deserializer reference clock interface.

[0027] Furthermore, the phase-locked loop further comprises: an auxiliary clock output interface; the step of the frequency detector comparing the clock frequency of the standard clock with the clock frequency of the local clock of the switch comprises:

[0028] The frequency discriminator receives the local clock of the switch sent by the auxiliary clock output interface, and compares the clock frequency of the standard clock with the clock frequency of the local clock of the switch.

[0029] Further, the step of the switch correcting the local clock of the switch according to the clock frequency difference and the clock phase difference includes:

[0030] The switch performs delay calibration on the clock phase of the local clock of the switch, and corrects the local clock of the switch according to the clock frequency difference and the clock phase difference.

[0031] Furthermore, the number of switches in the FC network is at least one.

[0032] The technical solution of a FC network clock synchronization system of the present invention is as follows:

[0033] Including: FC network switches;

[0034] The switch is used to: receive a standard clock sent by a source node of the FC network, and obtain a clock frequency difference and a clock phase difference according to the standard clock and a local clock of the switch;

[0035] The switch is also used for: the switch corrects the local clock of the switch according to the clock frequency difference and the clock phase difference, obtains the corrected local clock of the switch and sends it to each node of the FC network connected to the switch, so that the local clock of each node corresponding to the switch is synchronized with the standard clock.

[0036] The beneficial effects of the FC network clock synchronization system of the present invention are as follows:

[0037] The system of the present invention obtains data sent by a source node based on a high-precision clock source, so that the node and the switch extract the clock from the received data and complete the clock synchronization of the entire FC network, thereby improving the accuracy of the FC network clock synchronization.

[0038] Based on the above solution, the FC network clock synchronization system of the present invention can also be improved as follows.

[0039] Further, the switch includes: FPGA;

[0040] The switch is specifically used for: the FPGA receives the standard clock sent by the source node, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic flow chart of an embodiment of a FC network clock synchronization method provided by the present invention is shown;

[0042] Figure 2A schematic diagram showing the structure of a switch in an embodiment of a FC network clock synchronization method provided by the present invention;

[0043] Figure 3 A schematic diagram showing the structure of an FPGA in an embodiment of a FC network clock synchronization method provided by the present invention;

[0044] Figure 4 A schematic diagram of the structure of a phase-locked loop in an embodiment of a FC network clock synchronization method provided by the present invention is shown;

[0045] Figure 5 The overall structural block diagram of a switch / node in an embodiment of a FC network clock synchronization method provided by the present invention is shown;

[0046] Figure 6 The overall structural block diagram of the FC network in an embodiment of the FC network clock synchronization method provided by the present invention is shown;

[0047] Figure 7 A schematic diagram showing the principle of delay calibration in an embodiment of a FC network clock synchronization method provided by the present invention;

[0048] Figure 8 The overall structural block diagram of a source node in an embodiment of a FC network clock synchronization method provided by the present invention is shown;

[0049] Fig. 9 A structural schematic diagram of an embodiment of a FC network clock synchronization system provided by the present invention is shown. DETAILED DESCRIPTION

[0050] Figure 1 FIG. 2 is a flow chart showing an embodiment of a method for synchronizing a clock in an FC network provided by the present invention. Figure 1 As shown, the following steps are included:

[0051] Step 110: The switch of the FC network receives the standard clock sent by the source node of the FC network, and obtains a clock frequency difference and a clock phase difference according to the standard clock and the local clock of the switch.

[0052] Among them, ①FC network is: Fiber Channel network. ②FC network includes: a source node, at least one switch and at least one node, and the source node is connected to any node through at least one switch. ③Standard clock is: a high-precision clock source, specifically including high-precision clock frequency and high-precision clock phase. ④Local clock is: the current clock information of the corresponding terminal device (here refers to the switch). ⑤The clock frequency difference is: the frequency difference between the standard clock and the local clock of the switch; the clock phase difference is: the phase difference between the standard clock and the local clock of the switch.

[0053] Step 120: The switch corrects the local clock of the switch according to the clock frequency difference and the clock phase difference, obtains the corrected local clock of the switch and sends it to each node of the FC network connected to the switch, so that the local clock of each node corresponding to the switch is synchronized with the standard clock.

[0054] The clock synchronization method in each node of the FC network connected to the switch is the same as the clock synchronization method of the switch. Specifically, the corrected local clock of the switch of the FC network is used as the standard clock and sent to the corresponding node. The node receives the standard clock sent by the switch, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the node. The node corrects the local clock of the node according to the clock frequency difference and the clock phase difference, obtains and performs clock synchronization according to the corrected local clock of the node. For specific steps, please refer to the clock synchronization method of the switch in this embodiment, which will not be repeated here.

[0055] It should be noted that ① the source node in the FC network uses a high-precision clock source as a reference (that is, the source node uses a high-precision clock source as a local clock) and communicates using a high-speed channel interface. At the same time, the source node can determine the clock frequency phase difference of the connected node by comparing the receiving clock (the node to which the source node is connected) with the local clock. ② The switch receives data from the source node and extracts the local clock of the source node (as the receiving clock), and calculates the frequency phase difference between the local clock of the switch and the receiving clock, thereby setting the local clock, and uses this clock as a reference to communicate with the connected node using a high-speed interface. ③ After receiving the data sent by the switch, the node (node ​​1 to n) extracts the local clock of the switch (as the receiving clock), calculates the frequency phase difference between the local clock and the receiving clock, and sets the local clock. ④ When any switch is connected to another switch, the same method as above is used to send the corrected local clock of the switch to the other connected switch to synchronize the clock of the other switch, until the clocks of each switch and each node in the entire FC network are synchronized.

[0056] Preferably, if Figure 2 As shown, the switch includes: FPGA.

[0057] Step 110 includes:

[0058] The FPGA receives the standard clock sent by the source node, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch.

[0059] Specifically, the FPGA receives a standard clock sent by a source node of the FC network, and obtains a clock frequency difference and a clock phase difference of the switch according to the standard clock and a local clock of the switch.

[0060] Preferably, if Figure 2 As shown, the switch also includes: a digital-to-analog converter, a voltage-controlled oscillator and a phase-locked loop.

[0061] The step of the switch correcting the local clock of the switch according to the clock frequency difference and the clock phase difference to obtain the corrected local clock of the switch includes:

[0062] The digital-to-analog converter receives the clock frequency difference in digital form sent by the FPGA and performs digital-to-analog conversion to obtain the clock frequency difference in analog form and sends it to the voltage-controlled oscillator.

[0063] Specifically, the digital-to-analog converter of the switch receives the clock frequency difference in digital form sent by the FPGA, performs digital-to-analog conversion on the clock frequency difference in digital form to obtain the clock frequency difference in analog form, and sends the clock frequency difference in analog form to the voltage-controlled oscillator. The clock frequency difference in analog form is the voltage value that controls the voltage-controlled oscillator.

[0064] The voltage-controlled oscillator corrects the frequency of the local clock of the switch according to the clock frequency difference in the analog form, obtains and sends the corrected local clock frequency to the phase-locked loop.

[0065] Specifically, the voltage-controlled oscillator of the switch corrects the frequency of the local clock of the switch according to the clock frequency difference in analog form to obtain a corrected local clock frequency, and sends the corrected local clock frequency to the phase-locked loop of the switch.

[0066] The phase-locked loop receives and corrects the phase of the local clock of the switch according to the clock phase difference sent by the FPGA to obtain a corrected local clock phase, and obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency.

[0067] Specifically, the phase-locked loop receives the clock phase difference sent by the FPGA, and corrects the phase of the local clock of the switch according to the clock phase difference to obtain a corrected local clock phase; the phase-locked loop obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency.

[0068] Preferably, if Figure 3 As shown, the FPGA includes: a data receiving module, a data sending module, a frequency detector, a phase detector, a DAC control module and a PLL control module.

[0069] Among them, ① the data receiving module is: serdes_rx of the serial deserializer. ② the data sending module is: serdes_tx of the serial deserializer.

[0070] The step of the FPGA receiving the standard clock sent by the source node and obtaining the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch includes:

[0071] The data receiving module receives the standard clock sent by the source node, sends the clock frequency of the standard clock to the frequency detector, and sends the clock phase of the standard clock to the phase detector.

[0072] Specifically, the data receiving module serdes_rx receives the standard clock sent by the source node, sends the clock frequency of the standard clock rx_clk to the frequency detector, and sends the clock phase of the standard clock rx_clk to the phase detector.

[0073] The frequency detector compares the clock frequency of the standard clock with the clock frequency of the local clock of the switch to obtain a frequency compensation value and sends it to the DAC control module, so that the DAC control module obtains the clock frequency difference according to the frequency compensation value.

[0074] Specifically, the frequency detector compares the clock frequency of the standard clock with the clock frequency of the local clock of the switch to obtain a frequency compensation value, and sends the frequency compensation value to the DAC control module. The DAC control module obtains a clock frequency difference value according to the frequency compensation value.

[0075] It should be noted that the process of calculating the clock frequency difference using the DAC control module is a prior art and will not be described in detail here.

[0076] The phase detector compares the clock phase of the standard clock with the clock phase of the local clock of the switch, obtains a phase compensation value and sends it to the PLL control module, so that the PLL control module obtains the clock phase difference value according to the phase compensation value.

[0077] Specifically, the phase detector compares the clock phase of the standard clock with the clock phase of the local clock of the switch to obtain a phase compensation value, and sends the phase compensation value to the PLL control module. The PLL control module obtains the clock phase difference value according to the phase compensation value.

[0078] Preferably, if Figure 4 As shown, the phase-locked loop includes: a reference clock input interface, a serial deserializer reference clock interface and a control interface.

[0079] The phase-locked loop receives and corrects the phase of the local clock of the switch according to the clock phase difference sent by the FPGA to obtain a corrected local clock phase, and obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency, comprising:

[0080] The phase-locked loop receives the clock phase difference value sent by the PLL control module through the control interface, and corrects the phase of the local clock of the switch according to the clock phase difference value to obtain a corrected local clock phase.

[0081] The phase-locked loop receives the corrected local clock frequency sent by the voltage-controlled oscillator through the reference clock input interface, obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency, and sends the corrected local clock of the switch through the serial deserializer reference clock interface.

[0082] Specifically, 1) the phase-locked loop receives the clock phase difference sent by the PLL control module through the control interface; 2) the phase-locked loop corrects the phase of the local clock of the switch according to the clock phase difference to obtain a corrected local clock phase; 3) the phase-locked loop receives the corrected local clock frequency sent by the voltage-controlled oscillator through the reference clock input interface; 4) the phase-locked loop obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency; 5) the phase-locked loop sends the corrected local clock of the switch to the FPGA through the serial deserializer reference clock interface, so that the FPGA sends the corrected local clock of the switch to the connected node through the serial deserializer.

[0083] Preferably, the phase-locked loop further includes: an auxiliary clock output interface.

[0084] The step of the frequency discriminator comparing the clock frequency of the standard clock with the clock frequency of the local clock of the switch comprises:

[0085] The frequency discriminator receives the local clock of the switch sent by the auxiliary clock output interface, and compares the clock frequency of the standard clock with the clock frequency of the local clock of the switch.

[0086] Specifically, the frequency discriminator receives the local clock of the switch sent by the auxiliary clock output interface, and compares the clock frequency of the standard clock with the clock frequency of the local clock of the switch.

[0087] In addition, the frequency discriminator receives the local clock of the switch sent by the auxiliary clock output interface, and compares the clock phase of the standard clock with the clock phase of the local clock of the switch.

[0088] It should be noted that Figure 5 The overall structure diagram of the switch and the node is shown. Figure 6 The overall structural block diagram of FC network clock synchronization is shown. Figure 5 In the figure, rx_clk is the standard clock (the clock recovered from the received data), and tx_clk is the local clock (synchronized with the external input reference clock MGT_REF_CLK). Figure 5 The functions of the remaining parts are described in detail above and will not be elaborated here. Figure 6 The difference between a switch and a node is that a switch needs to add selection logic to select the port connected to the source node to restore the clock to complete frequency and phase synchronization (that is, the switch can connect to multiple nodes and complete clock synchronization with multiple nodes, such as Figure 6 P1-Pn in.

[0089] Preferably, the step of correcting the local clock of the switch according to the clock frequency difference and the clock phase difference comprises:

[0090] The switch performs delay calibration on the clock phase of the local clock of the switch, and corrects the local clock of the switch according to the clock frequency difference and the clock phase difference.

[0091] It should be noted that since the delay of the FC network synchronization link will affect the synchronization of the clock phase, it is necessary to calibrate the link delay before the clock synchronization, and then synchronize with the standard clock after the delay is calibrated. Specifically, the delay consists of the following two parts: 1) The hardware delay of the master and slave node transceiver circuits, including the deterministic delay of the FPGA internal logic, the FPGA internal routing delay, the PCB routing delay, the high-speed serial transceiver and the fiber optic transceiver delay. This part of the delay can be considered to be relatively fixed. 2) The bit sliding delay is caused by the bit sliding of the serial-to-parallel conversion circuit during the word alignment operation. This part of the delay remains unchanged after the fiber optic link is established and can be automatically obtained by the software after each link is established. Figure 7 As shown in the figure, the master node and the slave node establish a link, at which time the bit sliding delay can be obtained through the internal software. After the master node and the slave node complete synchronization, the PPS pulse per second output by the master and slave nodes can be measured using an oscilloscope to calibrate the hardware delay.

[0092] In addition, if Figure 8 As shown, the source node of the FC network includes: a phase-locked loop and an FPGA. The specific structures of the phase-locked loop and the FPGA of the source node are the same as those of the phase-locked loop and the FPGA in the switch. Figure 8In the figure, ① the high-precision clock is a high-precision reference frequency source. ② The phase-locked loop (PLL) is a device that uses the feedback control principle to achieve frequency and phase synchronization. Its function is to synchronize the clock output by the circuit with its external reference clock. Among them, PLL_REFCLK (phase-locked loop reference clock input interface) is the reference clock frequency input of the PLL, which comes from the high-precision clock; AUX_CLK (auxiliary clock output) and MGT_REF_CLK (serializer reference clock interface) are both clock outputs generated by the PLL, and the frequency is the same as PLL_REFCLK (phase-locked loop reference clock input interface); MGT_REF_CLK (serializer reference clock interface) is input to the FPGA as the reference clock for FPGA high-speed communication, and AUX_CLK (auxiliary clock output) is input to the FPGA as an auxiliary clock for clock frequency and phase discrimination. PLL_CONTROL (phase-locked loop control interface) is the control interface of the PLL, and the source node clock is not used. ③FPGA is the main chip for the implementation of the solution. The FC protocol stack implements FC communication according to the FC protocol. SERDES serial deserializer is used as a high-speed data interface to complete data transmission and reception, where serdes_rx (serial deserializer data receiving interface) is high-speed data reception, and the clock recovered from it is rx_clk (receive reference clock), serdes_tx (serial deserializer data transmitting interface) is high-speed data transmission, and the transmission clock tx_clk (transmission reference clock) is synchronized with the external input reference clock MGT_REF_CLK (serial deserializer reference clock interface). The frequency detector and phase detector are used to compare the clock frequency and phase respectively. By comparing the received recovery clock rx_clk with the transmission reference clock MGT_REF_CLK (serial deserializer reference clock interface) (here, comparing AUX_CLK with the same frequency and phase as it), the frequency difference and phase difference between the two clocks can be obtained.

[0093] The technical solution of this embodiment obtains the source node to send data based on a high-precision clock source, so that the node and the switch extract the clock from the received data and complete the clock synchronization of the entire FC network, thereby improving the accuracy of the FC network clock synchronization.

[0094] Fig. 9 FIG. 2 is a schematic diagram showing a structure of an embodiment of a FC network clock synchronization system provided by the present invention. Fig. 9 As shown, the system 200 includes: a switch of a FC network;

[0095] The switch is used to: receive a standard clock sent by a source node of the FC network, and obtain a clock frequency difference and a clock phase difference according to the standard clock and a local clock of the switch;

[0096] The switch is also used for: the switch corrects the local clock of the switch according to the clock frequency difference and the clock phase difference, obtains the corrected local clock of the switch and sends it to each node of the FC network connected to the switch, so that the local clock of each node corresponding to the switch is synchronized with the standard clock.

[0097] Preferably, the switch comprises: an FPGA;

[0098] The switch is specifically used for: the FPGA receives the standard clock sent by the source node, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch.

[0099] The technical solution of this embodiment obtains the source node to send data based on a high-precision clock source, so that the node and the switch extract the clock from the received data and complete the clock synchronization of the entire FC network, thereby improving the accuracy of the FC network clock synchronization.

[0100] The parameters and steps for each module to implement corresponding functions in the FC network clock synchronization system 200 of this embodiment can refer to the parameters and steps in the implementation of the FC network clock synchronization method above, and will not be described in detail here.

[0101] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. Similarly, in order to simplify the present invention and help understand one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the embodiments of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. Wherein, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself is a separate embodiment of the present invention.

[0102] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be understood as limitations on the order of execution.

Claims

1. A FC network clock synchronization method, characterized in that: include: The switch of the FC network receives the standard clock sent by the source node of the FC network, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch; wherein the source node in the FC network uses a high-precision clock source as the local clock and communicates using a high-speed channel interface, and the source node determines the clock frequency phase difference of the connected node by comparing the node connected to the source node with the local clock; The switch corrects the local clock of the switch according to the clock frequency difference and the clock phase difference, obtains the corrected local clock of the switch and sends it to each node of the FC network connected to the switch, so that the local clock of each node corresponding to the switch is synchronized with the standard clock; The switch includes: an FPGA, a digital-to-analog converter, a voltage-controlled oscillator, and a phase-locked loop; the process of obtaining a clock frequency difference and a clock phase difference by the switch includes: The FPGA receives the standard clock sent by the source node, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch; The step of the switch correcting the local clock of the switch according to the clock frequency difference and the clock phase difference to obtain the corrected local clock of the switch includes: The digital-to-analog converter receives the clock frequency difference in digital form sent by the FPGA and performs digital-to-analog conversion to obtain the clock frequency difference in analog form and sends it to the voltage-controlled oscillator; The voltage-controlled oscillator corrects the frequency of the local clock of the switch according to the clock frequency difference in the analog form, obtains and sends the corrected local clock frequency to the phase-locked loop; The phase-locked loop receives and corrects the phase of the local clock of the switch according to the clock phase difference sent by the FPGA to obtain a corrected local clock phase, and obtains a corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency; The FPGA includes: a data receiving module, a data sending module, a frequency detector, a phase detector, a DAC control module and a PLL control module; the FPGA receives the standard clock sent by the source node, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch, including: The data receiving module receives the standard clock sent by the source node, and sends the clock frequency of the standard clock to the frequency detector, and sends the clock phase of the standard clock to the phase detector; The frequency detector compares the clock frequency of the standard clock with the clock frequency of the local clock of the switch, obtains a frequency compensation value and sends it to the DAC control module, so that the DAC control module obtains the clock frequency difference according to the frequency compensation value; The phase detector compares the clock phase of the standard clock with the clock phase of the local clock of the switch, obtains a phase compensation value and sends it to the PLL control module, so that the PLL control module obtains the clock phase difference value according to the phase compensation value; The phase-locked loop includes: a reference clock input interface, a serial deserializer reference clock interface and a control interface; The phase-locked loop receives and corrects the phase of the local clock of the switch according to the clock phase difference sent by the FPGA to obtain a corrected local clock phase, and obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency, comprising: The phase-locked loop receives the clock phase difference sent by the PLL control module through the control interface, and corrects the phase of the local clock of the switch according to the clock phase difference to obtain a corrected local clock phase; The phase-locked loop receives the corrected local clock frequency sent by the voltage-controlled oscillator through the reference clock input interface, obtains the corrected local clock of the switch according to the corrected local clock phase and the corrected local clock frequency, and sends the corrected local clock of the switch through the serial deserializer reference clock interface; The step of the switch correcting the local clock of the switch according to the clock frequency difference and the clock phase difference comprises: The switch performs delay calibration on the clock phase of the local clock of the switch, and corrects the local clock of the switch according to the clock frequency difference and the clock phase difference; wherein the delay consists of two parts: one is the hardware delay of the master-slave node transceiver circuit, including the deterministic delay of the internal logic of the FPGA, the internal routing delay of the FPGA, the PCB routing delay, the delay of the high-speed serial transceiver and the delay of the optical fiber transceiver, and this part of the delay is relatively fixed; the second is the bit sliding delay, which is caused by the bit sliding caused by the serial-to-parallel conversion circuit during the word alignment operation. The delay remains unchanged after the optical fiber link is connected, and is automatically obtained by the software after each link is established; the process of delay calibration is: when the master node and the slave node establish a link, the bit sliding delay is obtained through the internal software, and after the master node and the slave node complete synchronization, the PPS second pulse output by the master and slave nodes is measured using an oscilloscope, that is, the hardware delay is calibrated; The phase-locked loop further comprises: an auxiliary clock output interface; the frequency detector compares the clock frequency of the standard clock with the clock frequency of the local clock of the switch, comprising: The frequency discriminator receives the local clock of the switch sent by the auxiliary clock output interface, and compares the clock frequency of the standard clock with the clock frequency of the local clock of the switch.

2. The FC network clock synchronization method according to claim 1, characterized in that: The number of switches in the FC network is at least one.

3. A FC network clock synchronization system, using the FC network clock synchronization method according to claim 1 or 2, characterized in that: include: FC network switches; The switch is used to: receive a standard clock sent by a source node of the FC network, and obtain a clock frequency difference and a clock phase difference according to the standard clock and a local clock of the switch; The switch is also used for: the switch corrects the local clock of the switch according to the clock frequency difference and the clock phase difference, obtains the corrected local clock of the switch and sends it to each node of the FC network connected to the switch, so that the local clock of each node corresponding to the switch is synchronized with the standard clock.

4. The FC network clock synchronization system according to claim 3, characterized in that: The switch comprises: an FPGA; The switch is specifically used for: the FPGA receives the standard clock sent by the source node, and obtains the clock frequency difference and the clock phase difference according to the standard clock and the local clock of the switch.

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