An all-digital in-memory approximate computing circuit based on sram cells

Abstract

The application provides a full-digital in-memory approximate computing circuit based on SRAM, which comprises a memory-computing operator array, wherein the memory-computing operator array comprises an SRAM memory-computing circuit, the memory-computing circuit comprises 2 n row x column SRAM memory-computing units, 2 n single-bit signals are input into the SRAM memory-computing circuit every cycle, and 2 n x-bit multiplication results are generated; and an approximate addition tree, which accepts the 2 n x-bit multiplication results, performs accumulation summation on the multiplication results, and outputs x+n-bit signals. The application provides an in-memory computing circuit which performs computation in a full-digital manner and is resistant to process and noise disturbance; single-bit point multiplication operation can be completed by logic gates integrated in the SRAM without reading out the internal storage data of the SRAM, thereby reducing the delay and power consumption of data access; the accumulation summation part adopts an approximate addition tree design with adjustable precision, thereby reducing the area overhead of peripheral circuits and ensuring the summation performance and energy efficiency of the addition tree.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to an in-memory approximation calculation circuit based on SRAM cells in the all-digital domain. Background Technology

[0002] With the rise of a large number of data-intensive applications such as neural networks, the traditional von Neumann architecture, which separates processors and storage units, is often limited by the huge gap between memory and processor performance when performing such tasks—the memory wall problem—resulting in massive energy consumption and latency overhead during data movement. Recently, a new computing architecture based on in-memory computing has been proposed to address the memory wall problem faced by traditional computing architectures. On the one hand, this new architecture makes it possible to complete data-intensive applications with high energy efficiency; on the other hand, high-energy-efficiency processing of such tasks allows for wider deployment at resource-constrained edge computing, promoting the development of the intelligent ecosystem. Among these, Static Random Access Memory (SRAM), due to its high speed, logical compatibility, and mature technology, has received widespread attention from research institutions both domestically and internationally as a medium for in-memory computing. SRAM-based in-memory computing can be mainly divided into two categories: analog computing and digital computing.

[0003] Existing analog-domain in-memory computing schemes require the use of analog-to-digital conversion (ADC) units, which occupy a large area and consume extremely high power. In addition, analog-domain computing is very sensitive to circuit noise and process disturbances, and the output data is uncertain and has low accuracy. While existing digital-domain in-memory computing schemes do not require ADC units and are disturbance-resistant, they require the accumulation of partial sums in the in-memory circuit, thus requiring the extensive use of addition trees. The area and power consumption of addition trees are the main problems of digital-domain in-memory computing. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the purpose of this invention is to provide a fully digital in-memory approximation calculation circuit based on SRAM cells.

[0005] According to one aspect of the present invention, an SRAM-based all-digital domain in-memory approximation calculation circuit is provided, comprising an array of memory operators, including:

[0006] SRAM memory circuitry, the memory circuitry including 2 n Row x column SRAM storage unit, 2 are fed in each cycle n A single-bit signal, after passing through the SRAM storage circuit, generates 2 n x bits multiplication result;

[0007] An approximate addition tree that accepts the 2 nThe x-bit multiplication results are summed to output an x+n-bit signal.

[0008] Preferably, the storage operator array further includes:

[0009] The shift-add unit accumulates the summation results of the multi-period approximate addition tree to realize the multi-bit signal input of the storage operator array.

[0010] Preferably, each row of the memory operator array accommodates x SRAM memory units, correspondingly storing x bits of weight data; each column of the memory operator array accommodates 2 n There are 2 SRAM storage units, that is, there are 2 n Rows can store different weights 2 n indivual;

[0011] x-bit weight data are stored in x different columns of the same row, arranged from right to left according to the least significant bit to the most significant bit. Different weights will be stored in different rows, for a total capacity of 2. n Data with different weights.

[0012] Preferably, the SRAM storage unit includes:

[0013] A 6-transistor SRAM memory cell stores weight bits;

[0014] The NOR2 logic gate is used for dot multiplication operations. One input is connected to the QB node inside the SRAM cell, and the other input is connected to the input signal In_B.

[0015] Preferably, the approximate addition tree comprises n-level cascaded multi-bit approximate adders;

[0016] The multi-bit approximate adder includes:

[0017] A 28T adder, used to generate accurate high-order bit summation and carry signals;

[0018] The OR gate approximates adder, which is used to generate the sum of the lower bits and the carry signal.

[0019] Preferably, for a cumulative size of 2 n The input consists of x bits, and the addition tree has levels 1 to n. Starting from the i-th level adder, the adder supports a bit length of i+x-1 (1≤i≤n).

[0020] Starting from the first-level adder, if the current adder level is denoted as j (1≤j≤n), and if j+x-1=2k (k is an integer), the lower k bits of the j-th level adder are OR gate approximation adders, and the higher k bits are 28T standard full adder structures.

[0021] If j+x-1=2k+1 (k is an integer), the lower k bits of the j-th stage adder are OR gate approximation adders, and the higher k+1 bits are 28T standard full adder structures.

[0022] Preferably, the number of levels in the approximate addition tree is determined by the SRAM storage circuit. n The input determines the n levels, and each level consists of a full-precision adder and an approximate adder.

[0023] The number of full-precision adders and approximate adders varies depending on the bit width supported by the current series adders.

[0024] Preferably, for a cumulative size of 2 n The input consists of x bits, and the addition tree has levels 1 to n. Starting from the i-th level adder, the adder supports a bit length of i+x-1 (1≤i≤n).

[0025] Starting from the first-level adder, up to the nm-th level adder, there are a total of nm levels of adders, which are approximate adders;

[0026] A full-precision adder consists of m levels, from level n-m+1 to level n.

[0027] If we assume the current adder level is the j-th level (1≤j≤nm, m is an integer and m is a configurable quantity), then the low k-th level of the j-th level adder... j The bit is an OR gate, with high value j+x-1-k. j The bit is a standard full adder 28T structure (where k j For configurable quantities, 0 ≤ k j <(j+x-1) / 2, k j (integer);

[0028] If we assume the current adder stage is the p-th stage (n-m+1≤p≤n, m is an integer and m is a configurable quantity), then all bits of the p-th stage adder are of the standard full adder 28T structure.

[0029] Preferably, the approximation degree of the approximation tree is adjusted according to the accumulation accuracy requirements, specifically by adjusting the number of approximation calculation stages nm, and adjusting the number of approximation adder bits k for each stage. j Adjustments will be made.

[0030] Preferably, the OR full adder accepts two single-bit input signals, and the two single-bit input signals are passed through a NOR2 logic gate and an inverter to obtain an approximate summation signal.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] The embodiment provided by the present invention is an in-memory computing circuit that performs calculations in a fully digital domain, resisting process and noise disturbances; it can complete single-bit multiplication operations through logic gates integrated inside the SRAM without reading out the data stored inside the SRAM, reducing data access latency and power consumption.

[0033] The embodiments provided by this invention construct addition trees with different summation accuracies according to different neural network application requirements. By replacing the traditional 28T high-precision adder with an OR gate, the number of transistors in the addition tree can be effectively reduced, thereby reducing the signal switching energy consumption and area overhead in the adder used in digital domain in-memory computing. At the same time, since the traditional adder with some bit lengths is replaced with an OR gate, the carry length will be greatly shortened. Therefore, the critical path in the addition tree in digital domain in-memory computing will be greatly shortened, and the performance of the addition tree will be improved.

[0034] Furthermore, the present invention performs signal processing in the digital domain, and its calculation results are deterministic compared to analog domain calculations. Attached Figure Description

[0035] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0036] Figure 1 This is a circuit diagram of an SRAM-based in-memory computing unit according to an embodiment of the present invention;

[0037] Figure 2 This is a diagram of an SRAM-based memory operator array according to an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the shift accumulation unit structure according to an embodiment of the present invention;

[0039] Figure 4 This is the first approximate addition tree construction in the embodiments of the present invention;

[0040] Figure 5 This is a second approximate addition tree construction in an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of the OR adder structure in an embodiment of the present invention. Detailed Implementation

[0042] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0043] This invention provides an embodiment of an all-digital domain in-memory approximation calculation circuit based on SRAM cells, comprising: an all-digital domain in-memory approximation calculation system based on SRAM, wherein the memory operator array includes: a memory computing circuit, the memory computing circuit comprising 2... n Row x column SRAM storage unit, 2 are fed in each cycle n A single-bit signal, after passing through the storage and processing circuit, generates 2 n x-bit multiplication result; an approximate addition tree, the approximate addition tree accepting the 2 n The x-bit multiplication results are input and summed.

[0044] To better achieve in-memory computation, the present invention provides a preferred embodiment, such as... Figure 1 The diagram shows the structure of the SRAM storage unit circuit in this embodiment. The storage unit includes two parts: a 6-transistor unit, where the NMOS transistors are designated N1-N4 and the PMOS transistors are designated P1-P2. N3 and N4 are transmission transistors used for data reading and writing. P1 and N1 form an inverter, and P2 and N2 form another inverter. The two inverters are cross-coupled to form a data storage module. The second part is a 4-transistor logic gate unit, where the NMOS transistors are designated N5-N6 and the PMOS transistors are designated P3-P4. N5 to N6 are connected in series to form a pull-down network. The gates of N5 and N6 are controlled by the input signal In_B and the internal storage node QB of the SRAM, respectively. P3 to P4 are connected in parallel to form a pull-up network. The gates of P3 and P4 are controlled by the input signal In_B and the internal storage node QB of the SRAM, respectively. Finally, the above 4 transistors form a NOR logic function to complete the dot multiplication operation.

[0045] The SRAM storage unit circuit in this embodiment can perform a single-bit multiplication operation through logic gates integrated inside the SRAM without reading the data stored inside the SRAM, thus reducing data access latency and power consumption.

[0046] like Figure 2 The diagram shown is a memory operator array diagram in a preferred embodiment of the present invention.

[0047] The operator array includes SRAM memory circuitry, as well as peripheral approximate adder trees and shift-adder units. Each row of the SRAM memory circuitry can hold x SRAM memory cells, storing x bits of weight data accordingly; a column can hold 2... n There are 2 SRAM storage units, that is, there are 2 n Rows can store different weights 2 n That is, the storage operator array can store 2. n Single-bit data in rows x and columns, where the weight has x bits and contains a total of 2 bits. nEach weight. Simultaneously, this storage operator array can accept 2 [weights] per cycle. n The inverse signal of a single-bit input signal is represented in the figure as In_Bi (where 1≤i≤2). n The single-bit input signal In_Bi serves as the common input of a row of SRAM storage circuits. It is multiplied by the x-bit weight to obtain an x-bit wide output. The weight W is stored in the Q node of the 6-transistor SRAM, and the x-bit weights Wi[0] to Wi[x-1] are stored in the Q nodes of SRAM cells in different columns of the same row of the array, arranged from right to left from the least significant bit (LSB) to the most significant bit (MSB), where the index i is the row number of the weight. That is, when the input is a multi-bit signal, it will be sent serially from the least significant bit to the most significant bit, one bit per cycle. Since this SRAM storage circuit contains 2 n Row weights, therefore a single cycle can generate 2 n x-bit multiplication result.

[0048] Furthermore, the storage operator array also includes an acceptable 2 n An approximate adder tree with x bits of input, its function is to process all multiplication results (2^x, x^2) within that period. n The results of x-bit multiplications are summed.

[0049] Furthermore, after the addition tree, there is a shift-accumulate unit. This unit, in the case of multi-bit, multi-cycle input, is used to accept and store the calculation result of the approximate addition tree in the previous cycle, and to left-shift the calculation result of the approximate addition tree in the current cycle and sum it with the calculation result of the previous cycle. For example... Figure 3 The diagram shows the structure of the shift-accumulator unit provided in this embodiment. As can be seen, a left shift unit is used to shift the output of each cycle when the input is x+n bits; an x+n+p bit full-precision adder is used to sum the output of the current cycle and the output of the previous cycle; a multi-bit register is used to store the summation result of the previous cycle and output the summation result to the full-precision adder for summation in the current cycle. The above shift-accumulator unit is a traditional shift-accumulator unit.

[0050] In the memory operator array provided in the embodiment, IN_B is the inverse signal of the neural network input signal. A single bit signal is input in each cycle. The p-bit IN_B signal is serially sent to the SRAM memory circuit through p cycles. The output of p cycles will be summed by the shift accumulator unit.

[0051] To achieve better construction of the addition tree, this invention provides two preferred embodiments for constructing the addition tree. The approximate addition tree consists of n cascaded multi-bit adders, receiving input from SRAM storage circuitry. nThe multi-bit approximate adder takes an x-bit input signal and outputs an x+n-bit signal. It consists of a 28T adder and an OR gate approximate adder. The 28T adder generates accurate high-order bit summation and carry signals, while the OR gate approximate adder generates low-order bit summation and carry signals.

[0052] Specifically, the first type of addition tree construction is as follows: Figure 4 As shown, for a cumulative size of 2 n Given x-bit inputs, the adder tree has levels 1 to n. Starting from the i-th level adder, the adder supports i+x-1 bits (1≤i≤n). Starting from the 1st level adder, if the current adder level is denoted as j (1≤j≤n), and if j+x-1=2k (k is an integer), the lower k bits of the j-th level adder are OR gate approximations, and the higher k bits are a 28T standard full adder structure; if j+x-1=2k+1 (k is an integer), the lower k bits of the j-th level adder are OR gate approximations, and the higher k+1 bits are a 28T standard full adder structure. The following uses an SRAM storage circuit with a size of 32*4 (2... 5 *4) will be used as an example to illustrate the construction of an addition tree. Given the size of the SRAM storage circuit, this array can store 2... 5 Each 4-bit weighted data, can accept 2 simultaneously in a single cycle. 5 Each single-bit input signal is shared by the memory units in the same row. Each row outputs a 4-bit signal per cycle. Therefore, the approximate addition tree will process 2 bits per cycle. 5 The addition tree sums 4-bit data. It has 5 levels, with the first level being a 4-bit adder. The high two bits are 28T adders, and the low two bits are OR adders. This level's adder accepts 4-bit input and outputs a 5-bit sum. This level's adder has 2... 4 The second stage is a 5-bit adder, with the high three bits being 28T adders and the low two bits being OR adders. This stage adder will accept the 5-bit summation result from the first stage and output a 6-bit summation result. This stage adder has a total of 2... 3 The above structure continues until the final adder, the fifth-stage 8-bit adder, whose high four bits are 28T adders and its low four bits are OR adders, producing 9-bit outputs, for a total of 20. Replacing the traditional 28T full-precision adders with OR adders significantly reduces the number of transistors used in the adders, reducing the area and power consumption of the adder tree; at the same time, it shortens the critical path of carry propagation in the traditional adder, reduces the overall delay of the adder tree, and improves the performance of the adder tree.

[0053] In this embodiment, the number of levels in the addition tree is determined by the SRAM storage circuit 2. nThe addition tree has n levels, determined by a single input. Each level consists of full-precision adders and approximate adders. The number of full-precision adders and approximate adders varies depending on the bit width supported by the adders in the current level. By replacing full-precision adders with approximate adders in the addition tree, the overhead in terms of area, power consumption, and delay is reduced, while ensuring that signal processing is performed in the digital domain, thus resisting circuit noise and process disturbances.

[0054] The second type of addition tree construction is as follows: Figure 5 As shown, for a cumulative size of 2 n Given x bits of input, the adder tree has levels 1 to n. Starting from the i-th level adder, the adder supports i+x-1 bits (1≤i≤n). From the 1st level adder to the nm-th level adder, there are nm levels of approximate adders. From n-m+1 levels to the n-th level, there are m levels of full-precision adders. If the current adder level is j (1≤j≤nm, m is an integer and m is a configurable value), the low k bits of the j-th level adder... j The bit is an OR gate, with high value j+x-1-k. j The bit is a standard full adder 28T structure (where k j For configurable quantities, 0 ≤ k j <(j+x-1) / 2, k j (where m is an integer); if the current adder stage is the p-th stage (n-m+1≤p≤n, m is an integer and m is a configurable value), the total number of bits of the p-th stage adder is the standard full adder 28T structure. The following uses an SRAM storage circuit with a size of 32*4 (2... 5 *4) will be used as an example to illustrate the construction of an addition tree. Given the size of the SRAM storage circuit, this array can store 2... 5 4-bit weighted data, simultaneously accepting 2 5 Each single-bit input signal is shared by the memory units in the same row. Each row will output a 4-bit signal per cycle. Therefore, the approximate addition tree will process 2 bits per cycle. 5 Summing 4 bits of data. In configuring k... j With m = 1 and m = 4, the addition tree is constructed as follows: This addition tree has 5 levels of adders, with the first level being a 4-bit adder, and a total of 2... 4 The high three bits are 28T adders, and the low one bit is an OR adder. This stage receives 2 bits per cycle from the SRAM computing circuit. 5 Each input is 4 bits, and the output is 2. 4 Each of the following 5-bit outputs; the second to fifth levels of this adder tree each contain 2 3 ,2 2 ,2 1The addition tree consists of 20 adders of 5, 6, 7, and 8 bits, all of which are 28T full adders. The final output of the addition tree is 9 bits of data. Depending on the precision requirements of the neural network, k can be adjusted. j The size of m allows for the configuration of adder trees with different precisions, improving circuit performance and energy efficiency while ensuring a certain network accuracy, reducing the area overhead of the peripheral adder tree circuit. At the same time, since it is a fully digital domain signal processing, it is resistant to circuit noise and process disturbances, and has a definite output result.

[0055] In this embodiment, the approximation level of the adder tree can be adjusted by changing the number of approximation calculation stages nm in the adder tree according to the accumulation accuracy requirements, and the number of approximation adder bits k for each stage can also be adjusted. j Adjustments are needed. If high network accuracy is required, then in the second construction method, m should be a larger value, and k... j If the smaller value is taken, then m takes the smaller value, and k... j Take the larger value. While using approximate calculations to reduce the overhead of the addition tree area, power consumption, and latency, the summation accuracy of the addition tree can be further adjusted according to different application accuracy requirements to ensure application adaptability.

[0056] like Figure 6 The diagram shows an OR full adder structure in another embodiment of the present invention. It accepts two single-bit input signals, A and B, which are passed through a NOR2 logic gate and an inverter to obtain an approximate summation signal S. In this embodiment, the OR gate approximate adder replaces the traditional 28T full adder with an OR gate approximate adder composed of 4 NOR2 gates and 2T inverters. It can obtain an approximate summation signal without a carry signal, significantly reducing the number of transistors in a traditional full adder, lowering the adder area and power consumption, while shortening the carry critical path of the multi-bit adder and reducing the delay overhead of the multi-bit adder.

[0057] The embodiments provided by this invention perform calculations in the in-memory computing circuit using a fully digital domain approach, which is resistant to process and noise disturbances and provides deterministic output. Furthermore, depending on the application's accuracy requirements, it reduces the area, power consumption, and latency overhead of peripheral circuits in existing digital domain in-memory computing by using a precision-configurable approximate addition tree instead of a traditional full-precision addition tree. This invention can be widely applied to applications based on multiply-accumulate operations, such as neural networks and image filtering.

[0058] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention. The above preferred features can be used in any combination without conflict.

Claims

1. A fully digital in-memory approximation calculation circuit based on SRAM, characterized in that, include: Storage operator array, The storage operator array includes: SRAM memory circuitry, the memory circuitry including 2 n Row x column SRAM storage unit, 2 are fed in each cycle n A single-bit signal, after passing through the SRAM storage circuit, generates 2 n x bits multiplication result; An approximate addition tree that accepts the 2 n The x-bit multiplication results are summed to output an x+n bit signal. The approximate addition tree includes n-level cascaded multi-bit approximate adders; The multi-bit approximate adder includes: A 28T standard full adder is used to generate high-order summation and carry signals; The OR gate approximate adder is used to generate the low-order summation signal.

2. The SRAM-based in-memory approximation calculation circuit according to claim 1, characterized in that, The storage operator array further includes: The shift-add unit accumulates the summation results of the multi-period approximate addition tree to realize the multi-bit signal input of the storage operator array.

3. The SRAM-based all-digital in-memory approximation calculation circuit according to claim 1, characterized in that, The operator array has x SRAM memory units per row, storing x bits of weight data respectively; the operator array has 2... n There are 2 SRAM storage units, that is, there are 2 n Row, storing different weights 2 n indivual; x-bit weight data are stored in x different columns of the same row, arranged from right to left according to the least significant bit to the most significant bit. Different weights will be stored in different rows, for a total capacity of 2. n Data with different weights.

4. The SRAM-based all-digital in-memory approximation calculation circuit according to claim 1, characterized in that, The SRAM storage unit includes: A 6-transistor SRAM memory cell stores weight bits; The NOR2 logic gate is used for dot multiplication operations. One input is connected to the QB node inside the SRAM memory cell, and the other input is connected to the input signal In_B.

5. The SRAM-based in-memory approximation calculation circuit according to claim 1, characterized in that, For a cumulative size of 2 n The approximate adder tree has x bits as input, and the number of levels is 1 to n. Starting from the i-th level adder, the adder supports a bit length of i+x-1 (1≤i≤n). Starting from the first-level adder, if the current adder level is denoted as j (1≤j≤n), and if j+x-1=2k (k is an integer), the lower k bits of the j-th level adder are the OR gate approximation adder, and the higher k bits are the 28T standard full adder; If j+x-1=2k+1 (k is an integer), the lower k bits of the j-th stage adder are the OR gate approximation adder, and the higher k+1 bits are the 28T standard full adder.

6. The SRAM-based in-memory approximation calculation circuit according to claim 5, characterized in that, The number of levels in the approximate addition tree is determined by the SRAM storage circuit. n The input determines the n levels, and each level consists of a full-precision adder and an approximate adder. The number of full-precision adders and approximate adders varies depending on the bit width supported by the current series adders.

7. The SRAM-based in-memory approximation calculation circuit according to claim 1, characterized in that, For a cumulative size of 2 n The input consists of x bits, and the addition tree has levels 1 to n. Starting from the i-th level adder, the adder supports a bit length of i+x-1 (1≤i≤n). Starting from the first-level adder, up to the nm-th level adder, there are a total of nm levels of adders, which are approximate adders; A full-precision adder consists of m levels, from level n-m+1 to level n. If we assume the current adder level is the j-th level (1≤j≤nm, m is an integer and m is a configurable quantity), then the low k-th level of the j-th level adder... j The bit is an OR gate, with high value j+x-1-k. j A 28T standard full adder (where k is a bit) j For configurable quantities, 0 ≤ k j < (j+x-1) / 2, k j (integers) If we define the current adder stage as stage p (n-m+1≤p≤n, where m is an integer and m is a configurable quantity), then the total number of bits in the stage p adder is 28T, which is the standard full adder.

8. The SRAM-based all-digital in-memory approximation calculation circuit according to claim 7, characterized in that, The approximation level of the approximation tree is adjusted according to the accumulation accuracy requirements, specifically by adjusting the number of approximation calculation stages (nm) and the number of approximation adder bits (k) for each stage. j Adjustments will be made.

9. The SRAM-based in-memory approximation calculation circuit according to claim 5 or 7, characterized in that, The OR gate approximate adder accepts two single-bit input signals, and the two single-bit input signals are passed through a NOR2 logic gate and an inverter to obtain an approximate summation signal.

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