Power Management for Memory Devices

Abstract

The present application relates to power management of memory devices. An apparatus may include a memory die, the memory die including a power management circuit. The power management circuit may provide a voltage for operating a group of memory dies in the apparatus based on a power supply voltage received by the memory die. The voltage may be distributed to the group of memory dies in the apparatus.

Description

[0001] Cross Reference

[0002] This patent application is a national phase filing of international patent application No. PCT / US21 / 72580, entitled “POWER MANAGEMENT FOR A MEMORY DEVICE,” filed by KINSLEY et al. on November 23, 2021, which claims priority to U.S. patent application No. 17 / 110,197, entitled “POWER MANAGEMENT FOR A MEMORY DEVICE,” filed by KINSLEY et al. on December 2, 2020, each of which is assigned to its assignee, and the entire contents of each of which are expressly incorporated herein by reference.

[0003] The technical field relates to power management of memory devices. Background Art

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state in a memory device.

[0005] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-select memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods of time even in the absence of external power. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power source. Summary of the invention

[0006] An apparatus is described. The apparatus may include: a group of memory dies; a first power management circuit configured to provide a first voltage used by the apparatus to provide one or more voltages for operating the group of memory dies; and a second power management circuit on a memory die of the group of memory dies and coupled to the first power management circuit, the second power management circuit configured to provide a second voltage for operating the group of memory dies based at least in part on the first voltage.

[0007] A method is described. The method may include receiving a first voltage at a power management circuit on a memory die; and providing, by the power management circuit, a second voltage to a group of memory dies coupled to the power management circuit based at least in part on the first voltage.

[0008] An apparatus is described. The apparatus may include: a group of memory dies, a memory die coupled to the group of memory dies, and a controller coupled to the memory dies, the controller operable to cause the apparatus to: receive a first voltage at a power management circuit on the memory dies; and provide, by the power management circuit, a second voltage to the group of memory dies coupled to the power management circuit based at least in part on the first voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a system supporting power management of a memory device according to examples as disclosed herein is described.

[0010] Figure 2 An example of a memory device supporting power management of the memory device according to examples as disclosed herein is described.

[0011] Figure 3 An example of a memory device supporting power management according to examples as disclosed herein is described.

[0012] Figure 4 An example of a memory device supporting power management according to examples as disclosed herein is described.

[0013] Figure 5 A block diagram of a memory device supporting power management of the memory device according to examples as disclosed herein is shown.

[0014] Figure 6 A flow chart is shown illustrating a method or methods of supporting power management of a memory device according to examples as disclosed herein. DETAILED DESCRIPTION

[0015] A memory device may include a plurality of memory dies including a memory array for storing information. The memory dies may operate using different voltage levels. For example, a memory die may operate a memory array using a first voltage level, an input / output (I / O) circuit system using a second voltage level, and other components of the memory die using a third voltage level. In order to provide different voltage levels, each memory die may include a power management circuit for each voltage level, such as a power management integrated circuit (PMIC). For example, each memory die may include a first power management circuit that provides a first voltage level, a second power management circuit that provides a second voltage level, and a third power management circuit that provides a third voltage level. However, including multiple power management circuits on each memory die may be inefficient and may take up too much space on the memory die, among other disadvantages.

[0016] According to the techniques described herein, a subset of memory dies in a memory device ("provider memory dies") can be configured to provide different voltages to other memory dies. Because the provider memory dies supply voltages to other memory dies ("recipient memory dies"), the other memory dies can omit power management circuitry that would otherwise be included to generate the supplied voltages. Thus, the techniques described herein can allow for smaller size recipient memory dies or more die area for memory cells and greater storage capacity, among other advantages.

[0017] First, in the Figure 1 The features of the present disclosure are described in the context of the system described. Figures 2 to 4 Features of the present disclosure are described in the context of the memory device described. Figure 5 and 6 The features of the present disclosure are further illustrated and described with reference to device diagrams and flow charts related to memory device power management.

[0018] Figure 1 An example of a system 100 that supports power management of a memory device according to examples as disclosed herein is illustrated. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0019] The system 100 may include portions of an electronic device such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, the system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. The memory device 110 may be a component of the system that is operable to store data for one or more other components of the system 100.

[0020] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet computer, a smart phone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system on a chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0021] Memory device 110 may be a stand-alone device or component that is operable to provide a physical memory address / space that may be used or referenced by system 100. In some examples, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: a modulation scheme to modulate a signal, various pin configurations for communicating a signal, various form factors for physical packaging of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0022] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0023] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (such as one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using a bus 135.

[0024] The processor 125 is operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 may be a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 may be implemented by the processor 125 or may be part of the processor 125.

[0025] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of ROM, flash memory, or other non-volatile memory.

[0026] The memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support the desired capacity or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). The memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more tiles, one or more segments), where each memory cell is operable to store at least one data bit. A memory device 110 including two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0027] The memory die 160 may be an example of a two-dimensional (2D) array of memory cells, or may be an example of a three-dimensional (3D) array of memory cells. A 2D memory die 160 may include a single memory array 170. A 3D memory die 160 may include two or more memory arrays 170, which may be stacked on top of each other or positioned adjacent to each other (e.g., relative to a substrate). In some examples, the memory arrays 170 in a 3D memory die 160 may be referred to as levels, tiers, layers, or dies. A 3D memory die 160 may include any number of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high). In some 3D memory dies 160, different levels may share at least one common access line so that some levels may share one or more of a word line, a digit line, or a plate line.

[0028] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0029] The local memory controller 165 (e.g., local to the memory die 160) may include circuits, logic, or components operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate (e.g., receive or transmit data or commands or both) with the device memory controller 155. In some examples, the memory device 110 may not include a device memory controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0030] The external memory controller 120 is operable to enable communication of one or more of information, data, or commands between a component of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or the functions thereof described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or the functions thereof described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0031] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium that carries information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path that is operable to carry a signal. For example, channel 115 may include a first terminal that includes one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin may be an example of a conductive input or output point of a device of system 100, and a pin may be operable to serve as part of a channel.

[0032] The channels 115 (and associated signal paths and terminals) may be dedicated to conveying one or more types of information. For example, the channels 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or a combination thereof. In some examples, signaling may be conveyed through the channels 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal may be aligned for each clock cycle (e.g., on either a rising or falling edge of a clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal may be aligned for each clock cycle (e.g., on both a rising edge and a falling edge of a clock signal).

[0033] The memory dies 160 included in the memory device 110 may operate using different voltage levels ("operating voltages"). For example, the memory die 160 may operate the memory array(s) 170 using a first voltage level, operate the local memory controller 165 using a second voltage level, and operate the I / O circuitry using a third voltage, among other voltages. In other examples, one or more voltage levels may be used to operate the memory array(s) 170, or one or more voltage levels may be used to operate the local memory controller 165, or one or more voltage levels may be used to operate the I / O circuitry, or any combination thereof. Each memory die 160 may include one or more power management circuits that provide the operating voltage(s) to the memory die 160. Thus, each memory die 160 may include a set of power management circuits. However, including a set of power management circuits on each memory die 160 may consume space on the memory die 160, resulting in the memory die 160 having an increased size or reduced storage capacity due to having fewer memory cells for a given die area, among other disadvantages.

[0034] According to the techniques described herein, a group of memory dies 160 ("provider memory dies") may include power management circuits configured to supply operating voltages to other memory dies 160 ("recipient memory dies") such that the other memory dies 160 may have fewer power management circuits, smaller power management circuits, or no power management circuits. Thus, the size of the recipient memory dies 160 may be reduced (e.g., by omitting segments of the memory dies previously occupied by power management circuitry) or the capacity of the recipient memory dies 160 may be increased (e.g., by using segments of the memory dies previously occupied by power management circuitry for memory cells), among other advantages. In some cases, if another provider memory die supplies operating voltages to a provider memory die, the latter provider memory die may also be considered a recipient memory die.

[0035] Figure 2 An example of a memory device 200 supporting power management according to an example disclosed herein is described. The memory device 200 may be a memory device 200 as described in connection with Figure 1 1 or memory device 110. However, the techniques described herein are not limited to the devices described herein and may be implemented by any device having multiple memory dies. In some examples, memory device 200 may be referred to as a memory module and may be included in a memory device such as described with respect to FIG. Figure 1 The memory system 100 or memory device 110 described herein, or another type of device. For example, the memory device 200 may be a dual in-line memory module (DIMM).

[0036] The memory device 200 can be divided into power supply segments 205, which can define groupings of recipient memory dies 210 that are powered by a subset (e.g., one or more) of the provider memory dies 210. For example, a memory die 210-a in a power supply segment 205-a can use an operating voltage (e.g., V A ) to perform various operations or to power various components. And the memory die 210-b in the power supply segment 205-b can use the operating voltage (e.g., V B ) to perform various operations or to power various components. In some cases, the operating voltage V A and V B can have the same voltage level or different voltage levels (e.g., voltage V A and V B may have the same amplitude or different amplitudes). For the purpose of differentiation, Figures 2 to 4 In FIG, the donor memory die is shaded.

[0037] Using a subset of the provider memory dies 210 to supply operating voltages to the memory dies 210 in the power segments 205 can allow the recipient memory dies 210 to have fewer power management circuits (PMCs), smaller power management circuits, or no power management circuits, which in turn can reduce the size of the memory dies 210 and / or increase the capacity of the memory dies 210 relative to memory dies in devices using other power management schemes. In addition, using different subsets of the provider memory dies 210 to power different power segments 205 can isolate power problems in one power segment 205 from other power segments 205 (e.g., power segment 205-b can be shielded to avoid power problems in power segment 205-a), which can improve system performance. Furthermore, the use of power segments can enable local power management, as described in more detail below. In some cases, the power management circuit can be referred to as a power management integrated circuit (PMIC).

[0038] The operating voltage provided by the provider memory die 210 may be based on the supply voltage (eg, V Supply For example, the provider memory die 210 - a - 5 may be based on the power supply voltage V Supply Generates operating voltage V for memory dies (eg, memory dies 210-a-1 to 210-a-8) in power segment 205-a A The provider memory die 210 - b - 5 can be based on the power supply voltage V SupplyGenerates operating voltage V for memory dies in power segment 205-b (eg, memory die 210-b-1 through memory die 210-b-8) B In some cases, the operating voltage V A and V B may have the same voltage level and / or may be lower than the voltage V supplied by conductor 215. Supply .

[0039] The generation of the operating voltage may be performed by the power management circuit 220 on the provider memory die 210. For example, the power management circuit 220-a may generate the operating voltage V A , the operating voltage V A The power management circuit 220-b can be used to operate the provider memory die 210-a-5 and other memory dies in the power segment 205-a. And the power management circuit 220-b can generate an operating voltage V B , the operating voltage V B The operating voltage may be used to operate the provider memory die 210-b-5 and other memory dies in the power supply segment 205-b. Generating the operating voltage may include converting the received voltage (e.g., V Supply ) changes (e.g., reduces) a received voltage from one level to another level and / or adjusts (e.g., smoothes, maintains within a threshold range). For example, the power management circuit 220 can use a power supply voltage of x volts (V) to generate an operating voltage of y V with reduced fluctuations. Therefore, the power management circuit 220 can generate the operating voltage based on the power supply voltage that is higher than the operating voltage. In other words, the power management circuit 220 can generate the operating voltage by converting the original input voltage to a desired level.

[0040] Each provider memory die 210 can be configured to transmit a voltage V Supply As described, the voltage V Supply may be higher than the operating voltage of the memory die; however, in some instances, the voltage V SupplyThe main power management circuit 225-c may be lower than the operating voltage or the same as the operating voltage. In some examples, the conductor 215 may be supplied with current from the main power management circuit 225, which may regulate a voltage (e.g., from a power source, such as a battery) that is too high for the provider memory die 210 to handle. Thus, the main power management circuit 225 may reduce and / or smooth the voltage from the power source before outputting the regulated voltage to the provider memory die 210. Alternatively, the conductor 215 may be supplied with current directly from the power source (assuming that the memory die 210 is configured to handle unregulated voltage). In some cases, the main power management circuit 225-c may be disposed on the memory device 200 or may be external to the memory device 200. Furthermore, the conductor 215 may be positioned at the card edge of the memory device 200 (e.g., the conductor 215 may be positioned within a threshold distance of the edge of the substrate on which the memory die 210 is disposed).

[0041] The operating voltage generated by the power management circuit 220 can be used by the provider memory die 210, as well as output or supplied to the recipient memory die 210 in the associated power segment 205. Thus, the memory die 210 in a power segment 205 can operate using the operating voltage generated by the provider memory die 210 in the power segment. The use of the operating voltage can include applying the operating voltage to one or more components of the memory die 210 (e.g., to activate, deactivate, drive, bias, and / or power the one or more components). Although each power segment 205 is shown with a single provider memory die 210, in some cases, the power segment 205 can include additional power management circuits (e.g., on the same provider memory die 210 or on additional provider memory dies) that supply additional operating voltages to the memory die 210 in the power segment 205.

[0042] Although the receiving memory die are shown as being coupled with the provider memory die 210, in some cases the receiving memory die 210 may be further coupled with the power management circuit 220 in each provider memory die 210. For example, each receiving memory die 210 may be coupled with one or more permanent or activatable conductive paths that terminate at the power management circuit 220. Thus, each receiving memory die 210 may be configured to receive operating voltages from one or more provider memory die 210 in the power segment 205.

[0043] As described, dividing the memory die 210 into power supply segments 205 powered by respective provider memory die 210 can allow for local and independent power management, which can improve system performance. For example, power supply segment 205-a can be isolated from power supply problems (e.g., surges) in power supply segment 205-b, and vice versa. In addition, the power supply segments 205 can be managed based on the characteristics of each power supply segment 205, which can save power. For example, when a memory die 210 in power supply segment 205-a reaches a threshold activity level, the provider memory die 210-a-5 can be disconnected by stopping supplying an operating voltage V to the memory die 210-a. A Therefore, the provider power memory dies 210 can operate independently of each other.

[0044] Although the recipient memory die 210 is shown without power management circuitry, in some cases the recipient memory die 210 may include one or more power management circuits that further refine the operating voltage(s) received from the provider memory die(s) 210 to more precise values, or generate intermediate operating voltages based on the operating voltage(s) received from the provider memory die(s) 210. Additionally, the techniques described herein may be implemented for different configurations of the memory device 200, and thus are not limited to the illustrated configuration.

[0045] Figure 3 An example of a memory device 300 supporting power management according to an example disclosed herein is described. The memory device 300 may be a memory device 300 as described in connection with Figure 1 The system 100 or the memory device 110 described, or as described with respect to Figure 2 300 is an example of a memory device 200 described herein. However, the techniques described herein are not limited to the devices described herein and may be implemented by any device having multiple memory dies. In some examples, memory device 300 may be referred to as a memory module (e.g., memory device 300 may be a DIMM) and may be included in a memory device such as described with respect to FIG. Figure 1 The memory system 100 or memory device 110 described, or as described with respect to Figure 2 In the described memory device 200 or another type of device.

[0046] The memory device 300 can include a power segment 305, which can be an example of the power segment 205. Thus, the power segment 305 can define a grouping of memory dies 310 that are powered by a shared set of provider memory dies 310. Using a set of provider memory dies 310 to supply operating voltages to the memory dies 310 in a segment can allow the recipient memory dies 310 to have fewer power management circuits, smaller power management circuits, or no power management circuits, which in turn can reduce the size of the memory dies 310 and / or increase the capacity of the memory dies 310 relative to memory dies in devices using other power management schemes.

[0047] The memory device 300 may include a main power management circuit 325 that may generate a voltage (eg, V Supply ). Alternatively, the voltage V Supply may originate from a component other than the main power management circuit 325, such as a battery. Supply Regardless of the source of the voltage V Supply to the power management circuit 320 (eg, the conductor 315 may be configured to provide a voltage V Supply The power management circuit 320 may be coupled to the conductor 315 and may be configured to receive a voltage V via one or more permanent or activatable conductive paths coupling the power management circuit 320 to the conductor 315. Supply Thus, a voltage V may be received at each power management circuit 320 on each provider memory die 310. Supply .

[0048] The power management circuit 320 can be based on the voltage V Supply Different operating voltages are generated for the power supply segments 305. For example, the power management circuit 320-a on the provider memory die 310-a may generate an operating voltage V A , the operating voltage V A The power management circuit 320-b on the provider memory die 310-b can generate an operating voltage V B , the operating voltage V B The power management circuit 320-c on the provider memory die 310-c can generate an operating voltage V C , the operating voltage V CUsed to operate the provider memory die 310-c and distributed to other memory dies 310 in the power segment 305. The memory dies 310 can use different operating voltages to perform different functions, such as operating memory arrays, I / O circuitry, controllers, and other components on or coupled to the memory die 310.

[0049] Therefore, the memory dies 310 in the power segment 305 can use the operating voltage V generated by the power management circuit 320 on the provider memory dies 310-a, 310-b, and 310-c, respectively. A 、V B and V C Because the operating voltages are generated by power management circuits 320 on a subset of memory dies 310, other memory dies in power segment 305 can omit power management circuits that would otherwise be included to generate those operating voltages. As a result, the size of memory dies 310 can be smaller and / or the capacity of memory dies 310 can be larger relative to other power management techniques.

[0050] To facilitate passing operating voltages between memory dies 310, memory device 300 may include a network of permanent or activatable conductive paths that couple power management circuits 320 on a provider memory die 310 with other memory dies 310 in power segment 305. For example, power management circuit 320-a may be coupled to each of memory dies 310-b through 310-f via one or more respective conductive paths. The conductive paths may include a series of conductive traces, passive components, and / or activatable components that are collectively configured to transfer current from one termination device (e.g., power management circuit 320) to another termination device (e.g., memory die 310).

[0051] about Figure 2 The extended language and disclaimer discussed here also applies to Figure 3 In addition, regarding Figure 3 Aspects of the described technology may be related to Figure 2 Aspects of the described techniques are used in combination.

[0052] Figure 4 An example of a memory device 400 supporting power management according to an example disclosed herein is illustrated. The memory device 400 may be a memory device 400 as described in connection with Figure 1 The system 100 or the memory device 110 described above, as described with respect to Figure 2 The memory device 200 described or as described with respect to Figure 34 is an example of a memory device 300 described herein. However, the techniques described herein are not limited to the devices described herein and may be implemented by any device having multiple memory dies. In some examples, memory device 400 may be referred to as a memory module (e.g., memory device 400 may be a DIMM) and may be included in a memory device such as described with respect to FIG. Figure 1 The memory system 100 or memory device 110 described above, as described with reference to Figure 2 The memory device 200 described, as described with respect to Figure 3 In the described memory device 300 or another type of device.

[0053] Different from the power management circuit 320 in the memory device 300, the power management circuit 420 has only one usable voltage V Supply As a basis for generating operating voltages. For example, only the power management circuit 420-a can use V Supply As input voltage to generate operating voltage V A Other power management circuits 420 may use operating voltages from other power management circuits 420 as input voltages for generating additional operating voltages. This technique may allow at least some of the power management circuits 420 (e.g., power management circuit 420-b and power management circuit 420-c) to be smaller or simpler in size than power management circuit 320. Additionally, because the input voltages (e.g., V A 、V B ) is lower than the voltage V Supply , so the power management circuits 420-b and 420-c are comparable to Figure 3 Its counterpart described dissipates less heat.

[0054] Similar to memory device 300, memory device 400 may include a main power management circuit 425 that provides a voltage V Supply However, the main power management circuit 425 may only provide the voltage V to the power management circuit 420-a. Supply (providing a voltage V to each of the power management circuits 420 Supply On the contrary). The power management circuit 420-a can be powered by the voltage V Supply Generates operating voltage V A , and the operating voltage V A The power management circuit 420-a can also provide an operating voltage V to the power management circuit 420-b. A , the power management circuit 420-b can use the operating voltage V A To generate the operating voltage VB The power management circuit 420-b can adjust the operating voltage V B The other memory dies 410 and the power management circuit 420-c in the power segment 405 can use the operating voltage V B To generate the operating voltage V C The power management circuit 420-c can adjust the operating voltage V C is distributed to other memory dies 410. Therefore, the operating voltage V A 、V B and V C can be distributed throughout the power supply segment 405. In some examples, the operating voltage V A 、V B and V C Can have different amplitudes or magnitudes. For example, V A Can be V B High voltage, V B V C High voltage.

[0055] Although shown as originating from the main power management circuit 425, the voltage V Supply may come from components other than the main power management circuit 425, such as a battery. Supply Regardless of the source of the voltage V Supply to the power management circuit 420-a (eg, the conductor 415 may be configured to provide a voltage V Supply Power management circuit 420 - a may be coupled to conductor 415 and may be configured to receive voltage V via a permanent or activatable conductive path coupling power management circuit 420 - a to conductor 415 . Supply However, other power management circuits (eg, power management circuit 420 - b and power management circuit 420 - c ) may be isolated from conductor 415 (and therefore from main power management circuit 425 ).

[0056] about Figure 2 The extended language of description and disclaimer may also apply to Figure 4 In addition, regarding Figure 4 Aspects of the described technology may be related to Figure 2 and 3 Aspects of the described techniques are used in combination.

[0057] Figure 5 A block diagram 500 is shown of a memory device 505 that supports power management of the memory device according to examples as disclosed herein. The memory device 505 may be a memory device as described herein. Figures 1 to 4Memory device 505 may include a first power management circuit 510 and a second power management circuit 515. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses). First power management circuit 510 and second power management circuit 515 may be examples of PMICs.

[0058] The first power management circuit 510 can be on a memory die and can receive a first voltage. In some examples, the first power management circuit 510 can provide a second voltage to a group of memory dies coupled to the power management circuit based on the first voltage. In some examples, the first power management circuit 510 can operate the memory die based on a third voltage provided by a second memory die.

[0059] In some examples, the first power management circuit 510 can determine that the activity level of the memory die group meets the threshold. In some examples, the first power management circuit 510 can suspend providing the second voltage to the memory die group based on the activity level meeting the threshold.

[0060] The second power management circuit 515 may be on the second memory die and may provide a third voltage based on the first voltage, wherein the third voltage is provided to a second group of memory dies coupled to the second power management circuit on the second memory die. In some instances, the second power management circuit 515 may operate the second power management circuit independently of the power management circuit. In some instances, the second power management circuit 515 may provide a third voltage to a group of memory dies coupled to the second power management circuit. In some instances, the second power management circuit 515 may operate the second memory die based on a second voltage provided by the memory die. In some instances, the second power management circuit 515 may receive a first voltage, wherein the third voltage is based on the first voltage. In some instances, the second power management circuit 515 may receive a second voltage from the power management circuit, wherein the third voltage is based on the second voltage.

[0061] Figure 6 A flow chart illustrating a method or methods 600 of supporting power management of a memory device according to an example as described herein is shown. The operations of the method 600 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 600 may be implemented by a memory device or components thereof as described herein. Figure 5 The memory device described herein may be used to perform the functions described herein. In some examples, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0062] At 605, the method may include receiving a first voltage at a power management circuit on a memory die. The operations of 605 may be performed according to the methods described herein. In some examples, the first voltage may be received by a power management circuit on a memory die. Figure 5 A first power management circuit is described to perform aspects of the operation of 605 .

[0063] At 610, the method may include providing, by a power management circuit, a second voltage to a group of memory dies coupled to the power management circuit based on the first voltage. The operations of 610 may be performed according to the methods described herein. In some examples, the method may be performed by, for example, Figure 5 A first power management circuit is described to perform aspects of the operations of 610 .

[0064] In some examples, an apparatus as described herein may perform a method or methods, such as method 600. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a first voltage at a power management circuit on a memory die and providing, by the power management circuit, a second voltage to a group of memory dies coupled to the power management circuit based on the first voltage.

[0065] Some instances of the method 600 and apparatus described herein may further include operations, features, components, or instructions for providing, by a second power management circuit on a second memory die, a third voltage based on the first voltage, wherein the third voltage may be provided to a second group of memory dies coupled to the second power management circuit on the second memory die.

[0066] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for operating a second power management circuit independently of the power management circuit.

[0067] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for providing, by a second power management circuit on a second memory die, a third voltage to a group of memory dies coupled to the second power management circuit.

[0068] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for operating the memory die based on a third voltage provided by the second memory die and operating the second memory die based on the second voltage provided by the memory die.

[0069] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for receiving a first voltage at a second power management circuit, wherein the third voltage may be based on the first voltage.

[0070] Some examples of method 600 and apparatus described herein may further include operations, features, means, or instructions for receiving a second voltage from the power management circuit, wherein the third voltage may be based on the second voltage.

[0071] Some examples of the method 600 and apparatus described herein may further include operations, features, means, or instructions for determining that an activity level of the memory die group satisfies a threshold, and suspending providing the second voltage to the memory die group based on the activity level satisfying the threshold.

[0072] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0073] An apparatus is described. The apparatus may include: a group of memory dies; a first power management circuit configured to provide a first voltage used by the apparatus to provide one or more voltages for operating the group of memory dies; and a second power management circuit on a memory die of the group of memory dies and coupled to the first power management circuit, the second power management circuit configured to provide a second voltage for operating the group of memory dies based on the first voltage.

[0074] Some instances of the device may include a second group of memory dies; and a third power management circuit, which is on a second memory die of the second group of memory dies and is coupled to the first power management circuit, and the third power management circuit is configured to provide a third voltage for operating the second group of memory dies based on the first voltage.

[0075] In some examples, a third power management circuit can be isolated from the group of memory dies, and a second power management circuit can be isolated from the second group of memory dies.

[0076] Some examples of the apparatus may include a third power management circuit on a second memory die of the set of memory dies, the third power management circuit configured to provide a third voltage for operating the set of memory dies.

[0077] In some examples, the third power management circuit may be configured to provide the third voltage based on the first voltage. In some examples, the third power management circuit may be configured to provide the third voltage based on the second voltage.

[0078] Some examples of the apparatus may include a set of activatable conductive paths between the second power management circuit on the memory die and one or more other memory dies in the set of memory dies. In some examples, each memory die in the set of memory dies may be configured to receive the second voltage from the memory die.

[0079] Some instances of the device may include a second group of memory dies configured to be powered by a third power management circuit on a second memory die included in the second group of memory dies, wherein the second power management circuit and the third power management circuit may be configured to operate independently.

[0080] In some examples, the first power management circuit can be on a second memory die.Some examples of the apparatus can include a first power segment that includes the set of memory dies, and a second power segment that includes a second set of memory dies.

[0081] An apparatus is described. The apparatus may include a group of memory dies, a memory die coupled to the group of memory dies, and a controller coupled to the group of memory dies, the controller being operable to cause the apparatus to: receive a first voltage at a power management circuit on the memory dies; and provide, by the power management circuit, a second voltage to the group of memory dies coupled to the power management circuit based on the first voltage.

[0082] Some examples may further include providing, by a second power management circuit on a second memory die, a third voltage based on the first voltage, wherein the third voltage may be provided to a second group of memory dies coupled to the second power management circuit on the second memory die.

[0083] Some examples may further include operating the second power management circuit independently of the power management circuit.Some examples may further include providing, by a second power management circuit on a second memory die, a third voltage to the set of memory dies coupled to the second power management circuit.

[0084] Some examples may further include operating the memory die based on the third voltage provided by the second memory die, and operating the second memory die based on the second voltage provided by the memory die. Some examples may further include receiving the first voltage at the second power management circuit, wherein the third voltage may be based on the first voltage.

[0085] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0086] The terms "electronic communication," "conductive contact," "connected," and "coupled" may refer to a relationship between components that supports a signal flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact or connected or coupled to each other) if there is any conductive path between the components that can support a signal flow between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) may be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component, such as a switch, transistor, or other component. In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components, such as a switch or transistor.

[0087] The term "coupled" refers to the condition of transitioning from an open circuit relationship between components (where signals cannot currently communicate between components via conductive paths) to a closed circuit relationship between components (where signals can communicate between components via conductive paths). When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not allow signals to flow.

[0088] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0089] The devices discussed herein, including memory arrays, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping method.

[0090] The switch components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic components by conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0091] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples". The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0092] In the accompanying drawings, similar components or features may have the same reference label. In addition, individual components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the second reference label.

[0093] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted by a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0094] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0095] As used herein, "or," as used in the claims, as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one" or "one or more") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0096] Computer-readable media include both non-transitory computer storage media and communication media, and the communication media include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general or special computer. As an example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general or special computer or a general or special processor. Any other non-transitory media. Moreover, any connection is appropriately referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0097] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be in the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: a set of memory dies; a first power management circuit configured to provide a first voltage used by the apparatus to provide one or more voltages for operating the set of memory dies; a second power management circuit on a first memory die of the memory die set and coupled to the first power management circuit, the second power management circuit being configured to provide a second voltage for operating the memory die set based at least in part on the first voltage, and and a third power management circuit on the second memory die of the memory die group and coupled to the second power management circuit, the third power management circuit being configured to provide a third voltage for operating the memory die group to the first memory die based at least in part on the second voltage provided by the second power management circuit.

2. The apparatus according to claim 1, further comprising: a second set of memory dies; and A fourth power management circuit on a third memory die of the second group of memory die and coupled to the first power management circuit is configured to provide a fourth voltage for operating the second group of memory die based at least in part on the first voltage.

3. The apparatus of claim 2, wherein the fourth power management circuit is isolated from the group of memory dies and the second power management circuit is isolated from the second group of memory dies.

4. The apparatus according to claim 1, further comprising: A fourth power management circuit is on a third memory die of the memory die set, the fourth power management circuit being configured to provide a fourth voltage for operating the memory die set. 5 . The apparatus of claim 4 , wherein the fourth power management circuit is configured to provide the fourth voltage based at least in part on the first voltage.

6. The apparatus of claim 4, wherein the fourth power management circuit is configured to provide the fourth voltage based at least in part on the second voltage.

7. The apparatus of claim 1, further comprising: A plurality of activatable conductive paths between the second power management circuit on the first memory die and one or more other memory dies of the set of memory dies.

8. The apparatus of claim 1, wherein each memory die in the group of memory dies is configured to receive the second voltage from the first memory die.

9. The apparatus of claim 1 , wherein the memory die set is configured to be powered by the second power management circuit on the first memory die, the apparatus further comprising: A second group of memory dies is configured to be powered by a fourth power management circuit included on a third memory die in the second group of memory dies, wherein the second power management circuit and the fourth power management circuit are configured to operate independently.

10. The apparatus of claim 1, wherein the first power management circuit is on a third memory die.

11. The apparatus of claim 1 , further comprising: a first power section including the memory die set; and A second power segment includes a second group of memory dies.

12. A method comprising: receiving a first voltage from a second memory die at a power management circuit on the first memory die; and A second voltage is provided by the power management circuit to the second memory die and a group of memory die coupled to the power management circuit, the second voltage being a different level than the first voltage and based at least in part on the first voltage received from the second memory die.

13. The method according to claim 12, further comprising: A third voltage is provided by a second power management circuit on a third memory die based at least in part on the first voltage, wherein the third voltage is provided to a second group of memory dies coupled to the second power management circuit on the third memory die.

14. The method according to claim 13, further comprising: The second power management circuit is operated independently of the power management circuit.

15. The method according to claim 12, further comprising: A third voltage is provided to the set of memory dies by a second power management circuit on a third memory die.

16. The method according to claim 15, further comprising: operating the first memory die based at least in part on the third voltage provided by the third memory die; and The third memory die is operated based at least in part on the second voltage provided by the first memory die.

17. The method according to claim 15, further comprising: The first voltage is received at the second power management circuit, wherein the third voltage is based at least in part on the first voltage.

18. The method of claim 15, wherein the second power management circuit on the third memory die is coupled to the power management circuit on the first memory die, the method further comprising: The second voltage is received from the power management circuit, wherein the third voltage is based at least in part on the second voltage.

19. The method of claim 12, further comprising: determining that an activity level of the memory die group satisfies a threshold; and Based at least in part on the activity level satisfying the threshold, providing the second voltage to the group of memory dies is suspended.

20. An apparatus comprising: A set of memory dies, a first memory die coupled to the memory die set, and a controller coupled to the first memory die, the controller being operable to cause the device to: receiving a first voltage from a second memory die at a power management circuit on the first memory die; and A second voltage is provided by the power management circuit to the second memory die and the group of memory dies coupled to the power management circuit, the second voltage being a different level than the first voltage and based at least in part on the first voltage received from the second memory die.

21. The apparatus of claim 20, wherein the controller is further operable to cause the apparatus to: A third voltage is provided by a second power management circuit on a third memory die based at least in part on the first voltage, wherein the third voltage is provided to a second group of memory dies coupled to the second power management circuit on the third memory die.

22. The apparatus of claim 21, wherein the controller is further operable to cause the apparatus to: The second power management circuit is operated independently of the power management circuit.

23. The apparatus of claim 20, wherein the controller is further operable to cause the apparatus to: A third voltage is provided by a second power management circuit on a third memory die to the group of memory dies coupled to the second power management circuit.

24. The apparatus of claim 23, wherein the controller is further operable to cause the apparatus to: operating the first memory die based at least in part on the third voltage provided by the third memory die; and The third memory die is operated based at least in part on the second voltage provided by the first memory die.

25. The apparatus of claim 23, wherein the controller is further operable to cause the apparatus to: The first voltage is received at the second power management circuit, wherein the third voltage is based at least in part on the first voltage.

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