Substrate warpage control for mounting semiconductor dies

Abstract

A substrate and a method of manufacturing a substrate. The substrate is suitable for mounting at least one semiconductor die to a printed circuit board. The substrate comprises two opposing stacks, each stack comprising alternating layers of copper and electrically insulating film. The film and copper have different coefficients of thermal expansion, allowing the warpage behavior of the substrate to be controlled by providing different film thicknesses between the opposing stacks.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to substrates for mounting semiconductor dies onto printed circuit boards and methods of manufacturing such substrates. BACKGROUND

[0002] An integrated circuit is a set of electronic circuits fabricated on a single piece of semiconductor material, such as silicon. Typically, integrated circuits are mass produced on a single large wafer of semiconductor material, which is then diced into pieces, each containing a copy of the integrated circuit. Each of these pieces is called a die.

[0003] In order to provide the integrated circuit in the form of a useful electronic component that can be connected to other components to receive power and exchange signals, the die is mounted on a printed circuit board (PCB). Different techniques of mounting the die onto the PCB are known, each having its own advantages and disadvantages.

[0004] Some techniques of mounting the die onto the PCB utilize a substrate to bridge the interconnect pitch between the die technology and the PCB technology. The substrate includes multiple copper layers that provide electrical connections between the die and the PCB. These copper layers are interleaved with layers of electrically insulating material. The copper provides electrical connections between the two sides of the substrate through vias in the electrically insulating material.

[0005] Due to the arrangement of the copper layers across the substrate, which typically varies, there can be instances where there is a copper imbalance between one side of the substrate and the other. This copper imbalance results in an imbalance in the coefficient of thermal expansion (CTE) between one side of the substrate and the other side of the substrate. Due to the application of heat during the process of manufacturing the substrate and mounting the die, the imbalance in the CTE between the two sides of the substrate results in warping in the substrate.

[0006] The warping in the substrate presents certain problems during the packaging assembly process. For example, in flip chip packaging, multiple solder bumps with fine pitch and size are used to connect the die to the substrate. These solder bumps between the die and the substrate can be compromised. This can happen if the warping of the substrate causes regions of the substrate to become too close to the die during the mounting process, resulting in some of the solder joints between the substrate and the die being compressed and possibly fusing together as the waists of the solder bumps expand under compression. In addition, the warping in the substrate can also result in some of the expected connections between the substrate and the PCB not being formed, as some of the packaging solder balls are too far away from the PCB to form a reliable solder joint. SUMMARY

[0007] Therefore, there is a need to control the warpage of the substrate that occurs due to heating. One way to address this problem is to adjust the placement of the copper layers to minimize warpage due to imbalance in the amount of copper on different sides of the substrate. However, relying entirely on this approach places design restrictions on the copper layout in the substrate, which can make it more challenging to achieve the required connections between the die and the PCB as well as proper power and signal integrity.

[0008] According to a first aspect, there is provided a substrate for mounting at least one semiconductor die onto a printed circuit board, the substrate comprising: a first stack on a first side of the substrate adapted to be arranged towards the semiconductor die, the first stack comprising a plurality of copper layers interleaved with layers of an electrically insulating film; a second stack on a second side of the substrate adapted to be arranged towards the printed circuit board, the second stack comprising a plurality of copper layers interleaved with layers of an electrically insulating film, wherein the electrically insulating film has a different coefficient of thermal expansion than copper, wherein each of one or more layers of the electrically insulating film of the second stack has a different thickness than a corresponding one of the layers of the electrically insulating film of the first stack.

[0009] For this new substrate, the thickness of one or more layers of the electrically insulating film is set to be greater on one side of the substrate than on the other side of the substrate. By doing so, the warpage behavior can be controlled. By using the difference in thickness of the electrically insulating film to control the warpage of the substrate, a substrate can be produced that exhibits a more predictable warpage behavior. This allows problems associated with warpage to be addressed with less significant design restrictions on the substrate.

[0010] The effects exhibited by this new substrate are surprising to the inventors. It was thought that, although the coefficient of thermal expansion of the insulating film can be different than copper, changing the thickness of the insulating film would have little effect on the warpage of the substrate, as the Young’s modulus of the materials used for such insulating films is typically much lower than that of copper. However, experimental evidence has confirmed that even small differences in thickness between layers of the electrically insulating film have a significant effect on the warpage of the substrate.

[0011] In some embodiments, each of one or more layers of the electrically insulating film of the second stack has a greater thickness than a corresponding one of the layers of the electrically insulating film of the first stack, wherein the electrically insulating film has a greater coefficient of thermal expansion than copper.

[0012] In some embodiments, each of one or more layers of the electrically insulating film of the second stack has a greater thickness than a corresponding one of the layers of the electrically insulating film of the first stack, wherein the electrically insulating film has a smaller coefficient of thermal expansion than copper.

[0013] In some embodiments, each of one or more layers of the electrically insulating film of the second stack has a greater thickness than a corresponding one of the layers of the electrically insulating film of the first stack, wherein the electrically insulating film has a greater coefficient of thermal expansion than copper.

[0014] In some embodiments, each layer of the one or more layers of the second stack of electrically insulating films has a thickness that is less than a thickness of a corresponding layer of the first stack of electrically insulating films, wherein the electrically insulating films have a coefficient of thermal expansion that is less than copper.

[0015] In some embodiments, each layer of the one or more layers of the second stack of electrically insulating films differs from a thickness of a corresponding layer of the first stack of electrically insulating films by more than one micron.

[0016] In some embodiments, a portion of each layer of the one or more layers of the first stack of electrically insulating films has a first thickness, wherein the portion of each layer of the one or more layers of the first stack of electrically insulating films is between and adjacent to two copper layers of the first stack, wherein a portion of each corresponding layer of the second stack of electrically insulating films has a second thickness, wherein the portion of each corresponding layer of the second stack of electrically insulating films is between and adjacent to two copper layers of the second stack, wherein the first thickness is different than the second thickness.

[0017] In some embodiments, the first thickness is greater than the second thickness, wherein the electrically insulating films have a coefficient of thermal expansion that is greater than copper.

[0018] In some embodiments, the first thickness differs from the second thickness by more than one micron.

[0019] In some embodiments, the one or more layers of the second stack of electrically insulating films includes a layer of electrically insulating film of the second stack that is configured to be disposed furthest from the printed circuit board, wherein the corresponding layer of the first stack of electrically insulating films includes a layer of electrically insulating film of the first stack that is configured to be disposed furthest from the semiconductor die.

[0020] In some embodiments, the one or more layers of the second stack of electrically insulating films includes only a single layer of electrically insulating film, wherein the corresponding one or more layers of the first stack of electrically insulating films includes only a single layer of electrically insulating film.

[0021] In some embodiments, the one or more layers of the second stack of electrically insulating films includes a plurality of layers of electrically insulating film, wherein the corresponding one or more layers of the first stack of electrically insulating films includes a plurality of layers of electrically insulating film.

[0022] In some embodiments, the electrically insulating films are build-up films.

[0023] In some embodiments, the substrate further includes a core, wherein the first stack is disposed on a first side of the core, wherein the second stack is disposed on a second side of the core.

[0024] According to a second aspect, there is provided a method of manufacturing a substrate according to the first aspect, the method comprising: adding each of one or more layers of electrically insulating film of the second stack to the second stack such that each of the one or more layers of electrically insulating film of the second stack is stacked on one of the copper layers of the second stack, adding each of one or more corresponding layers of electrically insulating film of the first stack to the first stack such that each of the one or more corresponding layers of electrically insulating film of the first stack is stacked on one of the copper layers of the first stack, wherein each of the one or more layers of electrically insulating film of the second stack has a thickness when added to the second stack that is different to the thickness of the corresponding layer of the electrically insulating film of the first stack when the corresponding layer is added to the first stack, the method comprising: applying heat to cause each of the one or more layers of electrically insulating film of the second stack and each of the one or more corresponding layers of electrically insulating film of the first stack to become thinner at least at the region of the respective layer stacked on one of the copper layers, wherein after the heating process each of the one or more layers of electrically insulating film of the second stack has a thickness that is different to the thickness of the corresponding layer of the electrically insulating film of the first stack.

[0025] In some embodiments, after the heating process, each of the one or more layers of electrically insulating film of the second stack has a thickness at the region where it is stacked on one of the copper layers that is different to the thickness of the corresponding layer of the electrically insulating film of the first stack at the region where the corresponding layer is stacked on one of the copper layers.

[0026] In some embodiments, for each of the one or more layers of electrically insulating film of the second stack, the thickness when added to the second stack differs from the thickness of the corresponding layer of the electrically insulating film of the first stack when the corresponding layer is added to the first stack by at least one micron.

[0027] In some embodiments, after the heating process, each of the one or more layers of electrically insulating film of the second stack differs from the thickness of the corresponding layer of the electrically insulating film of the first stack by at least one micron.

[0028] In some embodiments, each of the one or more layers of electrically insulating film of the second stack has a thickness when added to the second stack that is greater than the thickness of the corresponding layer of the electrically insulating film of the first stack when the corresponding layer is added to the first stack, wherein after the heating process each of the one or more layers of electrically insulating film of the second stack has a thickness that is greater than the thickness of the corresponding layer of the electrically insulating film of the first stack.

[0029] In some embodiments, each of the one or more layers of electrically insulating film of the second stack has a thickness when added to the second stack that is less than the thickness of the corresponding layer of the electrically insulating film of the first stack when the corresponding layer is added to the first stack, wherein after the heating process each of the one or more layers of electrically insulating film of the second stack has a thickness that is less than the thickness of the corresponding layer of the electrically insulating film of the first stack.

[0030] According to a third aspect, there is provided a substrate manufactured using the method according to the second aspect.

[0031] According to a fourth aspect, there is provided an apparatus comprising: a substrate according to the first aspect; a semiconductor die mounted on the substrate; a printed circuit board; and a plurality of solder balls forming connections between the outer copper layer of the second stack and connection pads of the printed circuit board or a further substrate for mounting on the printed circuit board.

[0032] In some embodiments, the apparatus comprises a further plurality of solder bumps forming connections between the outer copper layer of the first stack and connection pads of the semiconductor die.

[0033] In some embodiments, the apparatus is a flip chip package. BRIEF DESCRIPTION OF DRAWINGS

[0034] For a better understanding of the present application, and to show how it can be put into effect, reference will now be made, by way of example, to the accompanying drawings in which:

[0035] Figure 1 An example of a flip chip package is shown;

[0036] Figure 2 An example of a wire bond package is shown;

[0037] Figure 3 is a cross-sectional view of the top of a substrate in a flip chip package;

[0038] Figure 4 is a cross-sectional view of a substrate;

[0039] Figure 5 A portion of a substrate and its associated warping behavior is shown, wherein the substrate has layers of electrically insulating film of the same thickness in two stacks;

[0040] Figure 6 A portion of a substrate and its associated warping behavior is shown, wherein the substrate has a layer of electrically insulating film in the top stack of the substrate that is thinner than the corresponding layer in the bottom stack of the substrate;

[0041] Figure 7 A portion of a substrate and its associated warping behavior is shown, wherein the substrate has a layer of electrically insulating film in the top stack of the substrate that is thicker than the corresponding layer in the bottom stack of the substrate;

[0042] Figure 8 The relationship between a portion of the thickness of the electrically insulating film and the warping of the substrate is shown;

[0043] Figure 9 A portion of a substrate is shown, wherein a plurality of respective pairs of layers of electrically insulating film have different thicknesses from each other; and

[0044] Figure 10 A method of manufacturing a substrate according to embodiments of the present application is shown. DETAILED DESCRIPTION

[0045] Embodiments will now be described in greater detail in reference to the drawings. These embodiments can be implemented with integrated circuits including intelligent processing units (IPUs), which are described in U.S. Application No. 15 / 886,065, the contents of which are incorporated by reference herein. Each of the dies discussed in the examples below can include such an IPU.

[0046] There are different techniques that can be used to mount a die to a PCB. A first of these techniques, called flip-chip, utilizes a series of solder bumps to form the connection between the die and the substrate. In this technique, the die is “flipped”, i.e., positioned such that the semiconductor wafer is facing away from the substrate, and the active side of the die, which includes the connection pads, is facing toward the substrate. Solder bumps are formed on these connection pads on the active side in order to connect the pads to the substrate.

[0047] REFERENCE Figure 1 , Figure 1 An example of a flip-chip package 100 is shown. The package 100 shows a die 101 with a series of solder bumps 102 arranged along one side of the die 101. During a reflow process, the package 100 is heated (e.g., to 240°C) to melt the solder bumps 102 to form a connection between the die 101 and a substrate 104. After the reflow process, the solder bumps 102 cool and solidify and secure the die 101 to the substrate 104. In a subsequent process, an adhesive 103, called underfill 103, is added on top of the substrate 104 and flows between the gaps between the solder bumps 102. This underfill 103 is then heated to harden it and form a supportive bond between the die 101 and the substrate 104 through the network of underfill 103 left between the solder bumps 102. This reduces the stress on the active circuitry of the die 101 due to the difference in thermal expansion coefficients and further prevents any solder bump 102 from fusing between the solder bumps 102 that can occur during any subsequent reflow of the package 100. The solder bumps 102 are secured at predetermined connection points on the substrate 104, allowing for electrical connections between the connection pads of the die 101 and the substrate 104 through the solder bumps 102. The predetermined connection points are part of the copper top layer of the substrate 104.

[0048] On the other side of the substrate 104, the substrate 104 is connected to a PCB 105 by a series of solder balls 106. These solder balls 106 are larger in size than the bumps 102 and can be referred to as ball grid array (BGA) solder balls 106. During a reflow process in which the package 100 is heated (e.g., to 240°C), the solder balls 106 are melted. After the process, the solder balls 106 cool, fixing the substrate 104 to the PCB 105. The solder balls 106 are fixed to predetermined connection points on the bottom copper layer of the substrate 104, providing electrical connections between the substrate 104 and the connection points on the PCB 105. These predetermined connection points are part of the copper top layer of the substrate 104.

[0049] A second technique for mounting a die to a PCB is referred to as wire bonding, utilizing a series of wire bond pads fixed to the active side of the die, which is positioned away from the substrate. These wire bond pads are connected to wires, the other end of which make connections with predetermined connection points on the substrate.

[0050] Reference is made to Figure 2 , Figure 2 An example of a wire bonded package 200 is shown. The die 201 shown can be functionally identical to the die 101, but in this case, the active side of the die 201 faces away from the substrate 204. Connection pads on the top of the die 201 are connected to the substrate 204 by wires 202. The wires 202 are connected to predetermined connection points on the copper top layer of the substrate 204, forming appropriate connections through the substrate 204 to a PCB 205.

[0051] The die 201 is fixed to the substrate 204 using a die attach adhesive 203, without the use of solder bumps 102.

[0052] As in the example of the flip chip package 100, the substrate 204 is connected to the PCB 205 by solder balls 206, which can be BGA balls. Just as Figure 1 The solder balls 206 are heated and positioned at connection points on the bottom copper layer of the substrate 204, as shown in the solder balls 106 in

[0053] Although Figure 1 and Figure 2Both show substrates 104, 106 connected directly to PCB 205 by solder balls 106, 206, but in some embodiments of the invention, the substrate to which the die is connected can be connected to one or more additional substrates positioned between the substrate and the PCB. In such a case, solder balls (such as balls 106, 206) would fix the substrate to the additional substrate(s), thereby mounting the die to the PCB through the additional substrate(s).

[0054] Embodiments of the invention have advantages for both flip-chip package 100 and wire-bond package 200. By controlling the warpage of the substrate, the likelihood of failure of the solder bump / solder ball connections used to connect the substrate to the die / PCB can be reduced. Since both flip-chip package 100 and wire-bond package 200 use solder balls 106, 206 to connect die 101, 201 to PCB 105, 205 (directly, or through one or more additional substrates), the invention is applicable to both flip-chip package 100 and wire-bond package 200. However, since flip-chip package 100 also includes an additional set of solder bumps 102 used to connect die 101 to substrate 104, the invention is particularly advantageous when applied to flip-chip package 100.

[0055] Reference is made to Figure 3 , Figure 3 An example showing multiple cross-sectional views along the top of substrate 104 used in flip-chip package 100 is shown. The cross-sectional views show the effect of warpage on solder bumps 102a-i used at different points along the bottom of die 101. First cross-sectional view 310 is a view of solder bumps 102a-c positioned at one edge of die 101. Second cross-sectional view 320 is a view of solder bumps 102d-f positioned approximately in the middle of die 101. Third cross-sectional view 330 is a view of solder bumps 102g-i positioned at the other edge of die 101.

[0056] The three different views 310, 320, 330 are for a substrate 104 that is warped in such a way that substrate 104 is closer to die 101 at the edges of die 101 than at the center of die 101. Such a substrate is said to exhibit positive warpage. The effect of this positive warpage can be observed by comparing cross-sectional views 310, 320, 330. In the center view 320, the distance between die 101 and substrate 104 is 62 μm, while in the edge views 310, 330, the distance between die 101 and substrate 104 is 52 μm and 44 μm, respectively.

[0057] As can be seen from views 310, 330, when the gap between the die 101 and the substrate 104 is small, the solder bumps 102 can be squished and deformed. Both the solder bumps 102a-c and the solder bump 102g exhibit some degree of deformation due to the proximity between the substrate 104 and the die 101 at their respective locations. If the deformation remains below a certain level, this is not necessarily problematic for the operation of the device. However, if the deformation becomes too large during the reflow process, the deformed solder bumps can connect, resulting in a single molten solder bump, and no two separate connections between the die 101 and the substrate 104. As shown in view 340, where the solder bump 102h merges with the solder bump 102i to form a single, expanded solder bump. Figure 3

[0058] It should be understood that, in addition to presenting connection problems at the interface between the die 101 and the substrate 104, warpage of the substrate 104 can also present connection problems at the interface between the substrate 104 and the PCB 105. For example, warpage of the substrate 104 causes the gap between the die 101 and the substrate 104 at the edge of the substrate 104 to narrow, as shown in view 350, which can cause the gap between the PCB 105 and the substrate 104 at the edge of the substrate 104 to widen. This larger gap can mean that the solder balls 106 located at the edge of the substrate 104 do not make contact with the PCB 105, and thus do not form the intended reliable solder joints. This problem at the substrate / PCB interface can also be presented in the wire bond package 200 shown in view 360, and in the flip chip package shown in view 370. If an additional substrate is used to mount the substrate 104, 204 and the die 101, 201 to the PCB 105, 205, a problem can also be presented at the interface between the substrate 104, 204 and such additional substrate. Figure 3 Figure 2 Figure 1

[0059] Referring to Figure 4 , Figure 4 shows a cross-section of the substrate 104. The solder bumps 102 are shown at the top of the substrate 104. The substrate 104 includes a core 405, around which two stacks 410a, 410b are built. Each of the stacks 410a, 410b includes a plurality of copper layers interleaved with a plurality of electrically insulating film layers. For example, Figure 4 shows an example of a copper layer 420 and an example of an electrically insulating film layer 425 that are part of the stack 410a. In this description, the term “first stack” refers to a stack that is suitable for attachment to a die. Thus, the stack 410a is an example of a first stack. In this description, the term “second stack” refers to a stack that is suitable for attachment to a PCB or to an additional substrate for mounting to a PCB. Thus, the stack 410b is an example of a second stack.

[0060] ​​​​The core 405 includes a mixture of glass and resin material on which the layers of the stacks 410a, 410b are built. A plurality of holes are drilled through the core 405, and copper plating is added to the holes to form vias 415. The vias 415 provide connections between the two stacks 410a, 410b, enabling connections to be made through the substrate 104.

[0061] In some cases, a copper layer and an electrically insulating film layer can be deposited sequentially on the core 405. In this case, the electrically insulating film can be referred to as a build-up film. For example, the build-up film can be an Ajinimoto build-up film (ABF). When constructing each stack 410a and 410b, a layer of copper is initially deposited on the core 405. The copper is patterned to provide the connections required for the layer, for example, to provide one or more vias 415 between the copper and the copper of the next layer up in the corresponding stack 410a, 410b. After the first layer of copper is formed and patterned, a first layer of build-up film is added to the exposed surface. The film is compressed and heated so that it flows into the gaps between the copper, leaving a planar surface. Holes are created in the film to expose the first copper layer at the base of the holes or vias, and a second layer of copper is added on top of the film. The second layer of copper enters the vias to provide connections between the first layer of copper and the second layer of copper. Figure 4 An example via 430 between layers of copper is shown. Additional layers of build-up film and additional layers of copper are added on both sides of the partially constructed substrate to provide the stacks 410a, 410b. The arrangement of copper in the stack 410a provides connections between the one or more solder bumps 102 and the one or more vias 415 in the core 405. Likewise, the arrangement of copper in the stack 410b provides connections between the one or more solder balls 106 (not shown in Figure 4

[0062] Although it has been described that each layer of the stacks 410a, 410b is built sequentially, in other examples, a layer of electrically insulating film can be provided with a layer of attached copper, rather than depositing separate individual layers of build-up film and copper. Each such layer is referred to as a prepreg, and layers of prepreg are deposited on top of one another to produce each stack 410a, 410b.

[0063] Although Figure 4 The substrate 104 used in the flip-chip package 100 is shown, but the substrate 204 used in the wire-bond package 200 can have the same features as the substrate 104 described herein, but without the solder bumps 102 on the top of the substrate 104.

[0064] Furthermore, although it has been described that each of the stacks 410a, 410b is provided on one side of the core 405, the substrate can be provided as a coreless substrate, with each stack 410a, 410b connected directly to one another.​

[0065] As Figure 4 shown, the arrangement of copper layers in stack 410a is significantly different from the arrangement of copper layers in stack 410b. The different arrangement of the layout can result in copper imbalance between the two stacks 410a, 410b, which can result in warping of the substrate 104 as it is heated.

[0066] Referring Figure 5 , Figure 5 shows how the warpage of any of these substrates 104, 204 varies with temperature for different samples, in the case where the layers of electrically insulating film on both sides of the substrate have the same thickness. Figure 5 A portion 500 of a substrate is shown. The portion 500 of the substrate includes a core 405 and two layers of electrically insulating film 505, 510 on either side of the core 405. The layers 505, 510 are in respective positions in their respective stacks. Each of the layers 505, 510 can be the layer of electrically insulating film in its respective stack that is furthest from the edge of the substrate (e.g. closest to the core 405).

[0067] The layers 505, 510 are added to stacks that are the same thickness as each other, in this example 40 pm. As will be described, the thickness of each layer can change when heat is applied to soften the layers to allow the layers to deform. Each of the remaining layers of the stacks (not shown in Figure 5 ) is provided with the same thickness as the corresponding layer in the opposite stack.

[0068] The graph 515 shows how the warpage behaviour of three different substrate samples varies with temperature. The warpage can be positive warpage or negative warpage. Positive warpage indicates that the substrate is curved upwards towards the die at the edge of the die. Negative warpage indicates the opposite, i.e. the substrate is curved away from the die at the edge of the die. Positive warpage is generally less desirable than the issues discussed above in relation to Figure 3 .

[0069] The first sample (substrate 1) shown in the graph 515 exhibits negative warpage (-26) when at 35°C, and also exhibits negative warpage (-30) when heated to 260°C. When the sample substrate is cooled to 55°C, the substrate still exhibits negative warpage (-36).

[0070] The second sample shown in the graph 515 exhibits positive warpage (23) when at 35°C, and exhibits even greater positive warpage (53) when heated to 260°C. When the sample substrate is cooled to 55°C, the substrate remains at a high positive warpage (52).

[0071] The third sample shown in the graph 515 shows positive warpage (31) when at 35°C, and shows positive warpage (21) when at 260°C. When the sample substrate is cooled to 55°C, the substrate still exhibits positive warpage (30).

[0072] Thus, it can be appreciated that when the thicknesses of the two films 505, 510 are equal, the warpage behavior is inconsistent between different substrate samples. The warpage can be positive or negative, and highly dependent on the specific arrangement of copper layers on both sides of the substrate. Furthermore, the direction of warpage can vary due to natural variations in the manufacturing process.

[0073] The effects of temperature variation can also be seen in Figure 5 As previously discussed, the copper imbalance between the two sides of the substrate causes warpage when the substrate is heated. Due to the application of heat during the manufacturing process, the finished substrate exhibits warpage. As Figure 5 shown, the substrate warpage can also change in response to the application of additional heat (e.g., during a reflow process used to mount a die to the substrate).

[0074] According to embodiments of the present invention, a new substrate is provided. In the new substrate, at least one layer of electrically insulating film is thicker in one copper, film stack than in a corresponding layer in another copper, film stack. In some embodiments, only one pair of corresponding layers in the stacks is of different thickness. In other embodiments, multiple pairs of corresponding layers in the stacks can be of different thickness. Because the electrically insulating film has a different coefficient of thermal expansion than copper, by controlling the thickness of the electrically insulating film layers on both sides of the substrate in this manner, the warpage of the substrate is controlled.

[0075] As used herein, "corresponding layer" refers to a layer occupying the same position in each of the stacks. For example, a first layer of electrically insulating film in a first stack (i.e., the layer farthest from the die in the first stack, or the layer closest to the core of the substrate if a core is present) can be said to correspond to a first layer of electrically insulating film in a second stack (i.e., the layer farthest from the PCB in the second stack, or the layer closest to the core of the substrate if a core is present).

[0076] The new substrate according to embodiments of the present invention can have the same features as the substrates 104, 204 discussed above, but with one or more corresponding layers in the stacks 410a, 410b of different thickness. Although each of the example substrates 104, 204 is shown with a core 405, in some embodiments of the new substrate, the core 405 can be absent, and the two stacks can be directly connected together.

[0077] Example embodiments of the present invention will now be described with reference to Figure 6 to Figure 9 and with reference to these figures. In these examples, the CTE of the electrically insulating film is greater than the CTE of copper, resulting in the behavior shown and described. In the description, the thickness of the electrically insulating film layers is discussed. As used herein, "thickness" refers to the average thickness of the relevant film layer across the substrate.

[0078] Referring to Figure 6 , Figure 6The warpage of the substrate as a function of temperature is shown for different samples of substrates according to embodiments of the application. Figure 6 A portion 600 of a substrate is shown, displaying two layers of electrically insulating film 605, 510 surrounding the core 405. The two layers 605, 510 are in respective positions in their respective stacks. In some embodiments, the layers 605, 510 can be the layers of electrically insulating film in their respective stacks that are furthest from the substrate (e.g. closest to the core 405).

[0079] The example portion 600 of a substrate can be the same as the portion 500 of a substrate, however, the difference is that the lower half of the substrate 510 is thicker than the upper half of the substrate 605. In this example, the film layer 510 is 5 microns thicker than the film layer 605.

[0080] Figure 6 The thickness values shown indicate the thickness of the film as it is added to the stack at the time of manufacture. The layer 605 that is added as part of the first stack is 35 pm thick when added to the first stack. The layer 510 that is added as part of the second stack is 40 pm thick when added to the second stack. When these two layers are added, the portion 600 of the substrate is heated and pressed, which will cause the film to become thinner at the points where it is stacked on the copper layer. However, after this heating and thinning process, the layer 605 will still be thinner than the layer 510.

[0081] From the graph 615, it can be understood that different samples of substrates exhibit consistent negative warpage as a function of temperature. For each of the three samples, the warpage is negative when the sample is at 35 °C, heated to 260 °C, or cooled to 55 °C.

[0082] The substrate including the portion 600 can be particularly well suited to address the above-discussed problem in which the small solder bumps 102 fuse together towards the edge of the die. By consistently exhibiting negative warpage, the substrate is less likely to cause the solder bumps 102 to fuse together at the edge of the die. Figure 3

[0083] Accordingly, the portion 600 allows the direction of warpage of the substrate to be set to a consistent negative direction, and reduces the variation in warpage between different samples due to small differences in copper balance or natural variations in the manufacturing process. Other design factors, such as the copper balance and aspects of the assembly process, can then be adjusted to minimize the magnitude of warpage exhibited by the substrate, to produce substrates that exhibit only a minimal amount of warpage. By reducing the amount of warpage to a low level, the resulting substrates will not only address the above-discussed bridging problem, but will also address additional connectivity problems, such as those between the substrate and a PCB. Figure 3

[0084] Reference is made to Figure 7 , Figure 7 ​​Another example of a portion 700 of a substrate according to embodiments of the application is shown. This figure shows how the warpage of different substrate samples comprising the portion 700 varies with temperature. Figure 7 A portion 700 of a substrate is shown, displaying two layers of electrically insulating film 505, 710 surrounding the core 405. The two layers 505, 710 are in respective positions in their respective stacks. Each of the layers 505, 710 can be the layer of electrically insulating film in its respective stack that is furthest from the substrate (e.g. closest to the core 405).

[0085] The example portion 700 can be the same as the portions 500, 600, however, the difference is that the upper half of the substrate 505 is thicker than the lower half of the substrate 710. In this example, the film layer 505 is 5 microns thicker than the film layer 710.

[0086] As Figure 6 , Figure 7 The thickness values shown indicate the thickness of the film added to the stack at the time of manufacture, the thickness of the film will decrease in response to the heating and pressing process. However, after the heating and thinning process, the layer 505 will still be thicker than the layer 710.

[0087] The graph 715 shows the warpage of different substrate samples, each comprising the portion 700. From the graph 715, it can be understood that the substrate samples exhibit consistent positive warpage as the temperature varies. For each of the three samples, the warpage is positive when the sample is at 35°C, heated to 260°C or cooled to 55°C.

[0088] Accordingly, the portion 700 allows the direction of warpage to be set to a consistent positive direction, resulting in a reduction in the variation in warpage between samples. By adjusting other design factors, such as copper balance, the magnitude of this warpage can be minimised. However, as perfect copper balance is not required to control warpage, greater design freedom is provided.

[0089] In Figure 6 and Figure 7 each of the example samples, all of the layers of film, except for one layer of film, have the same thickness (e.g. 40 pm). However, one of the layers of electrically insulating film (the layer 605 in Figure 7 and Figure 7 the layer 710 in) has a different thickness (e.g. 35 pm). Accordingly, the warpage behaviour of a substrate can be modified by modifying the thickness of only a single layer of electrically insulating film in the substrate. Although in the examples shown in Figure 6 and 7 the different layer has a reduced thickness relative to the other layers of the substrate, in other embodiments the different layer can have a greater thickness, resulting in a different warpage behaviour to that shown in the graphs 615, 715.

[0090] Reference is made to Figure 8, Figure 8 How warpage of different substrate samples varies depending on the thickness of the single layer electrically insulating film in those samples is shown. Specifically, graph 800 shows how warpage varies depending on the thickness of a film layer of a portion of a first stack of a substrate. This is represented on the bottom axis of the graph, which represents the thickness of this layer of film minus the thickness of the copper layer on which this layer of film is at least partially stacked. This copper layer can be the layer in the first stack that is stacked on the core 405, and the relevant film layer is the first layer of film stacked on the bottom-most copper layer of the stack. The relevant film layer can be referred to as L6_ABF, indicating that it is the sixth layer of film from the top of the substrate. The copper layer on which this film is stacked can be referred to as L7_Cu, indicating that it is the seventh layer of copper from the top of the substrate.

[0091] Figure 8 A portion of a substrate is shown 820 that visually represents the indicator shown along the bottom axis of graph 800. The portion 820 shows a core 405, the top of which is a layer of copper 805 and a layer of film 815. A portion of layer 815 is stacked directly on the top surface of the core 405, while another portion of layer 815 is stacked on top of the copper layer 805. When the film layer 815 is added as part of the manufacture of the substrate, the film layer 815 is heated and deformed into the gap in the copper 805. This causes the portion of the film 815 that is stacked on the copper to be thinner than the film layer 815 as provided, and thinner than the portion stacked on the core 405. The thicker portion of the film 815 stacked on the core 405 is indicated by arrow 830, while the thinner portion of the film 815 is indicated by arrow 810, which corresponds to the indicator shown by the bottom axis of graph 800. It is this indicator that is most closely related to the warpage observed for the substrate. This indicator is referred to herein as the film thickness on copper 810. This thickness 810 represents the thickness of the portion of the film 815 that is between and adjacent to the two copper layers 805, 825 in the finished substrate.

[0092] Graph 800 shows warpage of different substrate samples at 35°C. It can be seen that at certain values of the thickness 810, the warpage behavior changes from more likely to be negative to more likely to be positive. This point at which the warpage changes is referred to herein as the “turning point.” The turning point occurs when the film thickness on copper 810 is the same as the film thickness on copper of the corresponding layer in another stack. For the sample substrate data in graph 800, the value of this thickness 810 is equal to 14 pm.

[0093] When the distance 810 in a sample increases above the turning point (14 pm in this example), the sample is more likely to exhibit positive warpage. This portion of graph 800 is represented by the region “smiley face” (so named to indicate the visual impression that can result from a substrate exhibiting positive warpage). Below the turning point (14 pm in this example), the sample is more likely to exhibit negative warpage. This portion of graph 800 is represented by the region “frowny face” (so named to indicate the visual impression that can result from a substrate exhibiting negative warpage).

[0094] As mentioned above Figure 5 As discussed, when the films on both sides have the same thickness, the warpage behavior is highly unpredictable, and whether the warpage is positive or negative may depend on the level of copper balance in the substrate. Figure 8 This also demonstrates that, Figure 8 The results show that when the thickness 810 of the film 815 in the top stack is approximately equal to the copper overlay thickness of the corresponding film in the bottom stack (i.e., both are approximately 14 μm), the warpage varies widely among different substrate samples. Some samples exhibit positive warpage, while others exhibit negative warpage. Whether a sample exhibits negative or positive warpage will depend on factors other than film thickness, such as the precise copper balance associated with the substrate.

[0095] like Figure 8 As shown, as the difference in copper overlay thickness increases, warpage becomes reliably negative or reliably positive. If the thickness 810 of the film in the top stack is greater than the copper overlay thickness of the corresponding film in the bottom stack, the warpage behavior is more likely to be positive. If the thickness 810 of the film in the top stack is less than the copper overlay thickness of the corresponding film in the bottom stack, the warpage is more likely to be negative.

[0096] In embodiments, the substrate may have different values ​​for the difference in film thickness between corresponding films in the two stacks. In some embodiments, this difference may be at least 1 μm. In other embodiments, this difference may be 1.5 μm. Figure 8 As shown, when the difference in copper film thickness is greater than 1.5 μm, the warping behavior is consistent with the trend of all the samples shown.

[0097] from Figure 8 It is understandable that the magnitude of substrate warpage does not increase with the increase of the thickness difference between the corresponding film layers, but is more reliably negative or positive. Therefore, setting a higher film thickness difference value is beneficial for more reliably achieving positive or negative warpage.

[0098] In some embodiments, a greater influence on warpage can be achieved by introducing thickness differences between multiple corresponding layers in an opposing stack. This allows the warpage to not only reliably be negative or positive, but also to be of a greater magnitude. (Reference) Figure 9 , Figure 9 A portion 900 of a substrate according to an embodiment of this application is shown. Figure 9 This illustrates how multiple different film layers differ in thickness on both sides of a portion 900 of the substrate. Three layers 905a, 910a, and 915a are shown as a portion of a first stack (e.g., on top of core 920). Layers 905b, 910b, and 915b are shown as a portion of a second stack (e.g., at the bottom of core 920). It should be understood that in the embodiments, even... Figure 9Only three layers are shown, but the first and second stacks can each contain more than three layers.

[0099] Layer 905a corresponds to layer 905b, layer 910a corresponds to layer 910b, and layer 915a corresponds to layer 915b. The thickness of the bottom stack layers 905b, 910b, 915b are each greater than the thickness of the corresponding top stack layers 905a, 910a, 915a. In this example, the difference in film thickness added to the substrate portion 900 is 2 pm. By introducing a thickness difference between the multiple corresponding film layers in this way, it can be observed that the amplitude of the warpage is increased to a greater level than Figure 6 and Figure 8 than shown in

[0100] In the example described above in relation to Figure 6 to Figure 9 , the electrically insulating film has a greater CTE than copper. However, in other example embodiments of the invention, the copper can have a greater CTE than the electrically insulating film. In this case, the warpage behaviour is opposite to that discussed above in relation to Figure 6 to Figure 9 . To achieve negative warpage, at least one layer of electrically insulating film of the second stack has a thickness that is less than at least one layer of electrically insulating film of the first stack. In this case, Figure 7 the arrangement of the portion 700 shown in Figure 6 results in negative warpage. To achieve positive warpage, at least one layer of electrically insulating film of the second stack has a thickness that is greater than at least one layer of electrically insulating film of the first stack. Thus, Figure 9 the arrangement of the portion 600 shown in or the arrangement of the portion 900 shown in

[0101] results in positive warpage. Figure 10 Figure 10 An example method 1000 for manufacturing a substrate according to embodiments of the application is shown. It will be appreciated that not all steps of the method 1000 are necessary and one or more steps can be omitted in some embodiments. It will also be appreciated that the manufacturing process can include further steps not shown in Figure 10 , for example various cleaning or lamination steps, but these steps are known to the skilled person. It will also be appreciated that although the manufacturing process describes building up a stack of layers on a core, in some embodiments a substrate according to an embodiment can be manufactured by developing an opposing stack using similar steps, without a core between the opposing stacks.

[0102] At S1010, holes are drilled through the core material to the substrate. These holes are formed from one side of the core to the other and are used to form vias that provide electrical connections between the two stacks. In Figure 4 , these vias are shown as vias 415.

[0103] At S1020, copper plating is added to the holes formed through the core. The copper plating provides connections for the vias. After the copper plating is added, the holes are filled with resin. Thus, the copper plating forms connections along the edges of each via, and the vias are otherwise filled with resin.

[0104] At S1020, the copper plating added to the holes is also added to the top and bottom surfaces of the core material to form a first layer of copper for each stack.

[0105] At S1030, the copper plating is etched so that the only copper remaining on the top and bottom surfaces of the core is the copper needed to form connections through the vias and the copper needed to form connections to the copper layer above which is to be added. The nature of the etching depends on the precise requirements for connections from the copper layer to the vias that will be attached above that copper layer.

[0106] At S1040, a layer of electrically insulating film is added on both sides of the partially formed substrate. For the first layer of the substrate (the layer closest to the core among any layers of the substrate that are to be added later), part of the layer will be stacked on the surface of the core and part will be stacked on the layer of copper added at S1020 and etched at S1030. The first layer on one side is part of the first stack and the first layer on the other side is part of the second stack. In embodiments, these two first layers have different thicknesses when they are added to the stacks and after they are heated and deformed.

[0107] For example, if the method 1000 is applied to form the substrate portion 600 shown, Figure 6 the thickness of the film added to form the first layer of film of the second stack (which is arranged on the bottom side of the substrate to attach to the PCB) would be 40 pm. The thickness of the film added to form the first layer of film of the first stack (which is arranged on the bottom side of the substrate to attach to the die) would be 35 pm. In other embodiments, different thicknesses can be used for the films. In some embodiments, the minimum difference in thickness between the respective pairs of layers to which the thickness difference is applied can be 1 pm (when those films are added to the stacks).

[0108] When both layers of film have been added to each side of the partially constructed substrate, the partially constructed substrate is heated and the layers of film are deformed to the gaps between the layers of copper formed on the surfaces of the core. As a result of this process, both films become thinner at least in the areas of those films that are stacked on the copper. However, even after the films have been made thinner by the heating process, the two layers of film still have different thicknesses. For example, after the heating, the part of the first layer of film of the second stack that is stacked on the copper can have a thickness of 14 pm and the part of the first layer of film of the first stack that is stacked on the copper can have a thickness of 11 pm.

[0109] At S1050, a laser drilling process is performed to drill holes in the electrically insulating film layers. These holes are drilled at points where the film needs to be connected to the underlying copper layer. When the next layer of copper is added at S1060, the holes are used to form vias, such as Figure 4 vias 430 in FIG. 4.

[0110] At S1060, additional copper layers are added on both sides of the partially constructed substrate. The additional copper layers are partially stacked on top of the film layers added at S1040. Because a process was performed at S1050 to create holes in the film layers, the additional copper added at S1060 will be placed on top of the copper that is under the film layers added at S1040. This allows for connections in every stack between the second layer of copper (added at S1060) and the first layer of copper (added at S1030).

[0111] The process of adding copper to the surface of the partially constructed substrate at S1060 can be performed by first adding resist to portions of the surface of the partially constructed substrate. Copper can then be added to the rest of the surface. Alternatively, copper can be added to the entirety of both surfaces of the partially constructed substrate, and then an etching process can be performed to remove the copper at certain points. The result of both processes is to provide copper at selected points that are suitable for providing connections to underlying copper layers and suitable for providing connections to overlying copper layers.

[0112] At S1070, if all of the copper layers and electrically insulating film layers have been added, the process proceeds to S1080. If not, the process proceeds to S1040, where additional electrically insulating film layers are added. In some embodiments, the additional respective pairs of film layers added to the two stacks can be different from the first pair of film layers, each pair comprising film of the same thickness. In other embodiments, at least one additional pair of film layers of different thicknesses can be added between these additional respective film layers used. Furthermore, although it has been described that the first film layers (i.e., the respective pair of film layers farthest from the edges of the substrate) have different thicknesses from one another, in other embodiments these first film layers can instead have the same thickness, with the thickness difference instead being used for other one or more respective pairs of film layers in the substrate.

[0113] Steps S1040-S1060 are repeated as many times as needed to establish the stacked layers of the substrate.

[0114] At S1080, the substrate can be subjected to lamination, development, and pre- soldering steps. Once complete, the substrate is cut into small portions of the substrate, each small portion suitable for mounting a single die to a PCB.

[0115] The example method 1000 described uses a build-up technique where each layer of electrically insulating layer and copper is added separately. However, in other embodiments, the manufacturing method can apply a prepreg where one layer of electrically insulating film can be provided with one layer of attached copper, the prepreg layer being deposited on top of another layer to produce each of the two stacks.

[0116] It will be understood that the above embodiments are described by way of example only.

Claims

1. A substrate for mounting at least one semiconductor die onto a printed circuit board, the substrate comprising: A first stack, on a first side of the substrate adapted to be disposed toward the semiconductor die, the first stack comprising a plurality of copper layers interwoven with deposited film layers; as well as A second stack, on a second side of the substrate adapted to be disposed toward the printed circuit board, the second stack comprising a plurality of copper layers interwoven with the deposited film layers. The deposited film has a higher coefficient of thermal expansion than copper. Each of one or more layers of the second stacked film has a different thickness than the corresponding layer of the first stacked film. Each layer of one or more of the second stacked deposited films has a thickness greater than that of the corresponding layer of the first stacked deposited films, such that in response to heat, the substrate is configured to cause negative warping of the substrate, wherein the substrate bends away from at least one semiconductor die at the edge of at least one semiconductor die. or Each layer of one or more of the second stacked deposited films has a thickness less than that of the corresponding layer of the first stacked deposited films, such that in response to heat, the substrate is configured to cause positive warping of the substrate, wherein the substrate bends toward at least one semiconductor die at the edge of at least one semiconductor die.

2. The substrate of claim 1, wherein the thickness difference between each layer of the second stacked film and the corresponding layer of the first stacked film exceeds one micrometer.

3. The substrate of claim 1, wherein a portion of each layer of one or more of the first stacked deposited films has a first thickness, wherein a portion of each layer of one or more of the first stacked deposited films is between and adjacent to the two copper layers of the first stack. A portion of each corresponding layer of the second stacked deposited film has a second thickness, wherein a portion of each corresponding layer of the second stacked deposited film is between and adjacent to the two copper layers of the second stack. The first thickness is different from the second thickness.

4. The substrate according to claim 3, wherein the difference between the first thickness and the second thickness exceeds one micrometer.

5. The substrate of claim 1, wherein one or more layers of the second stack of deposited films include a layer of deposited film of the second stack arranged furthest from the printed circuit board, wherein a corresponding layer of the first stack of deposited films includes a layer of deposited film of the first stack arranged furthest from the semiconductor die.

6. The substrate of claim 1, wherein one or more layers of the second stacked deposited film comprises only a single-layer deposited film, and the corresponding one or more layers of the first stacked deposited film comprises only a single-layer deposited film.

7. The substrate of claim 1, wherein one or more layers of the second stacked deposited film comprises a multilayer stacked film, and the corresponding one or more layers of the first stacked deposited film comprises a multilayer stacked film.

8. The substrate according to claim 1, wherein the deposited film is an Ajinomoto deposited film.

9. The substrate according to claim 1, wherein the Young's modulus of the deposited film is lower than that of copper.

10. The substrate of claim 1, wherein the substrate further comprises a core, wherein the first stack is disposed on a first side of the core, and wherein the second stack is disposed on a second side of the core.

11. A method for manufacturing a substrate according to any one of claims 1 to 10, the method comprising: Each of one or more layers of the second stacked film is added to the second stack such that each of one or more layers of the second stacked film is stacked on one of the copper layers of the second stack. as well as Each of one or more layers of the first stacked film is added to the first stack such that each of one or more layers of the first stacked film is stacked on one of the copper layers of the first stack. Wherein, each layer of the second stacked film, when added to the second stack, has a thickness different from the thickness of a corresponding layer of the first stacked film when added to the first stack, the method comprising: Heat is applied to cause each layer of the second stacked deposited film and each corresponding layer of the first stacked deposited film to become thinner, at least in the region of their respective layers stacked on one of the copper layers. Wherein, after the heating process, each layer of one or more layers of the second stacked deposited film has a thickness different from the corresponding layer of the first stacked deposited film.

12. The method of claim 11, wherein after the heating process, each layer of the second stacked deposited film has a thickness in the region where it is stacked on one of the copper layers that is different from the thickness of the corresponding layer of the first stacked deposited film in the region where the corresponding layer is stacked on one of the copper layers.

13. The method of claim 11, wherein for each layer of the stacked film of the second stack, the thickness when added to the second stack differs from the thickness of the corresponding layer of the stacked film of the first stack when that corresponding layer is added to the first stack by at least one micrometer.

14. The method of claim 11, wherein after the heating process, the thickness of each layer of the second stacked film differs from that of the corresponding layer of the first stacked film by at least one micrometer.

15. The method of claim 11, wherein each layer of the second stack of deposited films, when added to the second stack, has a thickness greater than the thickness of a corresponding layer of the first stack of deposited films when that corresponding layer is added to the first stack. in, After the heating process, each layer of one or more layers of the second stacked film has a thickness greater than that of the corresponding layer of the first stacked film.

16. The method of claim 11, wherein each layer of the second stack of deposited films, when added to the second stack, has a thickness less than the thickness of a corresponding layer of the first stack of deposited films when that corresponding layer is added to the first stack. in, After the heating process, each layer of one or more layers of the second stacked film has a thickness less than the thickness of the corresponding layer of the first stacked film.

17. An apparatus comprising: Substrate according to any one of claims 1 to 10; Semiconductor die, mounted on the substrate; Printed circuit boards; as well as Multiple solder balls form a connection between the outer copper layer of the second stack and the connection pad of the printed circuit board or an additional substrate for mounting on the printed circuit board.

18. The device of claim 17, further comprising a plurality of additional solder bumps forming a connection between the outer copper layer of the first stack and the connection pad of the semiconductor die.

19. The device according to claim 17 or 18, wherein the device is a flip-chip package.

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