Voltage regulating control circuit for voltage stabilizing power supply circuit and voltage stabilizing power supply circuit

Abstract

Embodiments of the present disclosure provide a voltage regulating control circuit and a voltage regulator circuit. The voltage regulating control circuit includes a voltage conversion circuit, a switch circuit, a voltage holding circuit, and an error amplifier. The voltage conversion circuit converts a first reference voltage to a second reference voltage when the voltage regulator circuit is in a non-sleep mode, and stops working when the voltage regulator circuit is in a sleep mode. The switch circuit connects the voltage conversion circuit to a first input of the error amplifier when the voltage regulator circuit is in the non-sleep mode, and disconnects the voltage conversion circuit from the error amplifier when the voltage regulator circuit is in the sleep mode. The voltage holding circuit holds a voltage at the first input of the error amplifier. A second input of the error amplifier is coupled to an output of the voltage regulator circuit. An error signal output by the error amplifier is used to control an output voltage of the voltage regulator circuit such that the output voltage is held at the voltage at the first input of the error amplifier.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to a voltage regulation control circuit and a voltage regulator circuit for a regulated power supply circuit. Background Technology

[0002] Regulated power supply circuits (e.g., DC-DC converters, low-dropout linear regulators (LDOs)) are commonly used in various electronic devices to provide DC power. Traditional DC-DC converters and LDOs require a voltage divider resistor between the output voltage terminal and the feedback voltage terminal to achieve different output voltages. The feedback voltage terminal is connected to the input of the error amplifier in the loop to achieve different output voltages. In low-power applications, the quiescent current across this voltage divider resistor will prevent the quiescent current of the DC-DC converter and LDO from being further reduced, affecting efficiency. Summary of the Invention

[0003] The embodiments described herein provide a voltage regulation control circuit for a regulated power supply circuit, and a regulated power supply circuit.

[0004] According to a first aspect of this disclosure, a voltage regulation control circuit for a regulated power supply circuit is provided. The voltage regulation control circuit includes: a voltage conversion circuit, a switching circuit, a voltage holding circuit, and an error amplifier. The voltage conversion circuit is configured to: convert a first reference voltage from a first reference voltage terminal into a second reference voltage when the regulated power supply circuit is in a non-sleep mode; and to stop operating when the regulated power supply circuit is in a sleep mode. The switching circuit is configured to: connect the output terminal of the voltage conversion circuit to a first input terminal of the error amplifier via a first node when the regulated power supply circuit is in a non-sleep mode, thereby providing the second reference voltage to the first input terminal of the error amplifier; and disconnect the connection between the voltage conversion circuit and the first input terminal of the error amplifier when the regulated power supply circuit is in a sleep mode. The voltage holding circuit is configured to: hold the voltage at the first input terminal of the error amplifier. The second input terminal of the error amplifier is coupled to the output terminal of the regulated power supply circuit. An error signal output from the output terminal of the error amplifier is used to control the output voltage output from the output terminal of the regulated power supply circuit such that the output voltage is held at the voltage at the first input terminal of the error amplifier.

[0005] In some embodiments of this disclosure, the voltage conversion circuit includes an operational amplifier, a first transistor, a first feedback resistor, and a second feedback resistor. The first input terminal of the operational amplifier is coupled to a first reference voltage terminal. The second input terminal of the operational amplifier is coupled to a first terminal of the first feedback resistor and a first terminal of the second feedback resistor. The output terminal of the operational amplifier is coupled to the control electrode of the first transistor. The operational amplifier ceases operation when the regulated power supply circuit is in sleep mode. The first electrode of the first transistor is coupled to a second terminal and a first node of the first feedback resistor. The second electrode of the first transistor is coupled to a first voltage terminal. The second terminal of the second feedback resistor is coupled to a second voltage terminal.

[0006] In some embodiments of this disclosure, the voltage regulation control circuit further includes a resistor adjustment circuit. The resistor adjustment circuit is configured to generate an adjustment signal. The adjustment signal is used to adjust the resistance value of one of the first feedback resistor and the second feedback resistor, thereby adjusting the ratio of the first reference voltage to the second reference voltage.

[0007] In some embodiments of this disclosure, the resistor regulation circuit includes: a multiplexed reference voltage selection circuit, a voltage comparator, a counter, a register circuit, a reference resistor, an external voltage regulating resistor, an inverter, and a second transistor. The multiplexed reference voltage selection circuit is configured to: in voltage regulation mode, select a reference voltage from a plurality of reference voltages based on a counting signal output by the counter, and provide the selected reference voltage to the first input terminal of the voltage comparator; and cease operation in non-voltage regulation mode. The second input terminal of the voltage comparator is coupled to the first terminal of the reference resistor and the first terminal of the external voltage regulating resistor. The output terminal of the voltage comparator is coupled to the reset terminal of the counter. The second terminal of the external voltage regulating resistor is coupled to a second voltage terminal. The external voltage regulating resistor is disposed outside the package of the regulated power supply circuit. The second terminal of the reference resistor is coupled to the second terminal of the second transistor. The control terminal of the second transistor is coupled to the output terminal of the inverter. The first terminal of the second transistor is coupled to the first voltage terminal. A voltage regulation enable signal is provided to the input terminal of the inverter. The voltage regulation enable signal is at an active level in voltage regulation mode. The counter is configured to: count according to a first clock signal from a first clock signal terminal to generate a counting signal and provide the counting signal to a register circuit; and stop counting and clear the counting signal when a reset signal is provided at the reset terminal of the counter. The register circuit is configured to: store the counting signal when the counting signal is not equal to zero, and generate an adjustment signal based on the stored counting signal when the counting signal is equal to zero.

[0008] In some embodiments of this disclosure, the multi-reference voltage selection circuit includes: a third transistor, a first resistor to an nth resistor, and a first voltage-controlled switch to an nth voltage-controlled switch. The control electrode of the third transistor is provided with a voltage regulation enable signal. The first electrode of the third transistor is coupled to a second voltage terminal. The second electrode of the third transistor is coupled to a first terminal of the first resistor. The first resistor to the nth resistor are connected in series. The second terminal of the nth resistor is coupled to the first voltage terminal. The first terminals of the first voltage-controlled switches to the nth voltage-controlled switches are respectively coupled to the second terminals of the first resistor to the nth resistor. The second terminals of the first voltage-controlled switches to the nth voltage-controlled switches are commonly coupled to a first input terminal of a voltage comparator. The controlled terminals of the first voltage-controlled switches to the nth voltage-controlled switches are controlled by the first to the nth bits of a counting signal.

[0009] In some embodiments of this disclosure, the resistance values ​​of the first resistor to the nth resistor are equal.

[0010] In some embodiments of this disclosure, the switching circuit includes a sleep control switch. A first terminal of the sleep control switch is coupled to a first node. A second terminal of the sleep control switch is coupled to a first input terminal of an error amplifier. The sleep control switch is configured to close when the regulated power supply circuit is in non-sleep mode and to open when the regulated power supply circuit is in sleep mode.

[0011] In some embodiments of this disclosure, the voltage holding circuit includes a first capacitor. A first terminal of the first capacitor is coupled to a first input terminal of an error amplifier. A second terminal of the first capacitor is coupled to a second voltage terminal.

[0012] In some embodiments of this disclosure, the voltage regulation control circuit further includes a second capacitor. A first terminal of the second capacitor is coupled to a first reference voltage terminal. A second terminal of the second capacitor is coupled to a second voltage terminal.

[0013] According to a second aspect of this disclosure, a voltage regulation control circuit for a regulated power supply circuit is provided. The voltage regulation control circuit includes: an operational amplifier, a first transistor, a first feedback resistor, a second feedback resistor, a sleep control switch, an error amplifier, and a first capacitor. The first input terminal of the operational amplifier is coupled to a first reference voltage terminal. The second input terminal of the operational amplifier is coupled to a first terminal of the first feedback resistor and a first terminal of the second feedback resistor. The output terminal of the operational amplifier is coupled to the control electrode of the first transistor. The operational amplifier stops operating when the regulated power supply circuit is in sleep mode. The first electrode of the first transistor is coupled to a second terminal of the first feedback resistor and a first terminal of the sleep control switch. The second electrode of the first transistor is coupled to a first voltage terminal. The second terminal of the second feedback resistor is coupled to a second voltage terminal. The second terminal of the sleep control switch is coupled to a first input terminal of the error amplifier. The sleep control switch is configured to close when the regulated power supply circuit is in non-sleep mode and open when the regulated power supply circuit is in sleep mode. The first terminal of the first capacitor is coupled to the first input terminal of the error amplifier. The second terminal of the first capacitor is coupled to a second voltage terminal. The second input terminal of the error amplifier is coupled to the output terminal of the regulated power supply circuit. The error signal output from the error amplifier is used to control the output voltage from the output of the regulated power supply circuit so that the output voltage is maintained at the voltage at the first input of the error amplifier.

[0014] According to a third aspect of this disclosure, a regulated power supply circuit is provided. The regulated power supply circuit includes a voltage regulation control circuit as described in the first or second aspect of this disclosure.

[0015] In some embodiments of this disclosure, the regulated power supply circuit is one of the following: a DC-DC converter; or a low-dropout linear regulator.

[0016] According to a fourth aspect of this disclosure, a chip is provided. The chip includes a regulated power supply circuit as described in a third aspect of this disclosure.

[0017] According to a fifth aspect of this disclosure, an electronic device is provided. The electronic device includes the chip described in a fourth aspect of this disclosure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0019] Figure 1 An exemplary topology diagram of a DC-DC converter;

[0020] Figure 2A schematic block diagram of a voltage regulation control circuit for a regulated power supply circuit according to an embodiment of the present disclosure is shown.

[0021] Figure 3 An exemplary circuit diagram of a voltage regulation control circuit for a regulated power supply circuit according to an embodiment of the present disclosure is shown.

[0022] Figure 4 Further exemplary circuit diagrams of voltage regulation control circuits for regulated power supply circuits according to embodiments of the present disclosure are shown; and

[0023] Figure 5 Show Figure 4 An exemplary circuit diagram of a resistor adjustment circuit.

[0024] In the accompanying diagram, markers with the same last two digits correspond to the same elements. It should be noted that the elements in the diagram are schematic and not drawn to scale. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0026] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0027] In all embodiments of this disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. The transistors used in the embodiments of this disclosure are primarily switching transistors. Furthermore, for the sake of consistency, in this context, the base of a bipolar junction transistor (BJT) is referred to as the control terminal, the emitter of the BJT as the first terminal, and the collector of the BJT as the second terminal. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0028] Figure 1 An exemplary topology diagram of a DC-DC converter is shown. The DC-DC converter converts the input voltage VIN into the output voltage VOUT. Figure 1 The DC-DC converter shown includes the upper transistor Q1, the lower transistor Q2, the current sampling circuit sense, the inductor L, the output capacitor Cout, the first feedback resistor Rf1, the second feedback resistor Rf2, the reference voltage circuit BG, the error amplifier EA, the compensation capacitor C, the PWM voltage comparator COMP, the logic and drive circuits, and the inductor current zero-crossing detection circuit.

[0029] The non-inverting input of error amplifier EA is coupled to the reference voltage circuit BG, thus providing a reference voltage Vref. The inverting input of error amplifier EA is coupled to the feedback voltage terminal FB between the first feedback resistor Rf1 and the second feedback resistor Rf2. The first feedback resistor Rf1 and the second feedback resistor Rf2 divide the output voltage VOUT of the DC-DC converter. The error signal Vea output from the output of error amplifier EA is provided to the non-inverting input of PWM voltage comparator COMP. The current sampling circuit sense acquires the current signal flowing through the upper transistor Q1. This current signal is superimposed with the ramp signal Slop and then provided to the inverting input of PWM voltage comparator COMP. PWM voltage comparator COMP outputs a pulse width modulation signal PWM to the logic and drive circuit. The logic and drive circuit generates the upper transistor drive signal DR_Q1 and the lower transistor drive signal DR_Q2 based on the pulse width modulation signal PWM, the clock signal CLK, and the zero-crossing detection signal output by the inductor current zero-crossing detection circuit. The upper transistor drive signal DR_Q1 is used to control the conduction and cutoff of the upper transistor Q1. The lower transistor drive signal DR_Q2 is used to control the conduction and cutoff of the lower transistor Q2.

[0030] exist Figure 1In the example, different output voltages VOUT can be achieved by controlling the ratio of the resistance values ​​of the first feedback resistor Rf1 and the second feedback resistor Rf2. The first feedback resistor Rf1 and the second feedback resistor Rf2 are essential for voltage regulation. However, they generate additional quiescent current, reducing light-load efficiency.

[0031] Embodiments of this disclosure provide a voltage regulation control circuit for a regulated power supply circuit, which can eliminate the quiescent current on the first feedback resistor Rf1 and the second feedback resistor Rf2.

[0032] Figure 2 A schematic block diagram of a voltage regulation control circuit 200 for a regulated power supply circuit according to an embodiment of the present disclosure is shown. The voltage regulation control circuit 200 includes: a voltage conversion circuit 210, a switching circuit 220, a voltage holding circuit 230, and an error amplifier EA.

[0033] The input terminal of voltage conversion circuit 210 is coupled to a first reference voltage terminal Vref1. The output terminal of voltage conversion circuit 210 is coupled to switching circuit 220 via a first node N1. Voltage conversion circuit 210 is configured to: convert the first reference voltage Vref1 from the first reference voltage terminal Vref1 into a second reference voltage Vref2 when the regulated power supply circuit is in non-sleep mode; and to stop operating when the regulated power supply circuit is in sleep mode. In some embodiments of this disclosure, when voltage conversion circuit 210 stops operating, the second reference voltage Vref2 is equal to zero volts. When voltage conversion circuit 210 is operating normally, the second reference voltage Vref2 is greater than the first reference voltage Vref1.

[0034] Switching circuit 220 is coupled to a first enable terminal EN1. The first enable signal EN1 from the first enable terminal EN1 is active when the regulated power supply circuit is in non-sleep mode and inactive when the regulated power supply circuit is in sleep mode. Switching circuit 220 is coupled to the output of voltage conversion circuit 210 via a first node N1. Switching circuit 220 is also coupled to the first input of error amplifier EA and voltage holding circuit 230. Switching circuit 220 is configured to: when the regulated power supply circuit is in non-sleep mode, connect the output of voltage conversion circuit 210 to the first input of error amplifier EA via the first node N1, thereby providing the second reference voltage Vref2 to the first input of error amplifier EA; and disconnect the connection between voltage conversion circuit 210 and the first input of error amplifier EA when the regulated power supply circuit is in sleep mode.

[0035] Voltage holding circuit 230 is coupled to the first input terminal of error amplifier EA. Voltage holding circuit 230 is configured to hold the voltage V+ at the first input terminal of error amplifier EA.

[0036] The second input terminal of the error amplifier EA is coupled to the output terminal of the regulated power supply circuit. The error signal Vea output from the output terminal of the error amplifier EA is used to control the output voltage VOUT output from the output terminal of the regulated power supply circuit so that the output voltage VOUT is maintained at the voltage V+ at the first input terminal of the error amplifier EA.

[0037] exist Figure 2 In the example, the first input of the error amplifier EA is the non-inverting input. The second input of the error amplifier EA is the inverting input.

[0038] When the regulated power supply circuit is in non-sleep mode (normal operation), the second reference voltage Vref2 is provided to the first input terminal of the error amplifier EA. The voltage V+ at the first input terminal of the error amplifier EA is equal to the second reference voltage Vref2, and the output voltage VOUT is equal to the voltage V+ at the first input terminal of the error amplifier EA. Thus, through loop regulation, the output voltage VOUT of the regulated power supply circuit is set to the second reference voltage Vref2. Therefore, the voltage conversion circuit 210 can adjust the output voltage VOUT according to the first reference voltage Vref1.

[0039] When the regulated power supply circuit is in sleep mode, the switching circuit 220 disconnects the voltage conversion circuit 210 from the first input terminal of the error amplifier EA. The voltage conversion circuit 210 stops operating, thereby reducing the quiescent current in sleep mode. The voltage holding circuit 230 maintains the voltage V+ at the first input terminal of the error amplifier EA at the second reference voltage Vref2. This allows the loop to be quickly established when the regulated power supply circuit returns to non-sleep mode.

[0040] Figure 3 An exemplary circuit diagram of a voltage regulation control circuit 300 for a regulated power supply circuit according to an embodiment of the present disclosure is shown.

[0041] The voltage conversion circuit 310 includes an operational amplifier AMP, a first transistor M1, a first feedback resistor Rf1, and a second feedback resistor Rf2. The first input terminal of the operational amplifier AMP is coupled to a first reference voltage terminal Vref1. The second input terminal of the operational amplifier AMP is coupled to the first terminal of the first feedback resistor Rf1 and the first terminal of the second feedback resistor Rf2. The output terminal of the operational amplifier AMP is coupled to the control terminal of the first transistor M1. The operational amplifier AMP stops operating when the regulated power supply circuit is in sleep mode. The first terminal of the first transistor M1 is coupled to the second terminal of the first feedback resistor Rf1 and the first node N1. The second terminal of the first transistor M1 is coupled to a first voltage terminal V1. The second terminal of the second feedback resistor Rf2 is coupled to a second voltage terminal V2. In some embodiments of this disclosure, the operational amplifier AMP can be stopped by setting its supply voltage Vsource to zero volts. In other embodiments of this disclosure, the operational amplifier AMP can be stopped by setting its bias current to zero amperes.

[0042] The switching circuit 320 includes a sleep control switch S1. The sleep control switch S1 can be a voltage-controlled switch or a switching transistor. A first terminal of the sleep control switch S1 is coupled to a first node N1. A second terminal of the sleep control switch S1 is coupled to a first input terminal of an error amplifier EA. The controlled terminal of the sleep control switch S1 is coupled to a first enable terminal EN1. The sleep control switch S1 is configured to close when the regulated power supply circuit is in non-sleep mode and to open when the regulated power supply circuit is in sleep mode.

[0043] The voltage holding circuit 330 includes a first capacitor C1. The first terminal of the first capacitor C1 is coupled to the first input terminal of the error amplifier EA. The second terminal of the first capacitor C1 is coupled to the second voltage terminal V2.

[0044] exist Figure 3 In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1 is an NMOS transistor. The first input terminal of the operational amplifier AMP is the non-inverting input terminal. The second input terminal of the operational amplifier AMP is the inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 3 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 3 The examples shown have different settings.

[0045] like Figure 3As shown, the first reference voltage Vref1 can be provided by the reference voltage circuit BG. In some embodiments of this disclosure, the voltage regulation control circuit 300 may further include a second capacitor C2. The first terminal of the second capacitor C2 is coupled to the first reference voltage terminal Vref1. The second terminal of the second capacitor C2 is coupled to the second voltage terminal V2.

[0046] When the regulated power supply circuit is in non-sleep mode (normal operation), according to the virtual short and virtual open characteristics of the operational amplifier AMP, the voltage at the first terminal of the first feedback resistor Rf1 is equal to the first reference voltage Vref1.

[0047] Vref2=Vref1×(Rf1+Rf2) / Rf2 (1)

[0048] Where Vref2 represents the voltage value of the second reference voltage Vref2, Vref1 represents the voltage value of the first reference voltage Vref1, Rf1 represents the resistance value of the first feedback resistor Rf1, and Rf2 represents the resistance value of the second feedback resistor Rf2. When the sleep control switch S1 is closed, the second reference voltage Vref2 is provided to the first input terminal of the error amplifier EA. Thus, through loop adjustment, the output voltage VOUT of the regulated power supply circuit is set to the second reference voltage Vref2. According to equation (1), the voltage conversion circuit 310 can adjust the output voltage VOUT by adjusting the resistance value of the first feedback resistor Rf1 or the resistance value of the second feedback resistor Rf2.

[0049] When the regulated power supply circuit is in sleep mode, the sleep control switch S1 is open, and the second reference voltage Vref2 is no longer supplied to the first input terminal of the error amplifier EA. The first capacitor C1 ensures that the voltage V+ at the first input terminal of the error amplifier EA is maintained at the second reference voltage Vref2. This allows the loop to be quickly established when the regulated power supply circuit returns to non-sleep mode. The supply voltage Vsource of the operational amplifier AMP is now zero volts, or the bias current of the operational amplifier AMP is now zero amperes, and the operational amplifier AMP stops operating. Therefore, the current flowing through the first feedback resistor Rf1 and the second feedback resistor Rf2 is zero, thereby reducing the quiescent current of the regulated power supply circuit in sleep mode.

[0050] Furthermore, in Figure 1In the example, the first feedback resistor Rf1 and the second feedback resistor Rf2 are typically placed inside the chip package of the regulated power supply circuit. To achieve voltage regulation, the conventional method is to use the I2C bus to adjust the value of either the first feedback resistor Rf1 or the second feedback resistor Rf2, thereby achieving different output voltages VOUT. However, since the first feedback resistor Rf1 and the second feedback resistor Rf2 are built-in, the user needs an external device to control the I2C bus, which undoubtedly increases the user's cost.

[0051] Therefore, embodiments of this disclosure further propose a voltage regulation control circuit 400 for implementing low-cost voltage regulation functionality. For example... Figure 4 As shown, in Figure 3 Based on the example, the voltage regulation control circuit 400 further includes a resistor adjustment circuit 440. The resistor adjustment circuit 440 is coupled to a first feedback resistor Rf1 or a second feedback resistor Rf2. In this embodiment, the resistance value of the first feedback resistor Rf1 or the second feedback resistor Rf2 can be varied according to a digital signal. The resistor adjustment circuit 440 is configured to generate an adjustment signal Adjust. The adjustment signal Adjust is a digital signal. The adjustment signal Adjust is used to adjust the resistance value of one of the first feedback resistor Rf1 and the second feedback resistor Rf2, thereby adjusting the ratio of the first reference voltage Vref1 to the second reference voltage Vref2. In some embodiments of this disclosure, the resistor adjustment circuit 440 includes an external voltage regulating resistor, which generates the adjustment signal Adjust based on the external voltage regulating resistor. The external voltage regulating resistor can be arranged outside the package of the regulated power supply circuit, thereby facilitating the adjustment of the resistance value of the first feedback resistor Rf1 or the second feedback resistor Rf2.

[0052] Figure 5 Show Figure 4 An exemplary circuit diagram of the resistor adjustment circuit 440 is shown below. The resistor adjustment circuit 540 includes: a multiplexed reference voltage selection circuit 543, a voltage comparator CMP, a counter 541, a register circuit 542, a reference resistor Rref, an external voltage regulating resistor Rx, an inverter NG, and a second transistor M2.

[0053] The multi-reference voltage selection circuit 543 is configured to: in voltage regulation mode, select a reference voltage Vref3 from multiple reference voltages according to the counting signal Cnt output by the counter 541, and provide the selected reference voltage Vref3 to the first input of the voltage comparator CMP; and stop operating in non-voltage regulation mode.

[0054] The second input terminal of the voltage comparator CMP is coupled to the first terminal of the reference resistor Rref and the first terminal of the external voltage regulating resistor Rx. The output terminal of the voltage comparator CMP is coupled to the reset terminal of the counter 541. The operating state of the voltage comparator CMP is controlled by the voltage regulation enable signal EN2. When the voltage regulation enable signal EN2 is at an active level, the voltage comparator CMP operates normally. When the voltage regulation enable signal EN2 is at an inactive level, the voltage comparator CMP stops operating.

[0055] The second terminal of the external voltage regulating resistor Rx is coupled to the second voltage terminal V2. The external voltage regulating resistor Rx is located outside the package of the regulated power supply circuit. The second terminal of the reference resistor Rref is coupled to the second terminal of the second transistor M2. The control terminal of the second transistor M2 is coupled to the output terminal of the inverter NG. The first terminal of the second transistor M2 is coupled to the first voltage terminal V1. The input terminal of the inverter NG is provided with a voltage regulation enable signal EN2. The voltage regulation enable signal EN2 is active in voltage regulation mode.

[0056] The counter 541 is configured to: count according to the first clock signal CLK1 from the first clock signal terminal CLK1 to generate a counting signal Cnt and provide the counting signal Cnt to the register circuit 542, and stop counting and clear the counting signal Cnt to zero when a reset signal Rset is provided at the reset terminal of the counter 541.

[0057] The register circuit 542 is configured to store the count signal Cnt when the count signal Cnt is not equal to zero, and to generate an adjustment signal Adjust based on the stored count signal Cnt when the count signal Cnt is equal to zero.

[0058] In some embodiments of this disclosure, the multiplexed reference voltage selection circuit 543 includes: a third transistor M3, first resistors R1 to nth resistors Rn, and first voltage-controlled switches K1 to nth voltage-controlled switches Kn. The control electrode of the third transistor M3 is provided with a voltage regulation enable signal EN2. The first electrode of the third transistor M3 is coupled to a second voltage terminal V2. The second electrode of the third transistor M3 is coupled to the first terminal of the first resistor R1.

[0059] The first resistor R1 to the nth resistor Rn are connected in series. For consistency in the context, the first terminal of each resistor is located below its second terminal. The second terminal of the first resistor R1 is coupled to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is coupled to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is coupled to the first terminal of the fourth resistor R4, and so on. The second terminal of the nth resistor Rn is coupled to the first voltage terminal V1.

[0060] The first terminals of the first voltage-controlled switches K1 to the nth voltage-controlled switches Kn are respectively coupled to the second terminals of the first resistors R1 to the nth resistors Rn. For example, the first terminal of the first voltage-controlled switch K1 is coupled to the second terminal of the first resistor R1. The first terminal of the second voltage-controlled switch K2 is coupled to the second terminal of the second resistor R2. The first terminal of the third voltage-controlled switch K3 is coupled to the second terminal of the third resistor R3. The first terminal of the fourth voltage-controlled switch K4 is coupled to the second terminal of the fourth resistor R4. And so on. The first terminal of the (n-1)th voltage-controlled switch Kn-1 is coupled to the first terminal of the nth resistor Rn. The first terminal of the nth voltage-controlled switch Kn is coupled to the second terminal of the nth resistor Rn. The second terminals of the first voltage-controlled switches K1 to the nth voltage-controlled switches Kn are all coupled to the first input terminal of the voltage comparator CMP. The controlled terminals of the first voltage-controlled switches K1 to the nth voltage-controlled switches Kn are controlled by the first to the nth bits of the counting signal Cnt.

[0061] In some embodiments of this disclosure, the resistance values ​​of the first resistor R1 to the nth resistor Rn are equal.

[0062] In voltage regulation mode, when the external voltage regulating resistor Rx is coupled between the first terminal of the reference resistor Rref and the second voltage terminal V2, the voltage Vx at the first terminal of the reference resistor Rref is Vx = V1 × Rx / (Rx + Rref). Under the control of the counting signal Cnt, only one of the voltage-controlled switches K1 to Kn is closed, while the others are open.

[0063] When the counting signal Cnt equals 1, the first voltage-controlled switch K1 closes first. At this time, the voltage at the first input terminal of the voltage comparator CMP is Vref3 = V1 × R1 / (R1 + R2 + ... + Rn) = V1 / n. If Vx > Vref3, the reset signal Rset output by the voltage comparator CMP is at an invalid level (low level). The counter 541 continues counting, and the counting signal Cnt increases to 2. At this time, the first voltage-controlled switch K1 opens, and the second voltage-controlled switch K2 closes. Therefore, Vref3 = V1 × (R1 + R2) / (R1 + R2 + ... + Rn) = 2 × V1 / n. If Vx > Vref3, the reset signal Rset output by the voltage comparator CMP is at an invalid level. The counter 541 continues counting, and the counting signal Cnt increases to 3. At this time, the second voltage-controlled switch K2 opens, and the third voltage-controlled switch K3 closes. At this point, Vref3 = V1 × (R1 + R2 + R3) / (R1 + R2 + ... + Rn) = 3 × V1 / n. This continues until Vx < Vref3, at which point the reset signal Rset output by the voltage comparator CMP flips to a valid level (high level), and counter 541 stops counting and is reset to zero. The result of each count by counter 541 (counting signal Cnt) is stored in register circuit 542. The value of the counting signal Cnt stored in register circuit 542 is updated after each count. When the counting signal Cnt is equal to zero, register circuit 542 generates an adjustment signal Adjust based on the stored counting signal Cnt. The value of the adjustment signal Adjust is equal to the value of the counting signal Cnt stored in register circuit 542.

[0064] The voltage regulation process is complete after the reset signal Rset output by the voltage comparator CMP flips to an active level. The voltage comparator CMP, the second transistor M2, and the third transistor M3 can be turned off by setting the voltage regulation enable signal EN2 to an inactive level (low level). This allows the resistor regulation circuit 540 to achieve zero quiescent current.

[0065] Assume that counter 541 stops counting when the i-th voltage-controlled switch is closed, and the count value at this time is i, i = Rx × n / (Rx + Rref) (2). The value of Rx can be determined according to equation (2). Rx = i × Rref / (ni) (3). Thus, the required external voltage regulating resistor Rx can be selected according to equation (3) and the desired i.

[0066] exist Figure 5In the example, a high-voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The second transistor M2 is a PMOS transistor. The third transistor M3 is an NMOS transistor. The effective level of the voltage regulation enable signal EN2 is high. The first input terminal of the voltage comparator CMP is the non-inverting input terminal. The second input terminal of the voltage comparator CMP is the inverting input terminal. Those skilled in the art will understand that, based on the above inventive concept... Figure 5 Any modifications to the circuit shown should also fall within the scope of this disclosure. In such modifications, the transistor and voltage terminals may also have the same characteristics as described above. Figure 5 The examples shown have different settings.

[0067] The voltage regulation control circuit according to the embodiments of this disclosure does not require external devices from the user to adjust the output voltage of the regulated power supply circuit. The user only needs to replace the external voltage regulating resistor Rx to achieve the voltage regulation function, which is simple, easy to operate and low in cost.

[0068] Embodiments of this disclosure also provide a regulated power supply circuit. This regulated power supply circuit includes a voltage regulation control circuit according to embodiments of this disclosure. Figure 2 In the example, the regulated power supply circuit is a DC-DC converter. In other embodiments of this disclosure, the regulated power supply circuit may also be a low-dropout linear regulator.

[0069] Embodiments of this disclosure also provide a chip. This chip includes a regulated power supply circuit according to embodiments of this disclosure. This chip is, for example, a power management chip.

[0070] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer or smartphone.

[0071] In summary, the voltage regulation control circuit for a regulated power supply circuit according to embodiments of the present disclosure can reduce the quiescent current of the regulated power supply circuit. Furthermore, the voltage regulation control circuit for a regulated power supply circuit according to embodiments of the present disclosure can also regulate the voltage of the regulated power supply circuit in a simple manner, thereby reducing voltage regulation costs.

[0072] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0073] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0074] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A voltage regulation control circuit for a regulated power supply circuit, comprising: The voltage conversion circuit, the switching circuit, the voltage holding circuit, and the error amplifier, The voltage conversion circuit is configured to convert a first reference voltage from the first reference voltage terminal into a second reference voltage when the voltage regulator circuit is in a non-sleep mode, and stop working when the voltage regulator circuit is in a sleep mode. The switching circuit is configured to connect the output terminal of the voltage conversion circuit to the first input terminal of the error amplifier via the first node to provide the second reference voltage to the first input terminal of the error amplifier when the voltage regulator circuit is in the non-sleep mode, and disconnect the connection between the voltage conversion circuit and the first input terminal of the error amplifier when the voltage regulator circuit is in the sleep mode. The voltage holding circuit is configured to hold the voltage at the first input terminal of the error amplifier. The second input terminal of the error amplifier is coupled to the output terminal of the voltage regulator circuit, and an error signal output from the output terminal of the error amplifier is used to control an output voltage output from the output terminal of the voltage regulator circuit so that the output voltage is held as the voltage at the first input terminal of the error amplifier. The voltage conversion circuit includes an operational amplifier, a first transistor, a first feedback resistor, and a second feedback resistor. The first input terminal of the operational amplifier is coupled to the first reference voltage terminal, the second input terminal of the operational amplifier is coupled to the first terminal of the first feedback resistor and the first terminal of the second feedback resistor, and the output terminal of the operational amplifier is coupled to the control electrode of the first transistor. The operational amplifier stops working when the voltage regulator circuit is in the sleep mode. The first electrode of the first transistor is coupled to the second terminal of the first feedback resistor and the first node, and the second electrode of the first transistor is coupled to a first voltage terminal. The second terminal of the second feedback resistor is coupled to a second voltage terminal. The voltage holding circuit further includes a resistance adjustment circuit. The resistance adjustment circuit is configured to generate an adjustment signal for adjusting the resistance value of one of the first feedback resistor and the second feedback resistor, so as to adjust the ratio of the first reference voltage to the second reference voltage. The resistance adjustment circuit includes a multipath reference voltage selection circuit, a voltage comparator, a counter, a register circuit, a reference resistor, an external voltage adjustment resistor, an inverter, and a second transistor. The multipath reference voltage selection circuit is configured to select one reference voltage from a plurality of reference voltages according to a count signal output by the counter and provide the selected reference voltage to the first input terminal of the voltage comparator in a voltage adjustment mode, and stop working in a non-voltage adjustment mode. The second input terminal of the voltage comparator is coupled to the first terminal of the reference resistor and the first terminal of the external voltage adjustment resistor, and the output terminal of the voltage comparator is coupled to the reset terminal of the counter. A second end of the external voltage regulating resistor is coupled to a second voltage terminal, and the external voltage regulating resistor is arranged outside a package of the voltage regulator circuit; A second end of the reference resistor is coupled to a second electrode of the second transistor; A control electrode of the second transistor is coupled to an output terminal of the inverter, and a first electrode of the second transistor is coupled to a first voltage terminal; An input terminal of the inverter is provided with a voltage regulating enable signal, wherein the voltage regulating enable signal is at an active level in the voltage regulating mode; The counter is configured to count according to a first clock signal from a first clock signal terminal to generate the count signal and provide the count signal to the register circuit, and stop counting and clear the count signal when a reset signal is provided at a reset terminal of the counter; The register circuit is configured to store the count signal when the count signal is not equal to zero, and generate the adjustment signal according to the stored count signal when the count signal is equal to zero.

2. The voltage regulation control circuit of claim 1, wherein, The multi-path reference voltage selection circuit comprises a third transistor, first to nth resistors, and first to nth voltage-controlled switches, wherein a control electrode of the third transistor is provided with the voltage regulating enable signal, a first electrode of the third transistor is coupled to the second voltage terminal, and a second electrode of the third transistor is coupled to a first end of the first resistor; The first to nth resistors are connected in series, and a second end of the nth resistor is coupled to the first voltage terminal; First ends of the first to nth voltage-controlled switches are respectively coupled to second ends of the first to nth resistors, second ends of the first to nth voltage-controlled switches are commonly coupled to the first input terminal of the voltage comparator, and controlled ends of the first to nth voltage-controlled switches are respectively controlled by first to nth bits of the count signal.

3. The pressure regulation control circuit of any one of claims 1-2, wherein, The switch circuit comprises a sleep control switch, wherein a first end of the sleep control switch is coupled to the first node, a second end of the sleep control switch is coupled to the first input terminal of the error amplifier, and the sleep control switch is configured to be closed when the voltage regulator circuit is in the non-sleep mode, and to be opened when the voltage regulator circuit is in the sleep mode.

4. The pressure regulation control circuit of any one of claims 1-2, wherein, The voltage holding circuit comprises a first capacitor, wherein a first end of the first capacitor is coupled to the first input terminal of the error amplifier, and a second end of the first capacitor is coupled to a second voltage terminal.

5. A voltage regulation control circuit for a regulated power supply circuit, comprising: An operational amplifier, a first transistor, a first feedback resistor, a second feedback resistor, a sleep control switch, an error amplifier, and a first capacitor, wherein a first input terminal of the operational amplifier is coupled to a first reference voltage terminal, a second input terminal of the operational amplifier is coupled to a first end of the first feedback resistor and a first end of the second feedback resistor, an output terminal of the operational amplifier is coupled to a control electrode of the first transistor, and the operational amplifier stops working when the voltage regulator circuit is in the sleep mode. a first electrode of the first transistor is coupled to a second end of the first feedback resistor and a first end of the sleep control switch, and a second electrode of the first transistor is coupled to a first voltage terminal; a second end of the second feedback resistor is coupled to a second voltage terminal; a second end of the sleep control switch is coupled to a first input terminal of the error amplifier, and the sleep control switch is configured to be closed when the voltage regulator circuit is in a non-sleep mode and to be opened when the voltage regulator circuit is in the sleep mode; a first end of the first capacitor is coupled to the first input terminal of the error amplifier, and a second end of the first capacitor is coupled to the second voltage terminal; a second input terminal of the error amplifier is coupled to an output terminal of the voltage regulator circuit, and an error signal output from an output terminal of the error amplifier is used to control an output voltage output from the output terminal of the voltage regulator circuit such that the output voltage is maintained as a voltage at the first input terminal of the error amplifier; wherein the voltage regulation control circuit further comprises a resistance adjustment circuit, wherein the resistance adjustment circuit is configured to generate an adjustment signal used to adjust a resistance value of one of the first feedback resistor and the second feedback resistor; wherein the resistance adjustment circuit comprises a multipath reference voltage selection circuit, a voltage comparator, a counter, a register circuit, a reference resistor, an external voltage regulation resistor, an inverter, and a second transistor, wherein the multipath reference voltage selection circuit is configured to select one reference voltage from a plurality of reference voltages according to a count signal output from the counter and provide the selected reference voltage to a first input terminal of the voltage comparator in a voltage regulation mode, and to stop working in a non-voltage regulation mode; a second input terminal of the voltage comparator is coupled to a first end of the reference resistor and a first end of the external voltage regulation resistor, and an output terminal of the voltage comparator is coupled to a reset terminal of the counter; a second end of the external voltage regulation resistor is coupled to a second voltage terminal, and the external voltage regulation resistor is arranged outside a package of the voltage regulator circuit; a second end of the reference resistor is coupled to a second electrode of the second transistor; a control electrode of the second transistor is coupled to an output terminal of the inverter, and a first electrode of the second transistor is coupled to a first voltage terminal; an input terminal of the inverter is provided with a voltage regulation enable signal, wherein the voltage regulation enable signal is at an active level in the voltage regulation mode; the counter is configured to count according to a first clock signal from a first clock signal terminal to generate the count signal and provide the count signal to the register circuit, and to stop counting and clear the count signal when a reset signal is provided to the reset terminal of the counter; the register circuit is configured to store the count signal when the count signal is not equal to zero, and to generate the adjustment signal according to the stored count signal when the count signal is equal to zero.

6. A regulated power supply circuit comprising: The voltage regulation control circuit according to any one of claims 1 to 5.

7. The regulated power supply circuit of claim 6, wherein, The voltage regulator circuit is one of: DC-DC converter; or Low-dropout linear regulator.

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