A security method, system and device based on a storage-computing integrated architecture

Abstract

The application discloses a security method, system and device based on a memory-computing integrated architecture, and relates to the security field.The method comprises the following steps: selecting a plurality of basic models from a model library; individually quantizing each basic model; constructing a memory-computing integrated architecture based on the quantized basic models; performing a security task based on the memory-computing integrated architecture and optimizing and accelerating; the input of the memory-computing integrated architecture comprises monitoring video, and the output of the memory-computing integrated architecture comprises the recognition result of the monitoring video; the optimization and acceleration comprises spatial mapping, time scheduling and time pipelining.The optimization and acceleration scheme can accelerate the inference speed of the model and improve the accuracy and efficiency of security.

Description

Technical Field

[0001] This invention relates to the field of security technology, and in particular to a security method, system and device based on an in-memory computing architecture. Background Technology

[0002] With the widespread application of intelligent security systems in urban safety management, such as facial recognition, video surveillance, and voice recognition, the performance requirements for deep neural networks in image and video analysis are becoming increasingly stringent. However, different security tasks require different neural network models, which are suitable for different quantization strategies. The compressed models also differ in their underlying computational execution mechanisms, making the processing of heterogeneous quantization models even more complex. The inflexibility of the data path within the cross-array limits the application scope of existing acceleration technologies in addressing this challenge.

[0003] Designing a dedicated hardware architecture to support various quantization schemes in smart security applications is extremely costly. While general-purpose hardware (such as graphics processors) supports some quantization weight formats, they employ the traditional von Neumann architecture, thus facing performance bottlenecks caused by large-scale data migration and off-chip data access.

[0004] Therefore, given the specific needs of heterogeneous compression in the security field, there is an urgent need for a deep neural network acceleration solution that can effectively support multiple quantization strategies, possesses high scalability, and boasts superior performance. This will help improve the real-time performance and energy efficiency of intelligent security systems and promote the widespread application of deep learning in the security field. Summary of the Invention

[0005] The purpose of this invention is to provide a security method, system, and device based on an in-memory computing architecture. By optimizing and accelerating security tasks through the in-memory computing architecture, the inference speed of the model can be increased, thereby improving the accuracy and efficiency of security.

[0006] To achieve the above objectives, the present invention provides the following solution:

[0007] A security method based on an in-memory computing architecture includes:

[0008] Select multiple basic models from the model library; the model library includes: convolutional neural network models, recurrent neural network models, and attention mechanism network models;

[0009] Each of the aforementioned basic models is quantified individually;

[0010] A storage-computing integrated architecture is built based on the quantized basic model;

[0011] Security tasks are performed based on the in-memory computing architecture and optimized and accelerated; the input of the in-memory computing architecture includes surveillance video, and the output of the in-memory computing architecture includes the recognition results of the surveillance video; the optimization and acceleration include: spatial mapping, time scheduling and time pipeline.

[0012] Optionally, each of the aforementioned basic models can be individually quantized, specifically including:

[0013] The parameters in each of the aforementioned basic models are converted to integers and powers of two.

[0014] Optionally, the in-memory computing architecture includes: an on-chip controller, multiple quantization computing units, and an on-chip buffer; the on-chip controller schedules the quantization computing units, and the on-chip buffer caches the calculation results of the quantization computing units; the quantization computing unit includes: a cross array, a quantization storage indicator, a data flow controller, and a digital unit; the cross array stores the quantized base model and the block-based base model; the data flow controller schedules each cross array according to the indication stored in the quantization storage indicator; and the digital unit processes the calculation results of each cross array.

[0015] Optionally, the in-memory computing architecture further includes special function units; the special function units include: pooling functions and activation functions.

[0016] Optionally, the digital unit includes: an accumulation unit, a shifter, and an adder.

[0017] Optionally, the spatial mapping specifically includes:

[0018] The weight matrix of the quantized base model is sliced ​​bit by bit to obtain multiple logical matrices of equal size; the number of logical matrices is equal to the maximum bit width required for all weights;

[0019] Divide the cross array into multiple groups, and compute a logical matrix for each group of cross arrays;

[0020] The logic matrix is ​​mapped onto a cross array; during mapping, if a column of the cross array is 0, the non-zero column on the right is shifted to the left; if a row of the cross array is 0, the non-zero row below is shifted up; if the block of the quantized base model is 0, the logic matrix is ​​cut into sub-matrices.

[0021] Optionally, the time scheduling specifically includes:

[0022] The data flow controller schedules the cross array and performs unified and cumulative operations on the calculation results of each cross matrix through the digital unit.

[0023] This invention also provides a security system based on an in-memory computing architecture, comprising:

[0024] The selection module is used to select multiple basic models from a model library; the model library includes: convolutional neural network models, recurrent neural network models, and attention mechanism network models.

[0025] The quantization module is used to perform personalized quantization on each of the aforementioned basic models;

[0026] The in-memory computing architecture building module is used to build an in-memory computing architecture based on the quantized base model.

[0027] The task execution and acceleration module is used to execute security tasks based on the in-memory computing architecture and to optimize and accelerate them; the input of the in-memory computing architecture includes surveillance video, and the output of the in-memory computing architecture includes the recognition results of the surveillance video; the optimization and acceleration include: spatial mapping, time scheduling, and time pipeline.

[0028] The present invention also provides an electronic device, including a memory and a processor, wherein the memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to perform the above-described security method based on a memory-computing architecture.

[0029] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described security method based on a storage-computing architecture.

[0030] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0031] The in-memory computing architecture constructed in this invention has high versatility and scalability. Furthermore, this invention optimizes and accelerates the execution of security tasks (such as video surveillance, behavior recognition, and image recognition in the security field) within the in-memory computing architecture. The acceleration scheme adopts a series of innovative optimization designs, including spatial mapping, time scheduling, and time pipeline, thereby accelerating the inference speed of the model and improving the accuracy and efficiency of security. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart of a security method based on an in-memory computing architecture provided in Embodiment 1 of the present invention.

[0034] Figure 2 This is a schematic diagram of the in-memory computing architecture provided in Embodiment 1 of the present invention;

[0035] Figure 3 This is a schematic diagram of spatial mapping provided in Embodiment 1 of the present invention;

[0036] Figure 4 This is a time scheduling diagram provided in Embodiment 1 of the present invention;

[0037] Figure 5 This is a schematic diagram of a spatial pipeline provided in Embodiment 1 of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] The purpose of this invention is to provide a security method, system, and device based on an in-memory computing architecture. By constructing an in-memory computing architecture and designing an optimized acceleration scheme when performing security tasks on the in-memory computing architecture, the inference speed of the model is accelerated, thereby improving the accuracy and efficiency of security.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Example 1

[0042] like Figure 1 As shown, the security method based on in-memory computing architecture provided in this embodiment includes the following steps:

[0043] S1: Select multiple basic models from the model library; the model library includes: convolutional neural network models, recurrent neural network models, and attention mechanism network models.

[0044] In practical applications, multiple representative basic models are selected from the existing model library involved in security tasks as the model pool, including but not limited to convolutional neural networks (CNN), recurrent neural networks (RNN), and attention mechanism networks.

[0045] S2: Perform personalized quantization on each of the aforementioned basic models.

[0046] Converting the parameters in the basic model into integer and idempotent encoding methods reduces the computational complexity and storage space overhead of the model.

[0047] S3: Construct an in-memory computing architecture based on the quantized base model.

[0048] The in-memory computing architecture unifies various quantized base models, enabling it to support diverse quantization methods. Specifically, the parameters of each compressed base model are deployed within the in-memory computing architecture, and the deployment scheme and computation process are adaptively adjusted based on the compression method. The final result is obtained through a coexistence mechanism.

[0049] In-memory computing architecture architecture such as Figure 4 As shown, the in-memory computing architecture includes: an on-chip controller, multiple quantization computation units, an on-chip buffer, and special function units (pooling functions and activation functions). The on-chip controller schedules the quantization computation units, and the on-chip buffer is used to cache the computation results of the quantization computation units. The quantization computation unit includes: eight 128*128 cross arrays, a quantization storage indicator, a data flow controller, and a digital unit. The cross arrays are used to store the quantized base model and the block-based base model. The data flow controller schedules each cross array according to the indication stored in the quantization storage indicator. The digital unit is used to process the computation results of each cross array. The digital unit includes: an accumulation unit, a shifter, and an adder.

[0050] Each cross array has an associated register. All associated registers are combined into a quantization storage indicator, which indicates that a portion of the input should be skipped when the logic matrix in the spatial mapping contains rows of zeros. The dataflow controller first generates continuous input data addresses, then masks a portion of the addresses corresponding to the inputs that undergo multiplication and accumulation operations with rows of zeros in the weight matrix, based on the content of the quantization storage indicator. Next, it fetches the input data into the row buffer based on the sparse input addresses, saving unnecessary computation and communication overhead. Furthermore, an accumulation unit is designed to flexibly accumulate all intermediate results of the cross array. Since different quantization schemes and quantization bit widths result in different meanings for the cross array outputs, the quantization calculation indicator in the accumulation unit indicates whether the shifted partial sums should be accumulated into the registers; if not, they are filled with zeros. The accumulation unit can flexibly accumulate all intermediate values. This invention also adds a shifter to each cross array output to unify the meaning of the outputs; the shifter strategy is controlled by the shift configuration in the dataflow controller.

[0051] S4: Execute security tasks based on the in-memory computing architecture and optimize and accelerate them; the input of the in-memory computing architecture includes surveillance video, and the output of the in-memory computing architecture includes the recognition results of the surveillance video; the optimization and acceleration include: spatial mapping, time scheduling, and time pipeline.

[0052] To meet the deployment requirements of complex application scenarios in security tasks, the acceleration solution of this invention adopts a series of innovative optimization designs, including spatial mapping, time scheduling, and time pipeline.

[0053] () space mapping

[0054] Different quantization schemes, and even different quantization bit widths under the same quantization scheme, will generate weights with different bit widths. To avoid filling all weights with the same bit width for processing, this invention proposes a spatial mapping method for bit-wise weight partitioning.

[0055] like Figure 3 As shown, the weight matrix is ​​first sliced ​​bit-by-bit to obtain multiple logical matrices of equal size. The number of logical matrices is equal to the maximum bit width required to represent all weights. Figure 3 In this algorithm, the maximum bit width of the weights is 4 bits, so the weight matrix is ​​divided into 4 logical matrices. Weights with a bit width less than the maximum bit width are set to 0 in the logical matrix representing the lower bits of the weights. Different quantization schemes based on channels may result in columns of the lower logical matrices being 0; based on convolution kernels, it may result in columns of 0; and based on other fine-grained structures, it may result in blocks of 0.

[0056] To address this situation, the cross array is divided into multiple groups, and a logical matrix is ​​calculated for each group. For example... Figure 3 As shown, they are divided into 4 groups. When mapping the logical matrix to the cross array, for the case where the column is 0 (such as... Figure 3 As shown in (a), shift the non-zero columns on the right to the left; for the case of rows 0 (such as... Figure 3 As shown in (b), shift the non-zero rows at the bottom upwards; for cases where the block is 0, cut the logical matrix into submatrices, and then according to... Figure 3 (a) Figure 3 The method in (b) is used to handle rows and columns.

[0057] This spatial mapping method effectively reduces the number of required cross arrays and corresponding peripheral circuits, making the structure simpler and more efficient.

[0058] (2) Time scheduling

[0059] Different quantization schemes may produce weights with different meanings, and some quantization schemes also include scaling factors. For example... Figure 4As shown in (a), after mapping various types of weights to the cross array using spatial mapping, directly adding the upper half of the cross array (representing the local sum of quantized weights calculated based on fixed-point scaling factors of 2^1) to the lower half (representing the local sum of quantized weights calculated based on powers of 2^-2) will lead to erroneous results. Furthermore, considering the limited number of rows and columns that can be activated simultaneously in the cross array, this invention proposes a time-scheduling strategy.

[0060] like Figure 4 As shown in (b), computation is performed using a block-activated cross array, with scheduling achieved through a data flow controller. The calculated local sums are then unified using a shifter before the accumulation operation is performed. This strategy simplifies the computation process and delegates the task of unifying multiple computation types to the shifter.

[0061] (3) Spatial pipeline

[0062] Because the number of rows or columns that can be activated simultaneously in a cross array is limited, such as Figure 5 As shown in the dashed box in (b), only a portion of the rows and columns can be activated at a time, so the entire cross array requires multiple cycles to complete the calculation. Figure 5 Figure (a) illustrates the access order of an input matrix with a 2x2 kernel and a stride of 2. A comparison of the pipeline employing the spatial mapping and temporal pipeline scheme of this invention with a traditional pipeline is provided. Figure 5 As shown in (b).

[0063] like Figure 5 As shown in (b), the scheme using spatial layout and temporal pipelines calculates the complete multiplication and summation (multiplication accumulation) of the feature vector and its corresponding weights in each cycle, resulting in an output ready for 2x2 convolution calculation in the third cycle. In contrast, the traditional pipeline calculates only the partial multiplication and summation of the feature vector and its corresponding weights in each cycle, only obtaining an output ready for the next layer in the fourth cycle. This design achieves a smoother and more efficient pipeline.

[0064] In this invention's in-memory computing architecture, the weight mapping scheme and pipeline for each layer of the network are determined offline and loaded into the control configuration (i.e., registers) to drive the finite state machine. These state machines ensure that the configuration is sent to the correct destination via the data flow controller. Data transmission in the bus, including the IR-bar bus and the output bus, is also statically scheduled to ensure that conflicts are avoided. If a large neural network layer is divided into multiple tiles, the results of these tiles must be aggregated before being fed to the activation units.

[0065] The in-memory computing architecture constructed in this invention is particularly suitable for application scenarios in intelligent security systems:

[0066] 1. Spatial Mapping Strategy: By partitioning the weight matrix bit-by-bit and mapping it onto the cross array, the number of required cross arrays and corresponding peripheral circuits is effectively reduced, thereby improving hardware resource utilization. This helps reduce equipment costs and power consumption in intelligent security systems.

[0067] 2. Time Scheduling Strategy: A block-based activation cross-array is used for computation, controlled by a data flow controller. The calculated local sums are unified using a shifter before being accumulated. This strategy achieves a concise and clear computation process, contributing to improved real-time performance of intelligent security systems.

[0068] 3. Highly efficient time pipeline: Benefiting from spatial mapping and time scheduling strategies, each computation is a complete multiplication-accumulation output, and there are no blockages in the cross array execution pipeline. This is a significant advantage for intelligent security systems that require real-time processing of large amounts of data.

[0069] 4. Offline-determined mapping scheme and pipeline: The weight mapping scheme and pipeline for each layer of the network are determined offline and loaded into the control configuration. This design simplifies runtime complexity and helps improve the stability and maintainability of the intelligent security system.

[0070] 5. Highly Scalable: The in-memory computing architecture is designed to accommodate various quantization schemes and bit widths, exhibiting high versatility and scalability. This allows the in-memory computing architecture to easily handle the needs of various deep neural network models in intelligent security systems.

[0071] In summary, the in-memory computing architecture constructed in this invention has significant advantages over traditional designs in terms of hardware resource utilization, computation process, data flow control, accumulation flexibility, design simplification, and scalability. It is particularly suitable for application scenarios with high real-time requirements and large computational demands, such as intelligent security systems.

[0072] Example 2

[0073] In order to implement the method corresponding to Embodiment 1 above and achieve the corresponding functions and technical effects, a security system based on an in-memory computing architecture is provided below.

[0074] The system includes:

[0075] The selection module is used to select multiple basic models from a model library; the model library includes: convolutional neural network models, recurrent neural network models, and attention mechanism network models.

[0076] The quantization module is used to perform personalized quantization on each of the aforementioned basic models;

[0077] The in-memory computing architecture building module is used to build an in-memory computing architecture based on the quantized base model.

[0078] The task execution and acceleration module is used to execute security tasks based on the in-memory computing architecture and to optimize and accelerate them; the input of the in-memory computing architecture includes surveillance video, and the output of the in-memory computing architecture includes the recognition results of the surveillance video; the optimization and acceleration include: spatial mapping, time scheduling, and time pipeline.

[0079] Example 3

[0080] Embodiment 3 of the present invention provides an electronic device, including a memory and a processor. The memory is used to store a computer program, and the processor runs the computer program to enable the electronic device to perform the security method based on the in-memory computing architecture provided in Embodiment 1.

[0081] In practical applications, the aforementioned electronic devices can be servers.

[0082] In practical applications, electronic devices include: at least one processor, memory, bus, and communication interface.

[0083] The processor, communication interface, and memory communicate with each other via a communication bus.

[0084] A communication interface is used to communicate with other devices.

[0085] The processor is used to execute programs, specifically the methods described in the above embodiments.

[0086] Specifically, the program may include program code, which includes computer operation instructions.

[0087] The processor may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention. The electronic device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or they may be processors of different types, such as one or more CPUs and one or more ASICs.

[0088] Memory is used to store programs. Memory may include high-speed RAM, and may also include non-volatile memory, such as at least one disk drive.

[0089] Example 4

[0090] Based on the description of Embodiment 3, Embodiment 4 of the present invention provides a storage medium on which a computer program is stored. The computer program can be executed by a processor to implement the security method based on the in-memory computing architecture of Embodiment 1.

[0091] The security system based on in-memory computing architecture provided in Embodiment 2 of this invention exists in various forms, including but not limited to:

[0092] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and primarily aim to provide voice and data communication. These terminals include: smartphones (e.g., iPhones), multimedia phones, feature phones, and low-end phones, etc.

[0093] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, possessing computing and processing capabilities, and generally also have mobile internet access capabilities. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0094] (3) Portable entertainment devices: These devices can display and play multimedia content. This category includes: audio and video players (such as iPods), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

[0095] (4) Other electronic devices with data interaction functions.

[0096] Specific embodiments of the subject matter have now been described. Other embodiments are within the scope of the appended claims. In some cases, the actions described in the claims can be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing can be advantageous.

[0097] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0098] For ease of description, the above apparatus is described by dividing it into various functional units. Of course, in implementing this invention, the functions of each unit can be implemented in one or more software and / or hardware components. Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0100] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0101] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0102] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0103] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0104] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined in this invention, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0105] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0106] This invention can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules.

[0107] Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific transactions or implement specific abstract data types. This invention can also be practiced in distributed computing environments where transactions are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0108] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0109] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A security method based on an in-memory computing architecture, characterized in that, include: Select multiple basic models from the model library; the model library includes: convolutional neural network models, recurrent neural network models, and attention mechanism network models; Each of the aforementioned basic models is quantified individually; A memory-to-computing architecture is constructed based on the quantized base model. This architecture includes an on-chip controller, multiple quantization computation units, and an on-chip buffer. The on-chip controller schedules the quantization computation units, and the on-chip buffer caches the computation results of the quantization computation units. Each quantization computation unit includes a cross array, a quantization storage indicator, a data flow controller, and a digital unit. The cross array stores the quantized base model and the partitioned base model. The data flow controller schedules each cross array according to the indicators stored in the quantization storage indicator. The digital unit processes the computation results of each cross array. Security tasks are performed based on the aforementioned in-memory computing architecture, and optimized and accelerated. The input of the in-memory computing architecture includes surveillance video, and the output of the in-memory computing architecture includes the recognition results of the surveillance video. The optimization and acceleration include: spatial mapping, time scheduling, and time pipeline. The spatial mapping specifically includes: slicing the weight matrix of the quantized base model bit-by-bit to obtain multiple logical matrices of equal size; the number of logical matrices is equal to the maximum bit width required for all weights; dividing the cross array into multiple groups, calculating a logical matrix for each group of cross arrays; mapping the logical matrices onto the cross arrays; during mapping, if a column of the cross array is 0, shifting the non-zero column on the right to the left; if a row of the cross array is 0, shifting the non-zero row below to the top; if a block of the quantized base model is 0, cutting the logical matrix into sub-matrices; The time scheduling specifically includes: scheduling the cross array through the data flow controller, and unifying and accumulating the calculation results of each cross matrix through the digital unit.

2. The security method based on in-memory computing architecture according to claim 1, characterized in that, Each of the aforementioned basic models is individually quantified, specifically including: The parameters in each of the aforementioned basic models are converted to integers and powers of two.

3. The security method based on in-memory computing architecture according to claim 1, characterized in that, The in-memory computing architecture also includes special function units; The special function units include: pooling functions and activation functions.

4. The security method based on in-memory computing architecture according to claim 1, characterized in that, The digital unit includes: an accumulation unit, a shifter, and an adder.

5. A security system based on an in-memory computing architecture, characterized in that, The system is applied to the security method based on in-memory computing architecture as described in any one of claims 1-4, and the system comprises: The selection module is used to select multiple basic models from a model library; the model library includes: convolutional neural network models, recurrent neural network models, and attention mechanism network models. The quantization module is used to perform personalized quantization on each of the aforementioned basic models; The in-memory computing architecture building module is used to build an in-memory computing architecture based on the quantized base model. The task execution and acceleration module is used to execute security tasks based on the in-memory computing architecture and to optimize and accelerate them; the input of the in-memory computing architecture includes surveillance video, and the output of the in-memory computing architecture includes the recognition results of the surveillance video; the optimization and acceleration include: spatial mapping, time scheduling, and time pipeline.

6. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory is used to store a computer program, and the processor runs the computer program to cause the electronic device to perform the security method based on the in-memory computing architecture as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the security method based on a storage-computing architecture as described in any one of claims 1-4.

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