Capacitive operational amplifier and signal establishment method thereof
By adopting a cascade structure of the primary and secondary amplifier units in the capacitive operational amplifier, combined with the control strategy of pre-charge and closed-loop establishment stage, the problem of increasing power consumption in traditional capacitive operational amplifiers when improving signal establishment accuracy is solved. , achieves the effects of fast signal establishment and low power consumption.
Patent Information
- Application Number
- CN202310645498.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-01
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2043-06-01
AI Technical Summary
When traditional capacitive operational amplifiers improve signal establishment accuracy, their power consumption increases and they cannot effectively reduce signal establishment time, resulting in cost and energy efficiency problems.
Using a cascade structure of the first-level amplification unit and the second-level amplification unit, the control unit alternately performs pre-charge and closed-loop establishment stages, and uses the second-level amplification unit to quickly pre-charge in the open-loop state, and uses the first-level amplification unit and the second-level amplification unit. Units are cascaded to form a closed loop to achieve rapid signal establishment.
It improves signal establishment speed, reduces power consumption of capacitive op amps, reduces bandwidth requirements, and reduces chip costs in high-speed applications.
Smart Images
Figure CN116566330B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of operational amplifiers, and in particular to a capacitive operational amplifier and a signal establishment method thereof. Background Art
[0002] For capacitive operational amplifiers, the signal settling time is related to the bandwidth of the operational amplifier. In order to meet the requirement of fast signal settling, the method often adopted is to increase the current, but this method will cause the power consumption to increase.
[0003] For a traditional capacitive operational amplifier, the output signal Vout is:
[0004] Vout=-Vstep*Cs / CF*(1-e -t / τ )(1)
[0005] Wherein, Vstep is the step signal generated by the sampling-amplification of the capacitive operational amplifier, Cs / CF is the amplification factor, t is the settling time of the capacitive operational amplifier, and τ is the time constant of the capacitive operational amplifier;
[0006] When the signal establishment accuracy N is required to reach n bits, the establishment time t is:
[0007] t=N*τ
[0008] N=ln(Vo / LSB)
[0009] Among them, Vo=Vstep*Cs / CF, LSB is the least significant bit.
[0010] When the accuracy requirement is higher, that is, the least significant bit LSB is smaller, the time t required for establishment is generally longer. The way to reduce the time t is generally to reduce the time constant τ, but at the same time the power consumption is also increased; another way is to reduce the accuracy N, that is, to reduce Vstep, which is obviously not what we want.
[0011] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention
[0012] The object of the present invention is to provide a capacitive operational amplifier and a signal establishment method thereof, which can be beneficial to the stability of the amplification unit, ensure the improvement of signal establishment accuracy and reduce power consumption at the same time.
[0013] To achieve the above objectives, an embodiment of the present invention provides a capacitive operational amplifier, including: a primary amplification unit and a secondary amplification unit, a sampling unit, a group of feedback capacitors, a first control unit and a second control unit.
[0014] The first-stage amplification unit has a group of first input terminals and a group of first output terminals, the second-stage amplification unit has a group of second input terminals and a group of second output terminals, the first output terminal of the first-stage amplification unit is connected to the second input terminal of the second-stage amplification unit; the sampling unit is used to sample the input signal and output the sampled signal to the first input terminal of the first-stage amplification unit; a group of feedback capacitors has a group of first terminals and a group of second terminals, the first terminal of the feedback capacitor is connected to the first input terminal of the first-stage amplification unit, and the second terminal of the feedback capacitor is connected to the second output terminal of the second-stage amplification unit; the first control unit is used to control the on-off between a group of first output terminals of the first-stage amplification unit and the on-off between the first output terminal of the first-stage amplification unit and the second input terminal of the second-stage amplification unit; the second control unit is used to control the on-off between the second terminal of the feedback capacitor and the second output terminal of the second-stage amplification unit.
[0015] In one or more embodiments of the present invention, the second control unit is further used to control the on-off between a group of second terminals of the feedback capacitor.
[0016] In one or more embodiments of the present invention, the first control unit includes a fifth switch, and a first end and a second end of the fifth switch are connected to a group of first output ends of the first-stage amplification unit.
[0017] In one or more embodiments of the present invention, the first control unit includes an eighth switch and a ninth switch, the first end of the eighth switch and the first end of the ninth switch are connected to a group of first output ends of the first-stage amplification unit, and the second end of the eighth switch and the second end of the ninth switch are connected to a group of second input ends of the second-stage amplification unit.
[0018] In one or more embodiments of the present invention, the second control unit includes a tenth switch and an eleventh switch, a first end of the tenth switch and a first end of the eleventh switch are connected to a group of second output ends of the secondary amplification unit, and a second end of the tenth switch and a second end of the eleventh switch are connected to a group of second ends of a group of feedback capacitors.
[0019] In one or more embodiments of the present invention, the second control unit includes a sixth switch, and a first terminal and a second terminal of the sixth switch are respectively connected to a group of second terminals of a group of feedback capacitors.
[0020] In one or more embodiments of the present invention, the secondary amplification unit includes a second operational amplifier and a group of Miller capacitors, a group of first ends of the Miller capacitors are connected to a group of input ends of the second operational amplifier to form a group of first input ends of the secondary amplification unit, and a group of second ends of the Miller capacitors are connected to a group of output ends of the second operational amplifier to form a group of second output ends of the secondary amplification unit.
[0021] In one or more embodiments of the present invention, the second operational amplifier comprises:
[0022] A first differential pair of transistors and a second differential pair of transistors, wherein the first differential pair of transistors has a first input terminal and a second input terminal for receiving differential signals, the second differential pair of transistors has a third input terminal and a fourth input terminal for receiving differential signals, the first differential pair of transistors has a first output terminal and a second output terminal for outputting amplified signals, and the second differential pair of transistors has a third output terminal corresponding to the first output terminal and a fourth output terminal corresponding to the second output terminal;
[0023] A first current mirror circuit is connected to the first output terminal and the fourth output terminal of the first differential pair tube;
[0024] A second current mirror circuit is connected to the second output terminal and the third output terminal of the first differential pair tube;
[0025] A first precharge establishment circuit is connected to the first input terminal of the first differential pair tube and the first current mirror circuit; and
[0026] The second pre-charge establishment circuit is connected to the second input terminal of the first differential pair tube and the second current mirror circuit.
[0027] In one or more embodiments of the present invention, the second operational amplifier further includes: a first bias current source and a second bias current source, wherein the first end of the first bias current source is connected to the first differential pair of tubes, the second end of the first bias current source is connected to the ground voltage, the first end of the second bias current source is connected to the second differential pair of tubes, and the second end of the second bias current source is connected to the ground voltage.
[0028] In one or more embodiments of the present invention, the first differential pair transistor includes a first MOS transistor and a second MOS transistor, the gate of the first MOS transistor is a first input terminal, the gate of the second MOS transistor is a second input terminal, the source of the first MOS transistor and the source of the second MOS transistor are connected to a ground voltage, the drain of the first MOS transistor is a first output terminal, and the drain of the second MOS transistor is a second output terminal; and / or
[0029] The second differential pair of transistors includes a third MOS transistor and a fourth MOS transistor, the gate of the third MOS transistor is the third input terminal, the gate of the fourth MOS transistor is the fourth input terminal, the drain of the third MOS transistor is the third output terminal, the drain of the fourth MOS transistor is the fourth output terminal, and the source of the third MOS transistor and the source of the fourth MOS transistor are connected to the ground voltage.
[0030] In one or more embodiments of the present invention, the first current mirror circuit includes a fifth MOS tube and a sixth MOS tube, the gate of the fifth MOS tube is connected to the first pre-charge establishment circuit, the gate of the sixth MOS tube is connected to the drain of the sixth MOS tube and the fourth output terminal, and is simultaneously connected to the first pre-charge establishment circuit, the drain of the fifth MOS tube is connected to the first output terminal, and the source of the fifth MOS tube and the source of the sixth MOS tube are connected to the power supply voltage; and / or
[0031] The second current mirror circuit includes a seventh MOS tube and an eighth MOS tube, the gate of the seventh MOS tube is connected to the second pre-charge establishment circuit, the gate of the eighth MOS tube is connected to the drain of the eighth MOS tube and the third output terminal, and is also connected to the second pre-charge establishment circuit, the drain of the seventh MOS tube is connected to the second output terminal, and the source of the seventh MOS tube and the source of the eighth MOS tube are connected to the power supply voltage.
[0032] In one or more embodiments of the present invention, the first pre-charge establishment circuit includes a first capacitor, a first end of the first capacitor is connected to the first input end, and a second end of the first capacitor is connected to the first current mirror circuit.
[0033] In one or more embodiments of the present invention, the first pre-charge establishment circuit further includes a first resistor, a first end of the first resistor is connected to the second end of the first capacitor, and a second end of the first resistor is connected to the fourth output end.
[0034] In one or more embodiments of the present invention, the second pre-charge establishment circuit includes a second capacitor, a first end of the second capacitor is connected to the second input end, and a second end of the second capacitor is connected to the second current mirror circuit.
[0035] In one or more embodiments of the present invention, the second pre-charge establishment circuit further includes a second resistor, a first end of the second resistor is connected to the second end of the second capacitor, and a second end of the second resistor is connected to the third output end.
[0036] In one or more embodiments of the present invention, the sampling unit includes a group of sampling capacitors, a first switch, a second switch, a seventh switch, a third switch and a fourth switch; the first ends of a group of the sampling capacitors are respectively connected to the signal input end through the first switch and the second switch to receive the input signal, and the first ends of a group of the sampling capacitors are connected through the seventh switch, the second ends of a group of the sampling capacitors are respectively connected to the common mode signal through the third switch and the fourth switch, and the second ends of the sampling capacitors are connected to the first input end of the first-stage amplification unit and the first end of the feedback capacitor.
[0037] The present invention also discloses a signal establishment method for a capacitive operational amplifier, comprising: a first stage and a second stage performed alternately, wherein the second stage comprises a pre-charging stage and a closed-loop establishment stage, wherein:
[0038] In the first stage, the input signal is sampled by the sampling unit;
[0039] In the pre-charging stage, the feedback capacitor is pre-charged based on the sampling signal output by the sampling unit through the secondary amplification unit;
[0040] In the closed-loop establishment stage, the first-stage amplification unit and the second-stage amplification unit are cascaded to establish the output signal.
[0041] In one or more embodiments of the present invention, in the first stage and the pre-charging stage, a group of first output terminals of the first-stage amplification unit are short-circuited by the first control unit.
[0042] In one or more embodiments of the present invention, in the first stage, a group of second ends of a group of feedback capacitors are short-circuited by a second control unit.
[0043] In one or more embodiments of the present invention, precharging the feedback capacitor based on the sampling signal output by the sampling unit through the secondary amplification unit includes: connecting the second end of the feedback capacitor to the second output end of the secondary amplification unit through the second control unit.
[0044] In one or more embodiments of the present invention, the step of cascading the first-stage amplification unit and the second-stage amplification unit to establish an output signal includes: connecting the first output end of the first-stage amplification unit to the second input end of the second-stage amplification unit through a first control unit.
[0045] Compared with the prior art, according to the capacitive operational amplifier and the signal establishment method thereof of the embodiment of the present invention, the second-stage amplification unit is placed in an open-loop state through the control of the first control unit and the second control unit, and the feedback capacitor is quickly precharged based on the sampling signal of the sampling unit, and the first control unit cascades the first-stage amplification unit and the second-stage amplification unit to form a closed loop, which can improve the signal establishment speed while reducing the power consumption of the capacitive operational amplifier, and can greatly reduce the cost of the chip in high-speed applications. The present invention first quickly establishes the signal to the vicinity of the target value, and then establishes the signal to the target value for the second time through the closed loop of the first-stage amplification unit and the second-stage amplification unit, so as to achieve the signal establishment accuracy, from a small amplitude signal to a high-precision large swing signal, while reducing the bandwidth requirements and the establishment time. BRIEF DESCRIPTION OF THE DRAWINGS
[0046] Figure 1 4 is a circuit diagram of a capacitive operational amplifier according to an embodiment of the present invention.
[0047] Figure 2 is a circuit schematic diagram of a second operational amplifier according to an embodiment of the present invention.
[0048] Figure 3 is a flow chart of signal establishment of a capacitive operational amplifier according to an embodiment of the present invention. DETAILED DESCRIPTION
[0049] The specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.
[0050] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.
[0051] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.
[0052] like Figure 1 As shown, a capacitive operational amplifier includes: a sampling unit 10, a first-stage amplifying unit 20, a second-stage amplifying unit 30, a set of feedback capacitors Cf, a first control unit 40 and a second control unit 50.
[0053] The sampling unit 10 is used for sampling an input signal and outputting the sampled signal to a first input terminal of the first-stage amplification unit 20 .
[0054] The first-stage amplifying unit 20 has a set of first input terminals and a set of first output terminals, the second-stage amplifying unit 30 has a set of second input terminals and a set of second output terminals, and the first output terminal of the first-stage amplifying unit 20 is connected to the second input terminal of the second-stage amplifying unit 30 .
[0055] A set of feedback capacitors Cf has a set of first ends and a set of second ends. The first ends of the feedback capacitors Cf are connected to the first input end of the first-stage amplifying unit 20 , and the second ends of the feedback capacitors Cf are connected to the second output end of the second-stage amplifying unit 30 .
[0056] The first control unit 40 is used to control the on-off between a group of first output terminals of the first-stage amplifying unit 20 and to control the on-off between the first output terminal of the first-stage amplifying unit 20 and the second input terminal of the second-stage amplifying unit 30 .
[0057] The second control unit 50 is used to control the connection between the second end of the feedback capacitor Cf and the second output end of the secondary amplification unit 30 and to control the connection between a group of second ends of the feedback capacitor Cf.
[0058] like Figure 1 As shown, the sampling unit 10 includes a group of sampling capacitors Cs, a first switch S1, a second switch S2, a seventh switch S7, a third switch S3 and a fourth switch S4.
[0059] A group of first ends of a group of sampling capacitors Cs are respectively connected to the signal input terminals Vip and Vin through the first switch S1 and the second switch S2 to receive input signals, and the first ends of a group of sampling capacitors Cs are connected through the seventh switch S7, and the connection and disconnection between the group of first ends of a group of sampling capacitors Cs are realized by closing and opening the seventh switch S7. The second ends of a group of sampling capacitors Cs are respectively connected to the common mode signal through the third switch S3 and the fourth switch S4, and the second ends of a group of sampling capacitors Cs are respectively connected to a group of first input terminals of the first-stage amplification unit 20 and a group of first terminals of a group of feedback capacitors Cf.
[0060] like Figure 1 As shown, the primary amplification unit 20 includes a first operational amplifier Gm1. A group of input terminals of the first operational amplifier Gm1 is a group of first input terminals of the primary amplification unit 20, and a group of output terminals of the first operational amplifier Gm1 is a group of first output terminals of the primary amplification unit 20. A group of input terminals of the first operational amplifier Gm1 is respectively connected to a group of second terminals of a group of sampling capacitors Cs and a group of first terminals of a group of feedback capacitors Cf.
[0061] like Figure 1 As shown, the secondary amplification unit 30 includes a second operational amplifier Gm2 and a group of Miller capacitors Cc. A group of first ends of a group of Miller capacitors Cc are respectively connected to a group of input ends of the second operational amplifier Gm2 to form a group of first input ends of the secondary amplification unit 30, and a group of second ends of a group of Miller capacitors Cc are respectively connected to a group of output ends of the second operational amplifier Gm2 to form a group of second output ends of the secondary amplification unit 30.
[0062] like Figure 1 As shown, the first control unit 40 includes a fifth switch S5, an eighth switch S8 and a ninth switch S9.
[0063] The first end and the second end of the fifth switch S5 are respectively connected to a group of first output ends of the first-stage amplifying unit 20. The on and off of the group of first output ends of the first-stage amplifying unit 20 are controlled by the fifth switch S5.
[0064] The first end of the eighth switch S8 and the first end of the ninth switch S9 are respectively connected to a group of first output ends of the primary amplifying unit 20 and the first end and the second end of the fifth switch S5, and the second end of the eighth switch S8 and the second end of the ninth switch S9 are respectively connected to a group of second input ends of the secondary amplifying unit 30. The on-off between a group of first output ends of the primary amplifying unit 20 and a group of second input ends of the corresponding secondary amplifying unit 30 is controlled by the eighth switch S8 and the ninth switch S9.
[0065] like Figure 1 As shown, the second control unit 50 includes a tenth switch S10, an eleventh switch S11 and a sixth switch S6.
[0066] The first end of the tenth switch S10 and the first end of the eleventh switch S11 are respectively connected to a group of second output ends of the secondary amplifying unit 30, and the second end of the tenth switch S10 and the second end of the eleventh switch S11 are respectively connected to a group of second ends of a group of feedback capacitors Cf. The on-off between a group of second ends of a group of feedback capacitors Cf and a group of second output ends of the secondary amplifying unit 30 is controlled by the tenth switch S10 and the eleventh switch S11.
[0067] The first and second ends of the sixth switch S6 are respectively connected to a group of second ends of a group of feedback capacitors Cf, the second ends of the tenth switch S10 and the second ends of the eleventh switch S11. The sixth switch S6 controls the on-off of a group of second ends of a group of feedback capacitors Cf.
[0068] like Figure 2 As shown, the second operational amplifier Gm2 includes: a first differential pair of tubes 31 and a second differential pair of tubes 32, a first current mirror circuit 33 and a second current mirror circuit 34, a first pre-charge establishment circuit 35 and a second pre-charge establishment circuit 36, and a first bias current source A1 and a second bias current source A2.
[0069] The first differential pair tube 31 has a first input terminal and a second input terminal for receiving differential signals, and the second differential pair tube 32 has a third input terminal and a fourth input terminal for receiving differential signals. In one embodiment, the first input terminal of the first differential pair tube 31 and the third input terminal of the second differential pair tube 32 are connected to form a first total input terminal Vip, and the second input terminal of the first differential pair tube 31 and the fourth input terminal of the second differential pair tube 32 are connected to form a second total input terminal Vin, that is, the first differential pair tube 31 and the second differential pair tube 32 receive the same differential signal.
[0070] The first differential pair transistor 31 has a first output terminal Von and a second output terminal Vop for outputting the amplified signal. The second differential pair transistor 32 has a third output terminal n corresponding to the first output terminal Von of the first differential pair transistor 31 and a fourth output terminal p corresponding to the second output terminal Vop of the first differential pair transistor 31 .
[0071] The first current mirror circuit 33 is connected to the first output terminal Von and the fourth output terminal p; the second current mirror circuit 34 is connected to the second output terminal Vop and the third output terminal n.
[0072] The first pre-charge establishing circuit 35 is connected to the first input terminal of the first differential pair tube 31 and the first current mirror circuit 33 ; the second pre-charge establishing circuit 36 is connected to the second input terminal and the second current mirror circuit 34 .
[0073] The first bias current source A1 is connected to the first differential pair of transistors 31 ; the second bias current source A2 is connected to the second differential pair of transistors 32 .
[0074] Specifically, the first differential pair transistor 31 includes a first MOS transistor M1 and a second MOS transistor M2. The gate of the first MOS transistor M1 is the first input terminal of the first differential pair transistor 31, and the gate of the second MOS transistor M2 is the second input terminal of the first differential pair transistor 31. The source of the first MOS transistor M1 and the source of the second MOS transistor M2 are connected to the first terminal of the first bias current source A1, and the second terminal of the first bias current source A1 is connected to the ground voltage. The drain of the first MOS transistor M1 is the first output terminal Von of the first differential pair transistor 31, and the drain of the second MOS transistor M2 is the second output terminal Vop of the first differential pair transistor 31.
[0075] Meanwhile, the second differential pair transistor 32 includes a third MOS transistor M3 and a fourth MOS transistor M4. The gate of the third MOS transistor M3 is the third input terminal of the second differential pair transistor 32, and the gate of the fourth MOS transistor M4 is the fourth input terminal of the second differential pair transistor 32. The drain of the third MOS transistor M3 is the third output terminal n, and the drain of the fourth MOS transistor M4 is the fourth output terminal p. The source of the third MOS transistor M3 and the source of the fourth MOS transistor M4 are connected to the first terminal of the second bias current source A2, and the second terminal of the second bias current source A2 is connected to the ground voltage.
[0076] like Figure 2 In the illustrated embodiment, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3 and the fourth MOS transistor M4 are all NMOS transistors. In other embodiments, one or more of M1 to M4 may also be implemented by PMOS transistors, and the circuit connection relationship may be adaptively adjusted.
[0077] like Figure 2As shown, the first current mirror circuit 33 includes a fifth MOS transistor M5 and a sixth MOS transistor M6. The gate of the fifth MOS transistor M5 is connected to the first pre-charge establishment circuit 35, and the gate of the sixth MOS transistor M6 is connected to the drain of the sixth MOS transistor M6 and the fourth output terminal p, and is also connected to the first pre-charge establishment circuit 35. The drain of the fifth MOS transistor M5 is connected to the first output terminal Von of the first differential pair transistor 31, and the source of the fifth MOS transistor M5 and the source of the sixth MOS transistor M6 are connected to the power supply voltage.
[0078] At the same time, the second current mirror circuit 34 includes a seventh MOS transistor M7 and an eighth MOS transistor M8. The gate of the seventh MOS transistor M7 is connected to the second pre-charge establishment circuit 36, the gate of the eighth MOS transistor M8 is connected to the drain of the eighth MOS transistor M8 and the third output terminal n, and is also connected to the second pre-charge establishment circuit 36, the drain of the seventh MOS transistor M7 is connected to the second output terminal Vop of the first differential pair transistor 31, and the source of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are connected to the power supply voltage.
[0079] like Figure 2 As shown, the first pre-charge establishment circuit 35 includes a first capacitor C1 and a first resistor R1. The first end of the first capacitor C1 is connected to the gate of the first MOS tube M1 and the gate of the third MOS tube M3, and the second end of the first capacitor C1 is connected to the gate of the fifth MOS tube M5 of the first current mirror circuit 33. The first end of the first resistor R1 is connected to the second end of the first capacitor C1, and the second end of the first resistor R1 is connected to the fourth output terminal p and the gate of the sixth MOS tube M6. In other embodiments, the first resistor R1 may not be provided, and in this case, the gate of the sixth MOS tube M6 is directly connected to the second end of the first capacitor C1 and the gate of the fifth MOS tube M5.
[0080] At the same time, the second pre-charge establishment circuit 36 includes a second capacitor C2 and a second resistor R2. The first end of the second capacitor C2 is connected to the gate of the second MOS tube M2 and the gate of the fourth MOS tube M4, and the second end of the second capacitor C2 is connected to the gate of the seventh MOS tube M7 of the second current mirror circuit 34. The first end of the second resistor R2 is connected to the second end of the second capacitor C2 and the gate of the seventh MOS tube M7, and the second end of the second resistor R2 is connected to the third output terminal n and the gate of the eighth MOS tube M8. In other embodiments, the second resistor R2 may not be provided, and in this case, the gate of the eighth MOS tube M8 is directly connected to the second end of the second capacitor C2 and the gate of the seventh MOS tube M7.
[0081] like Figure 3As shown, based on the above-mentioned capacitive operational amplifier, this embodiment also discloses a signal establishment method for a capacitive operational amplifier, including: a first stage Phase1 and a second stage Phase2 performed alternately, the first stage Phase1 and the second stage Phase2 constitute a signal sampling-amplification establishment cycle, and the second stage Phase2 includes a pre-charging stage Phase21 and a closed-loop establishment stage Phase22.
[0082] In the first phase Phase1, the input signal is sampled by the sampling unit 10. In one embodiment, in the first phase Phase1, a group of first output terminals of the first-stage amplification unit 20 are short-circuited by the first control unit 40, and a group of second terminals of a group of feedback capacitors Cf are short-circuited by the second control unit 50.
[0083] Specifically, in the first phase Phase1, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are closed, and the input signal is sampled through a group of sampling capacitors Cs. The fifth switch S5 of the first control unit 40 is closed to put the first operational amplifier Gm1 in a common mode state. The sixth switch S6 of the second control unit 50 is closed to short-circuit a group of second ends of a group of feedback capacitors Cf, so that the feedback capacitor Cf remains in the common mode signal driven and output by the second operational amplifier Gm2 during the closed-loop establishment phase Phase22 of the previous cycle, so that in the current cycle, the feedback capacitor Cf and the second operational amplifier Gm2 no longer need to establish a common mode signal, thereby improving the signal establishment speed.
[0084] In the pre-charging phase Phase 21 , the feedback capacitor Cf is pre-charged by the secondary amplifying unit 30 based on the sampling signal output by the sampling unit 10 . In one embodiment, the second end of the feedback capacitor Cf is connected to the second output end of the secondary amplifying unit 30 by the second control unit 50 .
[0085] Specifically, in the pre-charging stage Phase21, the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are disconnected, the fifth switch S5 remains closed, the sixth switch S6 is disconnected, the seventh switch S7, the tenth switch S10 and the eleventh switch S11 are closed, thereby entering the fast charging stage, and the second operational amplifier Gm2 is driven in an open-loop manner, so that a group of feedback capacitors Cf are quickly pre-charged based on the sampling signals output by a group of sampling capacitors Cs, so that the voltage on the feedback capacitor Cf is quickly established to near the target value.
[0086] In the closed loop establishment phase Phase 22 , the primary amplifying unit 20 and the secondary amplifying unit 30 are cascaded to establish an output signal. In one embodiment, the first output terminal of the primary amplifying unit 20 is connected to the second input terminal of the secondary amplifying unit 30 via the first control unit 40 .
[0087] Specifically, in the closed-loop establishment phase Phase22, the fifth switch S5 is opened, the sixth switch S6 remains opened, the eighth switch S8 and the ninth switch S9 are closed, and the first operational amplifier Gm1 and the second operational amplifier Gm2 are cascaded into a closed-loop state, so that the target signal is output, thereby ensuring the accuracy of signal establishment.
[0088] In this embodiment, the second operational amplifier Gm2 adopts a pseudo classAB structure, that is, the second differential pair tube 32 is equivalent to a mirror image of the first differential pair tube 31, and by adding the first capacitor C1 and the first resistor R1, the second resistor R2 and the second capacitor C2 structure, the gate voltage of the fifth MOS tube M5 and the gate voltage of the seventh MOS tube M7 can be quickly established to drive the fifth MOS tube M5 and the seventh MOS tube M7, so that the large swing signal is established more quickly, so that in the pre-charging stage Phase21, the step signal Vstep is quickly established to the vicinity of the expected value, so that in the closed-loop establishment stage Phase22, after the system is closed, the bandwidth requirement for the two-stage operational amplifier can be reduced, thereby achieving the purpose of reducing power consumption.
[0089] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and illustration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings, and the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts. The purpose of selecting and describing exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can implement and utilize various different exemplary embodiments of the present invention and various different selections and changes without departing from the scope and spirit of the present invention. The scope of the present invention is intended to be limited by the claims and their equivalents.
Claims
1. A capacitive operational amplifier, It is characterized in that include: A primary amplifying unit and a secondary amplifying unit, wherein the primary amplifying unit has a group of first input terminals and a group of first output terminals, the secondary amplifying unit has a group of second input terminals and a group of second output terminals, the first output terminal of the primary amplifying unit is connected to the second input terminal of the secondary amplifying unit, the secondary amplifying unit comprises a second operational amplifier and a group of Miller capacitors, a group of first terminals of a group of the Miller capacitors is connected to a group of input terminals of the second operational amplifier to form a group of first input terminals of the secondary amplifying unit, and a group of second terminals of a group of the Miller capacitors is connected to a group of output terminals of the second operational amplifier to form a group of second output terminals of the secondary amplifying unit; A sampling unit, used for sampling an input signal and outputting the sampled signal to a first input terminal of a first-stage amplification unit; A set of feedback capacitors, having a set of first ends and a set of second ends, wherein the first ends of the feedback capacitors are connected to the first input end of the first-stage amplification unit, and the second ends of the feedback capacitors are connected to the second output end of the second-stage amplification unit; A first control unit, used to control the on-off between a group of first output terminals of the first-stage amplifying unit and to control the on-off between the first output terminal of the first-stage amplifying unit and the second input terminal of the second-stage amplifying unit; as well as A second control unit, used for controlling the connection between the second end of the feedback capacitor and the second output end of the secondary amplification unit; Wherein, the second operational amplifier comprises: A first differential pair of transistors and a second differential pair of transistors, wherein the first differential pair of transistors has a first input terminal and a second input terminal for receiving differential signals, the second differential pair of transistors has a third input terminal and a fourth input terminal for receiving differential signals, the first differential pair of transistors has a first output terminal and a second output terminal for outputting amplified signals, and the second differential pair of transistors has a third output terminal and a fourth output terminal; A first current mirror circuit is connected to the first output terminal and the fourth output terminal of the first differential pair tube; A second current mirror circuit is connected to the second output terminal and the third output terminal of the first differential pair tube; A first precharge establishment circuit is connected to the first input terminal of the first differential pair tube and the first current mirror circuit; and The second pre-charge establishment circuit is connected to the second input terminal of the first differential pair tube and the second current mirror circuit.
2. The capacitive operational amplifier according to claim 1, It is characterized in that The second control unit is further used to control the on-off between a group of second terminals of the feedback capacitor.
3. The capacitive operational amplifier according to claim 1, It is characterized in that The first control unit includes a fifth switch, and a first end and a second end of the fifth switch are connected to a group of first output ends of the first-stage amplification unit.
4. The capacitive operational amplifier according to claim 1, It is characterized in that The first control unit includes an eighth switch and a ninth switch, wherein the first end of the eighth switch and the first end of the ninth switch are connected to a group of first output ends of the first-stage amplification unit, and the second end of the eighth switch and the second end of the ninth switch are connected to a group of second input ends of the second-stage amplification unit.
5. The capacitive operational amplifier according to claim 1, It is characterized in that The second control unit includes a tenth switch and an eleventh switch, a first end of the tenth switch and a first end of the eleventh switch are connected to a group of second output ends of the secondary amplification unit, and a second end of the tenth switch and a second end of the eleventh switch are connected to a group of second ends of a group of feedback capacitors.
6. The capacitive operational amplifier according to claim 2, It is characterized in that The second control unit includes a sixth switch, and a first end and a second end of the sixth switch are respectively connected to a group of second ends of a group of feedback capacitors.
7. The capacitive operational amplifier according to claim 1, It is characterized in that The second operational amplifier also includes: a first bias current source and a second bias current source, wherein the first end of the first bias current source is connected to the first differential pair of tubes, the second end of the first bias current source is connected to the ground voltage, the first end of the second bias current source is connected to the second differential pair of tubes, and the second end of the second bias current source is connected to the ground voltage.
8. The capacitive operational amplifier according to claim 1, It is characterized in that The first differential pair of transistors includes a first MOS transistor and a second MOS transistor, the gate of the first MOS transistor is a first input terminal, the gate of the second MOS transistor is a second input terminal, the source of the first MOS transistor and the source of the second MOS transistor are connected to a ground voltage, the drain of the first MOS transistor is a first output terminal, and the drain of the second MOS transistor is a second output terminal; and / or The second differential pair of transistors includes a third MOS transistor and a fourth MOS transistor, the gate of the third MOS transistor is the third input terminal, the gate of the fourth MOS transistor is the fourth input terminal, the drain of the third MOS transistor is the third output terminal, the drain of the fourth MOS transistor is the fourth output terminal, and the source of the third MOS transistor and the source of the fourth MOS transistor are connected to the ground voltage.
9. The capacitive operational amplifier according to claim 1, It is characterized in that The first current mirror circuit includes a fifth MOS tube and a sixth MOS tube, the gate of the fifth MOS tube is connected to the first pre-charge establishment circuit, the gate of the sixth MOS tube is connected to the drain of the sixth MOS tube and the fourth output terminal, and is also connected to the first pre-charge establishment circuit, the drain of the fifth MOS tube is connected to the first output terminal, and the source of the fifth MOS tube and the source of the sixth MOS tube are connected to the power supply voltage; and / or The second current mirror circuit includes a seventh MOS tube and an eighth MOS tube, the gate of the seventh MOS tube is connected to the second pre-charge establishment circuit, the gate of the eighth MOS tube is connected to the drain of the eighth MOS tube and the third output terminal, and is also connected to the second pre-charge establishment circuit, the drain of the seventh MOS tube is connected to the second output terminal, and the source of the seventh MOS tube and the source of the eighth MOS tube are connected to the power supply voltage.
10. The capacitive operational amplifier according to claim 1, It is characterized in that The first pre-charge establishment circuit includes a first capacitor, a first end of the first capacitor is connected to the first input end, and a second end of the first capacitor is connected to the first current mirror circuit.
11. The capacitive operational amplifier according to claim 10, It is characterized in that The first pre-charge establishment circuit also includes a first resistor, a first end of the first resistor is connected to the second end of the first capacitor, and a second end of the first resistor is connected to the fourth output end.
12. The capacitive operational amplifier according to claim 1, It is characterized in that The second pre-charge establishment circuit includes a second capacitor, a first end of the second capacitor is connected to the second input end, and a second end of the second capacitor is connected to the second current mirror circuit.
13. The capacitive operational amplifier according to claim 12, It is characterized in that The second pre-charge establishment circuit also includes a second resistor, a first end of the second resistor is connected to the second end of the second capacitor, and a second end of the second resistor is connected to the third output end.
14. The capacitive operational amplifier according to claim 1, It is characterized in that The sampling unit includes a group of sampling capacitors, a first switch, a second switch, a seventh switch, a third switch and a fourth switch; the first ends of a group of the sampling capacitors are respectively connected to the signal input end through the first switch and the second switch to receive the input signal, and the first ends of a group of the sampling capacitors are connected through the seventh switch, the second ends of a group of the sampling capacitors are respectively connected to the common mode signal through the third switch and the fourth switch, and the second ends of the sampling capacitors are connected to the first input end of the first-stage amplification unit and the first end of the feedback capacitor.
15. A signal establishment method for a capacitive operational amplifier, It is characterized in that Based on the capacitive operational amplifier according to any one of claims 1 to 14, the signal establishment method comprises: a first stage and a second stage performed alternately, the second stage comprises a pre-charging stage and a closed-loop establishment stage, wherein: In the first stage, the input signal is sampled by the sampling unit; In the pre-charging stage, the feedback capacitor is pre-charged based on the sampling signal output by the sampling unit through the secondary amplification unit; In the closed-loop establishment stage, the first-stage amplification unit and the second-stage amplification unit are cascaded to establish the output signal.
16. The signal establishment method according to claim 15, It is characterized in that In the first stage and the pre-charging stage, a group of first output terminals of the first-stage amplifying unit are short-circuited by the first control unit.
17. The signal establishment method according to claim 15, It is characterized in that In the first stage, a group of second ends of a group of feedback capacitors are short-circuited by the second control unit.
18. The signal establishment method according to claim 15, It is characterized in that The pre-charging of the feedback capacitor based on the sampling signal output by the sampling unit by the secondary amplification unit includes: connecting the second end of the feedback capacitor to the second output end of the secondary amplification unit by the second control unit.
19. The signal establishment method according to claim 15, It is characterized in that The step of cascading the primary amplifying unit and the secondary amplifying unit to establish the output signal includes: connecting the first output end of the primary amplifying unit to the second input end of the secondary amplifying unit through the first control unit.