Semiconductor memory element and method of making the same

Abstract

A semiconductor memory element and a method of fabricating the same are disclosed. The semiconductor memory element includes a substrate, a transistor disposed on the substrate and including a source doped region, a drain doped region disposed in the substrate, a channel region between the source doped region and the drain doped region, and a gate on the channel region, a data storage region adjacent to the transistor and recessed in the substrate, wherein the data storage region includes a ridge and a V-shaped groove, a bottom electrode layer conformally covering the ridge and the V-shaped groove in the data storage region, a resistance switching layer conformally covering the bottom electrode layer, and a top electrode layer covering the resistance switching layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a resistive random access memory element and its fabrication method. Background Technology

[0002] Resistive random access memory (RRAM) is a general term for reprogrammable devices that can be set to low or high resistance states. RRAM typically consists of a dielectric layer disposed between two electrodes. Some types of RRAM conduct electricity by forming different filaments in confined regions of the dielectric. Other types of RRAM conduct electricity by changing their properties throughout the dielectric region.

[0003] RRAM stores information by utilizing the variable resistance of a dielectric layer between two electrodes. This dielectric layer, acting as a resistive layer, is typically insulating, but can be made conductive by filaments or conductive paths formed after a sufficiently high voltage is applied (i.e., through a formation process). The formation of conductive paths can occur through various mechanisms, including defects, metal migration, etc. Once formed, the filaments can still be reset (i.e., broken, resulting in high resistance) or set (i.e., reformed, resulting in low resistance) by applying an appropriate voltage.

[0004] Current RRAM structures are typically vertical configurations with a single transistor and a single resistor. Due to the large current required, the size of the memory cells is affected by the transistor. In addition, current RRAM structures require the fabrication of a bottom electrode, a resistor switching layer, and a top electrode within the memory region. Therefore, compared to the surrounding circuit region, there is an additional thickness of the interlayer dielectric layer in the memory region, and the problem of low dielectric constant layer gap filling arises. Summary of the Invention

[0005] The main objective of this invention is to provide a semiconductor memory element and a method for manufacturing the same, so as to overcome the shortcomings and disadvantages of the prior art.

[0006] The present invention provides a semiconductor memory element comprising: a substrate; a transistor disposed on the substrate, wherein the transistor includes a source doped region disposed in the substrate, a drain doped region disposed in the substrate and spaced apart from the source doped region, a channel region in the substrate between the source doped region and the drain doped region, and a gate above the channel region; a data storage region adjacent to the transistor and recessed in the substrate, wherein the data storage region includes at least one ridge and at least one V-shaped groove; a bottom electrode layer conformally covering the at least one ridge and the at least one V-shaped groove in the data storage region; a resistor switching layer conformally covering the bottom electrode layer; and a top electrode layer covering the resistor switching layer.

[0007] According to an embodiment of the present invention, the semiconductor memory element further includes a diffusion region surrounding the bottom electrode layer, wherein the drain doped region is merged with the diffusion region.

[0008] According to an embodiment of the present invention, the semiconductor memory element further includes a metal silicide layer located between the substrate and the bottom electrode layer.

[0009] According to an embodiment of the present invention, the metal silicide layer comprises nickel silicide.

[0010] According to an embodiment of the present invention, the at least one V-shaped groove is completely filled by the bottom electrode layer, the resistance switching layer and the top electrode layer.

[0011] According to an embodiment of the present invention, the bottom electrode layer comprises titanium nitride or tantalum nitride.

[0012] According to an embodiment of the present invention, the resistor switching layer comprises a metal oxide.

[0013] According to an embodiment of the present invention, the resistor switching layer comprises hafnium oxide, tantalum oxide, titanium oxide, or aluminum oxide.

[0014] According to an embodiment of the present invention, the top electrode layer comprises titanium nitride or tantalum nitride.

[0015] According to an embodiment of the present invention, the top electrode layer comprises tungsten.

[0016] Another aspect of the present invention provides a method for forming a semiconductor memory element. First, a substrate is provided. Next, a transistor is formed on the substrate, wherein the transistor includes a source doped region disposed in the substrate, a drain doped region disposed in the substrate and spaced apart from the source doped region, a channel region in the substrate between the source doped region and the drain doped region, and a gate above the channel region. Then, a data storage region recessed in the substrate is formed near the transistor, wherein the data storage region includes at least one ridge and at least one V-shaped groove. A bottom electrode layer is conformally deposited on the at least one ridge and the at least one V-shaped groove in the data storage region. A resistor switching layer is conformally formed on the bottom electrode layer. A top electrode layer is formed on the resistor switching layer.

[0017] According to an embodiment of the present invention, the method further includes: forming a diffusion region surrounding the bottom electrode layer, wherein the drain doped region is merged with the diffusion region.

[0018] According to an embodiment of the present invention, the method further includes: forming a metal silicide layer between the substrate and the bottom electrode layer.

[0019] According to an embodiment of the present invention, the metal silicide layer comprises nickel silicide.

[0020] According to an embodiment of the present invention, the at least one V-shaped groove is completely filled by the bottom electrode layer, the resistance switching layer and the top electrode layer.

[0021] According to an embodiment of the present invention, the bottom electrode layer comprises titanium nitride or tantalum nitride.

[0022] According to an embodiment of the present invention, the resistor switching layer comprises a metal oxide.

[0023] According to an embodiment of the present invention, the resistor switching layer comprises hafnium oxide, tantalum oxide, titanium oxide, or aluminum oxide.

[0024] According to an embodiment of the present invention, the top electrode layer comprises titanium nitride or tantalum nitride.

[0025] According to an embodiment of the present invention, the top electrode layer comprises tungsten. Attached Figure Description

[0026] Figures 1 to 13 This is a schematic diagram illustrating a method for forming a semiconductor memory element according to an embodiment of the present invention.

[0027] Explanation of main component symbols

[0028] 100 base

[0029] 102 Insulation trench

[0030] 104 Grooves

[0031] Patterned photoresist layers 110, 210, 310, 410, 510

[0032] 110a, 210a, 310a, 410a Open

[0033] 112 Convex Ridge

[0034] 114 V-shaped groove

[0035] 250 and 350 ion implantation fabrication processes

[0036] BE bottom electrode layer

[0037] BI Embedded Oxide Layer

[0038] CH Channel Area

[0039] CS, CG, CD contact plugs

[0040] DD drain doped region

[0041] DF diffusion region

[0042] DR data storage area

[0043] DSS Data Storage Structure

[0044] GD gate dielectric layer

[0045] GE gate

[0046] IL dielectric layer

[0047] MC semiconductor memory device

[0048] MG metal gate

[0049] RS Resistor Switching Layer

[0050] SiC metal silicide layer

[0051] SP gap wall

[0052] SS source doped region

[0053] TE top electrode layer

[0054] TI trench insulation structure

[0055] TR transistor formation region Detailed Implementation

[0056] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0057] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0058] Please see Figures 1 to 13 This is a schematic diagram illustrating a method for forming a semiconductor memory element according to an embodiment of the present invention. Figure 1 As shown, firstly, a substrate 100 is provided, such as a semiconductor substrate like a silicon substrate. According to an embodiment of the present invention, the substrate 100 includes a transistor formation region TR and a data storage region DR, wherein the data storage region DR is adjacent to the transistor formation region TR.

[0059] like Figure 2As shown, next, photolithography and etching processes are performed to form insulating trenches 102 on the surface of substrate 100, defining active regions, and forming several grooves 104 in data storage area DR.

[0060] like Figure 3 As shown, a patterned photoresist layer 110 is then formed on the substrate 100. The patterned photoresist layer 110 includes an opening 110a, exposing a groove 104 within the data storage area DR. Then, using a wet etching method, the surface of the groove 104 within the data storage area DR is etched to form a ridge 112 and a V-shaped groove 114.

[0061] The aforementioned wet etching method can be performed using tetramethylammonium hydroxide (TMAH) to etch the substrate 100 between the grooves 104 in the data storage area DR into a structure with a spire-shaped or triangular outline.

[0062] like Figure 4 As shown, the patterned photoresist layer 110 is then removed. Next, a dielectric layer, such as a silicon oxide layer, is deposited over the substrate 100. Then, planarization is performed using a chemical mechanical polishing (CMP) process to form a trench insulating structure TI and a buried oxide layer BI within a V-shaped groove 114 filling the data storage region DR.

[0063] like Figure 5 As shown, a gate GE, for example a polysilicon gate, is formed on a substrate 100 within the transistor formation region TR. According to an embodiment of the invention, a spacer wall SP may be formed on the sidewall of the gate GE. According to an embodiment of the invention, a gate dielectric layer GD may be formed between the gate GE and the substrate 100. According to an embodiment of the invention, the gate GE is adjacent to the data storage region DR.

[0064] like Figure 6 As shown, a patterned photoresist layer 210 is then formed on the substrate 100. The patterned photoresist layer 210 includes an opening 210a, exposing the buried oxide layer BI within the data storage region DR. Then, an ion implantation process 250 is performed to implant a dopant, such as an N-type dopant, into the substrate 100 through the opening 210a. A tempering process is then performed to form the diffusion region DF, such as an N-type dopant. + Diffusion zone.

[0065] like Figure 7 As shown, a patterned photoresist layer 310 is then formed on the substrate 100. The patterned photoresist layer 310 includes an opening 310a that exposes the transistor formation region TR and the gate GE located within the transistor formation region TR.

[0066] Next, an ion implantation process 350 is performed to form a source doped region SS and a drain doped region DD in the substrate 100 on both sides of the gate GE, thus completing the fabrication of transistor T. A channel region CH is formed in the substrate 100 between the source doped region SS and the drain doped region DD of transistor T. The gate GE is located above the channel region CH. According to an embodiment of the present invention, the source doped region SS and the drain doped region DD can be N... + Doped region. According to an embodiment of the present invention, the drain doped region DD and the diffusion region DF are connected and merged together.

[0067] like Figure 8 As shown, a patterned photoresist layer 410 is then formed on the substrate 100. The patterned photoresist layer 410 includes an opening 410a that exposes the buried oxide layer BI within the data storage area DR. Next, an etching process, such as dry etching or wet etching, is performed to remove the buried oxide layer BI, exposing the ridges 112 and the V-shaped grooves 114.

[0068] like Figure 9 As shown, next, a metal silicide layer (SIC) can be formed on the gate (GE), source doped region (SS), drain doped region (DD), and data storage region (DR). According to embodiments of the present invention, the metal silicide layer (SIC) may, for example, contain nickel silicide, but is not limited thereto. The metal silicide layer (SIC) can be formed using a self-aligned method.

[0069] A bottom electrode layer BE is deposited conformally on the ridge 112 and V-shaped groove 114 within the data storage region DR. Then, a resistance switching layer RS ​​is formed conformally on the bottom electrode layer BE. Next, a top electrode layer TE is formed on the resistance switching layer RS. According to an embodiment of the present invention, the V-shaped groove 114 is completely filled by the bottom electrode layer BE, the resistance switching layer RS, and the top electrode layer TE.

[0070] According to embodiments of the present invention, the bottom electrode layer BE may comprise titanium nitride or tantalum nitride. According to embodiments of the present invention, the resistor switching layer RS ​​may comprise a metal oxide. According to embodiments of the present invention, for example, the resistor switching layer RS ​​may comprise hafnium oxide, tantalum oxide, titanium oxide, or aluminum oxide. According to embodiments of the present invention, the top electrode layer TE may comprise titanium nitride or tantalum nitride. According to another embodiment of the present invention, the top electrode layer TE may comprise tungsten.

[0071] like Figure 10As shown, a patterned photoresist layer 510 is then formed on the substrate 100 within the data storage region DR, defining the location of the data storage structure. Then, an etching process, such as an anisotropic dry etching process, is performed to etch away the top electrode layer TE, the resistor switching layer RS, and the bottom electrode layer BE, which are not covered by the patterned photoresist layer 510, thus forming the data storage structure DSS. According to an embodiment of the present invention, the diffusion region DF surrounds the bottom electrode layer BE of the data storage structure DSS.

[0072] like Figures 11 to 13 As shown, subsequent steps include the deposition and planarization of the dielectric layer IL. Figure 11 ), replacement metal gate fabrication process ( Figure 12 ) and the fabrication of contact plugs ( Figure 13 ).like Figure 11 As shown, a chemical vapor deposition (CVD) process is first performed to deposit a dielectric layer IL, such as a silicon oxide layer, comprehensively on the surface of the substrate 100. Then, a chemical mechanical polishing (CMP) process is used to planarize the dielectric layer IL until the gate GE is exposed. Then, as... Figure 12 As shown, a metal gate replacement fabrication process is performed to form the metal gate MG. Finally, as... Figure 13 As shown, contact plugs CS, CG and CD are formed in the dielectric layer IL and electrically connected to the source doped region SS, the gate doped region GE and the drain doped region DD, respectively, thus forming a semiconductor memory element MC.

[0073] Structurally, the semiconductor memory element MC of this invention, such as Figure 13 As shown, the substrate includes a substrate 100 and a transistor T disposed on the substrate 100. The transistor T includes a source doped region SS disposed in the substrate 100, a drain doped region DD disposed in the substrate 100 and spaced apart from the source doped region SS, a channel region CH in the substrate 100 between the source doped region SS and the drain doped region DD, and a gate MG above the channel region CH. A data storage region DR is adjacent to the transistor T and recessed in the substrate 100.

[0074] According to an embodiment of the present invention, the data storage area DR includes at least one ridge 112 and at least one V-shaped groove 114. According to an embodiment of the present invention, the bottom electrode layer BE conformally covers the ridge 112 and the V-shaped groove 114 within the data storage area DR. According to an embodiment of the present invention, the resistor switching layer RS ​​conformally covers the bottom electrode layer BE. According to an embodiment of the present invention, the top electrode layer TE covers the resistor switching layer RS.

[0075] According to an embodiment of the present invention, the semiconductor memory element MC further includes a diffusion region DF surrounding the bottom electrode layer BE, wherein the drain doped region DD is merged with the diffusion region DF.

[0076] According to an embodiment of the present invention, the semiconductor memory element MC further includes a metal silicide layer SiC located between the substrate 100 and the bottom electrode layer BE. According to an embodiment of the present invention, the metal silicide layer includes nickel silicide.

[0077] According to an embodiment of the present invention, the V-shaped groove 114 is completely filled by the bottom electrode layer BE, the resistor switching layer RS, and the top electrode layer TE. According to an embodiment of the present invention, the bottom electrode layer BE comprises titanium nitride or tantalum nitride. According to an embodiment of the present invention, the resistor switching layer RS ​​comprises a metal oxide. According to an embodiment of the present invention, the resistor switching layer RS ​​comprises hafnium oxide, tantalum oxide, titanium oxide, or aluminum oxide. According to an embodiment of the present invention, the top electrode layer TE comprises titanium nitride or tantalum nitride. According to an embodiment of the present invention, the top electrode layer TE comprises tungsten.

[0078] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor memory element, comprising: Base; A transistor disposed on the substrate, wherein the transistor includes a source doped region disposed in the substrate, a drain doped region disposed in the substrate and spaced apart from the source doped region, a channel region in the substrate between the source doped region and the drain doped region, and a gate above the channel region. A data storage region is adjacent to the transistor and recessed in the substrate, wherein the data storage region includes at least one ridge and at least one V-shaped groove formed by etching the material of the substrate; The bottom electrode layer conformally covers the at least one ridge and the at least one V-shaped groove within the data storage area; A resistance switching layer conformally covers the bottom electrode layer; and Top electrode layer, covering the resistance switching layer, The at least one V-shaped groove is completely filled by the bottom electrode layer, the resistance switching layer and the top electrode layer.

2. The semiconductor memory element according to claim 1, wherein, Also includes: A diffusion region surrounds the bottom electrode layer, wherein the drain doped region is merged with the diffusion region.

3. The semiconductor memory element according to claim 1, wherein, Also includes: A metal silicide layer is located between the substrate and the bottom electrode layer.

4. The semiconductor memory element according to claim 3, wherein, The metal silicide layer contains nickel silicide.

5. The semiconductor memory element according to claim 1, wherein, The bottom electrode layer contains titanium nitride or tantalum nitride.

6. The semiconductor memory element according to claim 1, wherein, The resistance switching layer comprises a metal oxide.

7. The semiconductor memory element according to claim 1, wherein, The resistance switching layer comprises hafnium oxide, tantalum oxide, titanium oxide, or aluminum oxide.

8. The semiconductor memory element according to claim 1, wherein, The top electrode layer contains titanium nitride or tantalum nitride.

9. The semiconductor memory element according to claim 1, wherein, The top electrode layer contains tungsten.

10. A method of forming a semiconductor memory element, comprising: Provide a base; A transistor is formed on the substrate, wherein, The transistor includes a source doped region disposed in the substrate, a drain doped region disposed in the substrate and spaced apart from the source doped region, a channel region in the substrate between the source doped region and the drain doped region, and a gate above the channel region. A data storage region recessed in the substrate is formed near the transistor, wherein the data storage region includes at least one ridge and at least one V-shaped groove formed by etching the material of the substrate; A bottom electrode layer is deposited conformally on the at least one ridge and the at least one V-shaped groove within the data storage area; A resistance switching layer is compliantly formed on the bottom electrode layer; and A top electrode layer is formed on the resistor switching layer. The at least one V-shaped groove is completely filled by the bottom electrode layer, the resistance switching layer and the top electrode layer.

11. The method according to claim 10, wherein, Also includes: A diffusion region is formed around the bottom electrode layer, wherein the drain doped region is merged with the diffusion region.

12. The method according to claim 10, wherein, Also includes: A metal silicide layer is formed between the substrate and the bottom electrode layer.

13. The method according to claim 12, wherein, The metal silicide layer contains nickel silicide.

14. The method of claim 10, wherein, The bottom electrode layer contains titanium nitride or tantalum nitride.

15. The method according to claim 10, wherein, The resistance switching layer comprises a metal oxide.

16. The method of claim 10, wherein, The resistance switching layer comprises hafnium oxide, tantalum oxide, titanium oxide, or aluminum oxide.

17. The method according to claim 10, wherein, The top electrode layer contains titanium nitride or tantalum nitride.

18. The method according to claim 10, wherein, The top electrode layer contains tungsten.

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