Chip system packaging manufacturing method

Abstract

The present invention provides a chip system packaging manufacturing method. The chip system packaging manufacturing method according to the present invention includes the following steps: a first step: providing an adapter board and an electrical chip to manufacture an electrical chip packaging structure unit, wherein the electrical chip is arranged on the front surface of the adapter board, and an electrical connection structure electrically connected to the electrical chip and located in the same plane is formed on the back surface of the adapter board; a second step: providing a substrate having a substrate groove and an optical chip to manufacture an optical chip packaging structure unit, wherein the optical chip is arranged in the substrate groove formed on the upper surface of the substrate, and electrical connection contacts electrically connected to the optical chip and located in the same plane are formed on the upper surface of the substrate; a third step: mounting the electrical chip packaging structure unit on the substrate to form a combined structure of the electrical chip packaging structure unit and the optical chip packaging structure unit, wherein the electrical chip packaging structure is electrically connected to the electrical connection contacts of the optical chip packaging structure unit via the electrical connection structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a chip system packaging manufacturing method and a chip packaging structure manufactured thereby. Background Art

[0002] As global internet traffic grows, the demand for data center interconnection bandwidth will continue to grow exponentially. It is predicted that by 2030, data center energy consumption will continue to rise, exceeding 3PWh globally, and in the worst-case scenario, it could reach 8PWh.

[0003] To meet internet traffic demands, data center node bandwidth must reach 10Tb / s. To mitigate the growing trend of data center energy consumption, it's crucial to find ways to reduce system and device power consumption. The number of I / O pins per package roughly doubles every six years, while total I / O bandwidth doubles every three to four years. Addressing these speed disparities requires doubling I / O bandwidth every three to four years.

[0004] Silicon photonics is being introduced to increase I / O bandwidth and minimize power consumption. The packaging of optical integrated circuits (PICs) and electrical integrated circuits (EICs) is crucial. Photonics offers minimal signal degradation, low power consumption, high bandwidth, and the ability to leverage the mature CMOS ecosystem. These factors, in turn, directly impact I / O bandwidth and power consumption. Therefore, improper integration of optical and electrical components can negate any potential advantages of silicon photonics.

[0005] I / O to the compute node can be connected via wire bonds or flip-chip soldering to the PCB. In theory, this packaging approach is excellent; however, this is not always the case in practice. Specifically, silicon photonics process nodes lag behind those used for electronic chips. The most advanced processes developed for monolithic integration are 45 nm and 32 nm. Compared to electronic chip processes of 10 nm and below, these processes lag significantly in performance. This type of packaging is incapable of integrating the electronic chip and the optical chip together. Therefore, it is desirable to develop a technical solution that can effectively achieve higher-density integrated packaging of optical and electronic chips.

[0006] Chinese patent application CN115588618A discloses a three-dimensional stacked optoelectronic package structure and its fabrication method. However, the first and second connecting bumps have different heights. The height difference significantly increases the difficulty of the process and may reduce chip stability. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to address the above-mentioned defects in the prior art and provide a chip system packaging manufacturing method that integrates optical integrated circuits and electrical integrated circuits to achieve co-packaging between optical chips and electrical chips, and a chip packaging structure manufactured thereby.

[0008] According to the present invention, a chip system packaging manufacturing method is provided, comprising:

[0009] The first step is to provide an adapter board and an electric chip to manufacture an electric chip packaging structure unit, wherein the electric chip is arranged on the front surface of the adapter board, and an electrical connection structure electrically connected to the electric chip and located in the same plane is formed on the back surface of the adapter board;

[0010] Step 2: Providing a substrate having a substrate groove and an optical chip to manufacture an optical chip packaging structure unit, wherein the optical chip is arranged in the substrate groove formed on the upper surface of the substrate, and the upper surface of the substrate is formed with electrical connection contacts that are electrically connected to the optical chip and are located in the same plane;

[0011] The third step: installing the electrical chip packaging structure unit onto the substrate to form a combined structure of the electrical chip packaging structure unit and the optical chip packaging structure unit, wherein the electrical chip packaging structure is electrically connected to the electrical connection contacts of the optical chip packaging structure unit via the electrical connection structure.

[0012] Preferably, the chip system packaging manufacturing method further includes:

[0013] Step 4: providing a fiber optic coupler, and installing the fiber optic coupler on the combined structure of the electrical chip packaging structure unit and the optical chip packaging structure unit;

[0014] Step 5: Provide a heat dissipation plate and cover the heat dissipation plate on the substrate.

[0015] Preferably, manufacturing the electric chip packaging structural unit includes:

[0016] First, a temporary substrate and an adapter plate are provided. The back of the adapter plate is provided with an electrical connection structure that is coplanar and electrically connected to the conductive wiring in the adapter plate. The front of the adapter plate is provided with an intermediate dielectric layer, and the surface of the intermediate dielectric layer is provided with electrical contacts that are electrically connected to the adapter plate.

[0017] Subsequently, the adapter plate is arranged on the temporary base plate;

[0018] Thereafter, the electric chip is arranged on the front surface of the adapter plate through the conductive contacts, and the conductive contacts are in electrical contact with the electric contacts.

[0019] Afterwards, an underfill process is performed to form an underfill glue covering the conductive contacts; wherein the underfill glue is filled between the electrical chip and the adapter board through a capillary effect;

[0020] Subsequently, a packaging layer is formed to cover the front surface of the adapter board, exposing the upper surface of the electrical chip;

[0021] Then, the temporary substrate is removed to expose the electrical connection structure on the back side of the adapter plate, wherein the electrical connection structure is in the same plane.

[0022] Preferably, manufacturing the optical chip packaging structure unit includes:

[0023] providing a substrate having a substrate groove formed on a front surface;

[0024] disposing adhesive in the groove of the base;

[0025] An optical chip is arranged on the adhesive in the substrate groove, the optical chip having a first electrical connection contact and a second electrical connection contact in the same plane, and a third electrical connection contact coplanar with the first electrical connection contact and the second electrical connection contact on the surface of the optical chip on the front side, thereby forming an optical chip packaging structural unit.

[0026] Preferably, the chip system packaging manufacturing method further includes:

[0027] The electrical chip packaging structure is electrically connected to the first electrical connection contact and the third electrical connection contact of the optical chip packaging structure unit through the electrical connection structure, wherein the gap between the adapter plate and the optical chip packaging structure unit is filled with bottom filling glue;

[0028] The second electrical connection contact is optically coupled and provided with an optical fiber coupler extending to the outside;

[0029] A heat dissipation plate is arranged on the base, and the electric chip packaging structure is arranged between the heat dissipation plate and the base.

[0030] Preferably, a removable layer for protection and temporary bonding is arranged between the temporary substrate and the adapter plate.

[0031] Preferably, the adapter plate is temporarily bonded to the temporary substrate via a peelable layer.

[0032] Preferably, the packaging layer covers the upper surface of the electric chip, and the upper surface of the electric chip is exposed through a grinding process.

[0033] Preferably, the second electrical connection contact is used to connect to the optical fiber coupler, and the first electrical connection contact and the third electrical connection contact are used to connect to the electrical chip packaging structure.

[0034] This invention enables high-density integration of optical and electrical chips. The optical chip is embedded within a substrate, and the components of the electrical chip, arranged on an adapter board, are combined with the substrate, thereby achieving system integration of the optoelectronic chips. Because electrical connection is achieved through coplanar electrical connection structures and coplanar electrical connection contacts (first and third electrical connection contacts), there is no need to consider soldering pads or solder joints at different heights. This improves electrical connection quality, simplifies the connection process, and enhances chip stability. Furthermore, because the 2.5D process can be used to achieve high-density I / O integration with the electrical chip, high computational performance is achieved, resulting in a powerful computing architecture that supports large-scale system integration of multiple optical chip modules and electrical modules. This structure allows for a minimum line width and line spacing of 0.4um / 0.4um. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] A more complete understanding of the present invention and its attendant advantages and features will be more readily appreciated by reference to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0036] Figure 1 The overall flow chart of the chip system packaging manufacturing method according to the preferred embodiment of the present invention is schematically shown.

[0037] Figure 2 The temporary substrate provided in the step of manufacturing an electric chip packaging structure unit according to a preferred embodiment of the present invention is schematically shown.

[0038] Figure 3 The figure schematically shows an interposer provided in the steps of manufacturing an electric chip packaging structure unit according to a preferred embodiment of the present invention.

[0039] Figure 4 The structure after the interposer is arranged on the temporary substrate in the step of manufacturing the electric chip packaging structure unit according to a preferred embodiment of the present invention is schematically shown.

[0040] Figure 5 The structure after the electric chip packaging structure unit is provided in the step of manufacturing the electric chip packaging structure unit according to a preferred embodiment of the present invention is schematically shown.

[0041] Figure 6 The structure after filling with bottom filling glue in the step of manufacturing the electric chip packaging structure unit according to the preferred embodiment of the present invention is schematically shown.

[0042] Figure 7 The structure after forming a covering packaging layer in the step of manufacturing an electric chip packaging structure unit according to a preferred embodiment of the present invention is schematically shown.

[0043] Figure 8The structure after the electrical connection structure on the back side of the interposer is exposed in the step of manufacturing the electric chip packaging structure unit according to a preferred embodiment of the present invention is schematically shown.

[0044] Figure 9 The structure after providing a substrate in the steps of manufacturing an optical chip packaging structure unit according to a preferred embodiment of the present invention is schematically shown.

[0045] Figure 10 The structure after setting the adhesive in the steps of manufacturing the optical chip packaging structure unit according to a preferred embodiment of the present invention is schematically shown.

[0046] Figure 11 The structure after arranging the optical chip in the steps of manufacturing the optical chip packaging structure unit according to a preferred embodiment of the present invention is schematically shown.

[0047] Figure 12 The structure after the electric chip packaging structure unit is mounted on a substrate according to a preferred embodiment of the present invention is schematically shown.

[0048] Figure 13 The structure of a fiber optic coupler after being formed according to a preferred embodiment of the present invention is schematically shown.

[0049] Figure 14 The structure after covering the heat dissipation plate according to a preferred embodiment of the present invention is schematically shown.

[0050] Figure 15 Schematically shows Figure 14 A three-dimensional schematic diagram of the chip system packaging structure is shown, wherein, in order to clearly illustrate the structures such as the optical fiber coupler and the electrical chip packaging structure unit, the heat sink and the thermal conductive adhesive layer are not shown.

[0051] Description of reference numerals:

[0052] Temporary substrate 10; adapter plate 20; electrical connection structure 21; intermediate dielectric layer 22; electrical contact 23; conductive contact 24; peelable layer 30; electrical chip 40; bottom filler 41; packaging material 50; substrate 60; substrate groove 61; adhesive 70; optical chip 80; first electrical connection contact 91; second electrical connection contact 92; bottom filler 100; optical fiber coupler 110; heat sink 130; thermally conductive adhesive layer 140.

[0053] It should be noted that the accompanying drawings are intended to illustrate the present invention, not to limit it. Note that the accompanying drawings showing structures may not be drawn to scale. Furthermore, in the accompanying drawings, identical or similar elements are labeled with identical or similar reference numerals. DETAILED DESCRIPTION

[0054] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0055] For ease of description, spatial relational terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers. Among them, when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element.

[0056] Expressions such as "between..." may be used herein to indicate inclusiveness of both endpoints, and expressions such as "plurality" may be used to indicate two or more, unless otherwise specifically limited. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features.

[0057] Figure 1 The overall flow chart of the chip system packaging manufacturing method according to the preferred embodiment of the present invention is schematically shown. Figure 1 As shown, the chip system packaging manufacturing method according to the preferred embodiment of the present invention includes:

[0058] Step 1 S1: providing an adapter board and an electrical chip to manufacture an electrical chip packaging structure unit, wherein the electrical chip is arranged on the front surface of the adapter board, and an electrical connection structure electrically connected to the electrical chip and located in the same plane is formed on the back surface of the adapter board;

[0059] Step 2 S2: Providing a substrate having a substrate groove and an optical chip to manufacture an optical chip packaging structure unit, wherein the optical chip is arranged in the substrate groove formed on the upper surface of the substrate, and the upper surface of the substrate is formed with electrical connection contacts that are electrically connected to the optical chip and are located in the same plane;

[0060] The third step S3: installing the electrical chip packaging structure unit onto the substrate to form a combined structure of the electrical chip packaging structure unit and the optical chip packaging structure unit, wherein the electrical chip packaging structure is electrically connected to the electrical connection contacts of the optical chip packaging structure unit via the electrical connection structure.

[0061] Thus, the present invention enables high-density integration of optical and electrical chips. The optical chip is embedded in a substrate, and the components of the electrical chip, arranged on an adapter board, are combined with the substrate, thereby achieving optoelectronic chip system integration. Because electrical connection is achieved through electrical connection structures and electrical connection contacts located on the same plane, there is no need to consider soldering pads or solder joints at different heights, thereby improving electrical connection quality, simplifying the connection process, and enhancing chip stability.

[0062] Furthermore, the 2.5D process enables high-density I / O integration of electronic chips, meeting high computing requirements and enabling powerful computing performance. The resulting structure allows for large-scale system integration of multiple optical chip modules and electronic modules. This structure enables line widths and spacings as small as 0.4µm.

[0063] It should be noted that the terms "first" and "second" are only used to distinguish steps, etc., and are not used to indicate the sequential relationship between the steps. For example, the present invention does not limit the order between the first step and the second step. The first step can be executed first and then the second step, or the second step can be executed first and then the first step. In the latter case, the first and second steps can be executed simultaneously.

[0064] Furthermore, if Figure 1 As shown, the chip system packaging manufacturing method according to the preferred embodiment of the present invention may further include at least one of the following steps:

[0065] Step 4 S4: providing an optical fiber coupler, and setting the optical fiber coupler on the combined structure of the electrical chip packaging structure unit and the optical chip packaging structure unit;

[0066] The fifth step S5: providing a heat dissipation plate, and covering the heat dissipation plate on the substrate.

[0067] Further specific embodiments of the present invention are described below with reference to the accompanying drawings.

[0068] first Figures 2 to 6 The process of manufacturing the electrical chip packaging structure unit of the chip system packaging manufacturing method according to the preferred embodiment of the present invention is described as follows.

[0069] First, if Figure 2 and Figure 3As shown, a temporary substrate 10 and an adapter plate 20 are provided, wherein an electrical connection structure 21 in the same plane as the conductive wiring in the adapter plate 20 is arranged on the back of the adapter plate 20, and an intermediate dielectric layer 22 is formed on the front of the adapter plate 20, and an electrical contact 23 electrically connected to the adapter plate 20 is formed on the surface of the intermediate dielectric layer 22; specifically, for example, as shown in the figure, the electrical connection structure 21 in the same plane has pads of the same height.

[0070] Then, if Figure 4 As shown, the transfer plate 20 is placed on the temporary substrate 10; preferably, a peelable layer 30 for protection and temporary bonding is placed between the temporary substrate 10 and the transfer plate 20. The transfer plate 20 is temporarily bonded to the temporary substrate 10 via the peelable layer 30. Preferably, the temporary substrate 10 is a glass substrate.

[0071] Afterwards, if Figure 5 As shown, the electric chip 40 is arranged on the front surface of the adapter board 20 through the conductive contacts 24 , and the conductive contacts 24 are in electrical contact with the electric contacts 23 .

[0072] Afterwards, if Figure 6 As shown, an underfill process forms an underfill 41 covering the conductive contacts 24. The underfill 41 is filled between the electrical chip 40 and the interposer 20 through a capillary effect. The underfill 41 protects the connection between the electrical chip 40 and the conductive contacts 24 from corrosion or damage, and also improves the mechanical properties and strength of the connection between the electrical chip 40, the conductive contacts 24, and the interposer 20.

[0073] Then, if Figure 7 As shown, a packaging layer 50 is formed to cover the front surface of the interposer 20, exposing the upper surface of the electrical chip 40. Generally, the packaging layer 50 is coated on the front surface of the interposer 20 and surrounds the electrical chip 40 located on the front surface of the interposer, and the upper surface of the electrical chip 40 is exposed through a grinding process.

[0074] Then, if Figure 8 As shown, the temporary substrate 10 is removed to expose the electrical connection structure 21 on the back side of the adapter plate 20 , wherein the electrical connection structure 21 is in the same plane.

[0075] The following combination Figures 9 to 11 The process of manufacturing an optical chip packaging structure unit of the chip system packaging manufacturing method according to the preferred embodiment of the present invention is described as follows.

[0076] like Figure 9 As shown, a substrate 60 is provided with a substrate groove 61 formed on the front surface;

[0077] like Figure 10As shown, adhesive 70 is arranged in the base groove 61;

[0078] like Figure 11 As shown, an optical chip 80 is placed on the adhesive 70 in the substrate groove 61. The optical chip 80 has a first electrical connection contact 91 and a second electrical connection contact 92 in the same plane. The substrate 60 has a third electrical connection contact 93 on the front surface of the optical chip 80 that is coplanar with the first and second electrical connection contacts 91, 92. This forms an optical chip package structure unit. The second electrical connection contact 92 is used to connect to the optical fiber. The first and third electrical connection contacts 91, 93 are used to connect the electrical chip package structure.

[0079] The following combination Figures 12 to 14 The process of the subsequent steps of the chip system packaging manufacturing method according to the preferred embodiment of the present invention is described as follows.

[0080] like Figure 12 As shown, the electrical chip package structure is electrically connected to the first and third electrical connection contacts 91, 93 of the optical chip package structure unit via the electrical connection structure 21. The gap between the adapter plate 20 and the optical chip package structure unit is filled with underfill 100. The underfill 100 between the adapter plate 20 and the optical chip package structure unit is made of the same material as the underfill 41 between the electrical chip 40 and the adapter plate 20. The underfill 100 between the electrical connection structure 21 protects the connection between the electrical chip package structure and the first and third electrical connection contacts 91, 93, preventing corrosion or damage. It also improves the mechanical properties of the electrical chip package structure, the first and third electrical connection contacts 91, 93, and the optical chip package structure unit (optical chip 80 and substrate 60), enhancing mechanical strength.

[0081] like Figure 13 As shown, the second electrical connection contact 92 is optically coupled with a fiber optic coupler 110 extending to the outside.

[0082] like Figure 14 As shown, a heat sink 130 is finally placed on the base 60, with the chip package structure positioned between the heat sink 130 and the base 60. Preferably, a thermally conductive adhesive layer 140 is positioned between the inner side of the heat sink 130 and the top of the chip package structure to secure the chip package structure. Adhesive (not shown) is also placed around the base 60 between the locations supporting the heat sink 130 and the heat sink 130.

[0083] Figure 15 Schematically shows Figure 14A schematic perspective view of the chip system package structure in FIG. To clearly illustrate the fiber coupler and electrical chip package structure, the heat sink and thermally conductive adhesive layer are not shown. Multiple fiber couplers 110 are provided, corresponding to multiple optical chips 80. Multiple fiber couplers 110 extend outward from four sides of the package structure.

[0084] This invention enables high-density integration of optical and electrical chips. The optical chip is embedded within a substrate, and the components of the electrical chip, arranged on an adapter board, are combined with the substrate, thereby achieving system integration of the optoelectronic chips. Because electrical connection is achieved through coplanar electrical connection structures and coplanar electrical connection contacts (first and third electrical connection contacts), there is no need to consider soldering pads or solder joints at different heights, improving electrical connection quality and simplifying the connection process. Furthermore, because the 2.5D process can be used to achieve high-density I / O integration with the electrical chip, high computational performance is achieved, resulting in a powerful computing architecture that supports large-scale system integration of multiple optical chip modules and electrical modules. This structure allows for a minimum line width and line spacing of 0.4um / 0.4um.

[0085] Reference below Figure 14 The chip packaging structure according to the preferred embodiment of the present invention is described below. The chip packaging structure according to the preferred embodiment of the present invention can be manufactured using the above method.

[0086] like Figure 14 As shown, the chip system packaging structure according to the preferred embodiment of the present invention includes:

[0087] An electrical chip packaging structural unit comprises: an adapter board 20 and an electrical chip 40 arranged on the front surface of the adapter board 20, wherein an electrical connection structure 21 electrically connected to the conductive wiring in the adapter board 20 is arranged on the back surface of the adapter board 20;

[0088] An optical chip packaging structure includes a substrate 60 having a substrate groove 61 formed on the front side, wherein an adhesive 70 is arranged in the substrate groove 61, an optical chip 80 is arranged in the substrate groove 61 and is flush with the surface of the substrate 60, the surface of the optical chip 80 has a first electrical connection contact 91 and a second electrical connection contact 92, and a third electrical connection contact 93 is formed on the surface of the substrate and is in the same plane as the first electrical connection contact 91 and the second electrical connection contact 92 of the optical chip 80.

[0089] The electrical chip packaging structure unit is arranged on the optical chip packaging structure, wherein the electrical connection structure 21 is electrically connected to the first electrical connection contact 91 of the optical chip and the third electrical connection contact 93 of the substrate 60. Figure 13As shown, the chip system package structure further includes an optical fiber coupler 110 extending to the outside and optically coupled to the second electrical connection contact 92. For example, the first electrical connection contact 91, the second electrical connection contact 92, and the third electrical connection contact 93 on the same plane have pads at the same height.

[0090] Typically, second electrical connection contacts 92 are arranged outside first electrical connection contacts 91. Specifically, second electrical connection contacts 92 are arranged on a side of optical chip 80 that is away from the center of substrate 60, or on a side of optical chip 80 that is closer to the periphery of the chip package structure. Second electrical connection contacts 92 are used to connect to a fiber optic coupler, facilitating the outward extension of the fiber optic coupler.

[0091] Preferably, if Figure 14 and Figure 15 As shown, the chip packaging structure further includes a covering heat dissipation plate 130 disposed on the substrate 60 .

[0092] like Figure 14 As shown, preferably, a thermally conductive adhesive layer 140 is arranged between the inner side of the heat dissipation plate 130 and the top of the electric chip packaging structure to fix the electric chip packaging structure.

[0093] Preferably, an encapsulation layer 50 is provided around the front surface of the adapter plate 20 and the electrical chip 40 located on the front surface of the adapter plate, exposing the upper surface of the electrical chip 40. A thermally conductive adhesive layer 140 is provided on the upper surface of the electrical chip 40, which facilitates heat transfer from the electrical chip 40 to the heat sink 130 through the thermally conductive adhesive layer 140, thereby reducing the heat transfer path and accelerating heat dissipation.

[0094] Preferably, an underfill 41 is provided between the electrical chip 40 and the front surface of the adapter board 20. The underfill 41 protects the connection between the electrical chip 40 and the conductive contacts 24 from corrosion or damage, and also improves the mechanical properties and strength of the electrical chip 40, the conductive contacts 24, and the adapter board 20.

[0095] Preferably, an underfill 100 is provided between the electrical chip packaging structure unit and the optical chip packaging structure. The underfill 100 is filled between the electrical connection structures 21. This provides protection for the connection between the electrical chip packaging structure and the first and third electrical connection contacts 91, 93, preventing corrosion or damage. Furthermore, it improves the mechanical properties of the electrical chip packaging structure, the first and third electrical connection contacts 91, 93, and the optical chip packaging structure unit (optical chip 80 and substrate 60), thereby enhancing mechanical strength.

[0096] In this embodiment, for example, the electrical chip 40 and the adhesive 70 may be a bare chip or a pre-packaged chip. Furthermore, the specific type of chip may be selected as needed, and the specific manufacturing process of the chip may also be selected as needed.

[0097] Figure 15 Schematically shows Figure 14 A schematic perspective view of the chip system package structure in FIG. To clearly illustrate the fiber coupler and electrical chip package structure, the heat sink and thermally conductive adhesive layer are not shown. In this embodiment, multiple fiber couplers 110 are provided, corresponding to multiple optical chips 80. The multiple fiber couplers 110 extend outward from the four sides of the package structure.

[0098] Preferably, the minimum line width and line spacing of the chip system package is 0.4um.

[0099] Preferably, an intermediate dielectric layer 22 is formed on the front of the adapter board, and an electrical contact 23 electrically connected to the adapter board is formed on the surface of the intermediate dielectric layer 22; the electrical chip 40 is arranged on the front of the adapter board through the conductive contact, and the conductive contact 24 is in electrical contact with the electrical contact 23.

[0100] This invention enables high-density integration of optical and electrical chips. The optical chip is embedded within a substrate, and the components of the electrical chip, arranged on an adapter board, are combined with the substrate, thereby achieving system integration of the optoelectronic chips. Because electrical connection is achieved through coplanar electrical connection structures and coplanar electrical connection contacts (first and third electrical connection contacts), there is no need to consider soldering pads or solder joints at different heights, improving electrical connection quality and simplifying the connection process. Furthermore, because the 2.5D process can be used to achieve high-density I / O integration with the electrical chip, high computational performance is achieved, resulting in a powerful computing architecture that supports large-scale system integration of multiple optical chip modules and electrical modules. This structure allows for a minimum line width and line spacing of 0.4um / 0.4um.

[0101] It should be noted that, unless otherwise specified, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0102] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A chip system packaging manufacturing method, characterized in that include: Step 1: Providing an adapter board and an electrical chip, and manufacturing an electrical chip packaging structure unit, wherein the electrical chip is arranged on the front surface of the adapter board, and an electrical connection structure electrically connected to the electrical chip and located in the same plane is formed on the back surface of the adapter board; wherein manufacturing the electrical chip packaging structure unit includes: First, a temporary substrate and an adapter plate are provided. The back of the adapter plate is provided with an electrical connection structure that is coplanar and electrically connected to the conductive wiring in the adapter plate. The front of the adapter plate is provided with an intermediate dielectric layer, and the surface of the intermediate dielectric layer is provided with electrical contacts that are electrically connected to the adapter plate. Subsequently, the adapter plate is arranged on the temporary base plate; Thereafter, the electrical chip is arranged on the front surface of the adapter plate through the conductive contacts, and the conductive contacts are in electrical contact with the electrical contacts; Afterwards, an underfill process is performed to form an underfill glue covering the conductive contacts; wherein the underfill glue is filled between the electrical chip and the adapter board through a capillary effect; Subsequently, a packaging layer is formed to cover the front surface of the adapter board, exposing the upper surface of the electrical chip; Then, the temporary substrate is removed to expose the electrical connection structure on the back side of the adapter plate, wherein the electrical connection structure is in the same plane; Step 2: Providing a substrate having a substrate groove and an optical chip to manufacture an optical chip packaging structure unit, wherein the optical chip is arranged in the substrate groove formed on the upper surface of the substrate, and the upper surface of the substrate is formed with electrical connection contacts that are electrically connected to the optical chip and are located in the same plane; The third step: installing the electrical chip packaging structure unit onto the substrate to form a combined structure of the electrical chip packaging structure unit and the optical chip packaging structure unit, wherein the electrical chip packaging structure is electrically connected to the electrical connection contacts of the optical chip packaging structure unit via the electrical connection structure.

2. The chip system packaging manufacturing method according to claim 1, characterized in that Also includes: The fourth step is to provide a fiber optic coupler, and to set the fiber optic coupler on the combined structure of the electrical chip packaging structure unit and the optical chip packaging structure unit.

3. The chip system packaging manufacturing method according to claim 1 or 2, characterized in that Also includes: Step 5: Provide a heat dissipation plate and cover the heat dissipation plate on the substrate.

4. The chip system packaging manufacturing method according to claim 1, characterized in that: Manufacturing optical chip packaging structure units include: providing a substrate having a substrate groove formed on a front surface; disposing adhesive in the groove of the base; An optical chip is arranged on the adhesive in the substrate groove, the optical chip having a first electrical connection contact and a second electrical connection contact in the same plane, and a third electrical connection contact coplanar with the first electrical connection contact and the second electrical connection contact on the surface of the optical chip on the front side, thereby forming an optical chip packaging structural unit.

5. The chip system packaging manufacturing method according to claim 4, characterized in that Also includes: The electrical chip packaging structure is electrically connected to the first electrical connection contact and the third electrical connection contact of the optical chip packaging structure unit through the electrical connection structure, wherein the gap between the adapter plate and the optical chip packaging structure unit is filled with bottom filling glue; The second electrical connection contact is optically coupled and provided with an optical fiber coupler extending to the outside; A heat dissipation plate is arranged on the base, and the electric chip packaging structure is arranged between the heat dissipation plate and the base.

6. The chip system packaging manufacturing method according to claim 1, characterized in that: A peelable layer for protection and adhesion is arranged between the temporary substrate and the adapter plate.

7. The chip system packaging manufacturing method according to claim 6, characterized in that: The interposer is temporarily bonded to the temporary substrate via a peelable layer.

8. The chip system packaging manufacturing method according to claim 4, characterized in that: The packaging layer covers the upper surface of the electric chip, and the upper surface of the electric chip is exposed through a grinding process.

9. The chip system packaging manufacturing method according to claim 5, characterized in that: The second electrical connection contact is used to connect to the optical fiber coupler, and the first electrical connection contact and the third electrical connection contact are used to connect to the electrical chip packaging structure.

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