Signal evaluation method, apparatus and electronic device

Abstract

The present disclosure provides a signal evaluation method, device and electronic equipment. The method comprises: training a memory system, and writing first data into the memory corresponding to the trained memory system; setting one of a first parameter and a second parameter as an optimal read reference voltage, and setting the other as an optimal read offset time; adjusting the first parameter and the second parameter based on a first preset offset value and a second preset offset value, reading the memory to obtain second data, determining two second parameter boundary values of a target command / address signal under each first parameter and two first parameter boundary values of the first parameter according to the second data and the first data, and generating an eye diagram of the target command / address signal according to the two second parameter boundary values under each first parameter and the two first parameter boundary values of the first parameter. The embodiments of the present disclosure can obtain a complete digital eye diagram of the CA signal in the case of a set of optimal signal parameters that can run on the system.

Description

Technical Field

[0001] This disclosure relates to the field of information technology, and more specifically, to a signal evaluation method, apparatus, and electronic device.

[0002] First technique

[0003] An eye diagram is a schematic representation of a signal formed by superimposing the waveforms of each symbol obtained from scanning using the persistence effect of an oscilloscope. Eye diagrams can be used to observe the effects of inter-symbol interference and noise, providing overall signal characteristics to help estimate the quality of the system. Eye diagram analysis is the core of signal integrity analysis in high-speed interconnect systems. Figure One Eye diagrams can generally be divided into two types: analog eye diagrams and digital eye diagrams. The eye diagram of the CA signal (Command / Address) is an important type of digital eye diagram, used to reflect the signal quality of the Command / Address signal in DRAM. The quality of this signal directly affects whether the instructions given to the DRAM memory by the system will be executed correctly. Therefore, obtaining the eye diagram of the CA signal is crucial for analyzing memory performance.

[0004] Currently, the method for obtaining the eye diagram of CA signals is usually to use software to adjust different CA Vref voltages during the Command Bus Training (CBT) phase of DRAM initialization to find the left and right boundaries of each CA signal and the sampling point to form the eye diagram of each CA signal. Then, based on the eye diagram of the CA signal, the read point with the maximum signal integrity margin (i.e. the optimal read result) is found. This read point includes the optimal read reference voltage and the optimal read offset time.

[0005] Currently, some memory systems train the CA signal in hardware during the CBT (Completely Bit-Based Training) phase of memory initialization. In this training method, the memory controller provides a set of parameters that optimize system operation through its internal processes, but it cannot provide information about the entire training process or the digital eye diagram of the CA signal. However, the eye diagram of the CA signal is a key indicator for analyzing signal integrity during memory evaluation. Therefore, obtaining the eye diagram of the CA signal from a hardware-trained memory system is both necessary and valuable.

[0006] It should be noted that the information disclosed in the first technical section above is only used to enhance the understanding of the first aspect of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] The purpose of the present disclosure is to provide a signal evaluation method, device and electronic equipment, which at least partially overcomes the problem of being unable to obtain the eye diagram of the CA signal of the hardware-trained memory system due to the limitations and defects of the related art.

[0008] According to a first aspect of the embodiments of the present disclosure, a signal evaluation method is provided, comprising: training a memory system, and writing first data to the memory corresponding to the trained memory system; obtaining an optimal read reference voltage and an optimal read offset time of a target command / address signal, setting one of a first parameter and a second parameter as the optimal read reference voltage and the other as the optimal read offset time; adjusting the first parameter and the second parameter based on a first preset offset value and a second preset offset value, reading the memory based on the first parameter and the second parameter to obtain second data, determining two second parameter boundary values of the target command / address signal under each first parameter and two first parameter boundary values of the first parameter according to the second data and the first data, wherein the first preset offset value is an offset value of the first parameter, and the second preset offset value is an offset value of the second parameter; and generating an eye diagram of the target command / address signal according to the two second parameter boundary values under each first parameter and the two first parameter boundary values of the first parameter.

[0009] In an exemplary embodiment of the present disclosure, the reading of the memory based on the first parameter and the second parameter to obtain second data, and the determination of two second parameter boundary values of the target command / address signal under each first parameter and two first parameter boundary values of the first parameter according to the second data and the first data comprise: iteratively adjusting the second parameter according to the second preset offset value, iteratively reading the second data, and determining two second parameter boundary values of the target command / address signal under each first parameter according to the second data and the first data; when the two second parameter boundary values of the first parameter do not satisfy a preset condition, adjusting the first parameter according to the first preset offset value to determine two second parameter boundary values corresponding to each first parameter; and when the two second parameter boundary values of the first parameter satisfy the preset condition, determining the current first parameter as the first parameter boundary value.

[0010] In an example embodiment of the present disclosure, the adjusting the second parameter according to the second preset offset value, iteratively reading the second data, and determining two second parameter boundary values of the target command / address signal under each first parameter according to the second data and the first data comprises: adjusting the second parameter according to the second preset offset value; setting a sampling point of the target command / address signal as the first parameter and the second parameter, reading the memory, and obtaining the second data; when the second data is equal to the first data, returning to adjust the second parameter according to the second preset offset value; when the second data is not equal to the first data, recording the current second parameter as one second parameter boundary value under the first parameter; when the first parameter corresponds to one second parameter boundary value, reversing the second preset offset value and returning to adjust the second parameter according to the second preset offset value; and when the first parameter corresponds to two second parameter boundary values, recording two second parameter boundary values of the target command / address signal under the first parameter.

[0011] In an example embodiment of the present disclosure, when the two second parameter boundary values of the first parameter do not satisfy the preset condition, the adjusting the first parameter according to the first preset offset value to determine two second parameter boundary values corresponding to each first parameter comprises: after adjusting the first parameter according to the first preset offset value, returning to iteratively adjust the second parameter according to the second preset offset value to determine two second parameter boundary values of the target command / address signal under the adjusted first parameter.

[0012] In an example embodiment of the present disclosure, when the two second parameter boundary values of the first parameter satisfy the preset condition, the determining the current first parameter as the first parameter boundary value comprises: after determining the current first parameter as the first parameter boundary value, if there is one first parameter boundary value, reversing the first preset offset value and returning to adjust the first parameter according to the first preset offset value to determine two second parameter boundary values corresponding to the first parameter; and if there are two first parameter boundary values, recording two first parameter boundary values of the target command / address signal and two second parameter boundary values of the target command / address signal under each first parameter.

[0013] In an example embodiment of the present disclosure, the preset condition comprises that a difference between the two second parameter boundary values under the first parameter is less than or equal to a preset threshold.

[0014] In an exemplary embodiment of the present disclosure, the first parameter is a read reference voltage, the second parameter is a read offset time, the first preset offset value is a reference voltage offset value, and the second preset offset value is a read time offset value.

[0015] In an exemplary embodiment of the present disclosure, the first parameter is a read offset time, the second parameter is a read reference voltage, the first preset offset value is a read time offset value, and the second preset offset value is a reference voltage offset value.

[0016] In an exemplary embodiment of the present disclosure, the first preset offset value is a positive number or a negative number, and the second preset offset value is a positive number or a negative number.

[0017] In an exemplary embodiment of the present disclosure, after determining any of the first parameter boundary value and the second parameter boundary value, the memory system is retrained, and the first data is written.

[0018] In an exemplary embodiment of the present disclosure, the write address of the first data is such that the target command / address signal appears as high voltage and low voltage alternately in time domain.

[0019] In an exemplary embodiment of the present disclosure, the first data is such that the data written in each address is different.

[0020] In an exemplary embodiment of the present disclosure, after obtaining the eye diagram of the target command / address signal, a command / address signal is replaced for measurement to obtain the eye diagrams of all command / address signals in the memory.

[0021] According to a second aspect of the present disclosure, an electronic device is provided, comprising: a memory; and a processor coupled to the memory, the processor being configured to execute a method as described in any of the above aspects based on instructions stored in the memory.

[0022] According to a third aspect of the present disclosure, a computer readable storage medium is provided, having a program stored thereon, the program being executed by a processor to implement a signal evaluation method as described in any of the above aspects.

[0023] The data read test of the embodiment of the present disclosure is based on the step iteration of two preset offset values of the optimal read reference voltage and the optimal read offset time of the CA signal (target command / address signal), the eye diagram data of the CA signal can be obtained according to the comparison of the read data (second data) and the written data (first data), and then the effective analysis and control of the signal are realized. In the case that the memory controller trains the CA signal by the hardware mode and only gives a set of optimal parameters that can run on the system, the complete digital eye diagram of the CA signal can also be obtained. In addition, the barrier that the eye diagram of the CA signal must be obtained in the CBT stage is broken, and the eye diagram of the CA signal can also be obtained after the system training is completed.

[0024] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0026] Figure 1 is a flowchart of the signal evaluation method in the exemplary embodiment of the present disclosure.

[0027] Figure 2 is a process schematic diagram of the normal operation of the memory system in one embodiment of the present disclosure.

[0028] Figure 3 is a schematic diagram of the digital eye diagram in one embodiment of the present disclosure.

[0029] Figure 4 is a sub-flowchart of step S3 in one embodiment of the present disclosure.

[0030] Figure 5 is a schematic diagram of the internal iteration loop of step S3 in one embodiment of the present disclosure.

[0031] Figure 6 is a schematic diagram of the determination of the boundary value in one embodiment of the present disclosure.

[0032] Figure 7 is a schematic diagram of the determination of the boundary value in another embodiment of the present disclosure.

[0033] Figure 8 is a complete flowchart of the signal evaluation process in one embodiment of the present disclosure.

[0034] Figure 9is a block diagram of an electronic device in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Example implementations are now described in greater detail in conjunction with the figures. The example implementations, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example implementations to those skilled in the art. The features, structures, or characteristics described can be combined in one or more implementations. In the following description, numerous specific details are provided, such as examples of programming, software modules, user selections, etc., to provide a thorough understanding of the example implementations. One skilled in the relevant art will recognize, however, that the implementations can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. Some features, structures, or characteristics can be described as being implemented over one or more entities, portions of which can be implemented as hardware, software, or firmware. In other instances, some features can be implemented using software functioning as a standalone software program, or as part of a larger software program, such as an operating system. Examples implementations are described in sufficient detail to enable those skilled in the art to practice the implementations, and it will be apparent that other implementations can be employed, and that logical, arithmetic, and electrical design choices can be made without departing from the scope of the implementations. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the implementations are defined only by the appended claims.

[0036] In addition, the accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain principles of the present disclosure. In the drawings:

[0037] Example implementations of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0038] Figure 1 is a flowchart of a signal evaluation method in an exemplary embodiment of the present disclosure.

[0039] Referring to Figure 1 The signal evaluation method 100 can include:

[0040] At step S1, a memory system is trained, and first data is written to a memory corresponding to the trained memory system;

[0041] At step S2, an optimal read reference voltage and an optimal read offset time of a target command / address signal are obtained, one of the first parameter and the second parameter is set as the optimal read reference voltage, and the other is set as the optimal read offset time;

[0042] Step S3, adjusting the first parameter and the second parameter based on the first preset offset value and the second preset offset value, reading the second data from the memory based on the first parameter and the second parameter, determining two second parameter boundary values of the target command / address signal under each first parameter and two first parameter boundary values of the first parameter according to the second data and the first data, wherein the first preset offset value is an offset value of the first parameter, and the second preset offset value is an offset value of the second parameter;

[0043] Step S4, generating an eye diagram of the target command / address signal according to the two second parameter boundary values under each first parameter and the two first parameter boundary values of the first parameter.

[0044] The data read test of the embodiment of the present disclosure is based on the optimal read reference voltage and the optimal read offset time of the CA signal, two preset offset values, and step iteration, and the eye diagram data of the CA signal can be obtained according to the comparison between the read data (second data) and the written data (first data), and then effective analysis and control of the signal can be realized. In the case that the memory controller trains the CA signal by a hardware method and only gives a set of optimal parameters that can run on the system, the complete digital eye diagram of the CA signal can also be obtained. In addition, the barrier that the eye diagram of the CA signal must be obtained in the CBT stage is broken, and the eye diagram of the CA signal can also be obtained after the system training is completed.

[0045] Next, each step of the signal evaluation method 100 is described in detail.

[0046] In step S1, the memory system is trained, and the first data is written into the memory corresponding to the trained memory system.

[0047] The method of the embodiment of the present disclosure is based on the premise that the memory system can work normally.

[0048] Figure 2 is a process diagram of the normal operation of the memory system in one embodiment of the present disclosure.

[0049] Reference Figure 2 The process of the normal operation of the memory system can be divided into: 1. power on / initialization of the system; 2. training of the DRAM controller to the DRAM; 3. the DRAM training is completed, and the memory can perform normal read / write.

[0050] Once the memory system is functioning correctly, meaning it can perform normal read and write operations, the first data is written to the memory. This first data can also be called background data, and its type can be, for example, pseudo-random data. The principle of pseudo-random data is to ensure that the data written to each address is unique. By writing pseudo-random data to the memory, it can be guaranteed that if an error occurs in the CA signal, causing an error in the memory address information parsing, the data read from the erroneous address will be different from the data at the correct address, making it easier to determine whether a read error has occurred. In other words, the first data ensures that the data written to each address is different.

[0051] By writing the first data to the memory after training, it can be ensured that the first data is written correctly, so that the reading result can be used to determine whether a reading error has occurred during subsequent reading processes.

[0052] In step S2, the optimal read reference voltage and optimal read offset time of the target command / address signal are obtained, and one of the first parameter and the second parameter is set as the optimal read reference voltage and the other is set as the optimal read offset time.

[0053] Figure 3 This is a schematic diagram of a digital eye diagram in one embodiment of the present disclosure.

[0054] refer to Figure 3 In the digital eye diagram of Bit0, there are horizontal axes representing the read offset time and vertical axes representing the read reference voltage. The horizontal axis is in milliseconds (ms), and the vertical axis is in mV. To maximize the display of the eye diagram, the horizontal and vertical coordinates of the intersection points of the axes can be non-zero. The digital eye diagram 31 has an upper boundary 311, a lower boundary 312, a left boundary 313, a right boundary 314, and an optimal read signal point A. The optimal read signal point A has coordinates (980, 147.6). This means that the Bit0 signal has the best signal quality when the read offset time is 980ms and the read reference voltage is 147.6mV. Here, 980ms is also called the optimal read offset time, and 147.6mV is also called the optimal read reference voltage.

[0055] Depend on Figure 3 It can be seen that reading the signal at the optimal signal reading point A maximizes the signal integrity margin. Ideally, point A should be located in the center of the digital eye diagram 31. However, since the shape of the digital eye diagram is usually not a perfectly symmetrical figure, point A may not be located in the center of the digital eye diagram 31, for example... Figure 3 The situation.

[0056] After the memory system trains the CA signal through hardware training, it ultimately only provides information on the optimal read signal point A. This allows the CA signal to be read at this optimal read signal point A during subsequent operation (sampling the CA signal at the optimal read signal point A), maximizing the fault tolerance of the CA signal and ensuring its optimal quality. However, during memory evaluation, a complete signal eye diagram of the CA signal is required, which is the purpose of this embodiment. Therefore, in step S2, the information on the optimal read signal point A corresponding to the CA signal under test can be directly obtained, thereby directly obtaining the optimal read offset time and optimal read reference voltage corresponding to the CA signal.

[0057] Next, one of the first and second parameters is set to the optimal read reference voltage, and the other is set to the optimal read offset time. The first and second parameters are respectively one of the horizontal and vertical coordinates of the sampling point of the target command / address signal.

[0058] In one embodiment, the first parameter is the optimal read reference voltage, and the second parameter is the optimal read offset time. Then, according to... Figure 3 The rule is that the sampling point of the target command / address signal is set to (second parameter, first parameter). In another embodiment, the first parameter can also be the optimal read offset time, and the second parameter can be the optimal read reference voltage, then according to... Figure 3 As shown in the rule, the sampling point of the target command / address signal is set to (first parameter, second parameter).

[0059] In step S3, the first parameter and the second parameter are adjusted based on the first preset offset value and the second preset offset value. The memory is read to obtain second data based on the first parameter and the second parameter. The target command / address signal is determined according to the second data and the first data, along with two second parameter boundary values ​​and two first parameter boundary values ​​for each of the first parameters. The first preset offset value is the offset value of the first parameter, and the second preset offset value is the offset value of the second parameter.

[0060] In this embodiment, regardless of the type of the first and second parameters, or whether the first or second parameter is adjusted first, multiple boundary values ​​for determining the signal eye diagram can be obtained. The process of obtaining boundary values ​​is illustrated below using the example of adjusting the second parameter first and then the first parameter.

[0061] Figure 4 This is a sub-flowchart of step S3 in one embodiment of this disclosure.

[0062] refer to Figure 4 In one embodiment, step S3 may include:

[0063] Step S31, adjusting the second parameter according to the second preset offset value, iteratively reading the second data, and determining two second parameter boundary values of the target command / address signal under each first parameter according to the second data and the first data;

[0064] Step S32, when the two second parameter boundary values of the first parameter do not satisfy a preset condition, adjusting the first parameter according to the first preset offset value to determine two second parameter boundary values corresponding to each first parameter.

[0065] Step S33, when the two second parameter boundary values of the first parameter satisfy the preset condition, determining the current first parameter as the first parameter boundary value.

[0066] Figure 4 The embodiment shown is an iterative reading data process to iteratively determine second parameter boundary values corresponding to multiple first parameters. Figure 4 The step of the embodiment shown also provides an iterative reading process.

[0067] In an embodiment, step S31 can include: adjusting the second parameter according to the second preset offset value; setting a sampling point of the target command / address signal as the first parameter and the second parameter, reading the memory to obtain the second data; when the second data is equal to the first data, returning to adjust the second parameter according to the second preset offset value; when the second data is not equal to the first data, recording the current second parameter as a second parameter boundary value under the first parameter; when the first parameter corresponds to one second parameter boundary value, reversing the second preset offset value and returning to adjust the second parameter according to the second preset offset value; when the first parameter corresponds to two second parameter boundary values, recording the two second parameter boundary values of the target command / address signal under the first parameter.

[0068] Step S32 can include: after adjusting the first parameter according to the first preset offset value, returning to iteratively adjust the second parameter according to the second preset offset value to determine two second parameter boundary values of the target command / address signal under the adjusted first parameter.

[0069] Step S33 can include: after determining the current first parameter as the first parameter boundary value, if there is one first parameter boundary value, reversing the first preset offset value, returning to adjust the first parameter according to the first preset offset value, determining two second parameter boundary values corresponding to the first parameter; if there are two first parameter boundary values, recording the two first parameter boundary values of the target command / address signal and the two second parameter boundary values of the target command / address signal under each first parameter.

[0070] The following uses Figure 5 to more clearly illustrate the iteration process inside step S3.

[0071] Figure 5 is a schematic diagram of the internal iteration loop of step S3 in one embodiment of the present disclosure.

[0072] Figure 5 In the embodiment shown, for convenience of illustration, it is assumed that in step S2, the first parameter is set to the first optimal value and the second parameter is set to the second optimal value, wherein one of the first optimal value and the second optimal value is the optimal read offset time and the other is the optimal read reference voltage.

[0073] Referring to Figure 5 , in one embodiment, the iteration loop process inside step S3 can include:

[0074] Step S501, train the system and write the first data.

[0075] Step S502, adjust the second parameter according to the second preset offset value.

[0076] Step S503, set the sampling points of the target command / address signal to the first parameter and the second parameter, read the memory system, and obtain the second data.

[0077] Step S504, determine whether the second data is equal to the first data, if not, return to step S502; if yes, proceed to step S505.

[0078] Step S505, record the current second parameter as a second parameter boundary value of the current first parameter.

[0079] Step S506, determine whether the first parameter has two second parameter boundary values, if not, proceed to step S507, set the second parameter to the second optimal value and reverse the second preset offset value, and then return to step S501; if yes, proceed to step S508. The loop iteration of steps S501-S507 corresponds to step S31.

[0080] Step S508, it is judged whether the two second parameter boundary values corresponding to the first parameter satisfy the preset condition, if not, step S509 is entered, the first parameter is adjusted according to the first preset offset value, and then step S501 is returned to determine the two second parameter boundary values corresponding to the adjusted first parameter, if yes, step S510 is entered.

[0081] Step S510, the current first parameter is recorded as a first parameter boundary value.

[0082] Step S511, it is judged whether there are two first parameter boundary values, if yes, step S4 is entered, if not, step S512 is entered, the first parameter is set to the first optimal value, the first offset value is reversed, then step S509 is returned, and then step S501 is returned. The loop iteration of steps S508 to S512 corresponds to step S33.

[0083] So far, the two second boundary parameter values corresponding to each first parameter are determined, and the first parameter boundary value is determined, and all the boundary values required for generating an eye diagram are obtained.

[0084] From Figure 5 It can be concluded that after adjusting the first parameter or the second parameter each time, before reading the second data, the memory system needs to be retrained in step S501 to write the first data. This is to avoid the occurrence of boundary values leading to errors in the first data, so after any boundary value (first parameter boundary value or second parameter boundary value) occurs each time, the memory system needs to be retrained to correctly write the first data, to ensure the accuracy of the subsequent judgment on the read second data.

[0085] In an embodiment of the present disclosure, the first preset offset value and the second preset offset value can both be positive or negative. When the first preset offset value is positive, the first parameter is adjusted according to the first preset offset value, that is, the first parameter is increased, and the increase step is the first preset offset value; when the first preset offset value is negative, the first parameter is adjusted according to the first preset offset value, that is, the first parameter is decreased, and the decrease step is the first preset offset value. The second preset offset value is the same.

[0086] Figure 6 is a schematic diagram for determining boundary values in an embodiment of the present disclosure.

[0087] Referring to Figure 6 , let the first parameter be the read reference voltage Vref, and the second parameter be the read offset time Tbias. The optimal read reference voltage is V0, the optimal read offset time is T0, the first preset offset value is ΔV, and the second preset offset value is ΔT. The first preset offset value and the second preset offset value are both positive numbers.

[0088] Then, in step S2, Tbias = To and Vref = Vo are set. In step S3, each time the second parameter is adjusted according to the second preset offset value before the second parameter boundary value corresponding to Vo is detected, Tbias = Tbias + ΔT, the sampling point of the target command / address signal is set to (Tbias, Vo), the second data is read, and if the second data is equal to the first data, Tbias = Tbias + ΔT is again set, and the current second parameter is increased by ΔT. The second data is iteratively read until the second data is not equal to the first data, indicating that the CA signal address resolution of the memory is incorrect, and the current Tbias is set to the maximum Tbias boundary value Tbiasl (the second parameter boundary value) corresponding to Vo.

[0089] After the second parameter boundary value corresponding to Vo is detected, the second parameter is restored to the second optimal value, the second preset offset value is reversed, i.e., ΔT is multiplied by -1, and then each time the second parameter is adjusted according to the second preset offset value, Tbias = Tbias - ΔT (here, ΔT is the original positive number) is set. In this way, when the second data is not equal to the first data, the corresponding Tbias is set to the minimum Tbias boundary value Tbias2 corresponding to Vo.

[0090] Next, the first parameter Vref is adjusted according to the first preset offset value ΔV, i.e., Vref = Vref + ΔV. Returning to the above steps, the sampling point of the target command / address signal is set to (Tbias, Vref), Tbias is iteratively adjusted, and the maximum Tbias boundary value Tbiasl and the minimum Tbias boundary value Tbias2 corresponding to the current Vref are determined according to whether the second data is equal to the first data, until the maximum Tbias boundary value and the minimum Tbias boundary value corresponding to one Vref meet the preset condition, and the current Vref is set to the maximum Vref boundary value Vrefl (i.e., the first parameter boundary value). Next, the first parameter is restored to the first optimal value, the first preset offset value is reversed, i.e., ΔV is multiplied by -1, and each time the first parameter is adjusted according to the first preset offset value, Vref = Vref - ΔV (here, ΔV is the original positive number) is set. In this way, Vref can be gradually decreased, and the maximum Tbias boundary value and the minimum Tbias boundary value corresponding to each Vref can be determined. Until the maximum Tbias boundary value and the minimum Tbias boundary value corresponding to one Vref meet the preset condition, the current Vref is set to the minimum Vref boundary value Vref2 (i.e., the other first parameter boundary value).

[0091] The same principle applies when the first parameter is read bias time Tbias and the second parameter is read reference voltage Vref. In addition, the first preset offset value and the second preset offset value can also be negative numbers, and the principle is as described above, which is not repeated here.

[0092] In the embodiments of the present disclosure, the preset condition for determining whether the first parameter is a first parameter boundary value can be, for example, that the difference between the two second parameter boundary values corresponding to the first parameter is less than or equal to a preset threshold.

[0093] For example, if the first parameter is read reference voltage and the second parameter is read bias time, if the read reference voltage has reached a certain critical value, resulting in the inability to accurately transmit information, then no matter whether the read bias time is increased or decreased based on the optimal read bias time, the read second data cannot be equal to the first data. At this time, the increased read bias time is a second parameter boundary value, which is only one first preset offset value greater than the optimal read bias time, and the decreased read bias time is another second parameter boundary value, which is only one first preset offset value less than the optimal read bias time. The difference between the two second parameter boundary values is equal to two first preset offset values. The above-mentioned preset threshold can be set to twice the first preset offset value. When the difference between the two second parameter boundary values corresponding to one read reference voltage is less than or equal to two first preset offset values, it can be determined that no matter how the read bias time is adjusted, the second data cannot be equal to the first data. At this time, the current read reference voltage can be set as the boundary value of the read reference voltage in the current direction (for example, the positive direction of the Y-axis), that is, the upper boundary of the eye diagram. The determination of the boundary value of the read reference voltage in the opposite direction of the current direction (for example, the negative direction of the Y-axis) is the same as above, and only the first preset offset value is reversed, that is, the read reference voltage is adjusted in the opposite direction, to obtain the lower boundary of the eye diagram.

[0094] In another embodiment, when the first parameter is equal to the preset threshold, for example, Figure 3 Vref reaches a certain value, Vref is directly set as the first parameter boundary value to improve the efficiency of eye diagram acquisition.

[0095] In other embodiments of the present disclosure, the first parameter can also be set as read bias time, and the second parameter can be set as read reference voltage.

[0096] Figure 7 is a schematic diagram for determining the boundary value in another embodiment of the present disclosure.

[0097] Reference Figure 7In another embodiment, the maximum read reference voltage and the minimum read reference voltage (upper and lower boundaries of the eye diagram) corresponding to each read offset time can also be determined by adjusting the read reference voltage up and down based on different read offset times, and then the first parameter boundary value and the second parameter boundary value are obtained. Figure 7 The process of determining the boundary values is similar to Figure 6 The embodiments shown are similar, and the disclosure will not be repeated here.

[0098] In step S4, the eye diagram of the target command / address signal is generated according to the two second parameter boundary values under each first parameter, and the two first parameter boundary values of the first parameter.

[0099] In the embodiments of the disclosure, after obtaining the eye diagram of the target command / address signal, the command / address signal can be replaced for measurement to obtain the eye diagrams of all command / address signals in the memory system.

[0100] In one embodiment of the disclosure, the write address of the first data causes the target command / address signal to exhibit high voltage and low voltage alternately in the time domain.

[0101] The basic structure of the DRAM address is as follows:

[0102] 1. Channel: Each channel can correspond to multiple chip particles (die), and each channel has its own chip selection signal (Chip Select, CS). The chip selection signal CS indicates the selection state of a certain chip particle in the channel to determine the target chip particle for current testing.

[0103] 2. Bank: Multiple banks exist in each chip particle, and the target bank for current testing can be specified by address data BA0, BA1, and BA2.

[0104] 3. Row: The target row for current testing can be specified by address data R0-R15.

[0105] 4. Column: The target column for current testing can be specified by address data C0-C9.

[0106] Table 1 shows the correspondence between the address relationship contained in each CA signal in the LPDDR4 truth table and the read command.

[0107] Table 1

[0108]

[0109] Referring to Table 1, in the LPDDR4, each chip grain has six CA signal lines CA0-CA5, and the addresses of the currently operated storage units are selected by setting different data on different CA signal lines at the same time. For example, when the ACT-1 signal is sent, if the CS signal corresponding to the currently selected target chip grain is H, the signals on the CA0-CA5 signal lines at the same time are set to H, L, R12, R13, R14, R15, and are set to rising edge effective (CK_tedge=R1). If the CS signal corresponding to the currently selected target chip grain is L, the signals on the CA0-CA5 signal lines at the same time are set to BA0, BA1, BA2, R16, R10, R11, and are set to falling edge effective (CK_t edge=R2).

[0110] Other signals, such as ACT-2, WR-1, RD-1, CAS-2, and the like command signals are set in this way.

[0111] In the process of obtaining the CA digital eye diagram, the main process is the data read (Read) process. Taking the LPDDR4 as an example, the address relationship contained in each CA signal in the LPDDR4 truth table corresponding to these commands is shown in Table 1.

[0112] The address information represented by each CA in the Read process is as follows:

[0113] CA0 represents the address information of BA0, R17, R0, and C2.

[0114] CA1 represents the address information of BA1, R18, R1, and C3.

[0115] CA2 represents the address information of BA2, R12, R6, R2, and C4.

[0116] CA3 represents the address information of R13, R16, R7, R3, and C5.

[0117] CA4 represents the address information of R14, R10, R8, R4, C6, and C9.

[0118] CA5 represents the address information of R15, R11, R9, R5, C8, and C7.

[0119] During a read / write operation, control commands and address commands are output via the aforementioned command signals. For example, the instruction sending sequence for the Read command mainly includes: Activate1, Activate2, Read-1, CAS2. If the CS signal corresponding to the currently selected target chip is H, then during the transmission of the read command, signals H, R17, L, and L are sequentially presented on the CA0 signal line; if the CS signal corresponding to the currently selected target chip is L, then signals BA0, R0, BA0, and C2 are sequentially presented on the CA0 signal line during the transmission of the read command.

[0120] In order to improve the differentiation between different signals in the time domain of the target command / address signal line, in one embodiment of this disclosure, the write address of the first data causes the target command / address signal to exhibit alternating high and low voltages in the time domain.

[0121] For example, during CA0 testing, when selecting the data write address, BA0 can be set to 0, and both R0 and C2 can be set to 1. Therefore, if the CS signal corresponding to the currently selected target chip is L, during the read command transmission, the CA0 signal line will sequentially display the signals BA0, R0, BA0, and C2, exhibiting a high-low alternating timing state of 0, 1, 0, 1. If the Tbias of the sampling point is too large, and the previous or next signal is sampled, it can be immediately identified through a completely different level, avoiding mistaking the performance of the incorrectly sampled previous or next signal as the performance of the sampled target signal.

[0122] When testing different CA signals, one can... Figure 7 The diagram shows that the data write address is adjusted so that when the target command / address signal is sampled (i.e. during the process of sending the read data command), it appears as alternating high and low levels in the time domain.

[0123] In one embodiment of this disclosure, the signal evaluation process may include:

[0124] Step 1: The system is powered on, the controller trains the DRAM, and after training is completed, the memory can be read and written normally.

[0125] Step 2: Set the DRAM address information: channel information (target channel), CS data (target chip), CA (target command / address signal) and other values.

[0126] Step 3: Calculate the relevant address space based on the set DRAM address information.

[0127] Step 4: Write the first data into the address space obtained in Step 3.

[0128] Step 5, set the Vref voltage value of the CA signal, write into the system.

[0129] Step 6, read the optimal read time offset value (i.e. optimal Tbias) of the target command / address signal set in step 2.

[0130] Step 7, write into the system the offset value obtained in step 6 plus a fixed offset (preset read time offset value).

[0131] Step 8, read the second data of the address space in step 4 and compare with the first data written in.

[0132] Step 9, if the comparison result in step 8 is the same, write into the system the offset value written in step 7 plus a fixed offset (preset read time offset value), repeat step 8.

[0133] Step 10, if the comparison result in step 8 is different, the optimal read point and the right boundary of the sampling point of the target command / address signal set have been found, at this time the system needs to be reinitialized and the system is restored to the correct configuration.

[0134] Step 11, repeat steps 1-8, but add a fixed offset to step 7, change to subtract a fixed offset, to find the optimal read point and the left boundary of the sampling point of the target command / address signal set.

[0135] Step 12, if the left boundary in step 11 is also found, set step 2 to a different CA signal corresponding to the current chip grain, repeat steps 1-11.

[0136] Step 13, after the execution of step 12 is completed, the left and right boundary read offset times of all CA signals corresponding to the current chip grain at the current set CAvref voltage have been found.

[0137] Step 14, modify the vref voltage of the target command / address signal in step 5, repeat steps 1-13.

[0138] Step 15, after the execution of step 14 is completed, the left and right boundary of all CA signals corresponding to the current chip grain at different CAvref voltages have been found.

[0139] Step 16, modify the CS set in step 2 (replace the target chip grain), repeat steps 1-15.

[0140] Step 17, after the execution of step 16 is completed, modify the channel number set in step 1, repeat steps 1-16.

[0141] Step 18, after the execution of step 17 is completed, the CA digital eye diagram of the entire system is acquired and the acquisition is completed.

[0142] Figure 8 is a complete flowchart of the signal evaluation process in one embodiment of the present disclosure. Figure 8 The embodiments shown can be understood in combination with steps 1-18 described above.

[0143] Reference Figure 8 In one embodiment, the signal evaluation process can include:

[0144] Step S801, the system is powered on.

[0145] Step S802, the system initialization is completed.

[0146] Step S803, set the channel.

[0147] Step S804, set the chip select signal.

[0148] Step S805, set the read reference voltage Vref of the target CA signal.

[0149] Step S806, set the target CA signal.

[0150] Step S807, set the direction dir=0 or dir=1 of horizontal scanning (iterative detection), where dir=0 is for example left iterative detection to find the left boundary, and dir=1 is for example right iterative detection to find the right boundary.

[0151] Step S808, calculate the DRAM address information.

[0152] Step S809, write the first data to the calculated memory address.

[0153] Step S810, acquire the optimal read offset time of the set target CA signal.

[0154] Step S811, the system writes the set CA Vref voltage.

[0155] Step S812, write a new offset value (read offset time Tbias) between CA and sampling points according to the direction set by dir.

[0156] Step S813, read the second data and compare it with the first data.

[0157] Step S814, determine whether the second data is the same as the first data, if yes, return to step S812, if no, go to step S815.

[0158] Step S815: Determine whether dir=0 or dir=1 has completed the scan. If yes, proceed to step S816; otherwise, return to step S801.

[0159] Step S816: Determine whether all CA signals have been scanned. If yes, proceed to step S817; otherwise, return to step S801.

[0160] Step S817: Determine whether all CA Vref voltages have been scanned. If yes, proceed to step S818; otherwise, return to step S801.

[0161] Step S818: Determine whether all chip chips corresponding to the current chip select signal have been scanned. If yes, proceed to step S819; otherwise, return to step S801.

[0162] Step S819: Determine whether all chip particles corresponding to the current channel have been scanned. If yes, end the process; otherwise, return to step S801.

[0163] In this embodiment of the disclosure, the direction of iterative testing (scanning) can be multiple. For example... Figure 6 In the embodiments shown, scanning can proceed from the middle to the left and right, or from the left to the right (by directly setting a minimum Tbias that differs significantly from the optimal read offset time and gradually increasing the Tbias by a certain offset time), or from the right to the left, or from the middle to the top and bottom, from the top and bottom, or from the bottom and top, etc. This disclosure does not impose any special restrictions on these, as long as the eye diagram boundary of the target command / address signal can be detected.

[0164] In summary, the embodiments of this disclosure, by iteratively probing the eye diagram boundaries of the target command / address signal based on the optimal read point, can obtain a complete digital eye diagram of the CA signal even when the memory controller trains the CA signal in hardware and only provides a set of optimal parameters that can run on the system. Furthermore, it overcomes the traditional barrier that obtaining the eye diagram of the CA signal must be done during the CBT stage, enabling the acquisition of the eye diagram of the CA signal even after system training is complete.

[0165] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0166] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.

[0167] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0168] The following reference Figure 9 To describe an electronic device 900 according to this embodiment of the present invention. Figure 9 The electronic device 900 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0169] like Figure 9 As shown, the electronic device 900 is manifested in the form of a general-purpose computing device. The components of the electronic device 900 may include, but are not limited to: at least one processing unit 910, at least one storage unit 920, and a bus 930 connecting different system components (including the storage unit 920 and the processing unit 910).

[0170] The storage unit stores program code that can be executed by the processing unit 910, causing the processing unit 910 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 910 can perform the method shown in the embodiments of this disclosure.

[0171] Storage unit 920 may include readable media in the form of volatile storage units, such as random access memory (RAM) 9201 and / or cache memory 9202, and may further include read-only memory (ROM) 9203.

[0172] Storage unit 920 may also include a program / utility 9204 having a set (at least one) program module 9205, such program module 9205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0173] Bus 930 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0174] The electronic device 900 can also communicate with one or more external devices 1000 such as a keyboard or pointing device, a Bluetooth device, or a database, and can communicate with one or more devices enabling user interaction with the electronic device 900 (for example, a display, speakers, a haptic output device, or the like) and / or one or more devices enabling communication of the electronic device 900 with other computing devices (for example, a modem, a network adapter, or the like). Such communication can occur via Input / Output (I / O) interface 950. Still yet, the electronic device 900 can communicate with one or more networks, such as a local area network (LAN), a wide area network (WAN), and / or the Internet, through a network adapter 960. As depicted, the network adapter 960 communicates with the other components of the electronic device 900 via bus 930. It should be appreciated that the electronic device 900 can be a part of another device or can be a stand-alone device. In addition, the electronic device 900 can be connected to, or a part of, other devices such as a

[0175] Those skilled in the art will readily understand that the example embodiments described herein can be implemented by software and / or by hardware coupled with software, as described above. Thus, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product. The software product can be stored in a non-volatile storage medium (for example, a CD-ROM, a USB flash disk, a mobile hard disk, or the like) or a network, and includes a number of instructions for causing a computing device (for example, a personal computer, a server, a terminal device, or a network device, etc.) to perform the methods according to the embodiments of the present disclosure.

[0176] In the example embodiments of the present disclosure, a computer-readable storage medium is also provided, which stores a program product capable of implementing the above-mentioned methods. In some possible embodiments, various aspects of the present disclosure can also be implemented in the form of a program product, which includes program codes for causing a terminal device to perform the steps according to various example embodiments of the present disclosure described in the above-mentioned “example method” section of the specification when the program product is run on the terminal device.

[0177] The program product for implementing the above-mentioned methods according to the embodiments of the present disclosure can take the form of a portable compact disc read-only memory (CD-ROM) and include program codes, and can be run on a terminal device, for example, a personal computer. However, the program product of the present disclosure is not limited to this, and in this document, a readable storage medium can be any tangible medium containing or storing a program, which can be used by or in conjunction with an instruction execution system, device, or apparatus.

[0178] The program product can employ any combination of one or more computer-readable media. The computer-readable media can be a computer-readable storage medium or a computer-readable signal medium. The computer-readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium include the following: an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0179] The computer-readable signal medium can include a computer-readable storage medium that is propagated as a carrier wave. The computer-readable signal medium can further be any computer-readable medium that is not a storage medium. The computer-readable signal medium can be a computer-readable storage medium that is a propagated signal on a computer-readable storage medium.

[0180] The program code embodied on the computer-readable media can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0181] The program code can be executed by one or more programmable processors, which can be implemented in one or more computer devices including any combination of a microprocessor, a microcontroller, a digital signal processor, or other processing circuitry. The program code can be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, C++, or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code can execute entirely on the user's computer device, partly on the user's computer device, as a stand-alone software package, partly on the user's computer device and partly on a remote computer device or entirely on the remote computer device or server. In the latter scenario, the remote computer device can be connected to the user's computer device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer device such as through the Internet using an Internet Service Provider. The program code can also be downloaded to the user's computer device from the remote computer device or server through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer device such as through the Internet using an Internet Service Provider.

[0182] In addition, the above-described flowcharts are merely illustrative of the processes included in the method according to the exemplary embodiments of the present application, and are not intended to limit the present application. It is readily understood that the processes shown in the above-described flowcharts do not indicate or limit the time sequence of the processes. In addition, it is readily understood that the processes can be executed synchronously or asynchronously, for example, in a plurality of modules.

[0183] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A signal evaluation method, characterized by, The method comprises the following steps: training a memory system, and writing first data into a memory corresponding to the trained memory system; obtaining an optimal read reference voltage and an optimal read offset time of a target command / address signal, setting one of the first parameter and the second parameter as the optimal read reference voltage, and setting the other as the optimal read offset time; adjusting the first parameter and the second parameter based on a first preset offset value and a second preset offset value, reading the memory based on the first parameter and the second parameter to obtain second data, and determining two second parameter boundary values of the target command / address signal under each first parameter and two first parameter boundary values of the first parameter based on the second data and the first data, comprising: iteratively adjusting the second parameter based on the second preset offset value, iteratively reading the second data, and determining two second parameter boundary values of the target command / address signal under each first parameter based on the second data and the first data; when the two second parameter boundary values of the first parameter do not satisfy a preset condition, adjusting the first parameter based on the first preset offset value to determine two second parameter boundary values corresponding to each first parameter; when the two second parameter boundary values of the first parameter satisfy the preset condition, determining the current first parameter as the first parameter boundary value, wherein the first preset offset value is an offset value of the first parameter, and the second preset offset value is an offset value of the second parameter; generating an eye diagram of the target command / address signal based on the two second parameter boundary values under each first parameter and the two first parameter boundary values of the first parameter.

2. The signal evaluation method of claim 1, wherein The method of iteratively adjusting the second parameter based on the second preset offset value, iteratively reading the second data, and determining two second parameter boundary values of the target command / address signal under each first parameter based on the second data and the first data comprises: adjusting the second parameter based on the second preset offset value; setting a sampling point of the target command / address signal as the first parameter and the second parameter, reading the memory, and obtaining the second data; when the second data is equal to the first data, returning to adjust the second parameter based on the second preset offset value; when the second data is not equal to the first data, recording the current second parameter as one second parameter boundary value under the first parameter; when the first parameter corresponds to one second parameter boundary value, reversing the second preset offset value, and returning to adjust the second parameter based on the second preset offset value; when the first parameter corresponds to two second parameter boundary values, recording the two second parameter boundary values of the target command / address signal under the first parameter.

3. The signal evaluation method of claim 1, wherein The method of adjusting the first parameter based on the first preset offset value to determine two second parameter boundary values corresponding to each first parameter when the two second parameter boundary values of the first parameter do not satisfy a preset condition comprises: After adjusting the first parameter according to the first preset offset value, return to iteratively adjust the second parameter according to the second preset offset value to determine two second parameter boundary values of the target command / address signal under the adjusted first parameter.

4. The signal evaluation method of claim 1, wherein The determining the current first parameter as the first parameter boundary value when the two second parameter boundary values of the first parameter satisfy a preset condition comprises: After determining the current first parameter as the first parameter boundary value, if there is one first parameter boundary value, reverse the first preset offset value, return to adjust the first parameter according to the first preset offset value, and determine two second parameter boundary values corresponding to the first parameter. If there are two first parameter boundary values, record the two first parameter boundary values of the target command / address signal and the two second parameter boundary values of the target command / address signal under each first parameter.

5. The signal evaluation method according to any one of claims 1 to 4, characterized in that The preset condition comprises that the difference between the two second parameter boundary values under the first parameter is less than or equal to a preset threshold.

6. The signal evaluation method of claim 1, wherein The first parameter is a read reference voltage, the second parameter is a read offset time, the first preset offset value is a reference voltage offset value, and the second preset offset value is a read time offset value.

7. The signal evaluation method of claim 1, wherein The first parameter is a read offset time, the second parameter is a read reference voltage, the first preset offset value is a read time offset value, and the second preset offset value is a reference voltage offset value.

8. The signal evaluation method according to claim 1, 6 or 7, characterized in that, The first preset offset value is a positive number or a negative number, and the second preset offset value is a positive number or a negative number.

9. The signal evaluation method of claim 1, wherein, After determining any first parameter boundary value and second parameter boundary value, retrain the memory system and write the first data.

10. The signal evaluation method of claim 1, wherein, The write address of the first data makes the target command / address signal in the time domain appear as high voltage and low voltage interleaving.

11. The signal evaluation method of claim 1, wherein, The first data makes the data written in each address different.

12. The signal evaluation method of claim 1, wherein, After obtaining the eye diagram of the target command / address signal, replace the command / address signal for measurement to obtain the eye diagrams of all command / address signals in the memory.

13. An electronic device, comprising: Comprise: a memory; and a processor coupled to the memory, the processor configured to execute a signal evaluation method as claimed in any one of claims 1-12 based on instructions stored in the memory.

14. A computer readable storage medium having stored thereon a program which, when executed by a processor, implements a signal evaluation method as claimed in any one of claims 1-12.

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