Gate-oxidized silicon carbide devices and methods of making the same

Abstract

The application discloses a gate-oxidized silicon carbide device and a manufacturing method thereof. The manufacturing method of the gate-oxidized silicon carbide device comprises the following steps: providing an intermediate device, depositing a first preset thickness of a nitrogen-doped polysilicon layer on the top of a JFET layer through a first preset concentration of nitrogen-doped polysilicon; heating the intermediate device in a diffusion furnace to form a second oxide layer and a first oxide layer on the top of the nitrogen-doped polysilicon layer; depositing polysilicon on the top of the first oxide layer to form a gate electrode; preparing a passivation layer on the top of the first oxide layer; preparing a source electrode on the top of the passivation layer and a drain electrode on the bottom of a substrate layer. In the application, the nitrogen-doped polysilicon is deposited on the JFET layer, and when the nitrogen-doped polysilicon is oxidized, the nitrogen atoms in the nitrogen-doped polysilicon are pushed close to the JFET layer made of SiC material, the number of carbon clusters and near-interface traps formed on the contact surface of the JFET layer and the silicon oxide layer is reduced through the passivation of the nitrogen atoms, and the breakdown voltage, the mobility and the stability of the silicon carbide device are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a silicon carbide device with gate oxidation and a method for manufacturing the same. Background Technology

[0002] Silicon carbide (SiC) materials have attracted widespread attention and research due to their superior physical properties. Their high-temperature, high-power electronic devices possess advantages such as high input impedance, fast switching speed, high operating frequency, and resistance to high temperatures and pressures, leading to their widespread application in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] In semiconductor device manufacturing processes, the formation of the gate oxide layer is typically performed using heating. Silicon dioxide is grown by heating the surface of silicon carbide. In existing gate oxidation processes, the oxidation of silicon carbide (SiC) results in the formation of carbon clusters and near-interface traps with high-density accumulated charges at the oxide / silicon carbide interface. Existing technologies typically employ nitriding to mitigate these defects. However, in existing nitriding processes, during the high-temperature annealing stage, a dense silicon dioxide oxide film has already formed, which hinders nitrogen diffusion. This leads to insufficient removal of carbon clusters and near-interface traps at the oxide / silicon carbide interface, resulting in a large number of carbon clusters and near-interface traps remaining on the semiconductor device. This leads to reduced gate breakdown voltage, low mobility, and insufficient stability of the semiconductor device. Summary of the Invention

[0004] The main objective of this invention is to provide a silicon carbide device with gate oxidation and its manufacturing method, aiming to solve the problems of reduced breakdown voltage, low mobility, and insufficient stability of semiconductor devices produced by existing gate oxidation processes.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a silicon carbide device with gate oxidation, comprising the following steps:

[0006] An intermediate device is provided, comprising a substrate layer, an epitaxial layer and a JFET layer stacked sequentially from bottom to top, wherein the substrate layer, the epitaxial layer and the JFET layer are all made of N-type SiC, a PW region made of P-type SiC is disposed on the top of the JFET layer, and an impurity region made of N-type SiC is disposed on the top of the PW region.

[0007] A nitrogen-doped polysilicon layer of a first predetermined thickness is formed on top of the JFET layer by depositing nitrogen-doped polysilicon of a first predetermined concentration.

[0008] The intermediate device is placed in a diffusion furnace and oxidized at a temperature of 1700℃~1900℃ for 200min~300min to form a second oxide layer and a first oxide layer stacked sequentially from bottom to top on the nitrogen-doped polycrystalline silicon layer.

[0009] A gate electrode is formed by depositing polycrystalline silicon on top of the first oxide layer;

[0010] A passivation layer is prepared on top of the first oxide layer, wherein the passivation layer covers the gate electrode;

[0011] A source electrode is fabricated on top of the passivation layer and a drain electrode is fabricated at the bottom of the substrate layer, wherein the source electrode is connected to the PW region.

[0012] Preferably, the first preset thickness is A, and the sum of the thickness of the second oxide layer and the thickness of the first oxide layer is B, 1 / 5B. <A<1 / 3B。

[0013] Preferably, the first preset concentration is 1E19 / cm³. 3 -1E20 / cm 3 .

[0014] Preferably, the step of providing the intermediate device includes:

[0015] The substrate layer is formed by growing N-type SiC of a second preset concentration;

[0016] The epitaxial layer is formed on the substrate by growing N-type SiC with a third preset concentration, wherein the second preset concentration is greater than the third preset concentration;

[0017] The JFET layer is formed by implanting N-type SiC of a fourth predetermined concentration on top of the epitaxial layer;

[0018] An oxide layer is prepared on top of the JFET layer;

[0019] A MOSFET channel is fabricated on the JFET layer;

[0020] An ohmic contact is formed by injecting a fifth preset concentration of N-type SiC impurities into the MOS channel;

[0021] The oxide layer is peeled off to obtain the intermediate device.

[0022] Preferably, the second preset concentration is 1E17 / cm³. 3 ~1E19 / cm; the third preset concentration is 1E14 / cm 3 ~1E16 / cm 3 The fourth preset concentration is 1E15 / cm³. 3 ~1E17 / cm3 .

[0023] Preferably, the step of fabricating the MOSFET channel on the JFET layer includes:

[0024] The oxide layer at a predetermined location is etched to form a groove to expose a portion of the JFET layer;

[0025] A sixth predetermined concentration of P-type SiC impurities is implanted into the exposed portion of the JFET layer to form the PW region;

[0026] The sidewalls are fabricated on the sidewalls of the groove using a sidewall process to form the MOS channel;

[0027] The step of injecting a fifth preset concentration of N-type SiC impurities into the MOS channel to form an ohmic contact includes:

[0028] An ohmic contact is formed by injecting a fifth preset concentration of N-type SiC impurities above the PW region.

[0029] Preferably, the fifth preset concentration is 1E18 / cm³. 3 -1E19 / cm 3 The sixth preset concentration is 1E17 / cm³. 3 -5e17 / cm 3 .

[0030] Preferably, the step of etching a groove in the oxide layer at a predetermined location to expose a portion of the JFET layer includes:

[0031] A layer of photoresist is deposited on top of the oxide layer;

[0032] The photoresist at the preset location is etched using a hard mask process;

[0033] The oxide layer corresponding to the photoresist at the preset position is etched to form a groove;

[0034] Remove the photoresist to expose a portion of the JFET layer.

[0035] Preferably, the step of preparing sidewalls at the edge of the oxide layer using a sidewall process to form MOS channels includes:

[0036] A second predetermined dielectric layer is deposited on the etched oxide layer and the exposed portion of the JFET layer;

[0037] The dielectric layer is etched using a dry etching process to form sidewalls at the edges of the oxide layer, thereby forming the MOS channel.

[0038] The present invention also provides a silicon carbide device with gate oxidation, which is manufactured by the method for manufacturing a silicon carbide device with gate oxidation as described above.

[0039] In the technical solution of this invention, nitrogen-doped polysilicon of a first preset concentration is deposited on top of the JFET layer of the intermediate device. When heated in a diffusion furnace, the nitrogen-doped polysilicon is oxidized. The oxide layer grows slowly from top to bottom. After oxygen atoms combine with Si, they push nitrogen atoms in the nitrogen polysilicon closer to the SiC material JFET layer. In this way, the nitrogen atoms treat the aggregated carbon clusters and near-interface traps formed at the interface between the JFET layer and the silicon oxide layer, reducing the number of aggregated carbon clusters and near-interface traps at the interface between the JFET layer and the silicon oxide layer, thereby improving the breakdown voltage and mobility of the silicon carbide device and improving the stability of the silicon carbide device. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0041] Figure 1 This is a flowchart illustrating a method for manufacturing a silicon carbide device with gate oxidation according to an embodiment of the present invention.

[0042] Figure 2 This is a detailed flowchart of step S100 of a method for manufacturing a silicon carbide device with gate oxidation according to an embodiment of the present invention.

[0043] Figure 3 This is a detailed flowchart of step S150 of a method for manufacturing a silicon carbide device with gate oxidation according to an embodiment of the present invention.

[0044] Figure 4 This is a detailed flowchart of step S151 of a method for manufacturing a silicon carbide device with gate oxidation according to an embodiment of the present invention.

[0045] Figure 5 This is a schematic diagram of the structure of a silicon carbide device with gate oxidation according to an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of the substrate layer, epitaxial layer, and JFET layer of a silicon carbide device with gate oxidation according to an embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of the structure of the substrate layer, epitaxial layer, JFET layer and oxide layer of a silicon carbide device with gate oxidation according to an embodiment of the present invention;

[0048] Figure 8 This is a schematic diagram of the substrate layer, epitaxial layer, JFET layer, sidewall and oxide layer of a silicon carbide device with gate oxidation according to an embodiment of the present invention.

[0049] Figure 9 This is a schematic diagram of the substrate layer, epitaxial layer, JFET layer, sidewall and oxide layer of a silicon carbide device with gate oxidation according to an embodiment of the present invention.

[0050] Figure 10 This is a schematic diagram of the structure of an intermediate device in a silicon carbide device with gate oxidation according to an embodiment of the present invention.

[0051] Figure 11 This is a schematic diagram of the intermediate device and nitrogen-doped polysilicon layer of a gate-oxidized silicon carbide device according to an embodiment of the present invention.

[0052] Figure 12 This is a schematic diagram of the structure of the intermediate device, the first oxide layer, and the second oxide layer of a silicon carbide device with gate oxidation according to an embodiment of the present invention.

[0053] Explanation of icon numbers:

[0054]

[0055]

[0056] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0057] The technical solutions in this embodiment will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this embodiment are only used to explain the relative positional relationship and movement of each component in a specific posture (as shown in the attached figure). If the specific posture changes, the directional indicator will also change accordingly.

[0059] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0060] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0061] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible to those skilled in the art. If a combination of technical solutions contradicts each other or cannot be implemented, such a combination should be considered non-existent and not within the scope of protection claimed by the present invention. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0062] This invention proposes a silicon carbide device with gate oxidation 1 and its manufacturing method.

[0063] Please combine Figure 1 , Figure 10 , Figure 11 and Figure 12 The method for manufacturing the gate-oxidized silicon carbide device 1 in this embodiment includes the following steps:

[0064] S100: Provides an intermediate device 93, which includes a substrate layer 20, an epitaxial layer 30 and a JFET layer stacked sequentially from bottom to top. The substrate layer 20, the epitaxial layer 30 and the JFET layer are all made of N-type SiC. A PW region made of P-type SiC is provided on the top of the JFET layer, and an impurity region made of N-type SiC is provided on the top of the PW region.

[0065] Intermediate device 93 is a silicon carbide intermediate device 93 manufactured in a conventional process flow;

[0066] S200: A nitrogen-doped polysilicon layer 50 of a first preset thickness is formed on top of the JFET layer by depositing nitrogen-doped polysilicon of a first preset concentration;

[0067] When the concentration and thickness of nitrogen-doped polycrystalline silicon are at the first preset concentration and the first preset thickness, nitrogen atoms can be pushed more fully into the JFET layer during the oxidation process, thereby improving the processing efficiency of aggregated carbon clusters and near-interface traps.

[0068] S300: The intermediate device 93 is placed in a diffusion furnace and oxidized at a temperature of 1700℃~1900℃ for 200min~300min to form a second oxide layer 52 and a first oxide layer 51 stacked sequentially from bottom to top on the nitrogen-doped polycrystalline silicon layer 50.

[0069] Oxidizing nitrogen-doped polysilicon at a temperature of 1700℃~1900℃ for 200min~300min allows the nitrogen-doped polysilicon layer 50 to be fully oxidized. The nitrogen-doped polysilicon layer 50 is slowly oxidized from top to bottom, forming SiO or SiO2, which pushes nitrogen atoms toward the JFET layer. At this temperature and duration, the processing efficiency of nitrogen atoms on aggregated carbon clusters and near-interface traps can be improved. It should be noted that since the first oxide layer 51 formed by polysilicon is more porous than the silicon carbide oxide layer, it does not prevent oxygen from continuing to diffuse downwards. The oxygen diffuses downwards and continues to react to form a denser oxide layer. Furthermore, due to the passivation of nitrogen, the defects such as carbon atom clusters that were originally generated are neutralized. Therefore, the defects and traps at the interface between silicon carbide and oxide layer are reduced, which greatly improves the carrier mobility of the device itself.

[0070] S400: Polysilicon is deposited on top of the first oxide layer 51 to form a gate electrode 60;

[0071] S500: A passivation layer 70 is prepared on top of the first oxide layer 51, wherein the passivation layer 70 covers the gate electrode 60.

[0072] S600: A source electrode 80 is fabricated on top of the passivation layer 70 and a drain electrode 10 is fabricated at the bottom of the substrate layer 20, wherein the source electrode 80 is connected to the PW region.

[0073] In the technical solution of this invention, nitrogen-doped polysilicon of a first preset concentration is deposited on top of the JFET layer of the intermediate device 93. When heated in a diffusion furnace, the nitrogen-doped polysilicon is oxidized. The oxide layer grows slowly from top to bottom. After oxygen atoms combine with Si, they push nitrogen atoms in the nitrogen polysilicon closer to the SiC material JFET layer. In this way, the nitrogen atoms treat the aggregated carbon clusters and near-interface traps formed at the interface between the JFET layer and the silicon oxide layer, reducing the number of aggregated carbon clusters and near-interface traps at the interface between the JFET layer and the silicon oxide layer, thereby improving the breakdown voltage and mobility of the silicon carbide device and improving the stability of the silicon carbide device.

[0074] In one embodiment, the first preset thickness is A, the sum of the thickness of the second oxide layer 52 and the thickness of the first oxide layer 51 is B, and 1 / 5B < A < 1 / 3B. The thickness of the nitrogen-doped polysilicon layer 50 is the first preset thickness A, and the sum of the thicknesses of the second oxide layer 52 and the first oxide layer 51 generated after oxidation thereof is B. It is theoretically calculated before preparation that when 1 / 5B < A < 1 / 3B, the oxidation effect of the nitrogen-doped polysilicon layer 50 is better. Preferably, it is optimal when the thickness A of the nitrogen-doped polysilicon layer 50 is 1 / 4 of the sum B of the thicknesses of the second oxide layer 52 and the first oxide layer 51,

[0075] Further, the first preset concentration is 1E19 / cm³ - 1E20 / cm³. The concentration refers to the number of atoms per cubic centimeter. When the concentration of the nitrogen-doped polysilicon is 1E19 / cm³ - 1E20 / cm³, its oxidation effect and the treatment effect on aggregated carbon clusters and near-interface traps are better.

[0076] Refer to Figure 2 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Figure 9 , in one embodiment, step S100 includes:

[0077] S110: growing N-type SiC with a second preset concentration to form the substrate layer 20;

[0078] S120: growing N-type SiC with a third preset concentration on the substrate layer 20 to form the epitaxial layer 30, wherein the second preset concentration is greater than the third preset concentration;

[0079] S130: implanting N-type SiC with a fourth preset concentration on the top of the epitaxial layer 30 to form the JFET layer;

[0080] S140: preparing the oxide layer 90 on the top of the JFET layer;

[0081] S150: fabricating the MOS channel on the JFET layer;

[0082] S160: implanting N-type SiC impurities with a fifth preset concentration on the MOS channel to form an ohmic contact;

[0083] S170: stripping the oxide layer to obtain the intermediate device 93.

[0084] The second preset concentration is greater than the third preset concentration. The substrate layer 20 is configured to connect to the drain, and is doped at a high concentration to reduce its resistivity. The epitaxial layer 30 is configured to form a depletion region, and is doped at a low concentration to ensure its nominal withstand voltage. The silicon carbide device is fabricated according to standard procedures, and the intermediate device 93 is generated after stripping the oxide layer, which facilitates subsequent oxidation of the nitrogen-doped polysilicon above the JFET layer.

[0085] Furthermore, the second preset concentration is 1E17 / cm³ to 1E19 / cm³; the third preset concentration is 1E14 / cm³ to 1E16 / cm³; and the fourth preset concentration is 1E15 / cm³ to 1E17 / cm³. Multiple experiments have confirmed that when the second preset concentration is 1E17 / cm³ to 1E19 / cm³, the resistivity of the prepared substrate layer 20 is relatively low, meeting the usage standards while reducing costs; when the third preset concentration is 1E14 / cm³ to 1E16 / cm³, the epitaxial breakdown voltage is higher, meeting the usage standards.

[0086] Please combine Figure 7 and Figure 8 Furthermore, step S150 includes:

[0087] S151: Etch the oxide layer 90 at the preset position to form a groove 91 to expose part of the JFET layer;

[0088] S152: Implant a P-type SiC impurity of a sixth preset concentration onto the exposed portion of the JFET layer to form a PW region;

[0089] S153: Sidewall 92 is prepared on the sidewall of groove 91 by sidewall 92 process to form MOS channel;

[0090] The 92-inch sidewall process does not require a photomask, making the process simple and inexpensive.

[0091] Step S160 includes:

[0092] S164: An N-type SiC impurity of a fifth preset concentration is injected above the PW region to form an ohmic contact.

[0093] Injecting N-type SiC impurities into the P-type SiC impurities in the PW region to form ohmic contacts is beneficial for current input and output and improves carrier mobility.

[0094] Furthermore, the fifth preset concentration is 1E18 / cm3 - 1E19 / cm3, and the sixth preset concentration is 1E17 / cm3 - 5e17 / cm3. The fifth preset concentration is higher than the sixth preset concentration. Implanting a high concentration of N-type impurities into the PW region can narrow the semiconductor depletion region, giving electrons more opportunities to pass through directly, while simultaneously reducing the Rc resistance.

[0095] Please combine Figure 3 , Figure 7 and Figure 8 In one embodiment, step S151 includes:

[0096] S1511: A layer of photoresist is laid on top of the oxide layer;

[0097] S1512: Photoresist at a preset location is etched using a hard mask process;

[0098] S1513: The oxide layer below the photoresist at the preset etching position forms a groove 91;

[0099] S1514: Remove photoresist to expose part of the JFET layer.

[0100] The groove 91 is formed by etching using a hard mask process. The groove 91 formed by the hard mask process has a precise structure, which improves the etching accuracy of the groove 91 and can reduce costs.

[0101] In one embodiment, step S153 includes:

[0102] S1531: Deposit a dielectric layer of a second predetermined thickness on the etched oxide layer and the exposed portion of the JFET layer;

[0103] S1532: The dielectric layer is etched by a dry etching process to form sidewalls 92 at the edge of the oxide layer, thereby forming a MOS channel.

[0104] It is important to note that the dielectric layer is laid on the surface of the oxide layer and the JFET layer, and its thickness is the same at any position. On the sidewall of the oxide layer (i.e., on the sidewall of the groove 91), the dielectric layer extends vertically, and its thickness is equal to its horizontal width (i.e., the horizontal width of the dielectric layer on the sidewall of the groove 91 is the same as the vertical thickness of the dielectric layer on the surface of the oxide layer and the JFET layer, but its vertical thickness is greater than the vertical thickness of the dielectric layer on the surface of the oxide layer and the JFET layer). During dry etching of the dielectric layer, the dielectric layer is etched from top to bottom. When the etching depth of the dielectric layer on the surface of the oxide layer and the JFET layer is the second preset thickness, the dielectric layer on the surface of the oxide layer and the JFET layer is completely etched. Part of the dielectric layer on the sidewall of the groove 91 is still not etched, forming the sidewall 92, which improves its dielectric constant and obtains a better isolation effect.

[0105] The present invention also provides a gate-oxidized silicon carbide device 1, which is manufactured by the manufacturing method of the gate-oxidized silicon carbide device 1 as described above. The specific structure of the gate-oxidized silicon carbide device 1 in this embodiment refers to the above embodiment, and therefore has at least the beneficial effects of the above embodiment, which will not be repeated here.

[0106] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for manufacturing a silicon carbide device with gate oxidation, characterized in that, Includes the following steps: An intermediate device is provided, comprising a substrate layer, an epitaxial layer and a JFET layer stacked sequentially from bottom to top, wherein the substrate layer, the epitaxial layer and the JFET layer are all made of N-type SiC, a PW region made of P-type SiC is disposed on the top of the JFET layer, and an impurity region made of N-type SiC is disposed on the top of the PW region. A nitrogen-doped polysilicon layer of a first predetermined thickness is formed on top of the JFET layer by depositing nitrogen-doped polysilicon of a first predetermined concentration. The intermediate device is placed in a diffusion furnace and oxidized at a temperature of 1700°C to 1900°C for 200 min to 300 min to form a second oxide layer and a first oxide layer stacked sequentially from bottom to top on the nitrogen-doped polycrystalline silicon layer. A gate electrode is formed by depositing polycrystalline silicon on top of the first oxide layer; A passivation layer is prepared on top of the first oxide layer, wherein the passivation layer covers the gate electrode; A source electrode is fabricated on top of the passivation layer and a drain electrode is fabricated at the bottom of the substrate layer, wherein the source electrode is connected to the PW region.

2. The method for manufacturing a silicon carbide device with gate oxidation as described in claim 1, characterized in that, The first preset thickness is A, and the sum of the thickness of the second oxide layer and the thickness of the first oxide layer is B, 1 / 5B <A<1 / 3B。 3. The method for manufacturing a silicon carbide device with gate oxidation as described in claim 1, characterized in that, The first preset concentration is 1E19 / cm³-1E20 / cm³.

4. The method for manufacturing a silicon carbide device with gate oxidation as described in claim 1, characterized in that, The step of providing intermediate devices includes: The substrate layer is formed by growing N-type SiC of a second preset concentration; The epitaxial layer is formed on the substrate by growing N-type SiC with a third preset concentration, wherein the second preset concentration is greater than the third preset concentration; The JFET layer is formed by implanting N-type SiC of a fourth predetermined concentration on top of the epitaxial layer; An oxide layer is prepared on top of the JFET layer; A MOS channel is fabricated on the JFET layer; An ohmic contact is formed by implanting a fifth preset concentration of N-type SiC impurities into the MOS channel; The oxide layer is peeled off to obtain the intermediate device.

5. The method for manufacturing a silicon carbide device with gate oxidation as described in claim 4, characterized in that, The second preset concentration is 1E17 / cm³ to 1E19 / cm³. 3 The third preset concentration is 1E14 / cm³ to 1E16 / cm³; the fourth preset concentration is 1E15 / cm³ to 1E17 / cm³.

6. The method for manufacturing a silicon carbide device with gate oxidation as described in claim 4, characterized in that, The step of fabricating a MOS channel on the JFET layer includes: The oxide layer at a predetermined location is etched to form a groove to expose a portion of the JFET layer; A sixth predetermined concentration of P-type SiC impurities is implanted into the exposed portion of the JFET layer to form the PW region; The sidewalls are fabricated on the sidewalls of the groove using a sidewall process to form the MOS channel; The step of implanting a fifth preset concentration of N-type SiC impurities into the MOS channel to form an ohmic contact includes: An ohmic contact is formed by injecting a fifth preset concentration of N-type SiC impurities above the PW region.

7. The method for manufacturing a silicon carbide device with gate oxidation as described in claim 6, characterized in that, The fifth preset concentration is 1E18 / cm³-1E19 / cm³, and the sixth preset concentration is 1E17 / cm³-5E17 / cm³.

8. The method for manufacturing a silicon carbide device with gate oxidation as described in claim 6, characterized in that, The step of forming a groove in the oxide layer at the predetermined etching location to expose a portion of the JFET layer includes: A layer of photoresist is deposited on top of the oxide layer; The photoresist at the preset location is etched using a hard mask process; The oxide layer corresponding to the photoresist at the preset position is etched to form a groove; Remove the photoresist to expose a portion of the JFET layer.

9. The method for manufacturing a silicon carbide device with gate oxidation as described in claim 6, characterized in that, The step of fabricating sidewalls at the edge of the oxide layer using a sidewall process to form a MOS channel includes: A second predetermined dielectric layer is deposited on the etched oxide layer and the exposed portion of the JFET layer; The dielectric layer is etched using a dry etching process to form sidewalls at the edges of the oxide layer, thereby forming the MOS channel.

10. A silicon carbide device with gate oxidation, characterized in that, It is manufactured by the method for manufacturing a silicon carbide device with gate oxidation as described in any one of claims 1-9.

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