Driving circuit of display screen, display screen and electronic device

Abstract

The present disclosure provides a display screen driving circuit, a display screen and an electronic device. The driving circuit comprises N driving units. The nth driving unit comprises: an input branch connected with the (n-1)th driving unit, configured to receive the (n-1)th carry signal output by the (n-1)th driving unit, and output a control signal according to the (n-1)th carry signal and a clock signal; a first output branch connected with the input branch, configured to output the nth driving signal according to the control signal, wherein the nth driving signal changes in level with a delay of a predetermined number of clock periods of the clock signal relative to the level change of the (n-1)th carry signal; a second output branch connected with the input branch, configured to output the nth carry signal according to the control signal, wherein the nth carry signal changes in level with a delay of a predetermined number of clock periods of the clock signal relative to the level change of the (n-1)th carry signal, and the average level of the nth carry signal is higher than the average level of the nth driving signal. The present disclosure can optimize the power consumption caused by high-frequency PWM driving.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display screen driving circuit, a display screen and an electronic device. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode) screens have the characteristics of wide color gamut, high contrast ratio and flexible bending, and gradually replace LCD to become the standard configuration of high-end mobile phones. However, since OLED is a current-driven device, the uniformity of TFT (Thin Film Transistor) is very high in a low current state. In order to improve the low brightness uniformity, OLED screens use PWM (Pulse Width Modulation) dimming to improve the current modulation of TFT. SUMMARY

[0003] The present disclosure provides a display screen driving circuit, a display screen and an electronic device.

[0004] According to a first aspect of the present disclosure, a display screen driving circuit is provided, the display screen driving circuit comprising N driving units; N is a positive integer greater than or equal to 2; the nth driving unit comprises:

[0005] an input branch connected with the (n-1)th driving unit, configured to receive an (n-1)th carry signal output by the (n-1)th driving unit, and output a control signal according to the (n-1)th carry signal and a clock signal;

[0006] a first output branch connected with the input branch, configured to output an nth driving signal according to the control signal, wherein the nth driving signal changes in level with a delay of a predetermined number of clock periods of the clock signal relative to a change in level of the (n-1)th carry signal;

[0007] a second output branch connected with the input branch, configured to output an nth carry signal according to the control signal; wherein the nth carry signal changes in level with a delay of a predetermined number of clock periods of the clock signal relative to a change in level of the (n-1)th carry signal; and an average value of the level of the nth carry signal is higher than an average value of the level of the nth driving signal.

[0008] In some embodiments, the control signal comprises a first control signal and a second control signal; the level of the second control signal is opposite to the level of the first control signal.

[0009] The input branch comprises:

[0010] a conversion circuit configured to generate the first control signal and the second control signal according to a first clock signal of the clock signals and the (n-1)th carry signal;

[0011] wherein the first control signal and the second control signal are configured to control different controlled switches on the first output branch, and the first control signal and the second control signal are configured to control different controlled switches on the second output branch.

[0012] In some embodiments, the conversion circuit comprises:

[0013] a first controlled switch, wherein an input terminal of the first controlled switch is configured to receive the (n-1)th carry signal, and a control terminal of the first controlled switch is configured to receive the first clock signal;

[0014] a second controlled switch, which is a same type of controlled switch as the first controlled switch, wherein a control terminal of the second controlled switch is connected to an output terminal of the first controlled switch, and an input terminal of the second controlled switch is connected to a first voltage source;

[0015] a third controlled switch, which is a same type of controlled switch as the second controlled switch, wherein a control terminal of the third controlled switch is configured to receive the first clock signal, an output terminal of the third controlled switch is connected to an output terminal of the second controlled switch, and an input terminal of the third controlled switch is configured to receive a voltage signal provided by a second voltage source;

[0016] an output terminal of the first control signal is located on a connection line between the output terminal of the second controlled switch and the output terminal of the third controlled switch;

[0017] an output terminal of the second control signal is located on a connection line between the output terminal of the first controlled switch and the control terminal of the second controlled switch.

[0018] In some embodiments, the input branch further comprises:

[0019] a protection circuit of the second controlled switch, which is connected to the control terminal of the second controlled switch, and is configured to perform voltage division with the control terminal of the second controlled switch when the first controlled switch is turned off.

[0020] In some embodiments, the protection circuit comprises:

[0021] In some embodiments, the protection circuit comprises:

[0022] a fourth controlled switch, which is a controlled switch of the same type as the first controlled switch, wherein a control terminal of the fourth controlled switch is connected to the second voltage source, an input terminal of the fourth controlled switch is connected to the output terminal of the first controlled switch, and an output terminal of the fourth controlled switch is connected to the output terminal of the second control signal.

[0023] In some embodiments, the conversion circuit further comprises:

[0024] a fifth controlled switch, which is a controlled switch of the same type as the third controlled switch, wherein an input terminal of the fifth controlled switch is connected to the second voltage source, and an output terminal of the fifth controlled switch is connected to an input terminal of the third controlled switch;

[0025] a sixth controlled switch, wherein a control terminal of the sixth controlled switch is connected to the output terminal of the first controlled switch, an input terminal of the sixth controlled switch is connected to the second voltage source, and an output terminal of the sixth controlled switch is connected to a control terminal of the fifth controlled switch;

[0026] a seventh controlled switch, which is a controlled switch of a different type from the sixth controlled switch, wherein a control terminal of the seventh controlled switch is connected to the output terminal of the first controlled switch, an input terminal of the seventh controlled switch is connected to a third voltage source, and an output terminal of the seventh controlled switch is connected to the control terminal of the fifth controlled switch.

[0027] In some embodiments, the first output branch comprises:

[0028] an eighth controlled switch, wherein a control terminal of the eighth controlled switch is connected to the output terminal of the first control signal, and the eighth controlled switch is configured to be turned on or turned off according to the first control signal;

[0029] a ninth controlled switch, which is a controlled switch of the same type as the eighth controlled switch, wherein an input terminal of the ninth controlled switch is connected to the eighth controlled switch, and a control terminal of the ninth controlled switch is connected to the output terminal of the second control signal, and the ninth controlled switch is configured to be turned on or turned off according to the second control signal;

[0030] an output terminal of the first output branch is located between an output terminal of the eighth controlled switch and an input terminal of the ninth controlled switch, and an input terminal of the eighth controlled switch is configured to be connected to a first voltage source.

[0031] In some embodiments, the second output branch comprises:

[0032] a tenth controlled switch, wherein a control terminal of the tenth controlled switch is connected to the output terminal of the first control signal, and the tenth controlled switch is configured to be turned on or turned off according to the first control signal;

[0033] An eleventh controlled switch, which is a controlled switch of the same type as the tenth controlled switch, has an input end connected to the tenth controlled switch and a controlled end connected to an output end of the second control signal, for being turned on or off according to the second control signal;

[0034] An output end of the second output branch is located between an output end of the tenth controlled switch and an input end of the eleventh controlled switch, and the input end of the tenth controlled switch is configured to be connected to a third voltage source.

[0035] In some embodiments, the input branch further includes:

[0036] A storage capacitor, a first end of the storage capacitor being connected to the output end of the second control signal;

[0037] A twelfth controlled switch, a controlled end of the twelfth controlled switch being connected to the output end of the second control signal, and an output end of the twelfth controlled switch being connected to a second end of the storage capacitor, and an input end of the twelfth controlled switch being configured to receive a second clock signal in the clock signal;

[0038] In the eighth controlled switch is in the on state, the twelfth controlled switch is in the off state;

[0039] In the first controlled switch is in the off state, the twelfth controlled switch is in the on state.

[0040] According to a second aspect of the embodiments of the present disclosure, a display screen is provided, including the driving circuit of the display screen according to any one of the first aspect.

[0041] According to a third aspect of the embodiments of the present disclosure, an electronic device is provided, including the display screen according to the second aspect.

[0042] The display screen driving circuit, the display screen and the electronic device provided by the embodiments of the present disclosure, the driving circuit comprises N driving units, the nth driving unit comprises an input branch of the (n-1)th driving unit, and a first output branch and a second output branch connected with the input branch, the input branch outputs a control signal according to a clock signal and an (n-1)th carry signal output by the (n-1)th driving unit, the first output branch outputs an nth driving signal according to the control signal, and the second output branch outputs an nth carry signal according to the control signal, so that the carry signal output by the second output branch can be used as an input signal of the (n+1)th driving unit, instead of providing an input signal for the (n+1)th driving unit through the second output branch for outputting the driving signal, so that the driving signal output line and the carry signal output line are independent of each other, and the driving signal output line and the carry signal output line can form a parallel relationship, compared with the output signal of the carry signal and the driving signal being an output signal of one output branch, the phenomenon that the voltage of the carry signal is not enough when the carry signal is input to the next driving unit due to the impedance consumption of the output branch can be reduced, so that the problem that the PWM signal generated by the next driving unit cannot meet the high visual effect display due to the impedance consumption can be reduced, and the display effect of the display screen is improved.

[0043] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings incorporated in the specification and forming a part of it, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0045] Figure 1a FIG. 1 is a schematic diagram of an output line of a driving unit in a display screen driving circuit;

[0046] Figure 1b FIG. 2 is a cascade diagram of a driving unit in a display screen driving circuit;

[0047] Figure 1c FIG. 3 is a circuit schematic diagram of a driving unit in a display screen driving circuit;

[0048] Figure 1d FIG. 4 is a circuit schematic diagram of a light emitting control circuit;

[0049] Figure 1e FIG. 5 is a schematic diagram of the corresponding relationship between the duty cycle and the display brightness value in different dimming modes;

[0050] Figure 2 FIG. 6 is a block diagram of a display screen driving circuit according to an exemplary embodiment

[0051] Figure 3 is a circuit schematic diagram of a driving unit according to an exemplary embodiment;

[0052] Figure 4 is a state schematic diagram of a driving unit in P1 stage according to an exemplary embodiment;

[0053] Figure 5 is a state schematic diagram of a driving unit in P2 stage according to an exemplary embodiment;

[0054] Figure 6 is a state schematic diagram of a driving unit in P3 stage according to an exemplary embodiment;

[0055] Figure 7 is a state schematic diagram of a driving unit in P4 stage according to an exemplary embodiment;

[0056] Figure 8 is a circuit working timing diagram of a driving unit according to an exemplary embodiment;

[0057] Figure 9 is a cascade diagram of a circuit driving circuit of a display screen according to an exemplary embodiment;

[0058] Figure 10 is a positive bias characteristic schematic diagram of a transistor under double VGH voltage according to an exemplary embodiment;

[0059] Figure 11 is a structural block diagram of an electronic device according to an exemplary embodiment.

[0060] Reference signs:

[0061] 100 - driving unit, 110 - input branch, 120 - first output branch, 130 - second output branch, 111 - conversion circuit, 112 - protection circuit;

[0062] T1 - first controlled switch, T2 - second controlled switch, T3 - third controlled switch, T4 - fourth controlled switch, T5 - fifth controlled switch, T6 - sixth controlled switch, T7 - seventh controlled switch, T8 - eighth controlled switch, T9 - ninth controlled switch;

[0063] T10 - tenth controlled switch, T11 - eleventh controlled switch, T12 - twelfth controlled switch, T13 - thirteenth controlled switch, C1 - storage capacitor;

[0064] VGH represents a first voltage source, VGL represents a second voltage source, HVGH represents a third voltage source;

[0065] CK1 represents a first clock signal source, and CK2 represents a second clock signal source;

[0066] B - first node, A - second node, EOUT - driving signal output terminal, COUT - carry signal output terminal. DETAILED DESCRIPTION

[0067] The exemplary embodiments will be described in detail herein with reference to the attached drawings. In the following description, like reference numerals refer to like elements, unless the context clearly dictates otherwise. The following exemplary embodiments described herein represent the best currently known modes of implementing the embodiments of the present disclosure. However, the inventive concepts are not limited to these embodiments and the present disclosure is susceptible to modification and change by those skilled in the art without departing from the scope of the present disclosure.

[0068] The terminology used in the present disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used in the present disclosure and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0069] It should be understood that although the terms first, second, third, etc. can be used herein to describe various information, but these information should not be limited to these terms. These terms are only used to distinguish one type of information from another type of information. For example, without departing from the scope of the present disclosure, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon" or "in response to determining".

[0070] The OLED screen using low-frequency PWM dimming, for example, the PWM driving frequency is 240HZ, will make some sensitive users feel dizzy and headache. In order to improve the user experience and take into account the display effect under low brightness, high-frequency PWM dimming can be used, such as increasing the PWM driving frequency to 1920HZ. However, while increasing the PWM driving frequency, the product power consumption will also increase.

[0071] Figure 1a is a schematic diagram of an output line of a driving unit in a driving circuit of a display screen. As shown in Figure 1a , there is a parasitic capacitance / line resistance on the output line of the driving unit. Figure 1b is a cascade diagram of a driving unit in a driving circuit of a display screen. As shown in Figure 1bAs shown, the cascading method between drive units is as follows: each drive unit directly provides the input signal to the next drive unit through its drive signal output terminal. However, due to the parasitic capacitance / line resistance on the output line of the drive unit, increasing the PWM drive frequency will cause the power consumption of charging and discharging the parasitic capacitance to increase. Therefore, although high-frequency PWM achieves the purpose of protecting eyesight, it inevitably causes an increase in power consumption.

[0072] Figure 1c This is a circuit diagram of the driving unit in the driving circuit of a display screen. For example... Figure 1c As shown, the use of a PMOS inverter in this driving unit can lead to internal node leakage, which in turn increases circuit power consumption. Furthermore, when the clock signal provided by clock source CK2 is low, the low level couples to a high potential through a capacitor, pulling the potential of node P low. This causes instability in the gate signal of the P-type transistor connected to point P, resulting in leakage and further increasing circuit power consumption.

[0073] Figure 1d This is a circuit diagram of a light-emitting control circuit. (For example...) Figure 1d As shown, PWM can modulate the pulse width of the emission control signal (EM signal). By adjusting the duty cycle of the EM signal, the brightness of the OLED emission can be controlled.

[0074] Figure 1e This is a schematic diagram illustrating the correspondence between duty cycle and display brightness values ​​under different dimming modes. For example... Figure 1e As shown, the horizontal axis represents the display brightness value DBV, and the vertical axis represents the duty cycle. Using PWM dimming mode, the duty cycle and the display brightness value DBV have a linear relationship.

[0075] Figure 2 This is a block diagram illustrating a driving circuit for a display screen according to an exemplary embodiment. (Refer to...) Figure 2 The driving circuit of the display screen includes N driving units 100; N is a positive integer greater than or equal to 2; the nth driving unit 100 includes: an input branch 110, a first output branch 120 and a second output branch 130.

[0076] Input branch 110 is connected to the (n-1)th drive unit 100 and is used to receive the (n-1)th carry signal output by the (n-1)th drive unit 100, and output a control signal according to the (n-1)th carry signal and the clock signal;

[0077] The first output branch 120 is connected with the input branch 110, and is configured to output an nth driving signal according to the control signal, wherein the nth driving signal changes in level by a delay of a predetermined number of clock periods of the clock signal relative to a level change of the (n-1)th carry signal;

[0078] The second output branch 130 is connected with the input branch 110, and is configured to output an nth carry signal according to the control signal, wherein the nth carry signal changes in level by a delay of a predetermined number of clock periods of the clock signal relative to a level change of the (n-1)th carry signal, and an average value of the level of the nth carry signal is higher than an average value of the level of the nth driving signal.

[0079] The clock signal includes a first clock signal and a second clock signal, the first clock signal can be provided to the input branch 110 by a first clock signal source, and the second clock signal can be provided to the input branch 110 by a second clock signal source. Here, the first clock signal and the second clock signal can be clock signals with the same frequency and different phases.

[0080] Each of the different signals corresponds to a first level and a second level, where the first level and the second level can represent different state quantities of the signal. For example, the first level can refer to a low level, and the second level can refer to a high level. If the level value of a signal is less than a first level threshold, the level of the signal is the first level, and if the level value of a signal is greater than a second level threshold, the level of the signal is the second level.

[0081] Exemplarily, when the (n-1)th carry signal jumps from the first level to the second level, the nth driving signal jumps from the first level to the second level by a delay of a predetermined number of clock periods of the clock signal relative to the level change of the (n-1)th carry signal, and the nth carry signal jumps from the first level to the second level by a delay of a predetermined number of clock periods of the clock signal relative to the level change of the (n-1)th carry signal.

[0082] Exemplarily, when the (n-1)th carry signal jumps from the second level to the first level, the nth driving signal jumps from the second level by a delay of a predetermined number of clock periods of the clock signal relative to the level change of the (n-1)th carry signal, and the nth carry signal jumps from the second level by a delay of a predetermined number of clock periods of the clock signal relative to the level change of the (n-1)th carry signal.

[0083] Here, the predetermined number of clock periods of the clock signal can be 1 clock period of the clock signal, or 0.5 clock periods of the clock signal, or an integer multiple of the clock period.

[0084] Here, the average level of the nth carry signal can be the average of its lowest potential value when it is at the first level and its highest potential value when it is at the second level. Similarly, the average level of the nth drive signal can be the average of its lowest potential value when it is at the first level and its highest potential value when it is at the second level.

[0085] For example, when the lowest potential value of the nth carry signal at the first level is the same as the lowest potential value of the nth drive signal at the first level, and the highest potential value of the nth carry signal at the second level is higher than the highest potential value of the nth drive signal at the second level, the average level of the nth carry signal is higher than the average level of the nth drive signal.

[0086] This disclosure provides a driving circuit for a display screen. The driving circuit includes N driving units. The nth driving unit includes an input branch connected to the (n-1)th driving unit, and a first output branch and a second output branch connected to the input branch. The input branch outputs a control signal based on a clock signal and a carry signal output by the (n-1)th driving unit. The first output branch outputs an nth driving signal based on the control signal, and the second output branch outputs a carry signal based on the control signal. Thus, the carry signal output by the second output branch can be used as the input signal of the (n+1)th driving unit, instead of being output through the second output branch used for outputting the driving signal. The input signal is provided to the (n+1)th drive unit. In this way, the drive signal output line and the carry signal output line are independent of each other, which can form a parallel relationship between the drive signal output line and the carry signal output line. Compared with the output signal where the carry signal and the drive signal are in the same output branch, this can reduce the phenomenon that the carry signal is not strong enough when it is input to the next drive unit due to the impedance loss of the output branch caused by the coupling of the two signals. This reduces the problem that the PWM signal generated by the next drive unit cannot meet the display requirements of high visual effect due to this impedance loss, thus improving the display effect of the screen.

[0087] In some embodiments, the control signal includes: a first control signal and a second control signal; the level of the second control signal is opposite to the level of the first control signal.

[0088] like Figure 3 As shown, the input branch 110 may include:

[0089] The conversion circuit 111 is used to generate the first control signal and the second control signal according to the first clock signal in the clock signal and the (n-1)th carry signal.

[0090] The first control signal and the second control signal are used for controlling different controlled switches on the first output branch 120, and the first control signal and the second control signal are used for controlling different controlled switches on the second output branch 130.

[0091] Exemplarily, when the level of the first control signal is a first level, the level of the second control signal is a second level.

[0092] In some embodiments, as shown in the figure, the conversion circuit 111 comprises: Figure 3

[0093] A first controlled switch T1, wherein an input end of the first controlled switch T1 is used for receiving the (n-1)th carry signal, and a controlled end of the first controlled switch T1 is used for receiving the first clock signal.

[0094] A second controlled switch T2, which is a controlled switch of the same type as the first controlled switch T1, wherein a controlled end of the second controlled switch T2 is connected with an output end of the first controlled switch T1, and an input end of the second controlled switch T2 is connected with a first voltage source VGH.

[0095] A third controlled switch T3, which is a controlled switch of the same type as the second controlled switch T2, wherein a controlled end of the third controlled switch T3 is used for receiving the first clock signal, an output end of the third controlled switch T3 is connected with an output end of the second controlled switch T2, and an input end of the third controlled switch T3 is used for receiving a voltage signal provided by a second voltage source VGL.

[0096] An output end of the first control signal is located on a connection line between the output end of the second controlled switch T2 and the output end of the third controlled switch T3.

[0097] An output end of the second control signal is located on a connection line between the output end of the first controlled switch T1 and the controlled end of the second controlled switch T2.

[0098] The first voltage source VGH and the second voltage source VGL are direct current voltage sources. The output voltage of the first voltage source VGH can be a positive voltage, for example, the output voltage is between 20V and 30V. The output voltage of the second voltage source VGL can be a negative voltage, for example, the output voltage is between -5V and -10V.

[0099] The first clock signal is used for controlling the conduction or disconnection of the first controlled switch T1.

[0100] ​Exemplarily, taking the first controlled switch T1 as a P-type transistor as an example, when the level value of the first clock signal is less than the first level threshold value, the first controlled switch T1 is turned on, and when the level value of the first clock signal is greater than the second level threshold value, the first controlled switch T1 is turned off.

[0101] As shown in the figure, for the convenience of description, the first node B represents the output end of the first control signal, and the second node A represents the output end of the second control signal. It can be understood that the output end of the first control signal and the output end of the second control signal are not actual components, but different convergence points of the input branch in the driving unit and the first output branch and the second output branch. Figure 3

[0102] When the first controlled switch T1 is turned on, the input end of the first controlled switch T1 receives the (n-1)th carry signal, and if the level value of the (n-1)th carry signal is greater than the second level threshold value, the first controlled switch T1 will output the (n-1)th carry signal to the control end of the second controlled switch T2, so that the second controlled switch T2 is turned off. Since when the level value of the first clock signal is less than the first level threshold value, the third controlled switch T3 is turned on, and the voltage signal provided by the second voltage source VGL received by the input end of the third controlled switch T3 will be transmitted as the first control signal to the first node B, so that the level value of the first node B is rewritten as the voltage signal provided by the second voltage source VGL, that is, the first control signal transmitted to the first output branch 120 and the second output branch 130 is a low-level signal.

[0103] In addition, when the first controlled switch T1 is turned on, the (n-1)th carry signal is transmitted to the second node A, so that the level value of the second node A is rewritten as the level value of the (n-1)th carry signal, that is, the second control signal transmitted to the first output branch 120 and the second output branch 130 is a high-level signal.

[0104] In some embodiments, as shown in the figure, the input branch 110 further includes: Figure 3

[0105] The protection circuit 112 of the second controlled switch T2 is connected to the control end of the second controlled switch T2, and is used to divide the voltage at the control end of the second controlled switch T2 when the first controlled switch T1 is turned off.

[0106] In this embodiment, when the first controlled switch T1 is turned off, the protection circuit of the second controlled switch T2 divides the voltage at the control end of the second controlled switch T2, which can prevent the voltage Vgs between the gate and the source of the second controlled switch T2 from being too low and causing the second controlled switch T2 to be easily burned out.

[0107] In some embodiments, as shown in the figure, the input branch 110 further includes: Figure 3 ​​As shown, the protection circuit 112 comprises:

[0108] A fourth controlled switch T4, which is a controlled switch of the same type as the first controlled switch T1, wherein a control terminal of the fourth controlled switch T4 is connected with the second voltage source VGL; an input terminal of the fourth controlled switch T4 is connected with an output terminal of the first controlled switch T1; and an output terminal of the fourth controlled switch T4 is connected with an output terminal of the second control signal.

[0109] In this embodiment, the fourth controlled switch T4 can be a P-type transistor. When the potential of the output terminal of the second control signal is an excessively low negative voltage, for example, much smaller than the voltage signal provided by the second voltage source VGL to connect the control terminal of the fourth controlled switch T4, so that the gate-source voltage Vgs of the fourth controlled switch T4 is greater than the threshold voltage Vth, the fourth controlled switch T4 is turned off. In this way, turning off the fourth controlled switch T4 makes the potential of the output terminal of the second control signal not affect the potential of the control terminal of the second controlled switch T2, so that the potential of the control terminal of the second controlled switch T2 is prevented from being excessively low, so that the Vgs of the fourth controlled switch T4 is not excessively low, and the fourth controlled switch T4 is prevented from being easily burned out.

[0110] In some embodiments, as shown in FIG. 1B, the conversion circuit 111 further comprises: Figure 3 As shown, the protection circuit 112 comprises:

[0111] A fifth controlled switch T5, which is a controlled switch of the same type as the third controlled switch T3, wherein an input terminal of the fifth controlled switch T5 is connected with the second voltage source VGL; and an output terminal of the fifth controlled switch T5 is connected with an input terminal of the third controlled switch T3.

[0112] A sixth controlled switch T6, wherein a control terminal of the sixth controlled switch T6 is connected with an output terminal of the first controlled switch T1; an input terminal of the sixth controlled switch T6 is connected with the second voltage source VGL; and an output terminal of the sixth controlled switch T6 is connected with a control terminal of the fifth controlled switch T5.

[0113] A seventh controlled switch T7, which is a controlled switch of a different type from the sixth controlled switch T6, wherein a control terminal of the seventh controlled switch T7 is connected with an output terminal of the first controlled switch T1; an input terminal of the seventh controlled switch T7 is connected with a third voltage source HVGH; and an output terminal of the seventh controlled switch T7 is connected with a control terminal of the fifth controlled switch T5.

[0114] In some embodiments, as shown in FIG. 1B, the conversion circuit 111 further comprises:

[0115] The sixth controlled switch T6 and the seventh controlled switch T7 are controlled switches of different types, for example, the sixth controlled switch T6 is an N-type transistor, and the seventh controlled switch T7 is a P-type transistor. When the output end of the first controlled switch T1 is at a low level, the sixth controlled switch T6 is turned off, and the seventh controlled switch T7 is turned on. The seventh controlled switch T7 provides an output voltage of the third voltage source HVGH to the controlled end of the fifth controlled switch T5, so that the fifth controlled switch T5 is turned off. When the output end of the first controlled switch T1 is at a high level, the sixth controlled switch T6 is turned on, and the seventh controlled switch T7 is turned off. The sixth controlled switch T6 provides an output voltage of the second voltage source VGL to the controlled end of the fifth controlled switch T5, so that the fifth controlled switch T5 is turned on.

[0116] In some examples, the sixth controlled switch T6 can be an N-type IGZO (indium gallium zinc oxide) thin film transistor, and the seventh controlled switch T7 can be a P-type IGZO thin film transistor. In this way, the low leakage level of IGZO can be used to improve the internal node leakage of the driving unit, thereby further optimizing the power consumption caused by high-frequency PWM driving.

[0117] In some embodiments, as shown in FIG. 1, the first output branch 120 includes: Figure 3

[0118] An eighth controlled switch T8, a controlled end of the eighth controlled switch T8 being connected to an output end of the first control signal, for being turned on or turned off according to the first control signal;

[0119] A ninth controlled switch T9, the ninth controlled switch T9 being a controlled switch of the same type as the eighth controlled switch T8, an input end of the ninth controlled switch T9 being connected to the eighth controlled switch T8, a controlled end of the ninth controlled switch T9 being connected to an output end of the second control signal, for being turned on or turned off according to the second control signal;

[0120] An output end of the first output branch 120 being located between an output end of the eighth controlled switch T8 and an input end of the ninth controlled switch T9; wherein an input end of the eighth controlled switch T8 is configured to be connected to a first voltage source VGH.

[0121] ​In this embodiment, the eighth controlled switch T8 and the ninth controlled switch T9 can be P-type transistors, the eighth controlled switch T8 is turned on when the first control signal is at a low level, and the ninth controlled switch T9 is turned on when the second control signal is at a low level. Since the low levels of the first control signal and the second control signal do not overlap, and the high levels also do not overlap, at any moment, one of the eighth controlled switch T8 and the ninth controlled switch T9 will be a P-type transistor that is turned on, and then through the turned-on P-type transistor, the first output branch 120 can stably output the nth driving signal.

[0122] In some embodiments, as shown in Figure 3 The second output branch 130 includes:

[0123] The tenth controlled switch T10, a controlled end of the tenth controlled switch T10 is connected with an output end of the first control signal, for turning on or off according to the first control signal;

[0124] The eleventh controlled switch T11, which is a controlled switch of the same type as the tenth controlled switch T10, an input end of the eleventh controlled switch T11 is connected with the tenth controlled switch, a controlled end of the eleventh controlled switch T11 is connected with an output end of the second control signal, for turning on or off according to the second control signal;

[0125] An output end of the second output branch 130 is located between an output end of the tenth controlled switch T10 and an input end of the eleventh controlled switch T11; wherein an input end of the tenth controlled switch T10 is used for being connected with a third voltage source HVGH.

[0126] The tenth controlled switch T10 and the eleventh controlled switch T11 can be P-type transistors, the tenth controlled switch T10 is turned on when the first control signal is at a low level, and the eleventh controlled switch T11 is turned on when the second control signal is at a low level. Since the low levels of the first control signal and the second control signal do not overlap, and the high levels also do not overlap, at any moment, one of the tenth controlled switch T10 and the eleventh controlled switch T11 will be a P-type transistor that is turned on, and then through the turned-on P-type transistor, the second output branch 130 can stably output the carry signal.

[0127] The third voltage source HVGH is a direct current voltage source. When the tenth controlled switch T10 is turned on, the tenth controlled switch T10 can output the output voltage of the third voltage source HVGH to the carry signal output end COUT, so that the carry signal output end COUT outputs the carry signal with the same voltage as the output voltage of the third voltage source HVGH.

[0128] In some examples, the output voltage of the third voltage source HVGH can be equal to or greater than the output voltage of the first voltage source VGH. For example, the output voltage of the third voltage source HVGH can be greater than 30V.

[0129] In the embodiment, the first voltage source VGH is connected through the first output branch and the third voltage source HVGH is connected through the second output branch, and since the first voltage source VGH and the third voltage source HVGH respectively provide high-level signals, the double-VGH design can make the first output branch output the driving signal and the second output branch output the carry signal without mutual interference. In addition, when the output voltage of the third voltage source HVGH is greater than the output voltage of the first voltage source VGH, the high-level signals of the carry signal, the first clock signal and the second clock signal can all be the output voltage of the third voltage source HVGH, which helps to prevent the leakage current of the ninth controlled switch in the first output branch due to the positive bias of the transistor characteristics, thereby further optimizing the power consumption of the driving circuit.

[0130] In some embodiments, as shown in FIG. 1B, the input branch 110 further includes: Figure 3

[0131] a storage capacitor C1, a first end of the storage capacitor C1 being connected to the output end of the second control signal;

[0132] a twelfth controlled switch T12, a controlled end of the twelfth controlled switch T12 being connected to the output end of the second control signal, an output end of the twelfth controlled switch T12 being connected to a second end of the storage capacitor C1, and an input end of the twelfth controlled switch T12 being configured to receive a second clock signal in the clock signal;

[0133] wherein, when the eighth controlled switch T8 is in the conductive state, the twelfth controlled switch T12 is in the open state; and when the first controlled switch T1 is in the open state, the twelfth controlled switch T12 is in the conductive state.

[0134] ​In the embodiment, when the eighth controlled switch T8 is in the on state, the output voltage of the first voltage source VGH connected to the input end of the eighth controlled switch T8 can be output through the output end of the eighth controlled switch T8, so as to obtain the high-level nth drive signal. At this time, the potential at the output end of the second control signal is in the high level, so that the ninth controlled switch T9 in the first output branch 120 is turned off. By turning off the twelfth controlled switch T12, the second clock signal received by the input end of the twelfth controlled switch T12 cannot be transmitted to the storage capacitor C1, so that the second clock signal cannot lower the potential at the output end of the second control signal through the coupling of the storage capacitor C1, thereby the leakage current of the ninth controlled switch T9 in the first output branch 120 can be inhibited, and the purpose of reducing the static power consumption is achieved.

[0135] In the embodiment, when the first controlled switch T1 is in the off state, the twelfth controlled switch T12 is in the on state. When the input end of the twelfth controlled switch T12 receives the low-level second clock signal, the second clock signal is coupled to the output end of the second control signal through the storage capacitor C1, so that the output end of the second control signal has a lower low level. In this way, the ninth controlled switch T9 in the first output branch 120 can be fully turned on, so that the output voltage of the second voltage source VGL connected to the input end of the ninth controlled switch T9 can be output through the output end of the ninth controlled switch T9, that is, the low-level nth drive signal is obtained, so as to ensure the normal control of the brightness of the OLED light emission.

[0136] In addition, the output end of the second control signal has a lower low level, so that the eleventh controlled switch T11 in the second output branch 130 is turned on more completely, so that the voltage provided by the second voltage source VGL connected to the input end of the eleventh controlled switch T11 can be output through the output end of the eleventh controlled switch T11, so as to obtain the low-level carry signal.

[0137] In some embodiments, as shown in Figure 3 The input branch 110 further includes:

[0138] The thirteenth controlled switch T13 has a controlled end connected to the input end of the third controlled switch T3, and an output end connected to the second end of the storage capacitor C1. The input end of the thirteenth controlled switch T13 is connected to the second voltage source.

[0139] When the twelfth controlled switch T12 is in the off state, the thirteenth controlled switch T13 is in the on state.

[0140] In this embodiment, when the twelfth controlled switch T12 is in an off state, in order to prevent the second end of the storage capacitor C1 from being floating without signal input, the output end of the thirteenth controlled switch T13 can be connected to the second end of the storage capacitor C1, and when the twelfth controlled switch T12 is off, the thirteenth controlled switch T13 is turned on to transmit the output voltage of the first voltage source VGH to the storage capacitor C1.

[0141] The controlled switches used in all embodiments of the present disclosure can be switching transistors, for example, thin film transistors TFT or field effect transistors or other devices with the same characteristics. It can be understood that the control end of each controlled switch described above is the gate of the TFT, and the input end and the output end of each controlled switch are the source and the drain, respectively. Since the source and the drain of the switching transistor used here are symmetrical, the source and the drain can be interchangeable, and of course, the "input end" and the "output end" of the controlled switch can be interchangeable.

[0142] In addition, the controlled switches used in the embodiments of the present disclosure can include P-type switching transistors and N-type switching transistors, wherein the P-type switching transistor is turned on when the gate is low and is turned off when the gate is high, and the N-type switching transistor is turned on when the gate is high and is turned off when the gate is low.

[0143] It can be understood that the first voltage source VGH and the third voltage source HVGH respectively serve as high-level signal ends and maintain input direct-current high-level signals when the driving circuit is working, and the second voltage source VGL serves as a low-level source and maintains input direct-current low-level signals when the driving circuit is working.

[0144] The driving circuit of the display screen provided by the present disclosure will be described below through specific embodiments.

[0145] Taking all the controlled switches as transistors as an example, except that the sixth controlled switch T6 is an N-type transistor, the other controlled switches are P-type transistors. Figure 4 to Figure 7 The state diagrams of the driving unit in the P1 stage, the P2 stage, the P3 stage and the P4 stage are shown respectively. Among them, when the driving unit is driving, the P1 stage, the P2 stage, the P3 stage and the P4 stage are stages occurring one after another in a display period, and the corresponding working timing is as shown in Figure 8 .

[0146] Referring to Figure 4 and Figure 8As shown in the P1 stage, the input signal provided by the input signal terminal EIN is at low level, the first clock signal provided by the first clock signal terminal CK1 is at high level, the transistor T1 controlled by the first clock signal is closed (i.e. disconnected), the second node A (i.e. the output terminal of the second control signal) maintains a negative voltage (i.e. maintains the potential of the second node A in the P4 stage of the last display period), the low level of the second node A makes the transistors T9 and T11 open (i.e. conduct), the voltage signal provided by the voltage source VGL reaches the output terminal EOUT through the transistor T9, the output terminal EOUT outputs a low level driving signal, and the voltage signal provided by the voltage source VGH reaches the output terminal COUT through the transistor T11, the output terminal COUT outputs a low level carry signal.

[0147] In this stage, the transistor T3 controlled by the first clock signal is closed, the transistor T8 is open, and the voltage signal provided by the voltage source VGH reaches the first node B (i.e. the output terminal of the first control signal) through the transistor T8, and the low level of the first node B makes the transistors T8 and T10 closed.

[0148] Referring to Figure 5 and Figure 8 As shown in the P2 stage, the input signal provided by the input signal terminal EIN is at high level, the first clock signal provided by the first clock signal terminal CK1 is at low level, the transistor T1 controlled by the first clock signal is open, the transistor T4 is open, and the potential of the second node A is rewritten to high level by the high level input signal, so that the transistors T9 and T11 are closed. Since the input signal is at high level, the input signal reaches the gate of the transistor T2 through the open transistor T11, so that the transistor T2 is closed, and at the same time, the input signal reaches the gate of the transistor T6 and the gate of the transistor T7 through the open transistor T11, so that the transistor T6 is open and the transistor T7 is closed, so that the voltage signal provided by the voltage source VGL reaches the gate of the transistor T5 through the open transistor T6, so that the transistor T5 is open, and the voltage signal provided by the voltage source VGL reaches the input terminal of the transistor T5 through the open transistor T5. The voltage signal provided by the voltage source VGL is written to the first node B, so that the transistors T8 and T10 are open, the voltage signal provided by the voltage source VGH reaches the output terminal EOUT through the transistor T8, the output terminal EOUT outputs a high level driving signal, and the voltage signal provided by the voltage source HVGH reaches the output terminal COUT through the transistor T10, the output terminal COUT outputs a high level carry signal.

[0149] In this stage, the second node A is rewritten by the high level input signal, so that the transistor T12 is closed, and the second clock signal provided by the second clock signal source CK2 cannot be transmitted to the capacitor C1 through the transistor T12, so that the second clock signal cannot be coupled to the potential of the second node A through the capacitor C1 to pull down the high potential of the second node A when the second clock signal is low, so as to inhibit the leakage current flowing through the transistor T9, thereby reducing the static power consumption.

[0150] Referring to Figure 6 and Figure 8 As shown in FIG. 3, in the P3 stage, the input signal provided by the input signal terminal EIN is low, the first clock signal provided by the first clock signal terminal CK1 is low, the transistor T1 controlled by the first clock signal is open, the transistor T4 is open, and the potential of the second node A is rewritten to VGL+|VTH1| by the low level input signal, so that the transistor T9 and the transistor T11 are open. In this stage, through the opening of the transistor T9, the potential of the carry signal output by the output terminal EOUT is VGL+|VTH1|+|VTH2|, and through the opening of the transistor T11, the potential of the carry signal output by the output terminal COUT is VGL+|VTH1|+|VTH2|, where the threshold voltage of the transistor T9 and the transistor T11 is |VTH2|.

[0151] In this stage, the voltage signal provided by the voltage source VGH is written to the first node B through the open transistor T2, so that the transistor T8 and the transistor T10 are open, the voltage signal provided by the voltage source VGH reaches the output terminal EOUT through the transistor T8, the output terminal EOUT outputs a high level driving signal, and the voltage signal provided by the voltage source HVGH reaches the output terminal COUT through the transistor T10, and the output terminal COUT outputs a high level carry signal.

[0152] In this stage, the input signal provided by the input signal terminal EIN is low, and since the gate voltage of the transistor T4 is VGL, in order to make the transistor T4 conduct, the gate-source voltage Vgs of the transistor T4 must be less than the threshold voltage VTH1 of the transistor T4, so the potential of the second node A is rewritten to VGL+|VTH1| by the low level input signal.

[0153] Referring to Figure 7 and Figure 8As shown, in the P4 stage, the first clock signal provided by the first clock signal terminal CK1 is at high level, the transistor T1 controlled by the first clock signal is closed, the transistor T4 is closed, and the potential of the second node A is at low level so that the transistor T12 is turned on. The second clock signal provided by the second clock signal source CK2 is transmitted to the capacitor C1 through the transistor T12, so that when the second clock signal is at low level, the second clock signal can be coupled to the potential of the second node A through the capacitor C1 to make the low potential of the second node A lower, so that the transistors T9 and T11 are both completely turned on, i.e., completely turned on. For example, in this stage, the potential of the second node A can be pulled down to VGL-VGH+a*|VTH2|, wherein a can be 1.

[0154] As shown in the embodiment of the present disclosure, Figure 9 The driving signal output terminal EOUT is used to output a driving signal, and the carry signal output terminal COUT is used to output a carry signal. Since the driving unit outputs the carry signal through the carry signal output terminal COUT, the input signal of the adjacent next stage driving unit is provided through the carry signal output terminal, so that the output impedance of the driving circuit caused by the need of the driving signal output terminal EOUT to provide the input signal for the adjacent next stage EM circuit can be suppressed, and thus the PWM driving power consumption can be optimized.

[0155] In the embodiment of the present disclosure, the transistor T6 and the transistor T7 constitute a complementary inverter. The transistor T6 can be an N-type IGZO transistor, and the transistor T7 can be a P-type transistor. Thus, the inverter constituted by the N-type IGZO transistor and the P-type transistor can improve the internal node leakage by using the low leakage level of IGZO.

[0156] As shown in the embodiment of the present disclosure, Figure 10 The power supply terminal VGL provides an input DC low-level signal, and the power supply terminal VGH and the power supply terminal HVGH both provide an input DC high-level signal. Thus, the input signal provided by the signal input terminal EIN, the first clock signal provided by the first clock signal source CK1, and the second clock signal provided by the second clock signal source CK2 can all be equal to the potential of the high-level signal provided by the power supply terminal HVGH when they are at high level. The potential of the high-level signal provided by the power supply terminal HVGH is greater than the potential of the high-level signal provided by the power supply terminal VGH, so that the leakage current caused by the positive bias of the transistor T9 characteristics can be prevented, and thus the product power consumption can be further optimized.

[0157] In addition, the present disclosure also provides a display screen, and the display device comprises the driving circuit of the display screen in any one of the embodiments. The display screen can be various display screens comprising a pixel array. Exemplarily, the display screen can be an organic light-emitting display screen, and the organic light-emitting display screen comprises an organic light-emitting display panel.

[0158] In addition, the embodiments of the present disclosure further provide an electronic device including the display screen with the driving circuit in the above embodiments. The electronic device can include various mobile terminals.

[0159] For example, the mobile terminal can include a smartphone, a wearable smart watch, smart glasses, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a car display, an electronic book, or any product or component having a display function.

[0160] In some embodiments, the electronic device further includes a processor and / or a memory; the display screen and the memory are both connected to the processor.

[0161] Figure 11 is a block diagram of an electronic device according to an exemplary embodiment. For example, the electronic device can be a mobile phone, a mobile computer, etc.

[0162] Referring to Figure 11 , the electronic device can include one or more of the following components: a processing component 802, a memory 804, a power supply component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0163] The processing component 802 usually controls overall operations of the electronic device, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 802 can include one or more processors 820 to execute instructions to complete all or part of steps of the methods described above. In addition, the processing component 802 can include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 can include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0164] The memory 804 is configured to store various types of data to support operations of the device 800. Examples of these data include instructions for any application or method operating on the electronic device, contact data, phonebook data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0165] Power component 806 provides power to various components of the electronic device. Power component 806 can include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the electronic device.

[0166] Multimedia component 808 includes a screen providing an output interface between the electronic device and a user. In some embodiments, the screen can include an OLED screen, a liquid crystal display (LCD), and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or a sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, multimedia component 808 includes a front camera and / or a rear camera. When the device 800 is in an operating state, such as a shooting state or a video state, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0167] Audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) configured to receive external audio signals when the electronic device is in an operating state, such as a call state, a recording state, and a voice recognition state. The received audio signals can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0168] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, which can be a keyboard, a click wheel, a button, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0169] The sensor component 814 includes one or more sensors for providing status assessments for various aspects of the electronic device. For example, the sensor component 814 can detect an open / closed position of the device 800, relative positioning of components, such as a display and a keypad of the electronic device, a change in position of the electronic device or a component of the electronic device, presence or absence of user contact with the electronic device, orientation or acceleration / deceleration / g-force and temperature of the electronic device. The sensor component 814 can include an accelerometer for measuring a tilt or motion of the electronic device. The sensor component 814 can further include a proximity sensor configured to detect presence of nearby objects without any physical contact. The sensor component 814 can also include a light sensor (e.g., a CMOS or CCD image sensor) for use in imaging applications. In some embodiments, the sensor component 814 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0170] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device and other devices. The electronic device can access a wireless network based on a corresponding communication standard, such as Wi-Fi, 2G, or 3G, or a combination thereof. In an example embodiment, the communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an example embodiment, the communication component 816 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) techniques, infrared data association (IrDA) techniques, ultra-wideband (UWB) techniques, Bluetooth (BT) techniques, and other techniques.

[0171] In an example embodiment, the electronic device can be implemented using one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements for performing the above-described methods.

[0172] In an example embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 804 including instructions, is also provided. The instructions can be executable by the processor 820 of the electronic device to implement the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disc, and an optical data storage device, and the like.

[0173] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the disclosure be construed as including any paterns of this disclosure that can be derived from the description and illustrations presented herein without departing from the scope and spirit of the disclosure. The specification and examples are exemplary only, with the true scope and spirit of the disclosure being indicated by the claims.

[0174] It is to be understood that the disclosure is not limited to the precise construction that has been described above and shown in the accompanying drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the disclosure is limited only by the claims that follow.

Claims

1. A driving circuit for a display screen, characterized in that, The driving circuit includes N driving units; where N is a positive integer greater than or equal to 2. The nth driving unit includes: The input branch is connected to the (n-1)th drive unit and is used to receive the (n-1)th carry signal output by the (n-1)th drive unit, and output a control signal according to the (n-1)th carry signal and the clock signal. The first output branch is connected to the input branch and is used to output the nth driving signal according to the control signal, wherein the nth driving signal changes its level after a predetermined number of clock cycles of the clock signal relative to the level change of the (n-1)th carry signal. The second output branch, connected to the input branch, is used to output the nth carry signal according to the control signal; wherein the level change of the nth carry signal is delayed by a predetermined number of clock cycles of the clock signal relative to the level change of the (n-1)th carry signal; and the average level of the nth carry signal is higher than the average level of the nth drive signal. The input branch includes: a conversion circuit; The conversion circuit includes: The first controlled switch, wherein the input terminal of the first controlled switch is used to receive the (n-1)th carry signal; the controlled terminal of the first controlled switch is used to receive the first clock signal in the clock signal; The second controlled switch is of the same type as the first controlled switch, wherein the controlled terminal of the second controlled switch is connected to the output terminal of the first controlled switch; and the input terminal of the second controlled switch is connected to the first voltage source. The third controlled switch is of the same type as the second controlled switch. The controlled terminal of the third controlled switch is used to receive the first clock signal. The output terminal of the third controlled switch is connected to the output terminal of the second controlled switch. The input terminal of the third controlled switch is used to receive the voltage signal provided by the second voltage source. The fifth controlled switch is of the same type as the third controlled switch. The input terminal of the fifth controlled switch is connected to the second voltage source, and the output terminal of the fifth controlled switch is connected to the input terminal of the third controlled switch. A sixth controlled switch, wherein the controlled terminal of the sixth controlled switch is connected to the output terminal of the first controlled switch, the input terminal of the sixth controlled switch is connected to the second voltage source, and the output terminal of the sixth controlled switch is connected to the controlled terminal of the fifth controlled switch; The seventh controlled switch is a different type of controlled switch from the sixth controlled switch. The controlled terminal of the seventh controlled switch is connected to the output terminal of the first controlled switch, the input terminal of the seventh controlled switch is connected to the third voltage source, and the output terminal of the seventh controlled switch is connected to the controlled terminal of the fifth controlled switch. The control signal includes: a first control signal and a second control signal; the level of the second control signal is opposite to the level of the first control signal; The output terminal of the first control signal is located on the connection line between the output terminal of the second controlled switch and the output terminal of the third controlled switch; The output terminal of the second control signal is located on the connection line between the output terminal of the first controlled switch and the controlled terminal of the second controlled switch.

2. The driving circuit according to claim 1, characterized in that, The conversion circuit is used to generate the first control signal and the second control signal according to the first clock signal and the (n-1)th carry signal; Wherein, the first control signal and the second control signal are used to control different controlled switches on the first output branch; and the first control signal and the second control signal are used to control different controlled switches on the second output branch.

3. The driving circuit according to claim 1, characterized in that, The input branch also includes: The protection circuit of the second controlled switch is connected to the controlled terminal of the second controlled switch and is used to divide the voltage with the controlled terminal of the second controlled switch when the first controlled switch is disconnected.

4. The driving circuit according to claim 3, characterized in that, The protection circuit includes: The fourth controlled switch is of the same type as the first controlled switch. The controlled terminal of the fourth controlled switch is connected to the second voltage source; the input terminal of the fourth controlled switch is connected to the output terminal of the first controlled switch; and the output terminal of the fourth controlled switch is connected to the output terminal of the second control signal.

5. The driving circuit according to claim 1, characterized in that, The first output branch includes: The eighth controlled switch, wherein the controlled terminal of the eighth controlled switch is connected to the output terminal of the first control signal, and is used to turn on or off according to the first control signal; The ninth controlled switch is of the same type as the eighth controlled switch. The input terminal of the ninth controlled switch is connected to the eighth controlled switch, and the controlled terminal of the ninth controlled switch is connected to the output terminal of the second control signal, for turning on or off according to the second control signal. The output terminal of the first output branch is located between the output terminal of the eighth controlled switch and the input terminal of the ninth controlled switch; wherein the input terminal of the eighth controlled switch is used to connect to the first voltage source.

6. The driving circuit according to claim 1, characterized in that, The second output branch includes: The tenth controlled switch, wherein the controlled terminal of the tenth controlled switch is connected to the output terminal of the first control signal, and is used to turn on or off according to the first control signal; The eleventh controlled switch is of the same type as the tenth controlled switch. The input terminal of the eleventh controlled switch is connected to the tenth controlled switch, and the controlled terminal of the eleventh controlled switch is connected to the output terminal of the second control signal, for turning on or off according to the second control signal. The output terminal of the second output branch is located between the output terminal of the tenth controlled switch and the input terminal of the eleventh controlled switch; wherein the input terminal of the tenth controlled switch is used to connect to the third voltage source.

7. The driving circuit according to claim 5, characterized in that, The input branch also includes: A storage capacitor, the first end of which is connected to the output terminal of the second control signal; The twelfth controlled switch has its controlled terminal connected to the output terminal of the second control signal, and its output terminal connected to the second terminal of the storage capacitor; the input terminal of the twelfth controlled switch is used to receive the second clock signal in the clock signal. Wherein, when the eighth controlled switch of the first output branch is in the on state, the twelfth controlled switch is in the off state; When the first controlled switch is in the off state, the twelfth controlled switch is in the on state.

8. A display screen, characterized in that, include: The driving circuit for the display screen as described in any one of claims 1 to 7.

9. An electronic device, characterized in that, include: The display screen as described in claim 8.

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