Napt entry management method and device, electronic equipment and storage medium

Abstract

The application provides an NAPT entry management method and device, electronic equipment and a storage medium, which sets multiple levels of storage chips to store table entry information of an NAPT table, including a TCAM and two levels of basic SRAM and two levels of auxiliary SRAM in parallel. The TCAM and the two levels of basic SRAM sequentially store a first level prefix, a second level prefix and a third part of the table entry information in a descending order. In this way, the first level prefix and the second level prefix of the table entry information can be stored through the TCAM and the first basic SRAM, and the third part is stored in the second basic SRAM, thereby effectively reducing the required storage space of the table entry information, and expanding the specification of the NAPT under the condition of the same storage chip resources. In addition, the auxiliary SRAM is additionally arranged, and the copied table entry information in the auxiliary SRAM is used to solve the influence caused by the routing coverage, so that the table entry information is not covered, and the situation that the message forwarding cannot be accurately performed can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a NAPT entry management method and device, an electronic device and a storage medium. BACKGROUND

[0002] The basic principle of NAT (Network Address Translation) is that a private network host is only assigned a legal public network address when it needs to access the Internet, and uses a private network address when interconnecting internally. When a message accessing the Internet passes through a NAT gateway, the NAT gateway replaces the source IP address in the original message with a legal public network address, and records this conversion. Subsequently, when the message returns from the Internet side, the NAT gateway looks up the original record, replaces the destination address of the message back to the original private network address, and sends it back to the host that made the request. In this way, the private network side or the public network side device sees no difference from ordinary network access.

[0003] NAPT (Network Address Port Translation) is a variant of basic address translation, which allows multiple internal addresses to be mapped to the same public address, and belongs to many-to-one address translation. It converts through the use of "IP address + port number", so that multiple private network users can share a public network IP address to access the external network, and is therefore the main form of address translation implementation.

[0004] The prior art uses TCAM (Ternary Content Addressable Memory) or SRAM (Static Random-Access Memory) to store NAPT entries, and each NAPT occupies one TCAM or SRAM entry. Each TCAM or SRAM entry indexes a Nexthop (next hop) to obtain the egress and edit information of the message. Since the routing and port number in NAPT are in a one-to-many relationship, for multiple NAPT entries with the same IP but different Port, the same number of complete TCAM or SRAM entries are occupied. This storage method causes a large waste of TCAM or SRAM resources. SUMMARY

[0005] The purposes of the present application include, for example, providing a NAPT entry management method, device, electronic equipment and storage medium, which can effectively reduce the storage space required for routing addresses, increase the specifications of storage chips, and realize accurate forwarding of messages.

[0006] Embodiments of the present application can be implemented as follows:

[0007] In a first aspect, the present application provides a NAPT entry management method, which comprises:

[0008] A multi-level storage chip is set to store table entry information of a NATP table, the table entry information being a routing address plus a port number, the table entry information being divided into three continuous and non-repeated information entries, the three information entries being a first-level prefix, a second-level prefix, and a third part remaining except the first-level prefix and the second-level prefix, the multi-level storage chip being TCAM and a parallel basic SRAM group and an auxiliary SRAM group from high to low, the basic SRAM group comprising two levels of basic SRAM, and the auxiliary SRAM group comprising two levels of auxiliary SRAM;

[0009] The second-level prefix and the third part are stored by the two levels of basic SRAM.

[0010] The first-level prefix is stored in the TCAM, wherein the first-level prefix is a common prefix of the second-level prefix, and the second-level prefix is a common prefix of the third part.

[0011] For the basic SRAM, if the second-level prefix in the basic SRAM is covered by the first-level prefix in the TCAM, the second-level prefix in the basic SRAM and the first-level prefix in the TCAM are copied to the auxiliary SRAM of the same level as the basic SRAM.

[0012] In an optional implementation, the two levels of basic SRAM comprise a first basic SRAM and a second basic SRAM.

[0013] The step of storing the second-level prefix and the third part by the two levels of basic SRAM comprises:

[0014] The third part is stored by a table entry of the second basic SRAM.

[0015] The second-level prefix is stored in a table entry of the first basic SRAM, and a pointer of the second-level prefix points to a table entry storing the third part in the second basic SRAM.

[0016] In an optional implementation, the two levels of auxiliary SRAM comprise a first auxiliary SRAM and a second auxiliary SRAM.

[0017] When the second level prefix in the first base SRAM is covered by the first level prefix in the TCAM, the first level prefix in the TCAM and the second level prefix in the first base SRAM are copied into the entry of the first auxiliary SRAM in the order of the first level prefix in front, the second level prefix behind and the two level prefixes being continuous;

[0018] When the second level prefix in the first base SRAM is covered by the first level prefix in the TCAM, the first level prefix in the TCAM and the second level prefix in the first base SRAM are copied into the entry of the first auxiliary SRAM in the order of the first level prefix in front, the second level prefix behind and the two level prefixes being continuous;

[0019] The index information of the entry of the first auxiliary SRAM is assigned to the second pointer of the entry of the TCAM storing the first level prefix;

[0020] The third part stored in the second base SRAM and indexed by the pointer of the second level prefix in the first base SRAM is moved into the entry of the second auxiliary SRAM, and the index information of the entry of the second auxiliary SRAM is assigned to the pointer of the entry of the first auxiliary SRAM.

[0021] In an optional embodiment, the method further comprises:

[0022] Obtaining a to-be-forwarded packet and obtaining NAPT information in the to-be-forwarded packet, the NAPT information being a routing address plus a port number;

[0023] Searching the TCAM based on the NAPT information, and searching a first level prefix having the longest match with the NAPT information according to the longest match principle;

[0024] Searching the base SRAM group based on the first pointer of the first level prefix pointing to the base SRAM group, if the base SRAM group has an information entry consistent with the NAPT information, forwarding the to-be-forwarded packet based on the information entry in the base SRAM group, otherwise, searching the auxiliary SRAM group based on the second pointer of the first level prefix pointing to the auxiliary SRAM group, and forwarding the to-be-forwarded packet based on the information entry in the auxiliary SRAM group.

[0025] In an optional embodiment, the step of searching the base SRAM group based on the first pointer of the first level prefix pointing to the base SRAM group, if the base SRAM group has an information entry consistent with the NAPT information, forwarding the to-be-forwarded packet based on the information entry in the base SRAM group, otherwise, searching the auxiliary SRAM group based on the second pointer of the first level prefix pointing to the auxiliary SRAM group, and forwarding the to-be-forwarded packet based on the information entry in the auxiliary SRAM group, comprises:

[0026] finding the first base SRAM based on the first pointer of the first level prefix pointing to the first base SRAM, matching the NAPT information with the second level prefix in the first base SRAM except the part covered by the first level prefix, determining the longest matching second level prefix, and obtaining the pointer of the second level prefix;

[0027] finding the second base SRAM based on the pointer of the second level prefix of the first base SRAM, matching the NAPT information with the third part in the second base SRAM except the part covered by the first level prefix and the second level prefix, determining the longest matching third part, and forwarding the to-be-forwarded packet based on the next hop information of the third part.

[0028] In an optional embodiment, the step of finding the auxiliary SRAM group based on the second pointer of the first level prefix pointing to the auxiliary SRAM group, and forwarding the to-be-forwarded packet based on the information entry in the auxiliary SRAM group, comprises:

[0029] finding the first auxiliary SRAM based on the second pointer of the first level prefix pointing to the first auxiliary SRAM, matching the NAPT information with the information entry in the first auxiliary SRAM, determining the longest matching information entry, and obtaining the pointer of the information entry;

[0030] finding the second auxiliary SRAM based on the pointer of the information entry of the first auxiliary SRAM, matching the NAPT information with the information entry in the second auxiliary SRAM except the part covered by the information entry in the first auxiliary SRAM, determining the longest matching information entry, and forwarding the to-be-forwarded packet based on the next hop information of the information entry.

[0031] In an optional embodiment, the port number is a protocol port number of TCP or UDP.

[0032] In a second aspect, the present application provides a NAPT entry management device, which comprises:

[0033] a setting module, configured to set a multi-level storage chip to store the table entry information of the NAPT table, the table entry information being a routing address plus a port number, the table entry information being divided into three continuous and non-repeated information entries, the three information entries being a first level prefix, a second level prefix, and a third part except the first level prefix and the second level prefix, the multi-level storage chip being TCAM and a base SRAM group and an auxiliary SRAM group arranged in parallel from high to low, the base SRAM group comprising two base SRAMs, and the auxiliary SRAM group comprising two auxiliary SRAMs.

[0034] The first storage module is configured to store the second-level prefix and the third part in the two-level base SRAM.

[0035] The second storage module is configured to store the first-level prefix in the TCAM, wherein the first-level prefix is a common prefix of the second-level prefix, and the second-level prefix is a common prefix of the third part.

[0036] The third storage module is configured to, for the base SRAM, if the second-level prefix in the base SRAM is covered by the first-level prefix in the TCAM, copy the second-level prefix in the base SRAM and the first-level prefix in the TCAM into an auxiliary SRAM at the same level as the base SRAM.

[0037] In a third aspect, the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the method of any one of the above aspects.

[0038] In a fourth aspect, the present application provides a computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is configured to execute the method of any one of the above aspects when running.

[0039] The beneficial effects of the embodiments of the present application include, for example:

[0040] The present application provides a NAPT entry management method and device, electronic equipment and storage medium, and sets multiple levels of storage chips to store the table entry information of NAPT, including TCAM and two levels of base SRAM and two levels of auxiliary SRAM in parallel. The TCAM and the two levels of base SRAM store the first-level prefix, the second-level prefix and the third part of the table entry information in order from high to low. In this way, the first-level prefix and the second-level prefix of the table entry information can be stored in the TCAM and the first base SRAM, and the third part is stored in the second base SRAM, thereby effectively reducing the storage space required by the table entry information, and expanding the specification of NAPT under the condition of the same storage chip resources. In addition, the auxiliary SRAM is additionally provided, and the table entry information copied in the auxiliary SRAM is used to solve the influence caused by routing coverage, so as to avoid the situation that the table entry information is covered and the packet forwarding cannot be accurately performed. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0042] Figure 1 A schematic diagram for network address translation in packet forwarding;

[0043] Figure 2 A schematic diagram for storing routing addresses in TCAM in the prior art;

[0044] Figure 3 A schematic diagram for storing routing addresses in SRAM in the prior art;

[0045] Figure 4 A flowchart of the NAPT entry management method provided by the embodiments of the present application;

[0046] Figure 5 A schematic diagram for the case that routing coverage exists in chip resources provided by the embodiments of the present application;

[0047] Figure 6 A schematic diagram for the logical relationship between routing trees and chip resources provided by the embodiments of the present application;

[0048] Figure 7 A schematic diagram for the relationship between chip resources provided by the embodiments of the present application;

[0049] Figure 8 A flowchart of the packet forwarding method in the NAPT entry management method provided by the embodiments of the present application;

[0050] Figure 9 A flowchart of the whole packet forwarding process provided by the embodiments of the present application;

[0051] Figure 10 A function module block diagram of the NAPT entry management device provided by the embodiments of the present application;

[0052] Figure 11 A structure block diagram of the electronic device provided by the embodiments of the present application.

[0053] Icon: 110-NAPT entry management device; 111-setting module; 112-first storage module; 113-second storage module; 114-third storage module; 120-processor; 130-memory; 140-communication module. DETAILED DESCRIPTION

[0054] Please refer toFigure 1 When a message accessing the Internet passes through a NAT gateway, the NAT gateway replaces the source IP address in the original message with a legal public network address and records the conversion. When the message returns from the Internet side, the NAT gateway looks up the original record, replaces the destination address of the message back to the original private network address, and sends it back to the host that made the request.

[0055] NAPT allows multiple internal addresses to be mapped to the same public address, and through the use of "IP address + port number" conversion, multiple private network users can share a public network IP address to access the external network.

[0056] Table 1 NAPT table

[0057] IP L4 Port 230.255.128.0 / 17 16383 230.255.128.0 / 17 16382 230.255.128.0 / 17 16381 230.255.128.0 / 17 16380 230.254.1.128 / 25 16370 230.254.1.128 / 25 16371 230.254.1.128 / 25 16372 230.254.1.128 / 25 16373 230.252.2.128 / 25 16350 230.252.2.128 / 25 16351 230.252.2.128 / 25 16352 230.252.2.128 / 25 16353 230.253.1.1 / 32 16360 230.253.1.1 / 32 16361 230.253.1.1 / 32 16362 230.253.1.1 / 32 16363

[0058] In the prior art, when there are 12 NAPT table entries as shown in Table 1, the existing method uses TCAM or SRAM to store the NAPT table entries, wherein the entries with masklen of the IP address less than 32 are stored in the TCAM, and the entries with masklen equal to 32 are stored in the SRAM, as shown in Figure 2 , Figure 3

[0059] As can be seen from Figure 2 , 3 , each NAPT in the prior art occupies one TCAM or SRAM entry. Each TCAM or SRAM entry indexes a Nexthop, which is used to obtain the egress and edit information of the message. Since the routing and port number in NAPT are in a one-to-many relationship, for multiple NAPT entries with the same IP but different L4 Port, the same number of complete TCAM or SRAM entries will be occupied. This storage method will cause a large waste of TCAM or SRAM resources.

[0060] Based on the above research findings, the present application provides a NAPT table entry management scheme, which sets multiple levels of storage chips from high to low based on levels, and sequentially stores the first level prefix, the second level prefix and the third part. In this way, the first level prefix and the second level prefix of the table entry information can be stored by TCAM and the first basic SRAM, and the second basic SRAM only stores the third part, thereby effectively reducing the storage space required by the table entry information, and expanding the NAPT specification under the same chip resources.

[0061] Further, an auxiliary SRAM is added, and the information entries copied in the auxiliary SRAM are used to solve the influence caused by routing coverage, so as to avoid the situation that the information entries are covered and the message forwarding cannot be accurately performed. ​

[0062] So that the purposes, technical solutions and advantages of the embodiments of the present application are more apparent, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0063] Therefore, the detailed description of the embodiments of the present application provided below in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0064] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0065] In the description of the present application, it should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0066] The embodiments of the present application provide a NAPT entry management method, Figure 4 For the flowchart of the NAPT entry management method according to the embodiments of the present application, the NAPT entry management method can be executed by a NAPT entry management device, which can be realized by software and / or hardware and can be configured in an electronic device. The detailed steps of the NAPT entry management method are introduced as follows.

[0067] S11, a multi-level storage chip is set to store table entry information of a NAPT table.

[0068] Wherein, the table entry information is a routing address plus a port number, the table entry information is divided into three continuous and non-repeating information entries, the three information entries are a first-level prefix, a second-level prefix and a third part remaining except the first-level prefix and the second-level prefix, the multi-level storage chip is TCAM and a parallel basic SRAM group and an auxiliary SRAM group from high to low, the basic SRAM group includes two basic SRAMs, and the auxiliary SRAM group includes two auxiliary SRAMs.

[0069] Wherein, the port number is a protocol port number of TCP (Transmission Control Protocol) or UDP (User Datagram Protocol).

[0070] S12, storing the second level prefix and the third part in the two-level base SRAM.

[0071] S13, storing the first level prefix into the TCAM, wherein the first level prefix is a common prefix of the second level prefix, and the second level prefix is a common prefix of the third part.

[0072] S14, for the base SRAM, if the second level prefix in the base SRAM is covered by the first level prefix in the TCAM, copying the second level prefix in the base SRAM and the first level prefix in the TCAM into an auxiliary SRAM at the same level as the base SRAM.

[0073] The NAPT entry management scheme provided by the embodiment can be applied to, but is not limited to, an Ethernet environment with high real-time requirement for data transmission, such as a data center network and an industrial network.

[0074] In the embodiment, the multi-level storage chip is a TCAM and a base SRAM group and an auxiliary SRAM group arranged in parallel, wherein the base SRAM group includes two levels of base SRAM, and the auxiliary SRAM group includes two levels of auxiliary SRAM. It should be noted that the scheme in the embodiment can also be applied to a scenario of multi-level TCAM, multi-level base SRAM and multi-level auxiliary SRAM, that is, the scheme provided by the embodiment is applicable to a scenario of not limited to two levels of SRAM and not limited to one level of TCAM. The embodiment does not make a specific limitation thereon, and the number of levels of TCAM, base SRAM and auxiliary SRAM can be set according to requirements.

[0075] In the embodiment, the entry information of the NAPT table is a routing address plus a port number, and the port number is a protocol port number of TCP or UDP. The entry information may, for example, be IPv4+L4 Port or IPv6+L4 Port.

[0076] Based on the order from high to low, the first level prefix and the second level prefix in the entry information can be stored by the TCAM and the first base SRAM, and the third part is stored in the second base SRAM, so as to effectively reduce the required storage space of the entry information, and expand the specification of NAPT in the case of the same storage chip resource.

[0077] In the embodiment, the routing tree algorithm is used for splitting and storing IP+L4Port. In the calculation process of the routing tree algorithm, the problem of route coverage may occur, for example Figure 5As shown in the figure, assuming the case of having one level of TCAM and one level of SRAM. If the route address in the packet received at this time is 230.255.0.0+16350, according to the characteristics of TCAM, it will definitely match the prefix 230.255.0.0 / 16 first, however, there is no corresponding entry in the SRAM entry of the Pointer index, thus leading to packet forwarding error. However, at this time, the SRAM has the entry of 230.255.0.0 / 16+16350, which is indexed by the prefix 230.0.0.0 / 8. In other words, 230.255.0.0 / 16+16350 is covered by the prefix 230.255.0.0 / 16.

[0078] If extended to the scenario of two SRAMs (SRAM1 and SRAM2), the TCAM prefix covers not IP+L4Port, but the prefix in SRAM1, and also the IP+L4Port tree indexed by the prefix in SRAM1. In other words, the TCAM prefix covers multiple IP+L4Ports.

[0079] In the embodiment, in order to solve the above-mentioned problems, an auxiliary SRAM group is additionally provided. For the basic SRAM, if the second level prefix in the basic SRAM is covered by the first level prefix in the TCAM, the second level prefix in the basic SRAM and the first level prefix in the TCAM can be correspondingly copied to the auxiliary SRAM of the same level as the basic SRAM.

[0080] In the embodiment, the auxiliary SRAM is additionally provided to solve the situation that the second level prefix in the basic SRAM is covered, thus leading to the situation that the subsequent packet forwarding cannot be accurately performed.

[0081] In the embodiment, in a possible implementation manner, the two level basic SRAMs in the basic SRAM group include a first basic SRAM and a second basic SRAM. The step of storing the second level prefix and the third part by the two level basic SRAM can be implemented in the following manner:

[0082] The third part is stored by the entry of the second basic SRAM;

[0083] The second level prefix is stored in the entry of the first basic SRAM, and the pointer of the second level prefix points to the entry of the second basic SRAM storing the third part.

[0084] Please refer to Figure 6 Take the case of having one level of TCAM and two level of SRAM (SRAM1 and SRAM2) as an example. The logical relationship between the route tree and the chip resources is as shown in the figure Figure 6As shown in FIG. 1, the three-level NAPT tree divides the complete NAPT table entry information into three continuous but non-overlapping NAPT information segments according to the Trie algorithm, and stores the segments into the three-level chip resources (TCAM, SRAM1, SRAM2). That is, the NAPT segments stored in the three-level NAPT tree collectively constitute a complete NAPT table entry information, and each level only stores the NAPT information segment of its corresponding length. Each tree in the SRAM2 is called NAPT tree.

[0085] In the embodiment, the two-level auxiliary SRAM in the auxiliary SRAM group includes a first auxiliary SRAM and a second auxiliary SRAM. In a possible implementation, the information segment can be stored by the following method:

[0086] When the second-level prefix in the first basic SRAM is covered by the first-level prefix in the TCAM, the first-level prefix in the TCAM and the second-level prefix in the first basic SRAM are copied into the table entry of the first auxiliary SRAM in the order of the first-level prefix first, the second-level prefix second, and the two prefixes being continuous.

[0087] The index information of the table entry of the first auxiliary SRAM is assigned to the second pointer of the table entry storing the first-level prefix in the TCAM.

[0088] The third part storing the second-level prefix in the second basic SRAM indexed by the pointer of the second-level prefix in the first basic SRAM is moved to the table entry of the second auxiliary SRAM, and the index information of the table entry of the second auxiliary SRAM is assigned to the pointer of the table entry of the first auxiliary SRAM.

[0089] Please refer to the schematic diagram of the relationship between the chip resources shown in FIG. 1, wherein the ALPM SRAM1 and the ALPM SRAM2 are two-level basic SRAM, and the ALPM SRAM1 Ext and the ALPM SRAM2 Ext are two-level auxiliary SRAM. Figure 7

[0090] Among them, the size of the SRAM1 Ext is at most one fourth of the size of the SRAM1, and the size of the SRAM2 Ext is at most one fourth of the size of the SRAM2.

[0091] The NAPT table entry information segments are stored in the TCAM, the ALPM SRAM1 and the ALPM SRAM2 (or the ALPM SRAM1 Ext and the ALPM SRAM2 Ext).

[0092] ​The common prefix of the third part stored in the same SRAM2 or SRAM2 Ext, i.e. the second level prefix, is stored in SRAM1 or SRAM1 Ext. The common prefix of the second level prefix stored in the same SRAM1, i.e. the first level prefix, is stored in TCAM. Each entry corresponding to the third part has a next hop (Nexthop), the entry corresponding to the second level prefix in SRAM1 has a next hop, and the entry corresponding to the first level prefix in TCAM has a next hop.

[0093] It should be noted that if the common prefix (*) in SRAM1 is not covered, it should be normally stored in SRAM1, and the NAPT tree with the Pointer index should be normally stored in SRAM2. If the common prefix (*) in SRAM1 is covered, the common prefix (**) information of the TCAM indexing the common prefix (*) should be copied to SRAM1 Ext (A) together with the common prefix (*), i.e. the prefix information covered by len1 (the length of the common prefix in TCAM) + len2 (the length of the common prefix in SRAM1) should be copied to SRAM1 Ext (A). Meanwhile, the index of SRAM1 Ext (A) is assigned to the Pointer2 (the second pointer) of the common prefix in TCAM. Meanwhile, the information of the NAPT tree stored in SRAM2 with the Pointer index in SRAM1 is moved to SRAM2 Ext (A), and the index of SRAM2 Ext (A) is assigned to the Pointer of SRAM1 Ext (A).

[0094] In this embodiment, the entry information (IP + L4 Port) of the NAPT forwarding table is taken as a whole, TCAM, SRAM1 (SRAM1 Ext) store the first level prefix and the second level prefix respectively, and SRAM2 (SRAM2 Ext) stores the third part of the entry information except the first level prefix and the second level prefix. Therefore, the length of the entry stored in TCAM, SRAM1 and SRAM1 Ext can be greatly shortened, and the number of the entry information of the NAPT forwarding table that can be stored after each TCAM, SRAM1 and SRAM1 Ext is greatly increased, so as to reduce the use of TCAM, SRAM1 and SRAM1 Ext, thereby reducing the chip cost and expanding the NAPT specification.

[0095] It should be noted that in the actual chip design process, the number of NAPT segments that can be stored by an SRAM Entry needs to be determined according to the specific SRAM resource allocation and the specific NAPT segment length (in the case of the same SRAM entry, the longer the NAPT segment length, the more segments are stored). In general, using LPM to manage NAPT entries can greatly improve the utilization of chip resources compared to the prior art.

[0096] The above process can be understood as a pre-configuration phase. Based on the above, please refer to Figure 8 In the actual application stage, the NAPT entry management method provided by the embodiment can further include the following steps:

[0097] S21, obtaining a to-be-forwarded packet and obtaining NAPT information in the to-be-forwarded packet, the NAPT information being a routing address plus a port number.

[0098] S22, searching the TCAM based on the NAPT information, and searching a first-level prefix having the longest match with the NAPT information according to the longest match principle;

[0099] S23, searching the basic SRAM group based on a first pointer of the basic SRAM group pointed by the first-level prefix, if there is an information entry consistent with the NAPT information in the basic SRAM group, forwarding the to-be-forwarded packet based on the information entry in the basic SRAM group, otherwise, searching the auxiliary SRAM group based on a second pointer of the auxiliary SRAM group pointed by the first-level prefix, and forwarding the to-be-forwarded packet based on the information entry in the auxiliary SRAM group.

[0100] In the embodiment, the NAPT information in the to-be-forwarded packet obtained can be IP+L4 Port. The step of searching the basic SRAM group in the above step S23 can be implemented by the following way:

[0101] Searching the first basic SRAM based on a first pointer of the first basic SRAM pointed by the first-level prefix, matching the remaining part of the NAPT information except the first-level prefix covered by the first-level prefix with the second-level prefix in the first basic SRAM, determining the second-level prefix having the longest match, and obtaining the pointer of the second-level prefix;

[0102] Searching the second basic SRAM based on the pointer of the second-level prefix of the first basic SRAM, matching the remaining part of the NAPT information except the first-level prefix and the second-level prefix covered by the first-level prefix and the second-level prefix with the third part in the second basic SRAM, determining the third part having the longest match, and forwarding the to-be-forwarded packet based on the next hop information of the third part.

[0103] Furthermore, if no information entry matching the NAPT information exists in the basic SRAM group, the step of searching the auxiliary SRAM group can be implemented in the following way:

[0104] The first auxiliary SRAM is searched based on the second pointer pointing to the first auxiliary SRAM using the first-level prefix. The NAPT information is used to match the information entries in the first auxiliary SRAM to determine the longest matching table information entry and obtain the pointer to that information entry.

[0105] The second auxiliary SRAM is searched based on the pointer of the table entry information of the first auxiliary SRAM. The remaining part of the NAPT information after removing the information entries in the first auxiliary SRAM is matched with the information entries in the second auxiliary SRAM to determine the longest matching information entry. The message to be forwarded is forwarded based on the next-hop information of the information entry.

[0106] Please refer to the following: Figure 9 Taking the NAPT information in the packet to be forwarded as IP+L4 Port as an example, and assuming that the chip resources are as follows: Figure 7 The diagram shows a single-level TCAM, two levels of basic SRAM, and two levels of auxiliary SRAM. The following is a combination of... Figure 7 and Figure 9 The process of forwarding messages is described below.

[0107] After receiving a packet containing NAPT information for the IP+L4 Port, the system searches for a common prefix in the TCAM based on the IP+L4 Port, finds the information entry with the highest matching degree with the IP+L4 Port, and records the length len1 of the longest match. If no matching information entry is found, the packet is discarded.

[0108] After finding the information entry with the highest matching degree, obtain the corresponding pointer1, pointer2, and nexthop_tcam. If pointer1 is valid, search for the best-matching information entry in SRAM1 indexed by pointer1 according to the longest match principle. In this step, use the portion of the IP+L4 Port excluding len1 covered by pointer1 to perform a line-by-line matching with the entries corresponding to SRAM1, find the longest-matching entry, and record the length of the longest match, len2. If found in SRAM1, obtain the corresponding pointer and Nexthop_tcam1.

[0109] In the case that the Pointer and the Nexthop_sram1 corresponding to the information entry are obtained, if the Pointer is valid, the longest matching principle is used to find the longest matching information entry in the SRAM2 indexed by the Pointer. In this step, the table entry corresponding to the SRAM2 is matched with the IP+L4 Port excluding the part covered by len1+len2, and a longest matching table entry is found, and a Nexthop (Nexthop_sram2) is obtained.

[0110] If the longest matching table entry is not found in the SRAM1 or the SRAM2, the SRAM1 Ext is indexed by the pointer2 obtained from the TCAM to obtain the corresponding entry. In this step, the entry corresponding to the SRAM1 Ext is matched with the complete IP+L4 Port, and if the matching is successful, the matching length len3 is recorded, and the Pointer corresponding to the matched information entry is obtained. The entry is matched with the IP+L4 Port excluding the part covered by len1+len3 in the SRAM2 Ext indexed by the Pointer according to the longest matching principle, and a longest matching entry is found. If the longest matching entry is found, a Nexthop (Nexthop_sram2_ext) is obtained.

[0111] In this process, finally, according to the longest matching principle, the priority of the nexthop of the SRAM2 or the SRAM2 Ext is higher than that of the SRAM1 nexthop, and higher than that of the TCAM nexthop. Finally, the nexthop with the highest priority is used for packet forwarding.

[0112] Based on the same application concept, please refer to Figure 10 , a functional module schematic diagram of the NAPT table management device 110 provided by the embodiment of the present application is shown, and the NAPT table management device 110 can be divided into functional modules according to the method embodiment. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The integrated module can be realized in the form of hardware or in the form of a software functional module. It should be noted that the division of the modules in the embodiment of the present application is illustrative, and is only a logical function division. When actually implemented, another division method can be used.

[0113] For example, in the case of dividing each functional module according to each function, Figure 10The illustrated NAPT table item management apparatus 110 is only a device schematic diagram. The NAPT table item management apparatus 110 can include a setting module 111, a first storage module 112, a second storage module 113, and a third storage module 114. The functions of the respective functional modules of the NAPT table item management apparatus 110 are described in detail below.

[0114] The setting module 111 is configured to set a multi-level storage chip to store table item information of a NATP table, the table item information being a routing address plus a port number, the table item information being divided into three continuous and non-repeated information entries, the three information entries being a first-level prefix, a second-level prefix, and a third part remaining except the first-level prefix and the second-level prefix, the multi-level storage chip being TCAM and a parallel basic SRAM group and an auxiliary SRAM group from high to low, the basic SRAM group including two levels of basic SRAM, and the auxiliary SRAM group including two levels of auxiliary SRAM.

[0115] It can be understood that the setting module 111 can be configured to perform the above step S11, and the detailed implementation of the setting module 111 can be referred to the above description about step S11.

[0116] The first storage module 112 is configured to store the second-level prefix and the third part through the two levels of basic SRAM.

[0117] It can be understood that the first storage module 112 can be configured to perform the above step S12, and the detailed implementation of the first storage module 112 can be referred to the above description about step S12.

[0118] The second storage module 113 is configured to store the first-level prefix into the TCAM, wherein the first-level prefix is a common prefix of the second-level prefix, and the second-level prefix is a common prefix of the third part.

[0119] It can be understood that the second storage module 113 can be configured to perform the above step S13, and the detailed implementation of the second storage module 113 can be referred to the above description about step S13.

[0120] The third storage module 114 is configured to, for the basic SRAM, if the second-level prefix in the basic SRAM is covered by the first-level prefix in the TCAM, copy the second-level prefix in the basic SRAM and the first-level prefix in the TCAM into an auxiliary SRAM at the same level as the basic SRAM.

[0121] It can be understood that the third storage module 114 can be used to execute the step S14, and the detailed implementation of the third storage module 114 can refer to the above description about the step S14.

[0122] In a possible implementation, the two-level basic SRAM includes a first basic SRAM and a second basic SRAM.

[0123] The first storage module 112 is used to:

[0124] The third part is stored in the entry of the second basic SRAM.

[0125] The second-level prefix is stored in the entry of the first basic SRAM, and a pointer of the second-level prefix points to the entry of the second basic SRAM storing the third part.

[0126] In a possible implementation, the two-level auxiliary SRAM includes a first auxiliary SRAM and a second auxiliary SRAM.

[0127] The third storage module 114 is used to:

[0128] When the second-level prefix in the first basic SRAM is covered by the first-level prefix in the TCAM, the first-level prefix in the TCAM and the second-level prefix in the first basic SRAM are copied into the entry of the first auxiliary SRAM in the order of the first-level prefix in front, the second-level prefix behind, and the two-level prefixes being continuous.

[0129] Index information of the entry of the first auxiliary SRAM is assigned to the second pointer of the entry storing the first-level prefix in the TCAM.

[0130] The third part stored in the second basic SRAM and indexed by the pointer of the second-level prefix in the first basic SRAM is moved to the entry of the second auxiliary SRAM, and index information of the entry of the second auxiliary SRAM is assigned to the pointer of the entry of the first auxiliary SRAM.

[0131] In a possible implementation, the NAPT entry management apparatus 110 further includes a forwarding module, which is used to:

[0132] Obtain a to-be-forwarded packet, and obtain NAPT information in the to-be-forwarded packet, the NAPT information being a routing address plus a port number;

[0133] Search the TCAM based on the NAPT information, and find a first-level prefix having the longest match with the NAPT information according to the longest match principle;

[0134] searching the base SRAM group based on a first pointer of the first level prefix pointing to the base SRAM group, if there is an information entry in the base SRAM group consistent with the NAPT information, forwarding the to-be-forwarded packet based on the information entry in the base SRAM group, otherwise, searching the auxiliary SRAM group based on a second pointer of the first level prefix pointing to the auxiliary SRAM group, and forwarding the to-be-forwarded packet based on an information entry in the auxiliary SRAM group.

[0135] In a possible implementation, the forwarding module is used for:

[0136] searching the first base SRAM based on a first pointer of the first level prefix pointing to the first base SRAM, matching a second level prefix in the first base SRAM with a part of the NAPT information remaining after the first level prefix is covered, determining a longest-matched second level prefix, and obtaining a pointer of the second level prefix;

[0137] searching the second base SRAM based on a pointer of the second level prefix of the first base SRAM, matching a third part in the second base SRAM with a part of the NAPT information remaining after the first level prefix and the second level prefix are covered, determining a longest-matched third part, and forwarding the to-be-forwarded packet based on next-hop information of the third part.

[0138] In a possible implementation, the forwarding module is used for:

[0139] searching the first auxiliary SRAM based on a second pointer of the first level prefix pointing to the first auxiliary SRAM, matching an information entry in the first auxiliary SRAM with the NAPT information, determining a longest-matched information entry, and obtaining a pointer of the information entry;

[0140] searching the second auxiliary SRAM based on a pointer of the information entry of the first auxiliary SRAM, matching an information entry in the second auxiliary SRAM with a part of the NAPT information remaining after the information entry in the first auxiliary SRAM is covered, determining a longest-matched information entry, and forwarding the to-be-forwarded packet based on next-hop information of the information entry.

[0141] In a possible implementation, the port number is a protocol port number of TCP or UDP.

[0142] For details, please refer to Figure 11A structural block diagram of an electronic device is provided in the embodiments of the present application, and the electronic device can be a gateway device. The electronic device comprises a memory 130, a processor 120 and a communication module 140. The memory 130, the processor 120 and the communication module 140 are electrically connected with each other directly or indirectly to realize data transmission or interaction. For example, the elements can be electrically connected with each other through one or more communication buses or signal lines.

[0143] The memory 130 is configured to store programs or data.

[0144] The processor 120 is configured to read / write the data or programs stored in the memory 130 and execute the NAPT entry management method provided in any of the embodiments of the present application.

[0145] The communication module 140 is configured to establish a communication connection between the electronic device and other communication terminals through a network and to receive / transmit data through the network.

[0146] It should be understood that, Figure 11 The structure shown is only a structural schematic diagram of the electronic device, and the electronic device can further comprise more or less components than those shown in the embodiments of the present application or have a different configuration from that shown in the embodiments of the present application. Figure 11 Figure 11

[0147] The embodiments of the present application further provide a computer readable storage medium, and the computer readable storage medium stores a computer program. The computer program is configured to execute any of the above methods when running.

[0148] Optionally, in the embodiments, the storage medium can include but is not limited to a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk and various program code storage media.

[0149] Optionally, specific examples in the embodiments can refer to the examples described in the above embodiments and optional implementation manners, and the embodiments will not be described herein again.

[0150] ​​In summary, the NAPT entry management method and device, the electronic device and the storage medium provided by the embodiments of the present application set multiple levels of storage chips to store the table entry information of the NAPT table, including TCAM and two levels of basic SRAM and two levels of auxiliary SRAM arranged in parallel. The TCAM and the two levels of basic SRAM store the first level prefix, the second level prefix and the third part of the table entry information in turn in the order from high to low. In this way, the first level prefix and the second level prefix in the table entry information can be stored through the TCAM and the first basic SRAM, and the third part is stored in the second basic SRAM, so as to effectively reduce the storage space required by the table entry information, and expand the specification of the NAPT in the case of the same storage chip resources. In addition, the auxiliary SRAM is additionally arranged, and the copied table entry information in the auxiliary SRAM is used to solve the influence caused by the routing coverage, so as to avoid the situation that the table entry information is covered and the packet forwarding cannot be accurately performed.

[0151] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for managing NAPT entries, characterized in that, The method comprises: Setting a multi-level storage chip to store table item information of the NATP table, the table item information being a routing address plus a port number, the table item information being divided into three continuous and non-repeated information items, the three information items being a first-level prefix, a second-level prefix, and a third part remaining except the first-level prefix and the second-level prefix, the multi-level storage chip being in order from high to low a TCAM and a parallel basic SRAM group, an auxiliary SRAM group, the basic SRAM group comprising two-level basic SRAM, the auxiliary SRAM group comprising two-level auxiliary SRAM, the two-level basic SRAM comprising a first basic SRAM and a second basic SRAM, the two-level auxiliary SRAM comprising a first auxiliary SRAM and a second auxiliary SRAM; storing the second-level prefix and the third part through the two-level basic SRAM; storing the first-level prefix into the TCAM, wherein the first-level prefix is a common prefix of the second-level prefix, and the second-level prefix is a common prefix of the third part; for the basic SRAM, if the second-level prefix in the basic SRAM is covered by the first-level prefix in the TCAM, copying the second-level prefix in the basic SRAM and the first-level prefix in the TCAM into the auxiliary SRAM at the same level as the basic SRAM, which comprises: when the second-level prefix in the first basic SRAM is covered by the first-level prefix in the TCAM, copying the first-level prefix in the TCAM and the second-level prefix in the first basic SRAM into the table item of the first auxiliary SRAM in a manner that the first-level prefix is in front, the second-level prefix is behind, and the two-level prefixes are continuous; assigning index information of the table item of the first auxiliary SRAM to a second pointer of a table item in the TCAM storing the first-level prefix; moving the third part stored in the second basic SRAM indexed by a pointer of the second-level prefix in the first basic SRAM to a table item of the second auxiliary SRAM, and assigning index information of the table item of the second auxiliary SRAM to the pointer of the table item of the first auxiliary SRAM.

2. The NAPT entry management method according to claim 1, characterized by, The step of storing the second-level prefix and the third part through the two-level basic SRAM comprises: storing the third part through a table item of the second basic SRAM; storing the second-level prefix into a table item of the first basic SRAM, and pointing a pointer of the second-level prefix to a table item storing the third part in the second basic SRAM.

3. The NAPT entry management method according to claim 2, wherein The method further comprises: obtaining a to-be-forwarded packet, and obtaining NAPT information in the to-be-forwarded packet, the NAPT information being a routing address plus a port number; based on the NAPT information, searching the TCAM, and searching a first-level prefix having the longest match with the NAPT information according to a longest match principle; The first SRAM group is searched based on the first pointer pointing to the first SRAM group according to the first level prefix, if there is an information entry consistent with the NAPT information in the first SRAM group, the to-be-forwarded packet is forwarded based on the information entry in the first SRAM group, otherwise, the second SRAM group is searched based on the second pointer pointing to the second SRAM group according to the first level prefix, and the to-be-forwarded packet is forwarded based on the information entry in the second SRAM group.

4. The NAPT entry management method according to claim 3, wherein The step of searching the first SRAM group based on the first pointer pointing to the first SRAM group according to the first level prefix, if there is an information entry consistent with the NAPT information in the first SRAM group, forwarding the to-be-forwarded packet based on the information entry in the first SRAM group, otherwise, searching the second SRAM group based on the second pointer pointing to the second SRAM group according to the first level prefix, and forwarding the to-be-forwarded packet based on the information entry in the second SRAM group, comprises: The first SRAM group is searched based on the first pointer pointing to the first SRAM group according to the first level prefix, if there is an information entry consistent with the NAPT information in the first SRAM group, the to-be-forwarded packet is forwarded based on the information entry in the first SRAM group, otherwise, the second SRAM group is searched based on the second pointer pointing to the second SRAM group according to the first level prefix, and the to-be-forwarded packet is forwarded based on the information entry in the second SRAM group. The first SRAM group is searched based on the first pointer pointing to the first SRAM group according to the first level prefix, if there is an information entry consistent with the NAPT information in the first SRAM group, the to-be-forwarded packet is forwarded based on the information entry in the first SRAM group, otherwise, the second SRAM group is searched based on the second pointer pointing to the second SRAM group according to the first level prefix, and the to-be-forwarded packet is forwarded based on the information entry in the second SRAM group.

5. The NAPT entry management method according to claim 3, wherein The first SRAM group is searched based on the first pointer pointing to the first SRAM group according to the first level prefix, if there is an information entry consistent with the NAPT information in the first SRAM group, the to-be-forwarded packet is forwarded based on the information entry in the first SRAM group, otherwise, the second SRAM group is searched based on the second pointer pointing to the second SRAM group according to the first level prefix, and the to-be-forwarded packet is forwarded based on the information entry in the second SRAM group. The port number is a protocol port number of TCP or UDP. The device for implementing the NAPT entry management method of any one of claims 1-6 comprises:

6. The NAPT entry management method of claim 1, wherein, The device for implementing the NAPT entry management method of any one of claims 1-6 comprises:

7. A NAPT entry management apparatus characterized by comprising: ​ The setting module is configured to set a multi-level storage chip to store table item information of the NATP table, the table item information being a routing address plus a port number, the table item information being divided into three continuous and non-repeated information items, the three information items being a first-level prefix, a second-level prefix, and a third part remaining except the first-level prefix and the second-level prefix, the multi-level storage chip being in a high-to-low order of a TCAM and a parallel basic SRAM group, the basic SRAM group including two levels of basic SRAM, and an auxiliary SRAM group including two levels of auxiliary SRAM; The first storage module is configured to store the second-level prefix and the third part through the two levels of basic SRAM; The second storage module is configured to store the first-level prefix into the TCAM, wherein the first-level prefix is a common prefix of the second-level prefix, and the second-level prefix is a common prefix of the third part; The third storage module is configured to, for the basic SRAM, if the second-level prefix in the basic SRAM is covered by the first-level prefix in the TCAM, copy the second-level prefix in the basic SRAM and the first-level prefix in the TCAM into an auxiliary SRAM at the same level as the basic SRAM.

8. An electronic device comprising a memory and a processor, characterized in that The memory stores a computer program, and the processor is configured to run the computer program to execute the method in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the computer program is configured to execute the method in any one of claims 1 to 6 when running.

Images