A sensitive amplifier circuit and semiconductor memory

Abstract

The embodiment of the application provides a sensitive amplification circuit and a semiconductor memory, the sensitive amplification circuit comprises a discharge circuit and a signal amplification circuit, and the signal amplification circuit comprises a first cross-coupled tube group and a second cross-coupled tube group, and the discharge circuit is connected between the first cross-coupled tube group and the second cross-coupled tube group; wherein the discharge circuit is used for receiving a to-be-transmitted signal and a reference signal, and performing discharge processing based on the to-be-transmitted signal and the reference signal respectively to obtain a to-be-processed signal; and the signal amplification circuit is used for amplifying the to-be-processed signal to obtain a target amplified signal. In this way, the embodiment of the application provides a new sensitive amplification circuit, the discharge circuit is arranged between the two pairs of cross-coupled tube groups, the time required by the signal amplification process can be shortened, and the amplification performance of the sensitive amplification circuit is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory technology, and more particularly to a sensitive amplifier circuit and a semiconductor memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor storage device in computers, consisting of many repeating memory cells. During data retrieval, the data signal of each memory cell is read out sequentially via the local data line, the global data line, and the data bus.

[0003] Currently, there is a sensitive amplifier circuit between the global data line and the data bus. The data signal output from the global data line needs to be transmitted to the data bus through this sensitive amplifier circuit. However, the sensitivity of the sensitive amplifier circuit in related technologies needs to be improved, which affects the performance of DRAM. Summary of the Invention

[0004] This application provides a sensitive amplifier circuit and a semiconductor memory. By changing the circuit connection structure, the time required for the sensitive amplifier circuit to amplify signals is shortened, thereby improving the sensitivity of the sensitive amplifier circuit.

[0005] In a first aspect, embodiments of this application provide a sensitive amplifier circuit, which includes a discharge circuit and a signal amplification circuit. The signal amplification circuit includes a first cross-coupled transistor group and a second cross-coupled transistor group, and the discharge circuit is connected between the first cross-coupled transistor group and the second cross-coupled transistor group.

[0006] The discharge circuit is used to receive the signal to be transmitted and the reference signal, and to perform discharge processing on the signal to be transmitted and the reference signal respectively to obtain the signal to be processed;

[0007] A signal amplification circuit is used to amplify the signal to be processed to obtain the target amplified signal.

[0008] In some embodiments, the discharge circuit includes a first discharge circuit and a second discharge circuit; wherein, the first discharge circuit is used to receive a signal to be transmitted and perform discharge processing based on the signal to be transmitted to obtain a first signal to be processed; the second discharge circuit is used to receive a reference signal and perform discharge processing based on the reference signal to obtain a second signal to be processed; the signal amplification circuit is specifically used to amplify the first signal to be processed to obtain a first target amplified signal; and to amplify the second signal to be processed to obtain a second target amplified signal.

[0009] In some embodiments, the first discharge circuit has a first connection terminal on the side near the first cross-coupled transistor group, and the first discharge circuit has a second connection terminal on the side near the second cross-coupled transistor group; the first discharge circuit includes a first transistors, and the first pin of each of the a first transistors is connected to the signal to be transmitted, and the third pin of each of the a first transistors is connected to the second connection terminal; the second pin of each of the a first transistors is connected to the first connection terminal, and the first connection terminal is used to output a first signal to be processed, or to output a first target amplified signal; wherein, a is a positive integer.

[0010] In some embodiments, the second discharge circuit has a third connection terminal on the side near the first cross-coupled transistor group, and a fourth connection terminal on the side near the second cross-coupled transistor group; the second discharge circuit includes b second transistors, and the first pin of each of the b second transistors is connected to a reference signal, and the third pin of each of the b second transistors is connected to the fourth connection terminal; the second pin of each of the b second transistors is connected to the third connection terminal, and the third connection terminal is used to output a second signal to be processed, or to output a second target amplified signal; wherein b is a positive integer.

[0011] In some embodiments, the first cross-coupled transistor group includes a third transistor and a fourth transistor; wherein the first pin of the third transistor and the third pin of the fourth transistor are both connected to a third connection terminal; the third pin of the third transistor and the first pin of the fourth transistor are both connected to a first connection terminal; the second pin of the third transistor is connected to a first power supply signal, and the second pin of the fourth transistor is connected to a second power supply signal.

[0012] In some embodiments, the second cross-coupled transistor group includes a fifth transistor and a sixth transistor; wherein, the first pin of the fifth transistor is connected to a third connection terminal, and the first pin of the sixth transistor is connected to a first connection terminal; the second pin of the fifth transistor is connected to a second connection terminal, and the second pin of the sixth transistor is connected to a fourth connection terminal; the third pins of both the fifth and sixth transistors are connected to ground.

[0013] In some embodiments, when b is 4, the reference signal includes a first reference signal, a second reference signal, a third power supply signal, and a ground signal, and the b second transistors include a second first transistor, a second second transistor, a second third transistor, and a second fourth transistor; wherein, the first pin of the second first transistor is connected to the first reference signal, the first pin of the second second transistor is connected to the second reference signal, the first pin of the second third transistor is connected to the third power supply signal, and the first pin of the second fourth transistor is connected to the ground signal.

[0014] In some embodiments, the sensitive amplifier circuit further includes a first reference output circuit and a second reference output circuit; wherein the first reference output circuit is used to receive a first control signal and output a first reference signal according to the first control signal; and the second reference output circuit is used to receive a second control signal and output a second reference signal according to the second control signal.

[0015] In some embodiments, the first reference output circuit includes a seventh transistor, an eighth transistor, and a ninth transistor; wherein, the first pin of the seventh transistor is connected to the first pin of the eighth transistor for receiving a first control signal; the third pin of the seventh transistor is connected to the second pin of the eighth transistor and the first pin of the ninth transistor for outputting a first reference signal; the second pin of the seventh transistor is connected to a fourth power supply signal, the third pin of the eighth transistor is connected to a ground signal, and both the second and third pins of the ninth transistor are connected to ground signals.

[0016] In some embodiments, the second reference output circuit includes a tenth transistor, an eleventh transistor, and a twelfth transistor; a first pin of the tenth transistor is connected to a first pin of the eleventh transistor for receiving a second control signal; a third pin of the tenth transistor is connected to a second pin of the eleventh transistor and a first pin of the twelfth transistor for outputting a second reference signal; a second pin of the tenth transistor is connected to a fifth power supply signal, a third pin of the eleventh transistor is connected to a ground signal, and both the second and third pins of the twelfth transistor are connected to ground signals.

[0017] In some embodiments, the sensitive amplification circuit further includes a pre-charge circuit; the pre-charge circuit is used to receive a pre-charge signal and perform pre-charge processing on the discharge circuit and the signal amplification circuit based on the pre-charge signal, so that both the first connection terminal and the third connection terminal are in a preset level state.

[0018] In some embodiments, the pre-charge circuit includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; wherein the first pin of each of the thirteenth, fourteenth, and fifteenth transistors is connected to a pre-charge signal; the second pin of the thirteenth transistor is connected to a sixth power supply signal, and the second pin of the fourteenth transistor is connected to a seventh power supply signal; the third pin of the thirteenth transistor and the second pin of the fifteenth transistor are both connected to a first connection terminal; and the third pin of the fourteenth transistor and the third pin of the fifteenth transistor are both connected to a third connection terminal.

[0019] In some embodiments, the sensitive amplification circuit further includes an output driving circuit; wherein the output driving circuit is configured to receive a first target amplified signal and a second target amplified signal, and to drive the first target amplified signal and the second target amplified signal to output a target data signal; wherein when the level of the first target amplified signal is lower than the level of the second target amplified signal, the level of the target data signal is a first level state; when the level of the first target amplified signal is higher than the level of the second target amplified signal, the level of the target data signal is a second level state.

[0020] In some embodiments, the output driving circuit includes a first output driving sub-circuit and a second output driving sub-circuit; the first output driving sub-circuit includes a first inverter and a first transistor group, and the second output driving sub-circuit includes a second inverter and a second transistor group; wherein; the input terminal of the first inverter is connected to a first connection terminal, and the output terminal of the first inverter is connected to the first transistor group; the input terminal of the second inverter is connected to a third connection terminal, and the output terminal of the second inverter is connected to the second transistor group.

[0021] In some embodiments, the first transistor, second transistor, fifth transistor, sixth transistor, eighth transistor, ninth transistor, eleventh transistor, and twelfth transistor are N-channel field-effect transistors; the third transistor, fourth transistor, seventh transistor, tenth transistor, thirteenth transistor, fourteenth transistor, and fifteenth transistor are P-channel field-effect transistors; wherein, the first pin of the N-channel field-effect transistor is the gate pin, the second pin of the N-channel field-effect transistor is the drain pin, the third pin of the N-channel field-effect transistor is the source pin, the first pin of the P-channel field-effect transistor is the gate pin, the second pin of the P-channel field-effect transistor is the source pin, and the third pin of the P-channel field-effect transistor is the drain pin.

[0022] Secondly, embodiments of this application provide a semiconductor memory, including the sensitive amplifier circuit described in the first aspect.

[0023] In some embodiments, the semiconductor memory includes at least dynamic random access memory (DRAM).

[0024] This application provides a sensitive amplifier circuit, which includes a discharge circuit and a signal amplification circuit. The signal amplification circuit includes a first cross-coupled transistor group and a second cross-coupled transistor group, and the discharge circuit is connected between the first and second cross-coupled transistor groups. The discharge circuit receives a signal to be transmitted and a reference signal, and performs discharge processing on the signal to be transmitted and the reference signal respectively to obtain a signal to be processed. The signal amplification circuit amplifies the signal to be processed to obtain a target amplified signal. Thus, this application provides a novel sensitive amplifier circuit that, by placing the discharge circuit between two pairs of cross-coupled transistor groups, can shorten the time required for the sensitive amplification process, thereby improving the performance of the DRAM. Attached Figure Description

[0025] Figure 1 A partial structural diagram of a DRAM provided in an embodiment of this application;

[0026] Figure 2 A partial structural diagram of another DRAM provided in an embodiment of this application;

[0027] Figure 3 A schematic diagram of a write driver circuit provided for related technologies;

[0028] Figure 4 A schematic diagram of a read amplifier circuit provided for related technologies;

[0029] Figure 5 A schematic diagram of an output drive circuit provided for related technologies;

[0030] Figure 6 A schematic diagram of a sensitive amplifier circuit provided in an embodiment of this application;

[0031] Figure 7 This is a schematic diagram of another sensitive amplifier circuit provided in an embodiment of this application;

[0032] Figure 8 A detailed structural schematic diagram of a sensitive amplifier circuit provided for an embodiment of this application;

[0033] Figure 9 A detailed structural schematic diagram of a reference output circuit provided for an embodiment of this application;

[0034] Figure 10 A detailed structural schematic diagram of an output driving circuit provided in an embodiment of this application;

[0035] Figure 11 A detailed structural schematic diagram of another sensitive amplifier circuit provided in an embodiment of this application;

[0036] Figure 12 This is a schematic diagram of the structure of a semiconductor memory provided in an embodiment of this application. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant application and not for limiting the application. Furthermore, it should be noted that, for ease of description, only the parts relevant to the application are shown in the accompanying drawings.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0039] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0040] It should be noted that the terms "first, second, and third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0041] DRAM is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. During data reading, the data signal of each memory cell is read out sequentially via the local data line, global data line, and data bus; during data writing, the data signal of each memory cell is written into the memory cell sequentially via the data bus, global data line, and local data line.

[0042] See Figure 1 This illustrates a partial structural diagram of a DRAM provided in an embodiment of this application. Figure 1 As shown, the core of DRAM consists of a memory array, a sense amplifier (Sa) array, a row decoder and control (XDEC) circuit, a column decoder and control (YDEC) circuit, a read amplifier (SSA) circuit, and a write driver circuit. The read amplifier circuit and the write driver circuit are collectively referred to as the SSA & Write Driver circuit.

[0043] A memory array consists of a large number of memory cells. Data can be read, written, or refreshed from selected memory cells via word lines (WL) and bit lines (BL). Specifically, row decoding and control circuits provide word line signals to activate all memory cells in the target word line. Then, column decoding and control circuits provide bit line signals (CSL signals) to write, read, or refresh data to the target memory cell. Generally, sensitive amplifier arrays can be divided into odd-numbered arrays and even-numbered arrays, used to control odd-numbered word lines and even-numbered word lines, respectively.

[0044] against Figure 1 The shaded area is enlarged, and its structure is as follows: Figure 2 As shown. The following is combined with... Figure 2 The working process of DRAM will be explained.

[0045] (1) During data refresh, when the target word line is selected by the XDEC circuit, the data is transmitted to the Sa array on the upper and lower sides, amplified by the Sa array, and then written back to the memory cell connected to the selected word line.

[0046] (2) When data needs to be changed / written, the target word line is selected by the XDEC circuit, and then the specified sensitive amplifier is selected by the YDEC circuit. The data to be written is transmitted from the data bus, enters the global data line through the write drive circuit to form the Gdata&Gdata# signal, and is then transmitted to the local data line by the read-write conversion (lrwap) circuit to form the Ldata&Ldata# signal. Then, it is written to the memory cell connected to the selected sensitive amplifier through the selected sensitive amplifier.

[0047] (3) When reading data, after the target word line is selected by the XDEC circuit, the specified sensitive amplifier is selected by the YDEC circuit. The target memory cell transmits the data to the local data line through the sensitive amplifier to form the Ldata&Ldata# signal. Then, the local read / write conversion (lrwap) circuit transmits the data to the global data line to form the Gdata&Gdata# signal. The Gdata&Gdata# signal is amplified by the read amplifier circuit and then transmitted to the data bus.

[0048] In the above process, the output signal of the write drive circuit and the input signal of the read amplifier circuit are conventionally referred to as the Yio&Yio# signal, that is, the Yio&Yio# signal is equivalent to the Gdata&Gdata# signal. Taking reading data as an example, the Yio&Yio# signal needs to be transmitted from the global data line to the data bus via the read amplifier circuit.

[0049] It should be understood that in the above process, the entire circuit uses a pair of YIO signals (or double-ended YIO signals), namely Yio & Yio# signals. Yio & Yio# are a two-phase pair, and they are in opposite complementary polarities in both data reading and writing modes. Alternatively, the entire circuit can use a single-ended YIO signal, with essentially the same operating principle.

[0050] The following explanation uses a two-terminal YIO signal as an example to illustrate the read amplifier circuit and the write drive circuit.

[0051] like Figure 1 As shown, the Yio&Yio# signal has many pairs, from Yio <0> &Yio# <0> ~Yio <n>&Will# <n>Here, n is a positive integer. For example, n = 135, indicating that there is a 136-bit data bus in the entire circuit, with half of the data associated with the odd-numbered Sa array and the other half associated with the even-numbered Sa array. Figure 2 A pair of Yio&Yio# signals connected to an odd-numbered Sa array and a pair of Yio&Yio# signals connected to an even-numbered Sa array are shown.

[0052] See Figure 3 It shows a schematic diagram of a write driver circuit provided in related technologies. For example... Figure 3 As shown, the write driver circuit receives the EQ signal (precharge signal), WrEn signal (write input control signal), and Data signal (data signal) from the data bus, and outputs the YIO signal according to the EQ signal, WrEn signal, and Data signal, and transmits the YIO signal to the global data line.

[0053] See Figure 4 It shows a schematic diagram of a read amplifier circuit provided in the related art. For example... Figure 4 As shown, the read amplifier circuit receives the YIO signal and reference signal (composed of VSS signal, VCC signal, and YIO_REF) from the global data line. <1> Signals and YIO_REF <0> The signal composition is as follows: the YIO signal and the reference signal are amplified to obtain the YIOloc and YIONloc signals, which are then transmitted to the data bus. Additionally, Figure 4 The DRAM also includes a Com signal and a Com control circuit for controlling the Com signal. The Com control circuit receives control signals (such as YIO_EN(rdEn) / EQN, power signal VCC) and outputs the Com signal. Here, the Com control circuit mainly plays a control role in different operating timing stages of the DRAM, but during the signal amplification process of the read amplifier circuit, the Com signal is grounded. In other words, in the technical process of this application, the Com signal is equivalent to a ground signal.

[0054] Additionally, after the read amplifier circuit obtains the YIOloc and YIONloc signals, the output driver circuit will output the YIOloc and YIONloc signals to the data bus. See also... Figure 5 It shows a schematic diagram of an output drive circuit provided in the related art. For example... Figure 5 As shown, the output driving circuit includes a first output driving circuit and a second output driving circuit. The first output driving circuit receives the YIONloc signal, outputs data signals such as Data and Data_N, and determines a reset signal Rst. The second output driving circuit receives the YIONloc signal and outputs data signals such as Data and Data_N. Here, the data signals such as Data and Data_N are signals transmitted to the data bus. The reset signal Rst is not related to the working principle of this embodiment and will not be explained further.

[0055] For the above read amplifier circuit, the signal sensing amplification time is relatively long, which leads to a decrease in DRAM performance.

[0056] This application provides a sensitive amplification circuit, which includes a discharge circuit and a signal amplification circuit. The signal amplification circuit includes a first cross-coupled transistor group and a second cross-coupled transistor group, and the discharge circuit is connected between the first and second cross-coupled transistor groups. The discharge circuit receives a signal to be transmitted and a reference signal, and performs discharge processing on the signal to be transmitted and the reference signal respectively to obtain a signal to be processed. The signal amplification circuit amplifies the signal to be processed to obtain a target amplified signal. Thus, this application provides a novel sensitive amplification circuit by placing the discharge circuit between two pairs of cross-coupled transistor groups, which can shorten the time required for the sensitive amplification process and thereby improve the performance of DRAM.

[0057] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0058] In one embodiment of this application, see Figure 6 This illustrates a schematic diagram of a sensitive amplifier circuit 10 provided in an embodiment of this application. Figure 6 As shown, the sensitive amplifier circuit 10 includes a discharge circuit 101 and a signal amplification circuit. The signal amplification circuit includes a first cross-coupled transistor group 1021 and a second cross-coupled transistor group 1022. The discharge circuit 101 is connected between the first cross-coupled transistor group 1021 and the second cross-coupled transistor group 1022.

[0059] The discharge circuit 101 is used to receive the signal to be transmitted and the reference signal, and to perform discharge processing on the signal to be transmitted and the reference signal respectively to obtain the signal to be processed.

[0060] A signal amplification circuit is used to amplify the signal to be processed to obtain the target amplified signal.

[0061] It should be noted that the sensitive amplification circuit 10 in this application embodiment is applicable to various signal amplification scenarios, such as DRAM, Static Random-Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), etc., and those skilled in the art can apply it flexibly.

[0062] For ease of explanation, the following explanation will use the application scenario of the read amplifier circuit in DRAM as the sensitive amplifier circuit 10 as an example, but this does not constitute a limitation on the embodiments of this application.

[0063] Based on the foregoing, during the DRAM data reading process, the data signal transmission path of the memory cell is as follows: local data line - read / write conversion (lrwap) circuit - global data line - read amplifier circuit (i.e., sensitive amplifier circuit 10) - data bus.

[0064] For the sensitive amplifier circuit 10, the input signal is called the signal to be transmitted (YIO signal), and the output signal is called the target amplified signal. Specifically, the sensitive amplifier circuit 10 includes a discharge circuit 101 and a signal amplification circuit. The discharge circuit 101 performs discharge processing based on the signal to be transmitted and the reference signal to obtain the signal to be processed; the signal amplification circuit amplifies the signal to be processed to obtain the target amplified signal.

[0065] In related technologies, such as Figure 4 As shown, the signal amplification circuit includes two cross-coupled transistor groups, and the discharge circuit is connected below the two cross-coupled transistor groups. In the embodiments of this application, as... Figure 6 As shown, the signal amplification circuit includes a first cross-coupled transistor group 1021 and a second cross-coupled transistor group 1022, and a discharge circuit 101 is connected between the first cross-coupled transistor group 1021 and the second cross-coupled transistor group 1022. Thus, this embodiment of the application provides a novel sensitive amplification circuit that can shorten the sensitive amplification time, improve the amplification performance of the sensitive amplification circuit, and thereby improve the performance of the DRAM.

[0066] It should also be noted that the sensitive amplifier circuit 10 can amplify both single-ended signals (YIO signal) and double-ended signals (Yio & Yio# signals). In the scenario of amplifying a single-ended signal (YIO signal), the signal to be transmitted is the YIO signal, and the reference signal is a signal with a fixed level value; in the scenario of amplifying double-ended signals (Yio & Yio# signals), the signal to be transmitted can be the Yio signal, and the reference signal can be the Yio# signal; or, the signal to be transmitted can be the Yio# signal, and the reference signal can be the Yio signal.

[0067] In the embodiments of this application, the following descriptions all use single-ended signal amplification as an example, but this does not constitute a limitation on the embodiments of this application. For dual-ended signal amplification applications, the descriptions and related principles of single-ended signal amplification can be referred to for implementation.

[0068] In some embodiments, see Figure 7 This illustrates a schematic diagram of another sensitive amplifier circuit 10 provided in an embodiment of this application. Figure 7 As shown, the discharge circuit 101 includes a first discharge circuit 1011 and a second discharge circuit 1012; wherein,

[0069] The first discharge circuit 1011 is used to receive the signal to be transmitted (YIO) and perform discharge processing based on the signal to be transmitted to obtain the first signal to be processed.

[0070] The second discharge circuit 1012 is used to receive the reference signal and perform discharge processing based on the reference signal to obtain the second signal to be processed.

[0071] The signal amplification circuit is specifically used to amplify a first signal to be processed to obtain a first target amplified signal; and to amplify a second signal to be processed to obtain a second target amplified signal.

[0072] It should be noted that the discharge circuit 101 includes two discharge paths, namely the first discharge circuit 1011 and the second discharge circuit 1012. The first discharge circuit 1011 is used to perform discharge processing according to the signal to be transmitted (YIO) to obtain the first signal to be processed, and the second discharge circuit 1012 is used to perform discharge processing according to the reference signal to obtain the second signal to be processed.

[0073] Here, the difference in the level states between the signal to be transmitted (YIO) and the reference signal leads to different discharge speeds along the discharge paths, resulting in a slight difference between the first signal to be processed and the second signal to be processed. This slight difference is captured and amplified by the signal amplification circuit, making the higher-level signal even higher and the lower-level signal even lower, ultimately yielding the first target amplified signal (YIONloc) and the second target amplified signal (YIOloc). Thus, by designing two discharge paths in the discharge circuit 101, the difference in the level states between the signal to be transmitted and the reference signal can be quickly compared, thereby achieving the signal amplification process.

[0074] Here, the reference signal can be composed of multiple signals with the same level state or multiple signals with different level states, and the level state of the reference signal can be considered as the average of multiple signals.

[0075] It should be understood that when the signal to be transmitted (YIO) is in the first level state, it indicates... <1> When the transmission signal (YIO) is in the second level state, it indicates <0> The reference signal is fixed at the midpoint between the first and second level states. Thus, if the level of the signal to be transmitted is higher than that of the reference signal, the subsequent discharge and signal amplification processes will determine the signal to be transmitted. <1> Conversely, if the level of the signal to be transmitted is lower than that of the reference signal, the signal to be transmitted will be determined through subsequent discharge and signal amplification processes. <0> .

[0076] In some embodiments, see Figure 8 This illustrates a detailed structural diagram of a sensitive amplifier circuit 10 provided in an embodiment of this application. For example... Figure 8 As shown, the first discharge circuit 1011 has a first connection terminal on the side near the first cross-coupled transistor group 1021, and the first discharge circuit 1011 has a second connection terminal on the side near the second cross-coupled transistor group 1022.

[0077] The first electronic discharge circuit 1011 includes a first crystal 201 ( Figure 8 (Taking a=4 as an example for illustration), and the first pin of each of the a first transistors 201 is connected to the signal to be transmitted (YIO), and the third pin of each of the a first transistors 201 is connected to the second connection terminal;

[0078] Each of the first transistors 201 has its second pin connected to a first connection terminal, which is used to output a first signal to be processed or to output a first target amplified signal (YIONloc).

[0079] Similarly, in some embodiments, the second discharge circuit 1012 is provided with a third connection terminal on the side near the first cross-coupled transistor group 1021, and the second discharge circuit 1012 is provided with a fourth connection terminal on the side near the second cross-coupled transistor group 1022.

[0080] The second electronic circuit 1012 includes b second transistors 202 ( Figure 8 (Taking a=4 as an example for illustration), and the first pin of each of the b second transistors 202 is connected to the reference signal, and the third pin of each of the b second transistors 202 is connected to the fourth connection terminal;

[0081] Each of the second transistors 202 has its second pin connected to a third connection terminal, which is used to output a second signal to be processed or to output a second target amplified signal (YIOloc).

[0082] It should be noted that the positions of the first connecting end, the second connecting end, the third connecting end, and the fourth connecting end are as follows: Figure 8 As shown.

[0083] The first amplification circuit 1011 includes *a* first transistors 201 connected in parallel. The first terminals of each of the *a* first transistors 201 are used to receive the signal to be transmitted (YIO), and the second terminals of the *a* first transistors 201 are used together to output the first signal to be processed / the first target amplified signal (YIONloc). The second amplification circuit 1012 includes *b* second transistors 202 connected in parallel. The first terminals of each of the *b* second transistors 202 are used to receive the signal to be transmitted, and the second terminals of the *b* second transistors 202 are used together to output the second signal to be processed / the second target amplified signal (YIOloc).

[0084] In this embodiment, for the first transistor and the second transistor, the first terminal is the gate of the transistor, which can control the transistor to turn on / off; when the transistor is on, the current direction is from the second terminal to the third terminal. Here, the higher the voltage at the first terminal, the faster the current flow of the transistor, and thus the faster the discharge speed.

[0085] Taking the case where the level of the signal to be transmitted (YIO) is greater than that of the reference signal as an example, the specific process of signal amplification will be explained.

[0086] It should be understood that before signal amplification begins, the initial voltage levels of the first and third connection terminals are the same, as are the initial voltage levels of the second and fourth connection terminals. After signal amplification begins, because the level of the signal to be transmitted (YIO) is greater than that of the reference signal, the discharge rate of the first discharge circuit is higher than that of the second discharge circuit. Therefore, the voltage drop rate of the first connection terminal is higher than that of the third connection terminal, and the voltage level of the first connection terminal is slightly lower than that of the third connection terminal. At this time, the first connection terminal can be considered to output the first signal to be processed, and the third connection terminal can be considered to output the second signal to be processed. Finally, the first and second signals to be processed are amplified by the amplifier circuit, causing the voltage level at the first connection terminal to continuously decrease, which turns on the fourth transistor 204, thereby causing the voltage level at the third connection terminal to continuously increase until the voltage difference between the first and third connection terminals meets the requirements. At this time, the first connection terminal can be considered to output the first target amplified signal (YIONloc), and the second connection terminal can be considered to output the second target amplified signal (YIOloc).

[0087] It should be noted that when the level of the signal to be processed (YIO signal) is higher than the level of the reference signal, the level of the first target amplified signal (YIONloc) is lower than the level of the second target amplified signal (YIONloc); when the level of the signal to be processed (YIO) is lower than the level of the reference signal, the level of the first target amplified signal (YIONloc) is higher than the level of the second target amplified signal (YIONloc).

[0088] It should be noted that the number of transistors in the first discharge circuit 1011 and the second discharge circuit 1012 needs to be designed according to the actual application scenario. Both a and b are positive integers, and a and b can be the same or different. That is, the number of transistors in the first discharge circuit 1011 and the second discharge circuit 1012 can be the same or different, depending on the actual application scenario. Specifically, when a = b, the first discharge circuit 1011 and the second discharge circuit 1012 have a symmetrical structure, which can balance the hardware errors in the two discharge paths and bring better amplification performance to the sensitive amplifier circuit 10.

[0089] In one specific embodiment, such as Figure 8 As shown, a = b = 4, that is, the first discharge circuit 1011 includes 4 first transistors 201, the first terminals of these 4 transistors are all connected to the signal to be transmitted (YIO), which is equivalent to introducing 4 identical signals to be transmitted (YIO); the second discharge circuit 1012 includes 4 second transistors 202, these 4 transistors are respectively connected to 4 reference signals.

[0090] Here, the four reference signals can all be the same signal, or they can be different signals. For example, the reference signals may include the first reference signal (YIO_REF). <1> ), second reference signal (YIO_REF) <0> The third power signal (VCC) and ground signal (VSS) are included, and the four second transistors 202 include a second first transistor, a second second transistor, a second third transistor, and a second fourth transistor; among them, such as Figure 8 As shown, the first pin of the second transistor is connected to the first reference signal (YIO_REF). <1> The first pin of the second transistor is connected to the second reference signal (YIO_REF). <0> The first pin of the second and third transistors is connected to the third power supply signal (VCC), and the first pin of the second and fourth transistors is connected to the ground signal (VSS).

[0091] Thus, the first discharge circuit 1011 and the second discharge circuit 1012 have a symmetrical structure. On the one hand, this can balance the errors generated during the manufacturing process and reduce the impact of mismatch defects in the manufacturing process on the amplification margin of the sensitive amplifier circuit 10. On the other hand, it can reduce the impact of noise on the amplification margin, more accurately compare the level difference between the signal to be transmitted and the reference signal, and improve the accuracy of the sensitive amplifier.

[0092] Specifically, the four first transistors can have the same or different specifications; the four second transistors can have the same or different specifications.

[0093] In one specific embodiment, such as Figure 8 As shown, the first cross-coupled transistor group 1021 includes a third transistor 203 and a fourth transistor 204; wherein, the first pin of the third transistor 203 and the third pin of the fourth transistor 204 are both connected to a third connection terminal; the third pin of the third transistor 203 and the first pin of the fourth transistor 204 are both connected to a first connection terminal; the second pin of the third transistor 203 is connected to a first power supply signal, and the second pin of the fourth transistor 204 is connected to a second power supply signal.

[0094] In some embodiments, such as Figure 8 As shown, the second cross-coupled transistor group 1022 includes a fifth transistor 205 and a sixth transistor 206; wherein, the first pin of the fifth transistor 205 is connected to the third connection terminal, and the first pin of the sixth transistor 206 is connected to the first connection terminal; the second pin of the fifth transistor 205 is connected to the second connection terminal, and the second pin of the sixth transistor 206 is connected to the fourth connection terminal; the third pins of both the fifth transistor 205 and the sixth transistor 206 are connected to the ground signal.

[0095] It should be noted that the first cross-coupled transistor group 1021 and the second cross-coupled transistor group 1022 are each composed of a pair of transistors, and their connection method is as follows: Figure 8 As shown.

[0096] The first cross-coupled transistor group 1021 and the second cross-coupled transistor group 1022 can amplify the difference between the first signal to be processed and the second signal to be processed, thereby obtaining the first target amplified signal (YIONloc) and the second target amplified signal (YIOloc). In addition, the first cross-coupled transistor group 1021 and the second cross-coupled transistor group 1022 are both classic cross-coupled amplification devices, and their specific amplification principles will not be elaborated.

[0097] Thus, in this embodiment of the application, the first discharge circuit discharges based on the signal to be transmitted (YIO) to obtain the first signal to be processed; the second discharge circuit discharges based on the reference signal to obtain the second signal to be processed; the signal amplification circuit amplifies the first signal to be processed and the second signal to be processed to obtain the first target amplified signal (YIONloc) and the second target amplified signal (YIOloc).

[0098] In some embodiments, the sensitive amplifier circuit 10 further includes a reference output circuit 103 for outputting a reference signal. As described above, the reference signal includes a first reference signal (YIO_REF). <0> ), second reference signal (YIO_REF) <1> The reference output circuit 103 includes a first reference output circuit 1031 and a second reference output circuit 1032, which are used to output the first reference signal (YIO_REF), ground signal VSS, and power signal VCC, respectively. <0> ) and the second reference signal (YIO_REF) <1> It should be understood that power signals and ground signals can be directly input through the power / ground terminals.

[0099] See Figure 9 This illustrates a schematic diagram of a reference output circuit 103 provided in an embodiment of this application. Figure 9 As shown, the reference output circuit 103 may include:

[0100] The first reference output circuit 1031 is used to receive the first control signal (CM_SESA). <0> ), and output the first reference signal (YIO_REF) according to the first control signal. <0> );

[0101] The second reference output circuit 1032 is used to receive the second control signal (CM_SESA). <1> ), and output the second reference signal (YIO_REF) according to the second control signal. <1> ).

[0102] It should be noted that various fixed or occasional defects may occur during the manufacturing process of the sensitive amplifier circuit 10, leading to hardware errors in the first and second amplifier circuits. Therefore, in this embodiment, a first reference output circuit 1031 and a second reference output circuit 1032 are also provided, which output corresponding reference signals according to the corresponding control signals. Here, if parameter errors occur in the first amplifier circuit 1011 and the second amplifier circuit 1012, the first control signal (CM_SESA) can be adjusted through the test mode. <0> ) / Second control signal (CM_SESA) <1> The level state of ) is adjusted, thereby adjusting the first reference signal (YIO_REF). <0> ) and the second reference signal (YIO_REF) <1> The level state of the first and second control signals is adjusted to compensate for errors caused by the manufacturing process, correct the amplification margin of the sensitive amplifier circuit, and thus ensure the performance of the sensitive amplifier circuit. Generally, the adjustment of the first and second control signals only occurs before leaving the factory or during maintenance. During normal use by the user, they are usually fixed; otherwise, it may easily cause system crashes.

[0103] In one specific embodiment, the first reference output circuit 1031 includes a seventh transistor 207, an eighth transistor 208, and a ninth transistor 209; wherein,

[0104] The first pin of the seventh transistor 207 is connected to the first pin of the eighth transistor 208 to receive the first control signal (CM_SESA). <0> );

[0105] The third pin of the seventh transistor 207 is connected to the second pin of the eighth transistor 208 and the first pin of the ninth transistor 209 to output the first reference signal (YIO_REF). <0> );

[0106] The second pin of the seventh transistor 207 is connected to the fourth power supply signal (VCCZ), the third pin of the eighth transistor 208 is connected to the ground signal (VSSZ), and the second and third pins of the ninth transistor 209 are both connected to the ground signal.

[0107] In addition, the second reference output circuit 1032 includes a tenth transistor 210, an eleventh transistor 211, and a twelfth transistor 212;

[0108] The first pin of the tenth transistor 210 is connected to the first pin of the eleventh transistor 211 to receive the second control signal (CM_SESA). <1> );

[0109] The third pin of the tenth transistor 210 is connected to the second pin of the eleventh transistor 211 and the first pin of the twelfth transistor 212, and is used to output the second reference signal (YIO_REF). <1> );

[0110] The second pin of the tenth transistor 210 is connected to the fifth power supply signal (VCCZ), the third pin of the eleventh transistor 211 is connected to the ground signal (VSSZ), and the second and third pins of the twelfth transistor 212 are both connected to the ground signal.

[0111] Generally, the seventh transistor 207 and the tenth transistor 210 are P-type transistors. In the embodiments of this application, the first reference output circuit 1031 and the second reference output circuit 1032 are both located on the reference signal side. The advantage is that the selection between the power supply signal VCCZ and the ground signal VSSZ is relatively fixed. If they are placed on the reference signal and the signal to be transmitted respectively, the disadvantage is that on the signal to be transmitted side, when the YIO signal is discharged to a very low level, the P-type transistor has poor ability to control the transmission of low potential, resulting in low efficiency and susceptibility to interference. The actual control efficiency will be lower than expected.

[0112] In some embodiments, to ensure that the first connection terminal and the third connection terminal are at the same level before the amplification process begins, the sensitive amplification circuit 10 also needs to be provided with a pre-charge circuit. The pre-charge circuit is used to receive a pre-charge signal and perform pre-charge processing on the discharge circuit 101 and the signal amplification circuit based on the pre-charge signal, so that both the first connection terminal and the third connection terminal are at a preset level.

[0113] It should be noted that the input to the pre-charge circuit is a pre-charge signal (EQ). When the pre-charge signal (EQ) is valid, the pre-charge circuit pre-charges the first and second connection terminals to a preset level. Here, the preset level can be determined according to the actual application scenario.

[0114] In one specific embodiment, please refer to Figure 8 The pre-charge circuit includes a thirteenth transistor 213, a fourteenth transistor 214, and a fifteenth transistor 215; wherein,

[0115] The first pin of each of the thirteenth transistor 213, the fourteenth transistor 214, and the fifteenth transistor 215 is connected to the precharge signal (EQ);

[0116] The second pin of the thirteenth transistor 213 is connected to the sixth power supply signal, and the second pin of the fourteenth transistor 214 is connected to the seventh power supply signal.

[0117] The third pin of the thirteenth transistor 213 and the second pin of the fifteenth transistor 215 are both connected to the first connection terminal; the third pin of the fourteenth transistor 214 and the third pin of the fifteenth transistor 215 are both connected to the third connection terminal.

[0118] In related technologies, such as Figure 4 As shown, since the discharge circuit is located below the two pairs of cross-coupled transistors, the pre-charge circuit needs to include two parts: the first part includes three pre-charge transistors located above the first pair of cross-coupled transistors, and the second part includes two pre-charge transistors located outside the second pair of cross-coupled transistors.

[0119] It should be understood that during the operation of DRAM, the level of the YIO signal is reset to a fixed value (VCC) after each read operation. In this embodiment, the discharge circuit 101 is located between two pairs of cross-coupled transistors. After the read operation is completed, since the level of the YIO signal is a fixed value (VCC), both discharge paths in the discharge circuit will be in the conducting state. Therefore, the entire circuit can be pre-charged by the three pre-charge transistors in the first pre-charge circuit.

[0120] In other words, such as Figure 8 As shown, the sensitive amplification circuit provided in this application embodiment can eliminate the need for two pre-charge transistors in the second part of the pre-charge circuit (i.e., Figure 4 (The part enclosed in the dashed box) For the overall sensitive amplifier circuit, due to the reduction in the number of pre-charge tubes, the total capacitance of the discharge path during the sensitive amplification process is smaller, and the time required for discharge is reduced, thereby shortening the time required for the signal amplification (Sense) process.

[0121] In addition, in this embodiment, the reduction in the number of pre-charge tubes inevitably leads to an increase in the time required for the pre-charge process. This problem can be solved by adjusting the performance parameters of the pre-charge tubes.

[0122] In the foregoing, the first transistor 201, the second transistor 202, the fifth transistor 205, the sixth transistor 206, the eighth transistor 208, the ninth transistor 209, the eleventh transistor 211, and the twelfth transistor 212 are N-channel field-effect transistors; the third transistor 203, the fourth transistor 204, the seventh transistor 207, the tenth transistor 210, the thirteenth transistor 213, the fourteenth transistor 214, and the fifteenth transistor 215 are P-channel field-effect transistors.

[0123] In this configuration, the first pin of an N-channel MOSFET is the gate pin, the second pin is the drain pin, and the third pin is the source pin. Similarly, the first pin of a P-channel MOSFET is the gate pin, the second pin is the source pin, and the third pin is the drain pin.

[0124] In addition, as mentioned above, the first power signal to the seventh power signal can have the same level state or different level states, which needs to be determined according to the actual application scenario.

[0125] Additionally, the sensitive amplifier circuit 10 also includes an output drive circuit 104. See also, in some embodiments, […]. Figure 10 This illustrates a schematic diagram of an output drive circuit 104 provided in an embodiment of this application. Figure 10 As shown, the output driving circuit 104 is used to receive the first target amplified signal (YIONloc) and the second target amplified signal (YIOloc), and to drive the first target amplified signal (YIONloc) and the second target amplified signal (YIOloc) to output the target data signal (Data).

[0126] It should be noted that the output terminal of the output drive circuit 104 is connected to the data bus and is used to determine the target data signal (Data) based on the first target amplified signal (YIONloc) and the second target amplified signal (YIOloc), and output the target data signal (Data) to the data bus.

[0127] For example, when the level of the first target amplified signal is lower than the level of the second target amplified signal, the level of the target data signal is a first level; when the level of the first target amplified signal is higher than the level of the second target amplified signal, the level of the target data signal is a second level.

[0128] In one specific embodiment, the output driving circuit 104 includes a first output driving sub-circuit 1041 and a second output driving sub-circuit 1042; the first output driving sub-circuit 1041 includes a first inverter and a first transistor group, and the second output driving circuit 1042 includes a second inverter and a second transistor group; wherein;

[0129] The input terminal of the first inverter is connected to the first connection terminal, and the output terminal of the first inverter is connected to the first transistor group; the input terminal of the second inverter is connected to the third connection terminal, and the output terminal of the second inverter is connected to the second transistor group.

[0130] It should also be noted that, such as Figure 10 As shown, the first output driving circuit 1041 includes a first inverter and a first transistor group, used to receive the first target amplified signal (YIONloc) and output the target data signal (Data) and the inverted data signal (Data_N); the second output driving circuit 1042 includes a second inverter and a second transistor group, used to receive the second target amplified signal (YIOloc) and output the target data signal (Data) and the inverted data signal (Data_N) for subsequent use.

[0131] Additionally, regarding related technologies (see [link]) Figure 5 Compared to the first output driving circuit 1041 and the second output driving circuit 1042, each of them includes an additional inverter. The first target amplified signal (YIONloc) and the second target amplified signal (YIOloc) are respectively introduced into the subsequent transistors after passing through the inverters, thereby ensuring that the capacitance on the output terminals YIONloc and YIOloc of the signal amplification circuit is consistent, and optimizing the problem of inconsistent output load.

[0132] For example, such as Figure 10 As shown, for the first output drive circuit 1041, the first transistor group includes transistors 301, 302, 303, 304, 305, and 306. The first terminal of transistor 301 is connected to the output terminal of the first inverter, the third terminal of transistor 301 is connected to the second terminal of transistor 305, and the third terminal of transistor 305 is connected to the second terminal of transistor 306; the third terminal of transistor 306 is connected to ground; and the second terminals of transistors 302, 303, and 304 are respectively connected to power supply signals.

[0133] The second terminal of transistor 301, the third terminal of transistor 302, the third terminal of transistor 303, and the third terminal of transistor 304 form a connection point and are used to output the target data signal (Data); the first terminal of transistor 302 is connected to the first terminal of transistor 301, and the first terminal of transistor 303 is connected to the first terminal of transistor 305 and are used to output the inverted data signal (Data_N).

[0134] Additionally, the first terminal of transistor 304 is connected to the first terminal of transistor 306 and is used to determine the reset signal (Rst). Here, the Rst signal is used for the reset process, which is not very relevant to the technical solution of the embodiments of this application and will not be explained in detail.

[0135] Here, transistors 301, 305, and 306 are N-type field-effect transistors (FETs), and transistors 302, 303, and 304 are P-type FETs, with the first terminal of the P-type FET serving as the gate pin. In this embodiment, the second terminal of the P-type FET is the source pin, and the third terminal of the P-type FET is the drain pin; similarly, the first terminal of the N-type FET is the gate pin, the second terminal of the N-type FET is the drain pin, and the third terminal of the N-type FET is the source pin.

[0136] For example, such as Figure 10 As shown, for the second output drive circuit 1042, the second transistor group includes transistors 307, 308, 309, and 310. The first terminal of transistor 307 is connected to the output terminal of the second inverter and the first terminal of transistor 308; the second terminals of transistors 308 and 309 are respectively connected to the power supply signal; the third terminal of transistor 307 is connected to the second terminal of transistor 310, and the third terminal of transistor 310 is grounded.

[0137] The second terminal of transistor 307, the third terminal of transistor 308, and the third terminal of transistor 309 form a connection point and are used to output an inverted data signal (Data); the first terminal of transistor 309 is connected to the first terminal of transistor 310 and is used to output a target data signal (Data_N).

[0138] Here, transistors 307 and 310 are N-type field-effect transistors, and transistors 308 and 309 are P-type field-effect transistors.

[0139] Please see Figure 11 It shows a schematic diagram of another sensitive amplifier circuit 10 provided in the embodiments of this application. Figure 11 and Figure 8 The difference is: Figure 11 The circuit adds a Com control circuit. The Com control can receive some control signals such as YIO_EN, EQN, and power signal VCC, and after some logic processing, it obtains the Com signal.

[0140] Here, the Com control circuit is used to play a control role in different working stages, that is, to output the Com signal according to YIO_EN, EQN, VCC, etc. The Com signal is a ground signal throughout the signal amplification (Sense) process of the entire sensitive amplifier circuit 10.

[0141] for Figure 11 In this application, the sensitive amplifier circuit 10 in the embodiment of the present application has at least the following advantages:

[0142] (1) After each read, the level of the YIO signal will be reset to VCC. Therefore, during the reset process, the two discharge paths in the sensitive amplifier circuit will be in the conducting state, and the Com control circuit can also be charged through the three pre-charge tubes at the top.

[0143] (2) Compared with related technologies, the sensitive amplifier circuit 10 moves the discharge path to the middle of the four cross-coupled transistors, thereby saving two pre-charge transistors. Figure 4 (The area enclosed by the dashed line) This reduces the total capacitance of the discharge path, and the circuit area is also reduced, so the sensitive amplifier circuit 10 can shorten the time required for the Sense process.

[0144] (3) The sensitive amplifier circuit has two inverters (Inv) connected after the output YIONloc and YIOloc, namely the first inverter in the first output drive circuit and the second inverter in the second output drive circuit. This makes the capacitors on the output terminals YIONloc and YIOloc of the signal amplifier circuit consistent, thus optimizing the problem of the Sense Margin deviation caused by the inconsistent load at the output terminals.

[0145] (4) Compared with related technologies, the sensitive amplifier circuit 10 reduces the number of pre-charge tubes, reduces the circuit layout area, and shortens the time consumed by the Sense process, but may cause the pre-charge stage to consume more time.

[0146] Additionally, for the circuit, reducing the number of two EQ transistors results in a longer pre-charge phase time after the Sense process ends compared to the original structure. However, this can be mitigated by appropriately increasing the size of the upper pre-charge transistor. Moreover, this circuit can be used when the Sense process time is tight, but the pre-charge process time is not critical.

[0147] In summary, the embodiments of this application provide a novel sensitive amplification circuit that places the discharge circuit between two pairs of cross-coupled transistors in the signal amplification circuit and reduces the number of pre-charge transistors, offering at least the following advantages:

[0148] (1) By reducing the pre-charge tube, the overall capacitance of the sensitive amplifier circuit is reduced, thereby reducing the total capacitance that needs to be discharged during the amplification process, increasing the amplification speed, and reducing the time required for the amplification process.

[0149] (2) The two discharge paths in the sensitive amplifier circuit have a symmetrical structure, thereby reducing the deviation caused by the manufacturing process.

[0150] (3) The sensitive amplifier circuit adds a MOS CAP structure (i.e., the first reference output circuit and the second reference output circuit) in the noise-sensitive area to reduce the impact of noise.

[0151] (4) Since the sensitive amplifier circuit includes a first reference output circuit and a second reference output circuit, the level of the first reference signal and the second reference signal can be adjusted in the test mode, thereby adjusting the sensitive amplification performance of the sensitive amplifier circuit. That is, the sensitive amplifier circuit introduces a structure with Fuse control to adjust the sense characteristics.

[0152] (5) Both the first and second reference output circuits are located on the reference signal side. The advantage is that the selection can be made between VCCZ / VSSZ, and the potential is relatively fixed. If they are placed on opposite sides, the disadvantage is that when the YIO signal is discharged to a very low level on the input side, the P-type transistor has poor ability to control the transmission of low potential, resulting in low efficiency and susceptibility to interference. The actual control efficiency will be lower than expected.

[0153] (6) The sensitive amplifier circuit uses a single-ended YIO signal for sensitive amplification, which can save YIO lines and power consumption.

[0154] This application provides a sensitive amplifier circuit, which includes a discharge circuit and a signal amplification circuit. The signal amplification circuit includes a first cross-coupled transistor group and a second cross-coupled transistor group, and the discharge circuit is connected between the first and second cross-coupled transistor groups. The discharge circuit receives a signal to be transmitted and a reference signal, and performs discharge processing on the signal to be transmitted and the reference signal respectively to obtain a signal to be processed. The signal amplification circuit amplifies the signal to be processed to obtain a target amplified signal. Thus, this application provides a novel sensitive amplifier circuit that, by placing the discharge circuit between two pairs of cross-coupled transistor groups, can shorten the time required for the sensitive amplification process, thereby improving the performance of the DRAM.

[0155] In another embodiment of this application, see [link to application]. Figure 12 This illustrates a schematic diagram of the structure of a semiconductor memory 40 provided in an embodiment of this application. Figure 12 As shown, the semiconductor memory 40 includes a sensitive amplifier circuit 10 of any of the foregoing embodiments.

[0156] In some embodiments, the semiconductor memory 40 includes at least dynamic random access memory (DRAM).

[0157] In this embodiment of the application, a novel sensitive amplification circuit is provided, which places the discharge circuit between two pairs of cross-coupled transistor groups, thereby shortening the time required for the sensitive amplification process and improving the performance of DRAM.

[0158] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application.

[0159] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0160] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0161] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0162] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0163] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0164] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.< / n> < / n>

Claims

1. A sensitive amplifier circuit, characterized in that, The sensitive amplification circuit includes a discharge circuit and a signal amplification circuit. The signal amplification circuit includes a first cross-coupled transistor group and a second cross-coupled transistor group, which together form a cross-coupled inverter pair. The discharge circuit is connected between the first cross-coupled transistor group and the second cross-coupled transistor group. The discharge circuit is used to receive the signal to be transmitted and the reference signal, and to perform discharge processing based on the signal to be transmitted and the reference signal respectively to obtain the signal to be processed. The signal amplification circuit is used to amplify the signal to be processed to obtain the target amplified signal; The discharge circuit includes a first discharge circuit and a second discharge circuit; wherein... The first discharge circuit is used to receive the signal to be transmitted and perform discharge processing based on the signal to be transmitted to obtain a first signal to be processed. The second discharge circuit is used to receive the reference signal and perform discharge processing based on the reference signal to obtain a second signal to be processed; The signal amplification circuit is specifically used to amplify the first signal to be processed to obtain a first target amplified signal; and to amplify the second signal to be processed to obtain a second target amplified signal; The first discharge circuit has a first connection terminal on the side near the first cross-coupled transistor group, and the first discharge circuit has a second connection terminal on the side near the second cross-coupled transistor group; The first discharge circuit includes a first transistors, and the first pin of each of the a first transistors is connected to the signal to be transmitted, and the third pin of each of the a first transistors is connected to the second connection terminal; The second pin of each of the a first transistors is connected to the first connection terminal, and the first connection terminal is used to output the first signal to be processed, or to output the first target amplified signal; Where a is a positive integer.

2. The sensitive amplifier circuit according to claim 1, characterized in that, The second discharge circuit has a third connection terminal on the side near the first cross-coupled transistor group, and the second discharge circuit has a fourth connection terminal on the side near the second cross-coupled transistor group. The second discharge circuit includes b second transistors, and the first pin of each of the b second transistors is connected to the reference signal, and the third pin of each of the b second transistors is connected to the fourth connection terminal; The second pin of each of the b second transistors is connected to the third connection terminal, and the third connection terminal is used to output the second signal to be processed, or to output the second target amplified signal; Where b is a positive integer.

3. The sensitive amplifier circuit according to claim 2, characterized in that, The first cross-coupled transistor group includes a third transistor and a fourth transistor; wherein, The first pin of the third transistor and the third pin of the fourth transistor are both connected to the third connection terminal. The third pin of the third transistor and the first pin of the fourth transistor are both connected to the first connection terminal; The second pin of the third transistor is connected to the first power supply signal, and the second pin of the fourth transistor is connected to the second power supply signal.

4. The sensitive amplifier circuit according to claim 3, characterized in that, The second cross-coupled transistor group includes a fifth transistor and a sixth transistor; wherein, The first pin of the fifth transistor is connected to the third connection terminal, and the first pin of the sixth transistor is connected to the first connection terminal; The second pin of the fifth transistor is connected to the second connection terminal, and the second pin of the sixth transistor is connected to the fourth connection terminal; The third pin of the fifth transistor and the third pin of the sixth transistor are both connected to ground.

5. The sensitive amplifier circuit according to claim 2, characterized in that, When b is 4, the reference signal includes a first reference signal, a second reference signal, a third power supply signal, and a ground signal; the b second transistors include a second first transistor, a second second transistor, a second third transistor, and a second fourth transistor; wherein, The first pin of the second transistor is connected to the first reference signal, the first pin of the second transistor is connected to the second reference signal, the first pin of the second transistor is connected to the third power supply signal, and the first pin of the second transistor is connected to the ground signal.

6. The sensitive amplifier circuit according to claim 5, characterized in that, The sensitive amplifier circuit further includes a first reference output circuit and a second reference output circuit; wherein... The first reference output circuit is used to receive a first control signal and output the first reference signal according to the first control signal; The second reference output circuit is used to receive the second control signal and output the second reference signal according to the second control signal.

7. The sensitive amplifier circuit according to claim 6, characterized in that, The first reference output circuit includes a seventh transistor, an eighth transistor, and a ninth transistor; wherein, The first pin of the seventh transistor is connected to the first pin of the eighth transistor and is used to receive the first control signal; The third pin of the seventh transistor is connected to the second pin of the eighth transistor and the first pin of the ninth transistor, and is used to output the first reference signal; The second pin of the seventh transistor is connected to the fourth power supply signal, the third pin of the eighth transistor is connected to the ground signal, and both the second and third pins of the ninth transistor are connected to the ground signal.

8. The sensitive amplifier circuit according to claim 6, characterized in that, The second reference output circuit includes a tenth transistor, an eleventh transistor, and a twelfth transistor; The first pin of the tenth transistor is connected to the first pin of the eleventh transistor and is used to receive the second control signal; The third pin of the tenth transistor is connected to the second pin of the eleventh transistor and the first pin of the twelfth transistor, and is used to output the second reference signal; The second pin of the tenth transistor is connected to the fifth power supply signal, the third pin of the eleventh transistor is connected to the ground signal, and the second and third pins of the twelfth transistor are both connected to the ground signal.

9. The sensitive amplifier circuit according to claim 2, characterized in that, The sensitive amplifier circuit also includes a pre-charging circuit; The pre-charging circuit is used to receive a pre-charging signal and perform pre-charging processing on the discharging circuit and the signal amplification circuit based on the pre-charging signal, so that the first connection terminal and the third connection terminal are both in a preset level state.

10. The sensitive amplifier circuit according to claim 9, characterized in that, The pre-charge circuit includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; wherein, The first pin of each of the thirteenth, fourteenth, and fifteenth transistors is connected to the precharge signal; The second pin of the thirteenth transistor is connected to the sixth power supply signal, and the second pin of the fourteenth transistor is connected to the seventh power supply signal. The third pin of the thirteenth transistor and the second pin of the fifteenth transistor are both connected to the first connection terminal; the third pin of the fourteenth transistor and the third pin of the fifteenth transistor are both connected to the third connection terminal.

11. The sensitive amplifier circuit according to claim 2, characterized in that, The sensitive amplifier circuit also includes an output drive circuit; wherein... The output driving circuit is used to receive the first target amplified signal and the second target amplified signal, and to drive the first target amplified signal and the second target amplified signal to output the target data signal. Wherein, when the level of the first target amplified signal is lower than the level of the second target amplified signal, the level of the target data signal is a first level state; when the level of the first target amplified signal is higher than the level of the second target amplified signal, the level of the target data signal is a second level state.

12. The sensitive amplifier circuit according to claim 11, characterized in that, The output driving circuit includes a first output driving sub-circuit and a second output driving sub-circuit; the first output driving sub-circuit includes a first inverter and a first transistor group, and the second output driving circuit includes a second inverter and a second transistor group; in; The input terminal of the first inverter is connected to the first connection terminal, and the output terminal of the first inverter is connected to the first transistor group; The input terminal of the second inverter is connected to the third connection terminal, and the output terminal of the second inverter is connected to the second transistor group.

13. The sensitive amplifier circuit according to any one of claims 2-10, characterized in that, The first, second, fifth, sixth, eighth, ninth, eleventh, and twelfth transistors are N-channel field-effect transistors; the third, fourth, seventh, tenth, thirteenth, fourteenth, and fifteenth transistors are P-channel field-effect transistors. In this configuration, the first pin of the N-channel MOSFET is the gate pin, the second pin of the N-channel MOSFET is the drain pin, and the third pin of the N-channel MOSFET is the source pin; the first pin of the P-channel MOSFET is the gate pin, the second pin of the P-channel MOSFET is the source pin, and the third pin of the P-channel MOSFET is the drain pin.

14. A semiconductor memory, characterized in that, Includes the sensitive amplifier circuit as described in any one of claims 1 to 13.

15. The semiconductor memory according to claim 14, characterized in that, The semiconductor memory includes at least dynamic random access memory.

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