Instruction processing method and processor based on multiple instruction engines

Abstract

An instruction processing method and processor based on multiple instruction engines relate to the field of computer technology and are used to improve the execution efficiency of instructions and the utilization of resources in the processor, thereby reducing costs and power consumption. The method is applied to a processor, which includes an instruction block scheduler, an instruction cache group, and an instruction engine group; multiple instruction caches in the instruction cache group correspond one-to-one with multiple instruction engines in the instruction engine group; in this method, the instruction block scheduler determines a first instruction engine for processing the first instruction set based on an instruction processing request for processing the first instruction set; based on the one-to-one correspondence between the instruction engines and the instruction caches, the first instruction cache for caching the first instruction set is determined; the instruction block scheduler sends an instruction pointer in the instruction processing request to the first instruction cache; and the first instruction engine retrieves the first instruction set from the first instruction cache to execute the instructions in the first instruction set.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction processing method and processor based on a multi-instruction engine. Background Art

[0002] With the adoption of fifth-generation (5G) mobile communication technology, processors have evolved to support multiple instruction engines (IEs) for parallel execution. This means that the number of instructions executed concurrently by a processor in a single cycle continues to increase, placing higher demands on instruction fetch bandwidth and latency. Therefore, a single cache memory can no longer meet the instruction fetch requirements of multi-IE processors, necessitating a multi-cache solution to increase instruction fetch bandwidth.

[0003] In the current solution to improve instruction fetch bandwidth through multiple cache memories, multiple IEs share multiple cache memories. When a new instruction processing request is received, the IE that executes the instruction processing request is determined based on the queue depth of the instruction queue (Inst Q) corresponding to each IE. The cache memory that caches the instruction corresponding to the instruction pointer (program counter, PC) in the instruction processing request is then determined. The instruction is retrieved from the cache memory and sent to the corresponding IE for processing through the crossbar switch matrix.

[0004] Therefore, in the current multi-cache memory scheme, which cache memory the instruction is cached in is determined by the PC of the instruction, and when fetching instructions continuously, it is necessary to fetch instructions cyclically in multiple cache memories, resulting in uneven distribution of instruction fetch requests in multiple cache memories, thereby causing the processor processing performance to decline and the execution efficiency to be low. Summary of the Invention

[0005] The embodiments of the present application provide an instruction processing method and a processor based on a multi-instruction engine, which are used to improve the execution efficiency of instructions and the utilization rate of resources in the processor, thereby reducing costs and power consumption.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, embodiments of the present application provide an instruction processing method based on multiple instruction engines. This instruction processing method is applied to a processor comprising: an instruction block scheduler, an instruction cache group, and an instruction engine group. The instruction cache group includes multiple instruction caches (e.g., cache 0 - cache 15), and the instruction engine group includes multiple instruction engines (e.g., IE 0 - IE 15). The multiple instruction caches in the instruction cache group correspond one-to-one with the multiple instruction engines in the instruction engine group (e.g., cache 0 corresponds to IE 0; cache 1 corresponds to IE 1; and so on). The instruction processing method includes: the instruction block scheduler receives an instruction processing request; the instruction processing request is used to request the processor to process a first instruction set. The instruction block scheduler determines a first instruction engine based on the instruction processing request; the first instruction engine is the instruction engine in the instruction engine group that processes the first instruction set. The instruction block scheduler sends the instruction processing request to the first instruction cache corresponding to the first instruction engine. The first instruction engine retrieves the first instruction set from the first instruction cache.

[0008] It should be noted that the instruction block scheduler includes an instruction block table, which records the instruction engines to which each instruction block in a program can be mapped (assigned). The instruction block identification number (PBID) in the instruction processing request can be used to determine the instruction engine to which each instruction block can be mapped (assigned). For example, the instruction engine that processes each instruction block can be determined based on certain rules. Furthermore, the instruction block scheduler also includes multiple instruction processing request queues, each of which corresponds one-to-one with multiple instruction engines. In turn, each of these multiple instruction processing request queues corresponds one-to-one with multiple instruction buffers, thereby achieving a one-to-one correspondence between instruction engines and instruction buffers. Furthermore, the instruction engines and corresponding instruction buffers can be connected via a hardware interface to facilitate instruction transmission.

[0009] Based on the multi-instruction engine-based instruction processing method provided in the first aspect, the instruction block scheduler determines the first instruction engine that processes the first instruction set based on the instruction processing request for processing the first instruction set; determines the first instruction cache for caching the first instruction set based on the one-to-one correspondence between the instruction engine and the instruction cache; the instruction block scheduler sends the instruction pointer PC in the instruction processing request to the first instruction cache; the first instruction engine obtains the first instruction set from the first instruction cache to execute the instructions in the first instruction set. In this solution, each instruction engine can exclusively enjoy the service of an instruction cache, so that the processor has a stable and certain instruction fetch bandwidth, thereby improving the instruction execution efficiency of the processor; in addition, when the program is executed by the processor, the instructions in the program are divided into blocks, and different instruction blocks are orderly allocated to different IEs for execution according to the execution order of the program, which can improve the resource utilization of the processor and reduce the copying of instructions between instruction caches, thereby reducing cost and power consumption.

[0010] In one possible implementation of the first aspect, the instruction block scheduler determines the first instruction engine based on the instruction processing request, which may include: the instruction block scheduler obtains, based on the instruction processing request, a candidate instruction engine for the first instruction set; the candidate instruction engine is an instruction engine that can be used to process the first instruction set. The instruction block scheduler selects an instruction engine from the candidate instruction engines as the first instruction engine. It is understood that the candidate instruction engine may be predetermined, i.e., may be obtained from an instruction block table in the instruction block scheduler. In the instruction block table, the mapping relationship between each instruction block and the instruction engine can generally be allocated and configured based on the characteristics of the program to be executed. For example, the allocation can be based on the uniformity of the number of instructions processed by each instruction engine. For example, taking the performance path of a program to be executed with three instruction blocks PBID=0, PBID=1, and PBID=2 as an example, assuming that the instruction blocks PBID=0 and PBID=1 each contain 24 instructions, while the instruction block PBID=2 contains 48 instructions; therefore, the instruction blocks PBID=0 and PBID=1 can be allocated to IE0 for execution, while the instruction block PBID=2 can be allocated to IE1 for execution, so that the number of instructions to be executed by different IEs is as uniform as possible. Therefore, through this possible implementation method, the instruction execution efficiency and resource utilization of the processor can be further improved.

[0011] Optionally, the instruction engine group may include a first alternative instruction engine group. The instruction block scheduler obtains the alternative instruction engine of the first instruction set according to the instruction processing request, which may include: if the first instruction set is an instruction set on a non-performance path, the instruction block scheduler uses the instruction engine in the first alternative instruction engine group as the alternative instruction engine of the first instruction set. In this optional scheme, since the instruction blocks on the non-performance path are mainly used to handle exceptions and process protocol messages, if the instruction block to be executed is an instruction block on the non-performance path, regardless of whether the instruction engine is congested or not, the instruction engine is directly selected from the instruction engine group (such as the static IE group) pre-allocated in the instruction block table, and other instruction engines are no longer expanded, thereby further reducing the instruction execution cost and power consumption of the processor.

[0012] Alternatively, the instruction engine group may include a first candidate instruction engine group and a second instruction engine group. The instruction block scheduler obtains the candidate instruction engines for the first instruction set based on the instruction processing request, which may include: if the first instruction set is an instruction set on the performance path, the instruction block scheduler uses the instruction engines in the first candidate instruction engine group or the second instruction engine group as the candidate instruction engines for the first instruction set. The first candidate instruction engine group is a static IE group pre-configured in the instruction block table, and the second instruction engine group is a collection of other instruction engines in the processor except for the IEs in the static IE group. In this optional solution, since the instruction blocks on the performance path belong to the main executed programs in the entire program, if the instruction block to be executed is an instruction block on the performance path, an instruction engine can be preferentially selected from the first candidate instruction engine group pre-assigned in the instruction block table. If the instruction engines in the pre-assigned first candidate instruction engine group are all in a congested state, the instruction engine can be expanded from other instruction engines of the processor, such as the second instruction engine group, to ensure that there are sufficient resources to process the instruction blocks on the performance path, thereby further improving the instruction execution efficiency of the processor.

[0013] Furthermore, the instruction block scheduler designates an instruction engine in the first candidate instruction engine group or the second instruction engine group as a candidate instruction engine for the first instruction set, which may include: if a first condition is met, the instruction block scheduler designates an instruction engine in the first candidate instruction engine group as a candidate instruction engine for the first instruction set. The first condition may be: the queue depth of the instruction processing request queue corresponding to at least one instruction engine in the first candidate instruction engine group is lower than a first preset threshold. Alternatively, if a second condition is met, the instruction block scheduler designates an instruction engine in the second instruction engine group as a candidate instruction engine for the first instruction set. The second condition may be: the queue depth of the instruction processing request queue corresponding to all instruction engines in the first candidate instruction engine group exceeds a first preset threshold. In this further embodiment, congestion of the instruction engines in the first candidate instruction engine group is determined by preconfiguring a first preset threshold. This first preset threshold can be modified based on the actual processor conditions. This improves the processor's instruction execution efficiency while minimizing processor power consumption.

[0014] Furthermore, the second instruction engine group may include a second candidate instruction engine group and a third candidate instruction engine group. The instruction block scheduler designating an instruction engine in the second instruction engine group as a candidate instruction engine for the first instruction set may include: the instruction block scheduler designating an instruction engine in the second candidate instruction engine group in the second instruction engine group as a candidate instruction engine for the first instruction set. If a third condition is met, the instruction block scheduler adds at least one instruction engine in the third candidate instruction engine group to the second candidate instruction engine group. The third condition may be: the second candidate instruction engine group is empty, or the queue depth of the instruction processing request queue corresponding to all instruction engines in the second candidate instruction engine group exceeds a second preset threshold. In this further solution, the second instruction engine group may be divided into a second candidate instruction engine group and a third candidate instruction engine group, wherein the second candidate instruction engine group is a dynamic IE group and is enabled; the third candidate instruction engine group is a disabled engine group. If the enabled instruction engines in the processor have fewer execution tasks, some instruction engines in the processor may be disabled to reduce processor power consumption. When the instruction engines in the second candidate instruction engine group, ie, the dynamic IE group, are all in a congested state, the instruction engines in the third candidate instruction engine group may be enabled to improve the instruction execution efficiency of the processor.

[0015] Optionally, the instruction block scheduler selects at least one instruction engine from the third candidate instruction engine group whose corresponding instruction processing request queue has a queue depth below a third preset threshold, and adds the selected instruction engine to the second candidate instruction engine group. In this optional solution, when expanding instruction engines from the third candidate instruction engine group, an instruction engine whose corresponding instruction processing request queue has a queue depth below the third preset threshold is selected, i.e., an instruction engine that is not congested is expanded, thereby improving instruction execution efficiency.

[0016] Optionally, the instruction processing method in the first aspect may further include: the instruction block scheduler records the instruction engine selection difference. If the instruction engine selection difference exceeds the fourth preset threshold, the instruction block scheduler deletes all instruction engines in the second alternative instruction engine group. The instruction engine selection difference is used to indicate: the difference between the number of times an instruction engine is selected from the first alternative instruction engine group and the number of times an instruction engine is selected from the second alternative instruction engine group. In this optional solution, in order to reduce the power consumption of the processor, for the instruction block to which the first instruction set belongs, if the number of times the instruction block selects the instruction engine IE from the second alternative instruction engine group, that is, the dynamic IE group, is very small, the instruction engine in the dynamic IE group can be deleted to reduce the power consumption of the processor.

[0017] Furthermore, the instruction block scheduler selects an instruction engine from the alternative instruction engines as the first instruction engine, which may include: the instruction block scheduler obtains the queue depth of the instruction processing request queue corresponding to the alternative instruction engine. The instruction block scheduler selects the alternative instruction engine corresponding to the instruction processing request queue with the smallest queue depth as the first instruction engine. In this further solution, the instruction engine that ultimately executes the first instruction set is determined from the alternative instruction engines, and the alternative instruction engine corresponding to the instruction processing request queue with the smallest queue depth is selected. This can reduce the number of instructions executed by each instruction engine, which is beneficial to improving the utilization of processor resources and improving the execution efficiency of the processor.

[0018] In one possible implementation, the instruction processing method of the first aspect may further include: when the first instruction buffer detects an end marker for the first instruction set, the first instruction buffer sends scheduling information to the instruction block scheduler, the scheduling information being used to indicate that the first instruction engine can process the next instruction processing request. In this manner, the polling scheduler in the instruction block scheduler can retrieve the next instruction processing request from the instruction processing request queue corresponding to the first instruction engine for processing by the first instruction engine, thereby ensuring sequential execution of instructions and improving processor efficiency.

[0019] In the second aspect, an embodiment of the present application provides a processor. The processor includes: an instruction block scheduler, an instruction cache group and an instruction engine group, the instruction cache group includes multiple instruction caches, and the instruction engine group includes multiple instruction engines; the multiple instruction caches in the instruction cache group correspond one-to-one to the multiple instruction engines in the instruction engine group. The instruction block scheduler is used to receive an instruction processing request; the instruction processing request is used to request the processor to process a first instruction set. The instruction block scheduler is used to determine the first instruction engine according to the instruction processing request; the first instruction engine is the instruction engine that processes the first instruction set in the instruction engine group, and the first instruction engine corresponds to the first instruction cache in the instruction cache group. The instruction block scheduler is used to send the instruction processing request to the first instruction cache corresponding to the first instruction engine. The first instruction engine is used to obtain the first instruction set from the first instruction cache.

[0020] Optionally, the processor further includes multiple instruction processing request queues, each corresponding one-to-one to the multiple instruction engines, and each corresponding one-to-one to the multiple instruction buffers; and an instruction block scheduler configured to determine a first instruction buffer corresponding to the first instruction engine based on the instruction processing request queue corresponding to the first instruction engine. Thus, a one-to-one correspondence between the multiple instruction engines and the multiple instruction buffers can be achieved through the one-to-one correspondence between the instruction processing request queues.

[0021] In a possible implementation of the second aspect, the instruction block scheduler may be specifically configured to: obtain, based on the instruction processing request, candidate instruction engines for the first instruction set, wherein the candidate instruction engines are instruction engines that can be used to process the first instruction set; and select an instruction engine from the candidate instruction engines as the first instruction engine.

[0022] Optionally, the instruction engine group may include a first candidate instruction engine group, which is specifically configured to use instruction engines in the first candidate instruction engine group as candidate instruction engines for the first instruction set if the first instruction set is an instruction set on a non-performance path.

[0023] Optionally, the instruction engine group may include a first candidate instruction engine group and a second instruction engine group. The instruction block scheduler is specifically configured to, if the first instruction set is an instruction set on the performance path, use an instruction engine in the first candidate instruction engine group or the second instruction engine group as a candidate instruction engine for the first instruction set.

[0024] Furthermore, the instruction block scheduler can be specifically used to: if the first condition is met, the instruction engines in the first alternative instruction engine group are used as alternative instruction engines for the first instruction set. The first condition may be: in the first alternative instruction engine group, there is at least one instruction engine whose corresponding instruction processing request queue has a queue depth lower than a first preset threshold. Alternatively, if the second condition is met, the instruction engines in the second instruction engine group are used as alternative instruction engines for the first instruction set. The second condition may be: in the first alternative instruction engine group, the queue depths of the instruction processing request queues corresponding to all instruction engines exceed the first preset threshold.

[0025] Furthermore, the second instruction engine group may include a second alternative instruction engine group and a third alternative instruction engine group. The instruction block scheduler can be specifically used to: use the instruction engines in the second alternative instruction engine group in the second instruction engine group as alternative instruction engines for the first instruction set. If the third condition is met, at least one instruction engine in the third alternative instruction engine group is added to the second alternative instruction engine group. The third condition can be: the second alternative instruction engine group is empty, or the queue depth of the instruction processing request queue corresponding to all instruction engines in the second alternative instruction engine group exceeds the second preset threshold.

[0026] Optionally, the instruction block scheduler may be specifically configured to select at least one instruction engine in the third candidate instruction engine group, the queue depth of the instruction processing request queue corresponding to the instruction engine being lower than a third preset threshold, and add the selected instruction engine to the second candidate instruction engine group.

[0027] Optionally, the instruction block scheduler may be further configured to record an instruction engine selection difference. If the instruction engine selection difference exceeds a fourth preset threshold, all instruction engines in the second candidate instruction engine group are deleted. The instruction engine selection difference indicates the difference between the number of times an instruction engine was selected from the first candidate instruction engine group and the number of times an instruction engine was selected from the second candidate instruction engine group.

[0028] In one possible implementation, the instruction block scheduler may be specifically configured to: obtain the queue depths of the instruction processing request queues corresponding to the candidate instruction engines, and select the candidate instruction engine corresponding to the instruction processing request queue with the smallest queue depth as the first instruction engine.

[0029] In a possible implementation, the first instruction buffer may be further configured to, upon detecting an end marker of the first instruction set, send scheduling information to the instruction block scheduler, where the scheduling information is used to indicate that the first instruction engine can process the next instruction processing request.

[0030] Optionally, the cache length of a single cache unit in each instruction cache in the instruction cache group is consistent with the number of instructions that can be processed in a single execution cycle of the corresponding instruction engine. Taking the instruction cache as a cache memory as an example, the cache length of a single cache unit in each instruction cache refers to the length of a cache line in each cache memory; the number of instructions that can be processed in a single execution cycle of the instruction engine refers to the size of the arithmetic logic unit (ALU) array that the instruction engine can process in a single execution cycle. For example, if the size of the ALU array that can be processed in a single execution cycle of instruction engine IE is 4 instructions, the length of the cache line in the cache memory corresponding to the instruction engine is also designed to cache 4 instructions. In this way, an instruction queue (Inst Q) is no longer required between the instruction engine IE and the cache memory to cache instructions, thereby reducing cost and power consumption.

[0031] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory coupled to the processor, wherein the processor is the processor provided by any possible implementation of the second aspect above.

[0032] It can be understood that any processor or electronic device of the instruction processing method based on multiple instruction engines provided above is used to execute the instruction processing method based on multiple instruction engines provided by the first aspect above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the instruction processing method based on multiple instruction engines provided by the first aspect above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a processor with multiple cache memories and multiple instruction engines;

[0034] Figure 2 A schematic diagram of the structure of a processor with multiple cache memories and multiple instruction engines provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of an instruction block allocation scheme provided in an embodiment of the present application;

[0036] Figure 4 A flowchart of an instruction processing method based on a multi-instruction engine provided in an embodiment of the present application;

[0037] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] Figure 1 The figure is a schematic diagram of the structure of a processor with multiple cache memories and multiple instruction engines. Figure 1 In the illustrated scheme, the processor consists of an instruction buffer (IBUF), multiple slice-based caches, a crossbar, multiple instruction engines (IEs), and instruction queues (Inst Q) corresponding to each of the IEs. Instructions are stored in the slice-based caches as follows: For example, using cache memories slice-based cache 0 – slice-based cache 15, assuming each cache line in the cache memories is eight instructions long, if the instruction corresponding to an instruction pointer (program counter) is stored in slice-based cache 0, then the eighth instruction following the instruction corresponding to the PC (i.e., the instruction corresponding to PC+8) is stored in slice-based cache 1, and so on. If the instruction corresponding to the PC is stored in slice-based cache 15, then the eighth instruction following the instruction corresponding to the PC (i.e., the instruction corresponding to PC+8) is stored in slice-based cache 0.

[0039] The specific processing flow is:

[0040] After receiving an instruction fetch request (hereinafter referred to as an instruction fetch request) containing an instruction pointer (program counter, PC), the instruction buffer (IBUF) caches the instruction fetch request in an instruction first-in, first-out (IFIFO) queue. The dispatcher (DISP) in the IBUF reads the instruction fetch request from the IFIFO queue and dispatches it to the execution thread corresponding to a specific instruction engine (IE). Each instruction engine (IE) corresponds to one execution thread.

[0041] When dispatching an instruction fetch request to the execution thread corresponding to the instruction engine IE, the following requirements must be met:

[0042] (1) The execution thread has completed the previous instruction fetch request;

[0043] (2) If there are multiple execution threads that can be allocated, they are allocated according to the queue depth of the instruction queue Inst Q corresponding to the instruction engine IE, and are allocated first to the execution thread corresponding to the instruction queue Inst Q with the shallowest queue depth.

[0044] After an instruction fetch request is assigned to an execution thread, the dispatcher (DISP) sends the instruction pointer (PC) in the instruction fetch request to the corresponding cache memory for fetching. After receiving the PC, the cache memory is dispatched by the scheduler (SCH) and enters the cache pipeline. In this pipeline, a tag lookup controller (Tag Lookup) searches the tag table, and then the arbiter (ARB) arbitrates the instruction. The tag table records the correspondence between the instruction pointer (PC) and the cached instruction data in the cache memory. By looking up the tag table, the arbiter determines whether the PC corresponds to a cache location (e.g., a cache line). If so, it's considered a hit; otherwise, it's a miss. The ARB arbiters evaluate the hit result obtained from the tag table to determine whether the instruction corresponding to the PC is a hit in the cache memory. After arbitration, if the instruction corresponding to the PC hits the cache memory, the instruction is retrieved from the cache data module within the cache memory and sent to the associated IE through the crossbar matrix. If the instruction misses the cache memory, a refill request, also known as a backfill request, is sent to the instruction memory (IMEM). This refill request requests that the instruction be retrieved from the IMEM and relearned into the corresponding cache memory. After the cache memory retrieves the instruction from the IMEM, it updates the tag table.

[0045] If there is no end indicator (EI) after the instruction corresponding to the PC (which can be obtained by looking up the tag table), then the PC+8 is sent to the next cache memory to initiate an instruction fetch request. The scheduler of the next cache memory schedules the instruction fetch request according to the state table and enters the pipeline of the next cache memory (the process after entering the pipeline of the cache memory is as described above and will not be repeated here).

[0046] If the backfill request reads the instruction from the instruction memory and returns it to the cache memory, the scheduler of the cache memory initiates an instruction backfill request according to the status table, fills the corresponding instruction into the cache memory data module, records the relevant information of the instruction in the tag table, and sends the instruction to the IE through the cross switch matrix.

[0047] If the instruction fetched from the cache memory has the EI flag, it indicates that the current PC has completed instruction fetching. If the execution thread corresponding to the current PC still has a PC waiting for instruction fetching, the execution thread uses the new PC to continue fetching instructions. If there are no PCs waiting for instruction fetching in the execution thread, it indicates that the current instruction fetch request has completed all instruction fetch operations and can process the next instruction fetch request.

[0048] It should be noted that in Figure 1 In the scheme, which cache memory the instruction is cached in is related to the PC of the instruction, and when fetching instructions continuously, it is necessary to fetch instructions cyclically in multiple cache memories, which may cause the instruction fetch requests to be unevenly distributed in multiple cache memories, resulting in a decrease in processor processing performance and low execution efficiency.

[0049] In addition, since multiple IEs share multiple high-speed cache memories, data transmission between the cache memories and the IEs needs to be performed through a crossbar switch matrix, which results in high hardware cost and power consumption.

[0050] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, ab, ac, bc or abc, where a, b and c can be single or multiple. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and execution order.

[0051] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0052] In addition, before introducing the embodiments of the present application, the technical terms involved in the embodiments of the present application are first introduced and explained.

[0053] Performance path: refers to the main execution path in a program.

[0054] Non-performance path: refers to the execution path in a program that handles exceptions or protocol messages.

[0055] Figure 2 A schematic diagram of the structure of a processor with multiple cache memories and multiple instruction engines provided in an embodiment of the present application, the processor comprising: an instruction block dispatcher (PBD), an instruction cache group (ICG), and an instruction engine group (IEG). The instruction cache group comprises multiple instruction caches, which may employ cache memories (cache), such as cache0-cache15; the instruction engine group comprises multiple instruction engines (IE), such as IE0-IE15; the multiple instruction caches in the instruction cache group correspond one-to-one to the multiple instruction engines in the instruction engine group, i.e., each IE exclusively uses one instruction cache, and the IE and instruction cache are bound one-to-one, so that each IE has a stable and deterministic instruction fetch bandwidth.

[0056] It should be noted that the processor may also include multiple instruction processing request queues, each corresponding one-to-one with multiple instruction engines; each corresponding one-to-one with multiple instruction buffers. In other words, each IE may correspond to an instruction processing request queue (IE-based queue), and each instruction request queue may correspond to an instruction buffer, thereby achieving a one-to-one correspondence between instruction processing request queues and instruction buffers. Furthermore, the instruction engines and corresponding instruction buffers may be connected via a hardware interface to facilitate instruction transmission. It should be understood that all instruction processing request queues may be managed by a queue manager (QM).

[0057] To reduce costs and power consumption, the cache length of a single cache unit in each instruction cache in the instruction cache group can be made consistent with the number of instructions that can be processed in a single execution cycle of the corresponding instruction engine. Taking the instruction cache as a cache memory cache as an example, the cache length of a single cache unit in each instruction cache refers to the length of a cache line in each cache memory; the number of instructions that can be processed in a single execution cycle of an instruction engine refers to the size of the arithmetic logic unit (ALU) array that the instruction engine can process in a single execution cycle. For example, if the size of the ALU array that can be processed in a single execution cycle of instruction engine IE is 4 instructions, the length of the cache line in the cache memory corresponding to the instruction engine is also designed to cache 4 instructions. In this way, an instruction queue (Inst Q) is no longer required between the instruction engine IE and the cache memory to cache instructions, thereby reducing costs and power consumption.

[0058] Of course, if the cache length of a single cache unit in each instruction cache in the instruction cache group is inconsistent with the number of instructions that can be processed in a single execution cycle of the corresponding instruction engine, an instruction queue can be set between the instruction cache and the IE to cache instructions so that the instructions can be executed sequentially by the IE.

[0059] Compared to Figure 1 In the processor shown in FIG, since the instruction cache and the instruction engine are bound one by one, the Figure 2 The processor shown in does not require a crossbar switch matrix, and the instruction cache length of a single cache unit of the bound instruction caches can be set to be the same as the number of instructions that can be processed in a single instruction cycle of the instruction engine, which can reduce the setting of the instruction queue Inst Q, thereby reducing the complexity of the processing flow and reducing the cost and power consumption of the processor.

[0060] exist Figure 2 The processor in [1] involves an instruction block scheduler. When executing a complete program using this processor, the program can be divided into several instruction blocks (program blocks). Each instruction block is assigned an identifier (ID) based on the program's execution order. This identifier is called a program block identifier (PBID). The program blocks are generally divided based on I / O operations or switch instructions.

[0061] It should be noted that a complete program can be divided into multiple phases based on the order in which it is executed. After the program is divided into several instruction blocks, each instruction block has only one PBID. Different instruction blocks in different phases are assigned different PBIDs, but they can also be the same. Different instruction blocks in the same phase are generally assigned different PBIDs.

[0062] In addition, according to the execution path of the program, the program can be divided into instruction blocks on the performance path and instruction blocks on the non-performance path. When allocating instruction blocks, for each instruction block at different stages on the same performance path, it can be evenly distributed to all IEs as much as possible, for example, each instruction block at different stages on the same performance path can be allocated to different IEs respectively. Of course, each instruction block at different stages on the non-performance path can also be evenly distributed to all IEs. In this way, it is possible to avoid the processing of each instruction block on the same performance path being concentrated on some IEs, increasing the processing burden of these some IEs, and increasing the burden on the instruction buffer corresponding to these some IEs, such as the cache memory, causing the cache memory hit rate to decrease, so as to improve the execution efficiency and resource utilization of the processor. In addition, since different instruction blocks at the same stage are usually located in different branches and are generally not executed at the same time, different instruction blocks at the same stage can be allocated to the same IE.

[0063] Below Figure 3 As an example, the allocation of instruction blocks is explained. Figure 3 A schematic diagram of an instruction block allocation scheme provided in an embodiment of the present application. Figure 3In the example shown, the program is divided into nine instruction blocks. On a performance path, the instruction blocks are PBID=0, PBID=2, PBID=4, PBID=5, and PBID=8; on a non-performance path, the instruction blocks are PBID=1, PBID=3, and PBID=4. The program is divided into five phases: Phase 1 has an instruction block with PBID=0; Phase 2 has an instruction block with PBID=1, PBID=2, and PBID=3; Phase 3 has an instruction block with PBID=4; Phase 4 has an instruction block with PBID=5 and PBID=6; and Phase 5 has an instruction block with PBID=7, PBID=8, and PBID=9. Therefore, according to the above IE allocation rule, for instruction blocks on the performance path, IEs can be allocated according to the following scheme. For example, the instruction block with PBID=0 is allocated IE0, the instruction block with PBID=2 is allocated IE1, the instruction block with PBID=4 is allocated IE2, the instruction block with PBID=5 is allocated IE3, and the instruction block with PBID=8 is allocated IE4. For instruction blocks on the non-performance path, IEs can be allocated according to the following scheme. For example, the instruction blocks with PBID=1 and PBID=2 belong to phase 2, and the instruction block with PBID=1 can also be allocated IE1. The instruction blocks with PBID=5 and PBID=6 belong to phase 4, and the instruction block with PBID=6 can also be allocated IE3. The instruction blocks with PBID=8 and PBID=9 belong to phase 5, and the instruction block with PBID=9 can also be allocated IE4.

[0064] In addition, it should be noted that the instruction blocks at different stages on the same performance path are evenly distributed to the IEs, which can also mean that the number of instructions allocated to each IE is basically the same. For example, a program has three instruction blocks on its performance path: PBID=0, PBID=1, and PBID=2. Assume that the instruction blocks with PBID=0 and PBID=1 each have 24 instructions, while the instruction block with PBID=2 has 48 instructions. Therefore, the instruction blocks with PBID=0 and PBID=1 can be allocated to IE0 for execution, while the instruction block with PBID=2 can be allocated to IE1 for execution. In this way, the number of instructions to be executed on IE0 and IE1 is equal.

[0065] Please refer to Figure 2,The instruction block scheduler includes the instruction block table (program block table,PBT), the lookup table controller (lookup table controller,LTC), the queue manager (queue management,QM) and the round robin (RR) scheduler.

[0066] The instruction block table PBT is pre-configured before the program is executed, for example, it can be generated during the program compilation process. The PBT may include the following fields:

[0067] PERF: Performance path field, which can be used to indicate whether the corresponding instruction block is on the performance path. It occupies 1 bit, where 1 can indicate that the corresponding instruction block is a performance path block, and 0 indicates that the corresponding instruction block is an instruction block on a non-performance path.

[0068] SF_BM: It is a bitmap-based static tag that can be used to specify whether the mapping relationship between the corresponding instruction block and all IEs is static or dynamic (taking 16 IEs, i.e. IE0-IE15, as an example). It occupies 16 bits. Each bit corresponds to an IE, i.e. SF_BM[0] corresponds to IE0, SF_BM[1] corresponds to IE1, and so on. When SF_BM[x]=1, it can be said that IEx and the instruction block have a static mapping relationship; when SF_BM[x]=0, it can be said that IEx and the instruction block have a dynamic mapping relationship. For instruction blocks and IEs with static mapping relationships, their mapping relationship will not be changed. For instruction blocks and IEs with dynamic mapping relationships, their mapping relationship can be changed according to the congestion status of the IE.

[0069] IE_BM: IE bitmap, which can be used to specify the mapping relationship between instruction blocks and IEs, occupies 16 bits. Each bit corresponds to an IE, that is, IE_BM[0] corresponds to IE0, IE_BM[1] corresponds to IE1, and so on. When IE_BM[x]=1, it means that the instruction block is mapped to IEx, that is, the instruction block can be assigned to IEx for execution, that is, the IEx is enabled; when IE_BM[x]=0, it means that the instruction block is not mapped to IEx, that is, the instruction block cannot be assigned to IEx for execution, that is, the IEx is disabled. x is an integer from 0 to 15.

[0070] DIFF_CNT: Records the difference between the number of times this instruction block selects an IE from a static mapping relationship and the number of times it selects an IE from a dynamic mapping relationship. This value indicates whether to delete the IE that has a dynamic mapping relationship with this instruction block. When an IE is selected from a static mapping relationship, DIFF_CNT increments by 1; when an IE is selected from a dynamic mapping relationship, DIFF_CNT decrements by 1.

[0071] It should be noted that when determining the IE to execute an instruction, priority is given to selecting an IE from a set of IEs that have a static mapping relationship with the instruction block to be executed. If no IE in the set of IEs that have a static mapping relationship with the instruction block to be executed meets the requirements, an IE can be selected from a set of IEs that have a dynamic mapping relationship with the instruction block to be executed. When determining the IE to execute an instruction, it should be ensured that the IE is in an enabled state. Therefore, IEs can be divided into three types: static IE group, dynamic IE group, and disabled IE group.

[0072] For a certain instruction block, the static IE group is a set of all IEs that have a static mapping relationship with the instruction block, and all IEs in the set are enabled, that is, IE_BM[m]=1 and SF_BM[m]=1.

[0073] The dynamic IE group is a set of all IEs that have a dynamic mapping relationship with the instruction block and are IE-enabled, that is, IE_BM[n]=1 and SF_BM[0]=0.

[0074] The disabled IE group is a set of all IEs that have a dynamic mapping relationship with the instruction block and are disabled, that is, IE_BM[t]=0 and SF_BM[t]=0.

[0075] The instruction block scheduler searches the instruction block table through a lookup table controller to determine the mapping between instruction blocks and IEs in the instruction engine group. It then determines the IE that will ultimately execute the instruction block based on the queue depth of the instruction processing request queue corresponding to each IE. The instruction processing request for the instruction block is then added to the instruction processing request queue corresponding to the corresponding IE, awaiting execution by the corresponding IE. The instruction processing request queue is managed by the queue associator QM; the instruction processing requests in the instruction processing request queue are scheduled by a round robin scheduler (RR).

[0076] also, Figure 2The processor shown may also include an input scheduler (IS) and an output scheduler (OS). The input scheduler IS is used to receive data from previous modules, which may include instruction processing requests, and is used to schedule and allocate instruction processing requests to the instruction block scheduler. The output scheduler OS is used to receive the processing results of the instruction blocks, determine whether the entire program has been executed, and schedule the instruction processing requests and instruction processing results based on the execution order of the various instruction blocks in the entire program.

[0077] Of course, the input scheduler and the output scheduler can also be designed as one scheduler, such as the input-output scheduler, which implements all the functions of the input scheduler and the output scheduler at the same time.

[0078] Figure 4 The flowchart of a multi-instruction engine-based instruction processing method provided in the embodiment of the present application can be applied to Figure 2 In the processor shown, the method includes the following steps.

[0079] S401: An instruction block scheduler receives an instruction processing request; the instruction processing request is used to request a processor to process a first instruction set.

[0080] Among them, the instruction processing request may include the PBID corresponding to the first instruction set and the instruction pointer (program counter, PC) corresponding to the first instruction set. The first instruction set is a set of all instructions in an instruction block; the PC corresponding to the first instruction set can be used to index the instructions in the first instruction set.

[0081] S402: The instruction block scheduler determines a first instruction engine according to the instruction processing request; the first instruction engine is an instruction engine in the instruction engine group that processes a first instruction set, and corresponds to a first instruction buffer in the instruction buffer.

[0082] Furthermore, the instruction block scheduler obtains candidate instruction engines for the first instruction set based on the instruction processing request; the candidate instruction engines are instruction engines that can be used to process the first instruction set. The instruction block scheduler selects an instruction engine from the candidate instruction engines as the first instruction engine.

[0083] It should be noted that the alternative instruction engine can be predetermined, such as determined by the above-mentioned PBT table, that is, the alternative instruction engine can be all IEs in the static IE group mapped to the instruction block belonging to the first instruction set; the alternative instruction engine can also be an IE dynamically added from the dynamic IE group mapped to the instruction block belonging to the first instruction set based on the congestion status of the instruction processing request queue corresponding to the IE in the static IE group.

[0084] Therefore, for different instruction blocks, the instruction engine group can be divided into a first candidate instruction engine group and a second instruction engine group. The first candidate instruction engine group can be a set of all IEs that have a static mapping relationship with the instruction block to which the first instruction set belongs, that is, the first candidate instruction engine group can be a static IE group. The second instruction engine group can be a set of all IEs that have a dynamic mapping relationship with the instruction block to which the first instruction set belongs, that is, the second instruction engine group can be a combination of a dynamic IE group and a disabled IE group.

[0085] The candidate instruction engines in the first instruction set may be determined in the following manner:

[0086] If the first instruction set is an instruction set on a non-performance path, the instruction block scheduler uses an instruction engine of the first candidate instruction engine group as a candidate instruction engine for the first instruction set.

[0087] If the first instruction set is an instruction set on the performance path, the instruction block scheduler uses an instruction engine in the first candidate instruction engine group or the second instruction engine group as a candidate instruction engine for the first instruction set.

[0088] Since instruction blocks (instruction sets) on the non-performance path primarily handle exceptions or protocol packets and generally don't consume much traffic, to ensure even resource distribution, the IEs that execute the instruction sets on the non-performance path can be directly selected based on the pre-configured mapping between instruction blocks and IEs. Specifically, the IEs with static mappings for the instruction blocks (IEs in the static IE group) can be selected. However, instruction blocks (instruction sets) on the performance path generally require more traffic and resources to execute. Therefore, the IEs with static mappings for the instruction blocks can be prioritized for execution. If all IEs with static mappings for the instruction block are congested, the IEs with dynamic mappings for the instruction block can be selected for execution. This approach allows for more even distribution of instruction blocks across IEs in a multi-IE processor while minimizing processor power consumption, thereby improving program execution efficiency and increasing processor resource utilization.

[0089] Specifically, if the first instruction set is an instruction set on the performance path, the candidate instruction engine may be determined as follows:

[0090] If a first condition is met, the instruction block scheduler selects an instruction engine in the first candidate instruction engine group as a candidate instruction engine for the first instruction set. The first condition is that the queue depth of the instruction processing request queue corresponding to at least one instruction engine in the first candidate instruction engine group is lower than a first preset threshold.

[0091] or,

[0092] If the second condition is met, the instruction block scheduler selects the instruction engines in the second instruction engine group as candidate instruction engines for the first instruction set. The second condition is that the queue depths of the instruction processing request queues corresponding to all instruction engines in the first candidate instruction engine group exceed a first preset threshold.

[0093] That is to say, if the queue depth of the instruction processing request queue corresponding to the IE reaches a first preset threshold, for example, 16, it means that the IE is in a congested state and is not suitable for allocating a new instruction set to be executed. If there is at least one IE in the first alternative instruction engine group that is not in a congested state, the instruction engine in the first alternative instruction engine group can still be used as an alternative instruction engine for the first instruction set; if there is no instruction engine in the first alternative instruction engine group that is not in a congested state, the instruction engine in the second instruction engine group can be used as an alternative instruction engine for the first instruction set. It should be understood that the first preset threshold is a pre-set specified value for determining whether the IE is congested, and the specified value can be changed according to the actual processing situation of the processor.

[0094] Furthermore, in order to reduce processor power consumption, some IEs can be disabled. When the disabled IEs are required to execute instructions, the IEs can be enabled to execute the corresponding instructions. Therefore, the second instruction engine group can be divided into a second alternative instruction engine group and a third alternative instruction engine group. The second alternative instruction engine group can be a set of all IEs that have a dynamic mapping relationship with the instruction block to which the first instruction set belongs, and the IE is enabled, that is, the above-mentioned dynamic IE group. The third alternative instruction engine group can be a set of all IEs that have a dynamic mapping relationship with the instruction block to which the first instruction set belongs, and the IE is not enabled, that is, the disabled IE group.

[0095] When the instruction block scheduler uses the instruction engines in the second instruction engine group as candidate instruction engines for the first instruction set, the instruction block scheduler uses the instruction engines in the second candidate instruction engine group in the second instruction engine group as candidate instruction engines for the first instruction set.

[0096] If a third condition is met, the instruction block scheduler adds at least one instruction engine from the third candidate instruction engine group to the second candidate instruction engine group. The third condition may be: the second candidate instruction engine group is empty, or the queue depth of the instruction processing request queue corresponding to all instruction engines in the second candidate instruction engine group exceeds a second preset threshold.

[0097] That is to say, when the instruction block scheduler uses the instruction engine in the second instruction engine group as the alternative instruction engine for the first instruction set, it gives priority to selecting an IE from the second alternative instruction engine group, that is, selecting an IE from the dynamic IE group. When there is no IE that meets the requirements in the second alternative instruction engine group, it selects an IE that meets the requirements from the third alternative instruction engine group and extends it to the second alternative instruction engine group, that is, it selects an IE that meets the requirements from the unenabled engine group and changes the state of the IE to an enabled state.

[0098] It should be noted that determining whether there are IEs meeting the requirements in the second candidate instruction engine group can also be based on the IE congestion status as a judgment condition. Similarly, a second preset threshold can be pre-set to determine whether there is IE congestion. When the queue depth of the instruction processing request queue corresponding to all instruction engines in the second candidate instruction engine group exceeds the second preset threshold, there are no IEs meeting the requirements to be selected in the second candidate instruction engine group. In this case, at least one IE needs to be added from the third candidate instruction engine group.

[0099] To improve instruction execution efficiency, when expanding IEs from the third candidate instruction engine group, non-congested IEs should also be expanded. Specifically, the instruction block scheduler selects at least one instruction engine from the third candidate instruction engine group whose corresponding instruction processing request queue has a queue depth below a third preset threshold and adds it to the second candidate instruction engine group. It should be understood that the third preset threshold is also a pre-set value used to determine whether an IE is congested, and this value can be changed based on the actual processing conditions of the processor.

[0100] It can be understood that the first preset threshold, the second preset threshold and the third preset threshold are specified values ​​used to determine whether the instruction engines in the first alternative instruction engine group, the second alternative instruction engine group and the third alternative instruction engine are congested, respectively. The first preset threshold, the second preset threshold and the third preset threshold can be the same or different.

[0101] In addition, to reduce processor power consumption, for an instruction block belonging to the first instruction set, if the number of times the instruction block selects an IE from the dynamic IE group is very small, the dynamic IE group can be deleted to reduce processor power consumption. Therefore, the instruction block scheduler records the instruction engine selection difference. The instruction engine selection difference is used to indicate the difference between the number of times an instruction engine is selected from the first candidate instruction engine group and the number of times an instruction engine is selected from the second candidate instruction engine group. That is, the instruction engine selection difference represents the difference between the number of times an IE is selected from the static IE group and the number of times an IE is selected from the dynamic IE group. Therefore, the instruction engine selection difference can be recorded using the DIFF_CNT field in the instruction block table.

[0102] If the instruction engine selection difference exceeds the fourth preset threshold, the instruction block scheduler deletes all instruction engines from the second candidate instruction engine group. In other words, when the instruction engine selection difference exceeds a certain value, this value is the fourth preset threshold, which is a value determined based on actual conditions, such as 500. When the instruction engine selection difference exceeds the fourth preset threshold, it indicates that the probability of the instruction block to which the first instruction set belongs selecting an instruction engine from the second candidate instruction engine group is very small. Therefore, the instruction block scheduler can configure IE_BM[n]=0 in the instruction block table to disable all instruction engines in the second candidate instruction engine group, thereby reducing the power consumption of the processor.

[0103] The above is an explanation of how to obtain the alternative instruction engines for the first instruction set. After the instruction block scheduler obtains the alternative instruction engines for the first instruction set, it can select an instruction engine from the alternative instruction engines of the first instruction set as the first instruction engine to process the first instruction set. The specific selection method is: the instruction block scheduler obtains the queue depth of the instruction processing request queue corresponding to the alternative instruction engine. The instruction block scheduler selects the alternative instruction engine corresponding to the instruction processing request queue with the smallest queue depth as the first instruction engine.

[0104] S403: The instruction block scheduler sends the instruction processing request to the first instruction buffer corresponding to the first instruction engine.

[0105] The instruction block scheduler may include multiple instruction processing request queues, each corresponding one-to-one to the multiple instruction engines, and each corresponding one-to-one to the multiple instruction buffers. The instruction block scheduler may determine the first instruction buffer corresponding to the first instruction engine based on the instruction processing request queue corresponding to the first instruction engine, thereby achieving a one-to-one correspondence between the first instruction engine and the first instruction buffer, i.e., the first instruction buffer is used to cache instructions processed by the first instruction engine.

[0106] When the instruction block scheduler determines that the first instruction set is processed by the first instruction engine, the instruction block scheduler sends the instruction pointer PC in the instruction processing request to the first instruction buffer. The first instruction buffer obtains the instructions of the first instruction set according to the instruction pointer PC and sends them to the first instruction engine for processing.

[0107] Of course, there may be a situation where the first instruction cache cannot hit the instruction in the first instruction set. In this case, the first instruction cache can learn from the instruction memory IMEM to obtain the instruction in the first instruction set.

[0108] S404: The first instruction engine obtains a first instruction set from the first instruction buffer.

[0109] After the first instruction buffer obtains the first instruction set based on the instruction pointer PC in the instruction processing request, the first instruction buffer can actively send it to the first instruction engine for processing, so that the first instruction engine can obtain the first instruction set from the first instruction buffer to process the first instruction set. It should be understood that the first instruction buffer and the first instruction engine can be connected via a hardware interface so that the first instruction buffer can send the first instruction set to the first instruction engine, or the first instruction engine can obtain the first instruction set from the first instruction buffer.

[0110] In addition, the multi-instruction engine-based instruction processing method provided in an embodiment of the present application may further include: when the first instruction buffer detects an end indicator (EI) of the first instruction set, the first instruction buffer sends scheduling information to the instruction block scheduler, the scheduling information being used to indicate that the first instruction engine can process the next instruction processing request. At this time, the polling scheduler RR in the instruction block scheduler can retrieve the next instruction processing request from the instruction processing request queue corresponding to the first instruction engine for processing by the first instruction engine.

[0111] When the first instruction engine detects the end marker EI of the first instruction set, the first instruction engine ends the processing of the first instruction set and initiates a scheduling request to the output scheduler OS.

[0112] The output scheduler OS responds to the scheduling request and determines whether the entire program has been executed. If it has been completed, the output scheduler OS outputs the processing result to the subsequent module; otherwise, the output scheduler OS will send the instruction processing request corresponding to the next instruction block to be executed to the input scheduler IS for further processing, and the cycle continues.

[0113] The above mainly introduces the instruction processing method based on a multi-instruction engine provided by the embodiment of the present application from the perspective of the processor. It can be understood that in order to implement the above functions, the processor includes a hardware structure and / or software module corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the network elements and algorithm steps of each example described in the embodiments disclosed in this document, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0114] The embodiment of the present application can divide the processor into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. In actual implementation, there may be other division methods.

[0115] The present application also provides a processor, the structure of which can be seen in the above Figure 2 As shown, the processor includes: an instruction block scheduler, an instruction cache group and an instruction engine group, the instruction cache group includes multiple instruction caches, and the instruction engine group includes multiple instruction engines; the multiple instruction caches in the instruction cache group correspond one-to-one to the multiple instruction engines in the instruction engine group. The instruction block scheduler is used to receive an instruction processing request; the instruction processing request is used to request the processor to process a first instruction set. The instruction block scheduler is used to determine the first instruction engine according to the instruction processing request; the first instruction engine is the instruction engine in the instruction engine group that processes the first instruction set, and the first instruction engine corresponds to the first instruction cache in the instruction cache group. The instruction block scheduler is used to send the instruction processing request to the first instruction cache corresponding to the first instruction engine. The first instruction engine is used to obtain the first instruction set from the first instruction cache.

[0116] Optionally, the processor further includes multiple instruction processing request queues, each corresponding one-to-one to the multiple instruction engines, and each corresponding one-to-one to the multiple instruction buffers; and an instruction block scheduler configured to determine a first instruction buffer corresponding to the first instruction engine based on the instruction processing request queue corresponding to the first instruction engine. Thus, a one-to-one correspondence between the multiple instruction engines and the multiple instruction buffers can be achieved through the one-to-one correspondence between the instruction processing request queues.

[0117] Specifically, the instruction block scheduler may be configured to: obtain candidate instruction engines for the first instruction set according to the instruction processing request; the candidate instruction engines are instruction engines that can be used to process the first instruction set; and select an instruction engine from the candidate instruction engines as the first instruction engine.

[0118] Optionally, the instruction engine group may include a first candidate instruction engine group, which is specifically configured to use instruction engines in the first candidate instruction engine group as candidate instruction engines for the first instruction set if the first instruction set is an instruction set on a non-performance path.

[0119] Optionally, the instruction engine group may include a first candidate instruction engine group and a second instruction engine group. The instruction block scheduler is specifically configured to, if the first instruction set is an instruction set on the performance path, use an instruction engine in the first candidate instruction engine group or the second instruction engine group as a candidate instruction engine for the first instruction set.

[0120] Furthermore, the instruction block scheduler can be specifically used to: if a first condition is met, the instruction engines in the first alternative instruction engine group are used as alternative instruction engines for the first instruction set. The first condition can be: in the first alternative instruction engine group, there is at least one instruction engine whose corresponding instruction processing request queue has a queue depth lower than a first preset threshold. Alternatively, if a second condition is met, the instruction engines in the second instruction engine group are used as alternative instruction engines for the first instruction set. The second condition can be: in the first alternative instruction engine group, the queue depths of the instruction processing request queues corresponding to all instruction engines exceed the first preset threshold.

[0121] Furthermore, the second instruction engine group may include a second alternative instruction engine group and a third alternative instruction engine group. The instruction block scheduler may be specifically used to: use the instruction engines in the second alternative instruction engine group in the second instruction engine group as alternative instruction engines for the first instruction set. If the third condition is met, at least one instruction engine in the third alternative instruction engine group is added to the second alternative instruction engine group. The third condition may be: the second alternative instruction engine group is empty, or the queue depth of the instruction processing request queue corresponding to all instruction engines in the second alternative instruction engine group exceeds the second preset threshold.

[0122] Optionally, the instruction block scheduler may be specifically configured to select at least one instruction engine in the third candidate instruction engine group, the queue depth of the instruction processing request queue corresponding to the instruction engine being lower than a preset threshold, and add the selected instruction engine to the second candidate instruction engine group.

[0123] Optionally, the instruction block scheduler may be further configured to record an instruction engine selection difference. If the instruction engine selection difference exceeds a fourth preset threshold, all instruction engines in the second candidate instruction engine group are deleted. The instruction engine selection difference indicates the difference between the number of times an instruction engine was selected from the first candidate instruction engine group and the number of times an instruction engine was selected from the second candidate instruction engine group.

[0124] Specifically, the instruction block scheduler may be configured to: obtain the queue depths of the instruction processing request queues corresponding to the candidate instruction engines, and select the candidate instruction engine corresponding to the instruction processing request queue with the smallest queue depth as the first instruction engine.

[0125] In addition, the instruction cache may be further configured to send scheduling information to the instruction block scheduler when an end marker of the first instruction set is detected, where the scheduling information is configured to indicate that the first instruction engine can process the next instruction processing request.

[0126] In an embodiment of the present application, each instruction engine in the processor can exclusively enjoy the services of an instruction cache, so that the processor has a stable and certain instruction fetch bandwidth, thereby improving the instruction execution efficiency of the processor; in addition, when the program is executed by the processor, the instructions in the program are divided into blocks, and different instruction blocks are orderly allocated to different IEs for execution according to the execution order of the program, which can improve the utilization of processor resources and reduce the copying of instructions between instruction caches, thereby reducing costs and power consumption.

[0127] In addition, since the instruction cache and instruction engine in the processor are bound one by one, the processor does not require a cross-switch matrix, and the instruction cache length of a single cache unit of the bound instruction cache can be set to the same as the processable instruction length of a single instruction cycle of the instruction engine, which can reduce the setting of the instruction queue Inst Q, thereby reducing the complexity of the processing flow and reducing the cost and power consumption of the processor.

[0128] like Figure 5 As shown, the embodiment of the present application also provides an electronic device, see Figure 5 The electronic device includes a memory 501 and a processor 502. The memory 501 is used to store the program code and data of the device, and the processor 502 is used to process the program code and data of the device. Figure 5 The structure of the processor 502 can be as described above. Figure 2 The structure shown is, for example, specifically used to support the instruction processing to execute S401-S403 in the above method embodiment, and / or other processes of the technology described herein. Figure 5 The electronic device shown may further include a communication interface 503, which is used to support the device to communicate.

[0129] The processor 502 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a processing chip, a field programmable gate array or other programmable logic device, a transistor logic device, a hardware component, or any combination thereof. It may implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of this application. The processor 502 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a digital signal processor and a microprocessor, and the like. The communication interface 503 may be a transceiver, a transceiver circuit, or a transceiver interface, and the like. The memory 501 may be a volatile memory or a non-volatile memory, and the like.

[0130] For example, the communication interface 503, the processor 502, and the memory 501 are interconnected via a bus 504; the bus 504 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus 504 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 The fact that only one thick line is used in FIG. 5 does not mean that there is only one bus or one type of bus. Optionally, the memory 501 may be included in the processor 502 .

[0131] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for processing instructions based on a multi-instruction engine, characterized in that: Applied in a processor, the processor comprising: an instruction block scheduler, an instruction cache group, and an instruction engine group, wherein the instruction cache group comprises a plurality of instruction caches, and the instruction engine group comprises a plurality of instruction engines; the plurality of instruction caches in the instruction cache group correspond one-to-one to the plurality of instruction engines in the instruction engine group; The method comprises: The instruction block scheduler receives an instruction processing request; the instruction processing request is used to request the processor to process a first instruction set; The instruction block scheduler determines a first instruction engine based on the instruction processing request; the first instruction engine is an instruction engine in the instruction engine group that processes the first instruction set; wherein the instruction block scheduler includes an instruction block table, the instruction block table records the instruction engines to which each instruction block in a program can be mapped; the instruction block scheduler determines the instruction engine to which each instruction block can be mapped based on the instruction block identification number in the instruction processing request; The instruction block scheduler sends the instruction processing request to a first instruction buffer corresponding to the first instruction engine; The first instruction engine obtains the first instruction set from the first instruction cache.

2. The method according to claim 1, characterized in that The instruction block scheduler determines a first instruction engine according to the instruction processing request, including: The instruction block scheduler obtains a candidate instruction engine of the first instruction set according to the instruction processing request; the candidate instruction engine is an instruction engine that can be used to process the first instruction set; The instruction block scheduler selects an instruction engine from the candidate instruction engines as the first instruction engine.

3. The method according to claim 2, characterized in that The instruction engine group includes a first candidate instruction engine group, which is a static instruction engine group pre-configured in the instruction block table; The instruction block scheduler obtains a candidate instruction engine of the first instruction set according to the instruction processing request, including: If the first instruction set is an instruction set on a non-performance path, the instruction block scheduler uses an instruction engine in the first candidate instruction engine group as a candidate instruction engine for the first instruction set.

4. The method according to claim 2, characterized in that The instruction engine group includes a first candidate instruction engine group and a second instruction engine group, the first candidate instruction engine group is a static instruction engine group pre-configured in the instruction block table, and the second instruction engine group is a collection of other instruction engines in the processor except the instruction engines in the static instruction engine group; The instruction block scheduler obtains a candidate instruction engine of the first instruction set according to the instruction processing request, including: If the first instruction set is an instruction set on the performance path, the instruction block scheduler uses an instruction engine in the first candidate instruction engine group or the second instruction engine group as a candidate instruction engine for the first instruction set.

5. The method according to claim 4, characterized in that The instruction block scheduler selects an instruction engine in the first candidate instruction engine group or the second instruction engine group as a candidate instruction engine for the first instruction set, including: If the first condition is met, the instruction block scheduler uses the instruction engine in the first candidate instruction engine group as the candidate instruction engine of the first instruction set; The first condition is: in the first candidate instruction engine group, there is at least one instruction engine whose corresponding instruction processing request queue has a queue depth lower than a first preset threshold; or, If the second condition is met, the instruction block scheduler uses the instruction engine in the second instruction engine group as a candidate instruction engine for the first instruction set; The second condition is that: in the first candidate instruction engine group, the queue depths of the instruction processing request queues corresponding to all the instruction engines exceed the first preset threshold.

6. The method according to any one of claims 4 to 5, characterized in that The second instruction engine group includes a second candidate instruction engine group and a third candidate instruction engine group; the second candidate instruction engine group is a dynamic instruction engine group in an enabled state, and the third candidate instruction engine group is a disabled engine group; The instruction block scheduler selects an instruction engine in the second instruction engine group as a candidate instruction engine for the first instruction set, including: The instruction block scheduler uses the instruction engines in the second candidate instruction engine group in the second instruction engine group as candidate instruction engines of the first instruction set; If the third condition is met, the instruction block scheduler adds at least one instruction engine in the third candidate instruction engine group to the second candidate instruction engine group; The third condition is: the second candidate instruction engine group is empty, or the queue depths of the instruction processing request queues corresponding to all the instruction engines in the second candidate instruction engine group exceed a second preset threshold.

7. The method according to claim 6, characterized in that The instruction block scheduler selects at least one instruction engine from the third candidate instruction engine group, the queue depth of the instruction processing request queue corresponding to the instruction engine being lower than a third preset threshold, and adds the selected instruction engine to the second candidate instruction engine group.

8. The method according to claim 6, characterized in that The method further comprises: The instruction block scheduler records the instruction engine selection difference; If the instruction engine selection difference exceeds a fourth preset threshold, the instruction block scheduler deletes all instruction engines in the second candidate instruction engine group; The instruction engine selection difference value is used to indicate the difference between the number of times an instruction engine is selected from the first candidate instruction engine group and the number of times an instruction engine is selected from the second candidate instruction engine group.

9. The method according to any one of claims 2 to 5, characterized in that The instruction block scheduler selects an instruction engine from the candidate instruction engines as the first instruction engine, including: The instruction block scheduler obtains the queue depth of the instruction processing request queue corresponding to the candidate instruction engine; The instruction block scheduler selects the candidate instruction engine corresponding to the instruction processing request queue with the smallest queue depth as the first instruction engine.

10. The method according to any one of claims 1 to 5, characterized in that The method further comprises: When the first instruction buffer detects the end marker of the first instruction set, the first instruction buffer sends scheduling information to the instruction block scheduler, where the scheduling information is used to indicate that the first instruction engine can process a next instruction processing request.

11. A processor, characterized in that: The processor includes: an instruction block scheduler, an instruction cache group, and an instruction engine group, wherein the instruction cache group includes a plurality of instruction caches, and the instruction engine group includes a plurality of instruction engines; the plurality of instruction caches in the instruction cache group correspond one-to-one to the plurality of instruction engines in the instruction engine group; The instruction block scheduler is configured to receive an instruction processing request; the instruction processing request is configured to request the processor to process a first instruction set; The instruction block scheduler is configured to determine a first instruction engine based on the instruction processing request; the first instruction engine is an instruction engine in the instruction engine group that processes the first instruction set; wherein the instruction block scheduler includes an instruction block table, the instruction block table recording the instruction engines to which each instruction block in a program can be mapped; the instruction block scheduler determines the instruction engine to which each instruction block can be mapped based on the instruction block identification number in the instruction processing request; The instruction block scheduler is configured to send the instruction processing request to a first instruction buffer corresponding to the first instruction engine; The first instruction engine is configured to obtain the first instruction set from the first instruction cache.

12. The processor according to claim 11, wherein: The processor also includes multiple instruction processing request queues, which correspond one-to-one to the multiple instruction engines, and the multiple instruction processing request queues correspond one-to-one to the multiple instruction caches; the instruction block scheduler is used to determine the first instruction cache corresponding to the first instruction engine based on the instruction processing request queue corresponding to the first instruction engine.

13. The processor according to claim 11, wherein: The instruction block scheduler is specifically used to: Obtaining, according to the instruction processing request, an alternative instruction engine for the first instruction set; the alternative instruction engine being an instruction engine that can be used to process the first instruction set; An instruction engine is selected from the candidate instruction engines as the first instruction engine.

14. The processor according to claim 13, wherein: The instruction engine group includes a first alternative instruction engine group; the first alternative instruction engine group is a static instruction engine group pre-configured in the instruction block table; the instruction engine group is specifically used to, if the first instruction set is an instruction set on a non-performance path, use the instruction engine in the first alternative instruction engine group as the alternative instruction engine for the first instruction set.

15. The processor according to claim 13, wherein: The instruction engine group includes a first alternative instruction engine group and a second instruction engine group; the first alternative instruction engine group is a static instruction engine group pre-configured in the instruction block table, and the second instruction engine group is a collection of other instruction engines in the processor except the instruction engines in the static instruction engine group; the instruction block scheduler is specifically used to, if the first instruction set is an instruction set on the performance path, use the instruction engines in the first alternative instruction engine group or the second instruction engine group as alternative instruction engines for the first instruction set.

16. The processor according to claim 15, wherein: The instruction block scheduler is specifically used for: If the first condition is met, the instruction engine in the first candidate instruction engine group is used as a candidate instruction engine for the first instruction set; The first condition is: in the first candidate instruction engine group, there is at least one instruction engine whose corresponding instruction processing request queue has a queue depth lower than a first preset threshold; or, If the second condition is met, using the instruction engine in the second instruction engine group as a candidate instruction engine for the first instruction set; The second condition is that: in the first candidate instruction engine group, the queue depths of the instruction processing request queues corresponding to all the instruction engines exceed the first preset threshold.

17. The processor according to any one of claims 15 to 16, characterized in that: The second instruction engine group includes a second candidate instruction engine group and a third candidate instruction engine group; the second candidate instruction engine group is a dynamic instruction engine group in an enabled state, and the third candidate instruction engine group is a disabled engine group; the instruction block scheduler is specifically configured to: using an instruction engine in a second candidate instruction engine group in the second instruction engine group as a candidate instruction engine for the first instruction set; If the third condition is met, adding at least one instruction engine in the third candidate instruction engine group to the second candidate instruction engine group; The third condition is: the second candidate instruction engine group is empty, or the queue depths of the instruction processing request queues corresponding to all the instruction engines in the second candidate instruction engine group exceed a second preset threshold.

18. The processor according to claim 17, wherein: The instruction block scheduler is specifically configured to select at least one instruction engine in the third candidate instruction engine group, the queue depth of the instruction processing request queue corresponding to the instruction engine being lower than a third preset threshold, and add the selected instruction engine to the second candidate instruction engine group.

19. The processor according to claim 18, wherein: The instruction block scheduler is further configured to: Record instruction engine selection difference; If the instruction engine selection difference exceeds a fourth preset threshold, all instruction engines in the second candidate instruction engine group are deleted; The instruction engine selection difference value is used to indicate the difference between the number of times an instruction engine is selected from the first candidate instruction engine group and the number of times an instruction engine is selected from the second candidate instruction engine group.

20. The processor according to any one of claims 13 to 16, wherein: The instruction block scheduler is specifically used for: Obtaining a queue depth of a command processing request queue corresponding to the candidate command engine; The candidate instruction engine corresponding to the instruction processing request queue with the smallest queue depth is selected as the first instruction engine.

21. The processor according to any one of claims 11 to 16, wherein: The instruction buffer is further configured to, upon detecting an end marker of the first instruction set, send scheduling information to the instruction block scheduler, wherein the scheduling information is configured to indicate that the first instruction engine can process a next instruction processing request.

22. An electronic device, characterized in that: The electronic device includes a processor and a memory coupled to the processor, wherein the processor is the processor according to any one of claims 11 to 21.

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