Semiconductor device, method for manufacturing the same, and electronic device

Abstract

Embodiments of the present disclosure provide a semiconductor device, a manufacturing method thereof, and an electronic device, which can solve the problems of low effective utilization rate of high-cost wafers in the process of manufacturing semiconductor devices and effectively improve the process stability in the production process of semiconductor devices. The semiconductor device includes: a first substrate, at least one transistor, an auxiliary carrier portion, and a plurality of metal patterns. The auxiliary carrier portion and the at least one transistor are disposed on the first substrate. The orthographic projection of the auxiliary carrier portion on the first substrate is located outside the orthographic projection of the at least one transistor on the first substrate, and a part of the boundary of the orthographic projection of the auxiliary carrier portion on the first substrate coincides with a part of the boundary of the orthographic projection of the at least one transistor on the first substrate. The plurality of metal patterns are formed on a side of the auxiliary carrier portion facing away from the first substrate, and at least one of the metal patterns is coupled to the gate of the transistor, and at least one of the metal patterns is coupled to the drain of the transistor.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and in particular, to a semiconductor device, a method for manufacturing the same, and an electronic device. Background Art

[0002] Nitrides and their alloys based on group III-V elements, such as gallium nitride (GaN), as the third-generation semiconductor materials, have excellent properties such as high breakdown field strength, high thermal stability, and high electron saturation drift velocity.

[0003] Currently, semiconductor devices prepared using wide-bandgap semiconductors such as gallium nitride as semiconductor materials, such as heterojunction field effect transistors (HFETs) or high electron mobility transistors (HEMTs), have characteristics such as heat resistance, high frequency, high power, and radiation resistance, and can be widely applied in fields such as wireless communication.

[0004] Exemplarily, a gallium nitride-based high electron mobility transistor (GaN-HEMT) can also be referred to as a gallium nitride-based two-dimensional electron gas field effect transistor or a gallium nitride-based modulation-doped field effect transistor, and it can be obtained by relying on the preparation of a gallium nitride wafer. However, the cost of gallium nitride wafers is high. In the case where a semiconductor device is composed of one or more GaN-HEMTs and the semiconductor device is batch-produced using gallium nitride wafers, if the area utilization rate of the gallium nitride wafer is low, it is easy to cause the production cost of the semiconductor device to remain high.

[0005] For example, in a GaN-HEMT device, the GaN semiconductor layer includes an active area and a passive area. The active area refers to the area in the GaN semiconductor layer used to form a conductive channel, and the passive area is the area outside the active area. Metal wires or bonding pads used for interconnecting with an external power supply or an external signal source in the GaN-HEMT device are correspondingly formed in the passive area. Thus, the portion of the GaN semiconductor layer located in the passive area actually does not play the role of a semiconductor. That is to say, only the portion of the GaN semiconductor layer located in the active area is the effective part for its operation. Therefore, the area ratio of the active area in the entire GaN semiconductor layer is the area utilization rate of the GaN semiconductor layer. In some cases, the area ratio of the active area in the entire GaN semiconductor layer is less than 50%, that is, the area utilization rate of the GaN semiconductor layer is less than 50%, which will cause serious cost waste. Summary of the Invention

[0006] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and an electronic device, which are used to solve the problem of low area utilization of wide bandgap semiconductor wafers such as gallium nitride during batch preparation of semiconductor devices, thereby reducing the production cost of semiconductor devices, and effectively improving the process stability during the production of semiconductor devices, as well as improving the heat dissipation capacity of semiconductor devices.

[0007] On the one hand, some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a first substrate, at least one transistor, an auxiliary carrier, and a plurality of metal patterns. The auxiliary carrier and the at least one transistor are arranged on the first substrate. The orthographic projection of the auxiliary carrier on the first substrate is located outside the orthographic projection of the at least one transistor on the first substrate, and the orthographic projection boundary of the auxiliary carrier on the first substrate partially overlaps with the orthographic projection boundary of the at least one transistor on the first substrate. Each transistor in the at least one transistor includes: a semiconductor layer, and a gate, a drain, and a source located on a side of the semiconductor layer away from the first substrate. The plurality of metal patterns are formed on a side of the auxiliary carrier away from the first substrate. At least one metal pattern among the plurality of metal patterns is coupled to the gate, at least one metal pattern is coupled to the drain, and the metal pattern coupled to the gate and the metal pattern coupled to the drain are insulated.

[0008] In the embodiment of the present disclosure, the auxiliary carrier part and the at least one transistor are arranged on the first substrate, which means that the auxiliary carrier part and the at least one transistor can be transferred to the first substrate synchronously. That is to say, the transistor or the component of the transistor (such as a semiconductor layer, etc.) can be prepared on the semiconductor wafer in advance, and then transferred to the first substrate synchronously with the auxiliary carrier part, that is, the first substrate is not the preparation substrate of the transistor. Since the orthographic projection of the auxiliary carrier part on the first substrate is outside the orthographic projection of the at least one transistor on the first substrate, and the orthographic projection boundary of the auxiliary carrier part on the first substrate partially overlaps with the orthographic projection boundary of the at least one transistor on the first substrate, the auxiliary carrier part can be formed beside the at least one transistor during the transfer process of the transistor, and transferred to the first substrate synchronously with the at least one transistor. In this way, the auxiliary carrier part is used to support and protect the at least one transistor, which can effectively improve the process stability during the production process of semiconductor devices.

[0009] In addition, the first substrate is not the substrate for fabricating the transistors. Moreover, the auxiliary carrier portion can be formed during the transfer process of the at least one transistor, and the metal pattern can be formed after the auxiliary carrier portion and the transistors are transferred onto the first substrate. Therefore, the fabrication of the transistors on the semiconductor wafer can be unaffected by the positions of other components such as the metal pattern in the semiconductor device. In this way, during the batch fabrication of transistors on the semiconductor wafer, only a small or no passive region needs to be reserved in the semiconductor layer on the semiconductor wafer. As a result, the semiconductor layer on the semiconductor wafer can be effectively utilized to fabricate the active regions of the transistors, ensuring that the semiconductor wafer has a high area utilization rate and a high die-per-wafer output.

[0010] Based on this, when the material cost and transfer process cost of the first substrate are lower than those of wide bandgap semiconductor wafers such as gallium nitride, the semiconductor device with the above structure can also reduce the production cost of the semiconductor device. Moreover, when the first substrate is made of a material with a high thermal conductivity, the first substrate can be used to effectively improve the heat dissipation capacity of the semiconductor device, so that a greater power density can be achieved on the same active region area, or the active region area can be correspondingly reduced on the premise of achieving the same power, thereby further reducing the production cost of the semiconductor device.

[0011] It should be noted that the transistors usually further include a first passivation layer located on the surface of the semiconductor layer facing away from the first substrate. The first passivation layer includes a plurality of openings. The gate, source, and drain in the transistors are respectively formed within the corresponding openings.

[0012] In a possible implementation, the surface of the auxiliary carrier portion facing away from the first substrate is flush or substantially flush with the surface of the gate or drain facing away from the first substrate. This is beneficial for forming a metal pattern with good flatness on the auxiliary carrier portion to ensure the film formation quality of the metal pattern.

[0013] In another possible implementation, the surface of the auxiliary carrier portion facing away from the first substrate is flush or substantially flush with the surface of the first passivation layer facing away from the first substrate. In this way, the transistors and the auxiliary carrier portion can be synchronously transferred onto the first substrate before the gates, sources, and drains of the transistors are fabricated, so as to effectively protect the semiconductor layer by using the first passivation layer and prevent the gates, sources, and drains of the transistors from being damaged due to the transfer of the transistors.

[0014] In yet another possible implementation, the transistor further includes a second passivation layer. The second passivation layer includes a plurality of openings. The second passivation layer is formed on the surface of the first passivation layer facing away from the semiconductor layer, and is located on the side of the gate, source, and drain facing away from the semiconductor layer. The surface of the auxiliary carrier portion facing away from the first substrate is flush or substantially flush with the surface of the second passivation layer facing away from the first substrate. The metal pattern is coupled to the gate or drain through the corresponding opening in the second passivation layer. In this way, after the gate, source, drain, and the second passivation layer of the transistor are fabricated, the transistor and the auxiliary carrier portion can be synchronously transferred onto the first substrate, so as to effectively protect the gate, source, and drain of the transistor by using the second passivation layer, thereby avoiding damage to the gate, source, and drain of the transistor due to the transfer of the transistor.

[0015] In some of the above embodiments, there can be various ways to arrange the auxiliary carrier portion beside the transistor. Optionally, the auxiliary carrier portion is disposed on at least two sides of the at least one transistor described above, and the two sides include opposite sides or adjacent sides. For example, the auxiliary carrier portion is disposed around the periphery of the at least one transistor described above. The embodiments of the present disclosure do not limit this.

[0016] Optionally, the orthographic projection area of the at least one transistor on the first substrate is a first area S1. The orthographic projection area of the auxiliary carrier portion on the first substrate is a second area S2. In the embodiments of the present disclosure, it is defined that:

[0017]

[0018] The auxiliary carrier portion can effectively support and protect the transistor, thereby improving the process stability during the production of semiconductor devices.

[0019] In some embodiments, the material of the auxiliary carrier portion includes silicon oxide, silicon nitride, silicon oxynitride, silicon, silicon carbide, aluminum nitride, aluminum oxide, epoxy resin, polyimide, or benzocyclobutene. The auxiliary carrier portion is prepared from an insulating material with certain mechanical strength, which can not only have good support strength but also effectively insulate the semiconductor layer and the metal pattern.

[0020] In some embodiments, the semiconductor device further includes a heat dissipation insulating layer. The heat dissipation insulating layer is formed on the surfaces of the auxiliary carrier portion and the transistor facing away from the first substrate. The metal pattern is formed on the surface of the heat dissipation insulating layer facing away from the auxiliary carrier portion. The heat dissipation insulating layer can be prepared from an insulating material with good heat dissipation ability. The heat dissipation insulating layer is, for example, a diamond layer. The metal pattern is formed on the surface of the heat dissipation insulating layer facing away from the auxiliary carrier portion, and can effectively conduct the heat generated during the operation of the transistor through the heat dissipation insulating layer, thereby effectively improving the heat dissipation ability of the semiconductor device.

[0021] Optionally, the orthographic projection of the auxiliary carrier portion on the first substrate is located within the orthographic projection of the heat dissipation insulating layer on the first substrate. A partial surface of the heat dissipation insulating layer is in direct contact with the first substrate. Thus, in the case where the first substrate has a high thermal conductivity, the heat dissipation insulating layer is in direct contact with the first substrate, and can also conduct heat to the first substrate to further improve the heat dissipation capacity of the semiconductor device.

[0022] In some embodiments, the semiconductor device further includes: a metal layer formed on a surface of the first substrate facing away from the transistor. In the embodiments of the present disclosure, forming a metal layer on the surface of the first substrate facing away from the transistor can also utilize the metal layer to improve the heat dissipation capacity of the first substrate. The metal layer can be made of a metal material with good heat dissipation capacity, and the metal material is, for example, at least one of copper, aluminum, platinum, tungsten, nickel, iridium, or cobalt.

[0023] Optionally, the semiconductor device further includes at least one first via hole. The first via hole penetrates at least the first substrate and the semiconductor layer. The orthographic projection of the first via hole on the metal layer is located within the orthographic projection of the source electrode in the corresponding transistor on the metal layer. The metal layer is coupled to the source electrode through the first via hole.

[0024] Optionally, the semiconductor device further includes at least one second via hole. The second via hole penetrates at least the first substrate and the auxiliary carrier portion. The orthographic projection of the second via hole on the metal layer is located within the orthographic projection of the corresponding metal pattern on the first substrate. The metal layer is coupled to the metal pattern through the second via hole.

[0025] In the above-mentioned some embodiments, the metal layer is coupled to the corresponding source electrode or metal pattern, and the metal layer can also be used as a common electrode to provide a ground signal or a floating signal to the transistors or other electronic components in the semiconductor device. In addition, the layer structures penetrated by the first via hole and the second via hole are all related to the layer structure in the semiconductor device, and can be set according to actual needs.

[0026] In some embodiments, the semiconductor device further includes a heat dissipation substrate. The heat dissipation substrate is located on a side of the metal layer facing away from the first substrate. The metal layer is welded to the heat dissipation substrate. Thus, the heat dissipation capacity of the semiconductor device can be further improved by using the heat dissipation substrate. Optionally, the heat dissipation substrate is a substrate with a high thermal conductivity such as an aluminum substrate, a copper substrate, a diamond / metal composite substrate, a ceramic substrate, a rigid printed circuit board, or a flexible printed circuit board.

[0027] In some embodiments, the surface of the auxiliary carrier close to the first substrate is flush or substantially flush with the surface of the semiconductor layer close to the first substrate. In this way, it is convenient to use the same polishing process to prepare the flush surfaces of the auxiliary carrier and the semiconductor layer, so as to ensure that both the auxiliary carrier and the semiconductor layer have good surface quality. Thereby, good bonding between the auxiliary carrier and the semiconductor layer and the first substrate is achieved, or a first substrate with good film quality is formed on the auxiliary carrier and the semiconductor layer. Further, it is helpful to improve the reliability of the semiconductor device.

[0028] Optionally, the semiconductor device further includes a non-conductive bonding layer. The auxiliary carrier and the semiconductor layer of the transistor are bonded to the first substrate via the non-conductive bonding layer. By using the non-conductive bonding layer, not only can the bonding strength between the auxiliary carrier and the transistor and the first substrate be enhanced, but also it can be ensured that the transistor will not have leakage current due to its presence, which is conducive to ensuring the electrical performance of the semiconductor device.

[0029] In some other embodiments, the transistor further includes: a transition layer and a second substrate stacked on the side of the semiconductor layer away from the gate. Here, the second substrate is a preparation substrate of the transistor or a part of the preparation substrate, such as a base of a semiconductor wafer, on which the transition layer and the semiconductor layer can be epitaxially grown. The second substrate is made of a material with good lattice matching and thermal matching with the semiconductor layer. For example, the semiconductor layer includes a GaN layer, and the second substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate.

[0030] On this basis, the surface of the auxiliary carrier close to the first substrate is flush or substantially flush with the surface of the second substrate close to the first substrate. In this way, it is convenient to use the same polishing process to prepare the flush surfaces of the auxiliary carrier and the second substrate, so as to ensure that both the auxiliary carrier and the second substrate have good surface quality. Thereby, good bonding between the auxiliary carrier and the second substrate and the first substrate is achieved, or a first substrate with good film formation quality is formed on the auxiliary carrier and the second substrate. Further, it is beneficial to improve the reliability of the semiconductor device.

[0031] Optionally, the semiconductor device further includes a bonding layer. The auxiliary carrier and the second substrate in the transistor can be bonded to the first substrate through a bonding layer, so as to utilize the bonding layer to enhance the bonding strength between the auxiliary carrier and the transistor and the first substrate. Furthermore, the bonding layer can be a non-conductive bonding layer, so as to utilize the non-conductive bonding layer to ensure that the transistor does not have leakage current and the like due to its existence, which is beneficial to ensure the electrical performance of the semiconductor device. Alternatively, when the second substrate retains a certain thickness and has insulating properties, for example, the second substrate is a semi-insulating silicon carbide substrate of 5μm-10um, the bonding layer can also be a conductive bonding layer. In this way, the use of the second substrate can eliminate the influence of the conductive bonding layer on the electrical performance of the semiconductor device.

[0032] In addition, in a possible implementation, the semiconductor device includes a first via hole, and the first via hole includes a first sub-via hole and a second sub-via hole which are arranged in segments. The first sub-via hole penetrates through the second substrate, the transition layer and the semiconductor layer, and two ends of the first sub-via hole are respectively coupled to the source electrode and the conductive bonding layer. The second sub-via hole penetrates through the first substrate, and two ends of the second sub-via hole are respectively coupled to the conductive bonding layer and the metal layer. In this way, when the bonding layer is a conductive bonding layer, the first via hole is composed of the first sub-via hole and the second sub-via hole, which can reduce the manufacturing difficulty of the first via hole and ensure the electrical connection performance of the first via hole, especially for the case where the thicknesses of the first substrate and the transistor are relatively large.

[0033] In another possible implementation, the semiconductor device includes a second via hole, and the second via hole includes a third sub-via hole and a fourth sub-via hole which are arranged in segments. The third sub-via hole penetrates through at least the auxiliary carrying portion, and two ends of the third sub-via hole are respectively coupled to the metal pattern and the conductive bonding layer. The fourth sub-via hole penetrates through the first substrate, and two ends of the fourth sub-via hole are respectively coupled to the conductive bonding layer and the metal layer. In this way, when the bonding layer is a conductive bonding layer, the second via hole is composed of the third sub-via hole and the fourth sub-via hole, which can reduce the manufacturing difficulty of the second via hole and ensure the electrical connection performance of the second via hole, especially for the case where the thicknesses of the first substrate and the auxiliary carrying portion are relatively large.

[0034] In some embodiments, the first substrate includes: a single-crystal silicon carbide substrate, a polycrystalline silicon carbide substrate, a single-crystal aluminum nitride substrate, a polycrystalline aluminum nitride substrate, a single-crystal diamond substrate, a polycrystalline diamond substrate, a graphite substrate, a multi-layer graphene substrate or a copper substrate. Among them, the single-crystal silicon carbide substrate includes: a high-purity semi-insulating single-crystal silicon carbide substrate or a vanadium-doped silicon carbide substrate. The first substrate uses a substrate with a cost lower than that of a wide-bandgap semiconductor wafer, which is beneficial to reducing the production cost of the semiconductor device. The first substrate uses a substrate with a relatively high thermal conductivity. For example, under the condition that the temperature is 300K, the thermal conductivity of the first substrate is greater than 200W / mK, which can ensure that the semiconductor device has good heat dissipation ability.

[0035] Optionally, the first substrate is a polycrystalline silicon carbide substrate, a polycrystalline aluminum nitride substrate or a polycrystalline diamond substrate. In this way, the first substrate can be prepared by a chemical vapor deposition process.

[0036] On this basis, the semiconductor device further includes a gas barrier layer. The gas barrier layer is, for example, at least one layer of a silicon layer, a silicon nitride layer, an aluminum nitride layer, or a silicon carbide layer. The gas barrier layer is formed on the surfaces of the auxiliary carrier portion and the transistor close to the first substrate. The first substrate is formed on the surface of the gas barrier layer facing away from the auxiliary carrier portion. In the embodiment of the present disclosure, by providing a gas barrier layer between the first substrate, the auxiliary carrier portion, and the transistor, during the preparation process of the semiconductor device, the gas barrier layer can effectively prevent the gas used in the first substrate deposition process from damaging or destroying the semiconductor layer.

[0037] In some embodiments, the semiconductor device further includes: a plurality of bonding pads. The bonding pads are formed on corresponding metal patterns, and the orthographic projection of the bonding pads on the first substrate is located in the area of the first substrate not covered by the transistors. This facilitates bonding an external metal wire to the surface of the bonding pad, so as to couple with an external component using the metal wire to achieve the transmission of electrical signals between the semiconductor device and the external component.

[0038] It should be added that, in the above-mentioned some embodiments, the semiconductor layer includes a channel layer and a barrier layer stacked in a direction away from the first substrate. Optionally, the channel layer is a gallium nitride layer, and the barrier layer is a gallium aluminum nitride layer or an aluminum nitride layer. Or, the channel layer is a gallium arsenide layer, and the barrier layer is a gallium aluminum arsenide layer. Or, the channel layer is a gallium oxide layer, and the barrier layer is an aluminum nitride layer or a gallium aluminum oxide layer.

[0039] In addition, optionally, the thickness of the transistor is less than 10 μm, which is beneficial to realizing the thinning and lightening of the semiconductor device and reducing the thermal resistance of the semiconductor device. The value range of the area ratio of the active region of the transistor in its semiconductor layer is 80% - 100%, which can make the area utilization rate of the semiconductor wafer required for preparing the transistor reach 80% or more, so as to reduce the production cost of the semiconductor device.

[0040] On the other hand, some embodiments of the present disclosure provide an electronic device. The electronic device includes: at least one semiconductor device as described in any of the above embodiments. The technical effects that can be achieved by the electronic device in the embodiments of the present disclosure are the same as those that can be achieved by the semiconductor device in the foregoing some embodiments, and will not be elaborated here.

[0041] On yet another aspect, some embodiments of the present disclosure provide a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes the following steps.

[0042] First, provide a wafer, and fabricate a plurality of transistors or partial layers of a plurality of transistors on the wafer, wherein the front side of the transistor or its partial layer is the outermost surface facing away from the wafer. Cut the wafer along the thickness direction of the wafer to obtain a plurality of device particles. One device particle includes at least one transistor or at least one partial layer of a transistor.

[0043] Secondly, a support substrate is provided, and the front surface of at least one device particle is bonded to the support substrate. The front surface of the device particle is the front surface of the aforementioned transistor or its partial layer.

[0044] Then, an auxiliary carrier film is formed on the surface of the support substrate not covered by the device particle and on the back surface of the device particle. The auxiliary carrier film and the device particle are polished to obtain at least one transistor and an auxiliary carrier portion beside the at least one transistor. The polished surface of the auxiliary carrier portion and the polished surface of the transistor are in the same plane.

[0045] After that, a first substrate is provided, and the polished surfaces of the auxiliary carrier portion and the at least one transistor are synchronously bonded to the first substrate. Alternatively, the first substrate is fabricated on the polished surfaces of the auxiliary carrier portion and the transistor.

[0046] After that, the support substrate is removed.

[0047] Finally, a plurality of metal patterns are formed on the side of the auxiliary carrier portion facing away from the first substrate, and the metal patterns are correspondingly coupled to the transistors. Thus, a semiconductor device is obtained.

[0048] The method for manufacturing a semiconductor device in an embodiment of the present disclosure has the same technical effects as the semiconductor device provided in the foregoing embodiment, which will not be elaborated here. In addition, in an embodiment of the present disclosure, with the aid of the support substrate, the transistor and the auxiliary carrier portion can be synchronously transferred onto the first substrate, and the operation is simple, which is beneficial to improving production efficiency.

[0049] In some embodiments, the transistor in the device particle at least includes: a second substrate and a semiconductor layer epitaxially grown on the second substrate. The second substrate is the part of the wafer located in the device particle. Polishing the device particle further includes: exposing the surface of the semiconductor layer in the transistor close to the second substrate; or exposing the polished surface of the second substrate in the transistor.

[0050] In some embodiments, the transistor in the device particle further includes: a first passivation layer, a gate, a source, a drain, and a second passivation layer.

[0051] Fabricating a plurality of transistors or partial layers of a plurality of transistors on a wafer includes: epitaxially growing a semiconductor layer on the wafer; forming a first passivation layer on the surface of the semiconductor layer facing away from the wafer; forming a plurality of openings in the first passivation layer, and respectively forming a gate, a source, and a drain in the plurality of openings; forming a second passivation layer on the surfaces of the first passivation layer, the gate, the source, and the drain facing away from the semiconductor layer.

[0052] Correspondingly, bonding the front surface of the device particle to the support substrate includes: bonding the surface of the second passivation layer facing away from the gate to the support substrate.

[0053] Correspondingly, a plurality of metal patterns are formed on a side of the auxiliary carrier portion facing away from the first substrate, and the metal patterns are correspondingly coupled to the transistors. It further includes: forming a plurality of openings in the second passivation layer; forming a plurality of metal patterns on a side of the auxiliary carrier portion facing away from the first substrate, such that the plurality of metal patterns are correspondingly coupled to the gates and drains through the openings in the second passivation layer.

[0054] As described above, during the process of synchronously transferring the auxiliary carrier portion and the transistors onto the first substrate, the gates, sources, and drains of the transistors are isolated and protected by the second passivation layer, which can prevent the gates, sources, and drains of the transistors from being damaged due to the transfer of the transistors.

[0055] In some embodiments, forming a plurality of metal patterns on a side of the auxiliary carrier portion facing away from the first substrate further includes: forming a heat dissipation insulating layer on a surface of the auxiliary carrier portion and the transistors facing away from the first substrate; forming the plurality of metal patterns on a surface of the heat dissipation insulating layer facing away from the auxiliary carrier portion. The function of the heat dissipation insulating layer is as described above.

[0056] In some embodiments, bonding the front surface of at least one device particle to a support substrate further includes: forming a temporary bonding layer on the support substrate; bonding the front surface of at least one device particle to the temporary bonding layer.

[0057] Correspondingly, removing the support substrate further includes: using at least one of laser treatment, heat treatment, chemical treatment, etching, grinding, or polishing to remove the temporary bonding layer and the support substrate.

[0058] In the embodiments of the present disclosure, using the temporary bonding layer to achieve the bonding between the device particle and the support substrate is beneficial to reducing the difficulty of removing the support substrate, so as to simplify the manufacturing process of the semiconductor device.

[0059] Optionally, forming a temporary bonding layer on the support substrate includes: using at least one of glass, silicon dioxide, or silicon nitride to form a temporary bonding layer on the support substrate by spin coating or chemical vapor deposition. In this way, it can be ensured that the temporary bonding layer will not be affected by the high-temperature environment in the subsequent process, and the temperature of the high-temperature environment is, for example, ≥200 °C.

[0060] In some embodiments, the first substrate is prepared on the polished surfaces of the auxiliary carrier portion and the transistors by chemical vapor deposition, for example, by chemical vapor deposition or physical vapor deposition.

[0061] Based on this, optionally, preparing a plurality of transistors or partial layers of a plurality of transistors on a wafer includes: epitaxially growing a semiconductor layer on the wafer; forming a first passivation layer on a surface of the semiconductor layer facing away from the wafer.

[0062] Correspondingly, bonding the front side of the device particles to the support substrate includes: bonding the surface of the first passivation layer facing away from the semiconductor layer to the support substrate.

[0063] Correspondingly, forming a plurality of metal patterns on the side of the auxiliary carrier portion facing away from the first substrate and coupling the metal patterns to the transistors correspondingly. It further includes: forming a plurality of openings in the first passivation layer, and respectively forming a gate, a source, and a drain in the plurality of openings; forming a plurality of metal patterns on the side of the auxiliary carrier portion facing away from the first substrate, and coupling at least one of the plurality of metal patterns to the gate, at least one metal pattern to the drain, and the metal pattern coupled to the gate and the metal pattern coupled to the drain are insulated from each other.

[0064] In some embodiments, preparing the first substrate on the polished surfaces of the auxiliary carrier portion and the transistors further includes: forming a gas barrier layer on the polished surfaces of the auxiliary carrier portion and the transistors, and the gas barrier layer is, for example, at least one layer of a silicon layer, a silicon nitride layer, an aluminum nitride layer, or a silicon carbide layer; forming the first substrate on the surface of the gas barrier layer facing away from the auxiliary carrier portion. In the embodiments of the present disclosure, before depositing the first substrate, the gas barrier layer is prepared in advance, and the gas barrier layer can be used to prevent the gases used in the first substrate deposition process from damaging or destroying the semiconductor layer of the transistors.

[0065] In other embodiments, the polished surfaces of the auxiliary carrier portion and the transistors are synchronously bonded to the first substrate.

[0066] Optionally, bonding the polished surfaces of the auxiliary carrier portion and the transistors to the first substrate further includes: forming a bonding layer on the first substrate and bonding the polished surfaces of the auxiliary carrier portion and the transistors to the bonding layer; or, forming a bonding layer on the polished surfaces of the auxiliary carrier portion and the transistors and bonding the first substrate to the bonding layer. The structure and function of the bonding layer are as described above.

[0067] According to the different structures of the semiconductor devices in the foregoing some embodiments, there are also various implementation manners for the manufacturing method of the semiconductor devices.

[0068] In a possible implementation manner, the manufacturing method of the semiconductor device further includes: forming a metal layer on the surface of the first substrate facing away from the transistors.

[0069] In another possible implementation manner, the manufacturing method of the semiconductor device further includes: forming a first via hole that at least penetrates the first substrate and the semiconductor layer, and making the orthographic projection of the first via hole on the first substrate be located within the orthographic projection of the source electrode in the corresponding transistor on the first substrate; forming a metal layer on the surface of the first substrate facing away from the transistors, and making the metal layer be coupled to the source electrode through the first via hole.

[0070] In the case where the semiconductor device further includes a bonding layer or a gas barrier layer, the first via hole also correspondingly penetrates through the bonding layer or the gas barrier layer.

[0071] Exemplarily, in the case where the transistor includes a transition layer and a second substrate, the semiconductor device further includes a conductive bonding layer located between the first substrate and the second substrate. The first via hole is composed of a first sub-via hole and a second sub-via hole which are arranged in sections. Correspondingly, forming the first via hole that at least penetrates through the first substrate and the semiconductor layer includes: forming the first sub-via hole that penetrates through the second substrate, the transition layer and the semiconductor layer, such that one end of the first sub-via hole is in direct contact with the corresponding source electrode; forming a conductive bonding layer on the auxiliary carrier portion and the polished surface of the transistor, such that the conductive bonding layer is in direct contact with the other end of the first sub-via hole; bonding the first substrate to the conductive bonding layer; forming the second sub-via hole that penetrates through the first substrate, such that one end of the second sub-via hole is in direct contact with the conductive bonding layer; forming a metal layer on the first substrate, such that the metal layer is in direct contact with the other end of the second sub-via hole.

[0072] In another possible implementation manner, the method for manufacturing a semiconductor device further includes: forming a second via hole that at least penetrates through the first substrate and the auxiliary carrier portion, and making the orthographic projection of the second via hole on the first substrate be located within the orthographic projection of the corresponding metal pattern on the first substrate; forming a metal layer on the surface of the first substrate facing away from the semiconductor layer, such that the metal layer is coupled to the metal pattern through the second via hole.

[0073] In the case where the semiconductor device further includes a bonding layer or a gas barrier layer, the second via hole also correspondingly penetrates through the bonding layer or the gas barrier layer.

[0074] Exemplarily, the semiconductor device further includes a conductive bonding layer located between the first substrate and the auxiliary carrier portion. The second via hole is composed of a third sub-via hole and a fourth sub-via hole which are arranged in sections. Correspondingly, forming the second via hole that at least penetrates through the first substrate and the auxiliary carrier portion includes: forming the third sub-via hole that penetrates through the auxiliary carrier portion; forming a conductive bonding layer on the auxiliary carrier portion and the polished surface of the transistor, such that the conductive bonding layer is in direct contact with one end of the third sub-via hole; bonding the first substrate to the conductive bonding layer; forming the fourth sub-via hole that penetrates through the first substrate, such that one end of the fourth sub-via hole is in direct contact with the conductive bonding layer; forming a metal layer on the first substrate, such that the metal layer is in direct contact with the other end of the fourth sub-via hole. In this way, after the metal pattern is formed subsequently, making the metal pattern be in direct contact with the other end of the third sub-via hole can realize the coupling between the metal pattern and the conductive bonding layer through the third sub-via hole.

[0075] Based on the above-mentioned some embodiments, optionally, the method for manufacturing a semiconductor device further includes: providing a heat dissipation substrate and welding the metal layer to the heat dissipation substrate. The function of the heat dissipation substrate is as described above.

[0076] Optionally, the method for manufacturing a semiconductor device further includes: forming at least one bonding pad on the metal pattern, such that the orthographic projection of the bonding pad on the first substrate is located within the region of the first substrate not covered by the transistor. The function of the bonding pad is as described above.

[0077] The method for manufacturing a semiconductor device in the embodiments of the present disclosure has the same technical effects as the semiconductor device provided in the foregoing embodiments, and will not be elaborated herein. Description of the Drawings

[0078] To more clearly illustrate the technical solutions in some embodiments of the present disclosure, the following briefly introduces the drawings required for description in some embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings.

[0079] Figure 1 FIG. [X] is a schematic structural diagram of a semiconductor device according to some embodiments;

[0080] Figure 2 is Figure 1 a schematic cross-sectional view of the semiconductor device shown along the A-A' direction;

[0081] Figure 3 FIG. [X] is a schematic diagram of S100 of a method for manufacturing a semiconductor device according to some embodiments;

[0082] Figure 4 FIG. [X] is a schematic structural diagram of a transistor according to some embodiments;

[0083] Figure 5 FIG. [X] is a schematic diagram of S200 of a method for manufacturing a semiconductor device according to some embodiments;

[0084] Figure 6 FIG. [X] is a schematic diagram of S300 of a method for manufacturing a semiconductor device according to some embodiments;

[0085] Figure 7 FIG. [X] is a schematic diagram of one of S400 of a method for manufacturing a semiconductor device according to some embodiments;

[0086] Figure 8 FIG. [X] is a schematic diagram of another S400 of a method for manufacturing a semiconductor device according to some embodiments;

[0087] Figure 9 FIG. [X] is a schematic diagram of S500 of a method for manufacturing a semiconductor device according to some embodiments;

[0088] Figure 10Schematic diagram of the preparation of a non-conductive bonding layer according to some embodiments;

[0089] Figure 11 Schematic diagram of the preparation of another non-conductive bonding layer according to some embodiments;

[0090] Figure 12 Schematic diagram of S600 of a method for manufacturing a semiconductor device according to some embodiments;

[0091] Figure 13 Schematic diagram of S700 of a method for manufacturing a semiconductor device according to some embodiments;

[0092] Figure 14 Supplementary schematic diagram of a method for manufacturing a semiconductor device according to some embodiments;

[0093] Figure 15 Schematic diagram of S100' of another method for manufacturing a semiconductor device according to some embodiments;

[0094] Figure 16 Schematic diagram of S200' of another method for manufacturing a semiconductor device according to some embodiments;

[0095] Figure 17 Schematic diagram of S300' to S500' of another method for manufacturing a semiconductor device according to some embodiments;

[0096] Figure 18 Schematic diagram of the preparation of a gas barrier layer according to some embodiments;

[0097] Figure 19 Schematic diagram of the preparation of a first substrate according to some embodiments;

[0098] Figure 20 Schematic diagram of S600' to S700' of another method for manufacturing a semiconductor device according to some embodiments;

[0099] Figure 21 For Figure 1 Cross-sectional schematic diagram of another semiconductor device along the A-A' direction as shown;

[0100] Figure 22 For Figure 1 Cross-sectional schematic diagram of yet another semiconductor device along the A-A' direction as shown;

[0101] Figure 23 For Figure 1 Cross-sectional schematic diagram of yet another semiconductor device along the A-A' direction as shown;

[0102] Figure 24Schematic structural diagram of another semiconductor device according to some embodiments;

[0103] Figure 25 is Figure 24 Schematic cross-sectional view of a semiconductor device shown along the B-B' direction;

[0104] Figure 26 is Figure 1 Schematic cross-sectional view of yet another semiconductor device shown along the A-A' direction;

[0105] Figure 27 is Figure 26 Schematic diagram of the fabrication of a transistor in the semiconductor device shown;

[0106] Figure 28 is Figure 26 Schematic diagram of the bonding of a device particle during the fabrication process of the semiconductor device shown;

[0107] Figure 29 Schematic diagram of the positional relationship between an auxiliary carrier portion and a transistor according to some embodiments;

[0108] Figure 30 Schematic diagram of another positional relationship between an auxiliary carrier portion and a transistor according to some embodiments;

[0109] Figure 31 Schematic diagram of yet another positional relationship between an auxiliary carrier portion and a transistor according to some embodiments;

[0110] Figure 32 Schematic structural diagram of yet another semiconductor device according to some embodiments;

[0111] Figure 33 Schematic structural diagram of yet another semiconductor device according to some embodiments;

[0112] Figure 34 Schematic structural diagram of yet another semiconductor device according to some embodiments;

[0113] Figure 35 Schematic structural diagram of yet another semiconductor device according to some embodiments;

[0114] Figure 36 Schematic structural diagram of yet another semiconductor device according to some embodiments;

[0115] Figure 37 Schematic structural diagram of yet another semiconductor device according to some embodiments;

[0116] Figure 38 Schematic structural diagram of yet another semiconductor device according to some embodiments;

[0117] Figure 39 Schematic structural diagram of another semiconductor device according to some embodiments;

[0118] Figure 40 Schematic structural diagram of another semiconductor device according to some embodiments;

[0119] Figure 41 Schematic structural diagram of another semiconductor device according to some embodiments;

[0120] Figure 42 Is Figure 41 Schematic cross-sectional view of a semiconductor device shown along the C-C' direction;

[0121] Figure 43 Is Figure 41 Schematic cross-sectional view of a semiconductor device shown along the E-F-G direction;

[0122] Figure 44 Schematic cross-sectional view of an electronic device according to some embodiments;

[0123] Figure 45 Schematic cross-sectional view of another electronic device according to some embodiments.

[0124] Reference numerals:

[0125] 100 - Semiconductor device; 11 - First substrate; 111 - Gas barrier layer;

[0126] 12 - Wafer; 121 - Substrate; 122 - Gallium nitride layer;

[0127] 201 and 201' - Device particles; 20 - Transistor; 21 - Second substrate;

[0128] 22 - Transition layer; 23 - Semiconductor layer; 231 - Channel layer;

[0129] 232 - Barrier layer; 24 - First passivation layer; 25 - Gate;

[0130] 26 - Source; 27 - Drain; 28 - Second passivation layer;

[0131] 30 - Auxiliary carrier part; 31 - Auxiliary carrier film; 32 - Insulating layer;

[0132] 40 - Bonding layer; 50 - Heat dissipation insulating layer; 60 - Metal pattern;

[0133] 61 - First metal pattern; 62 - Second metal pattern; 63 - Third metal pattern;

[0134] 70 - Bonding pad; 71 - First bonding pad; 72 - Second bonding pad;

[0135] 73 - Third bonding pad; 80 - Metal layer; 81 - Soldering layer;

[0136] 82 - Heat dissipation substrate; 90 - Support substrate; 91 - Temporary bonding layer;

[0137] 1000 - Electronic device; 1001 - Metal lead; 1002 - External pin;

[0138] 1003 - Insulating part; 1004 - Encapsulation cover plate;

[0139] H1 - First via hole; H11 - First sub - via hole; H12 - Second sub - via hole;

[0140] H2 - Second via hole; H21 - Third sub - via hole; H22 - Fourth sub - via hole;

[0141] C1 - First capacitor; C2 - Second capacitor;

[0142] L1 - First inductor; L2 - Second inductor; R1 - Resistor. Detailed implementation manners

[0143] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in some embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on some embodiments of the present disclosure, all other embodiments that can be obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0144] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular form "comprises" and the present participle form "comprising", are interpreted in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, terms such as "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples" are intended to indicate that specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any suitable manner.

[0145] Hereinafter, orientation terms such as "upper", "lower", "left", "right", etc. may include, but are not limited to, being defined relative to the schematic placement of components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and they may change accordingly with the change of the orientation of the components placed in the drawings.

[0146] Ordinal numbers such as "first", "second", etc. are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0147] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Another example is that when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. However, the term "coupled" or "communicatively coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0148] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0149] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0150] The use of "suitable for" or "configured to" in this document means open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. Additionally, the use of "based on" means open and inclusive because a process, step, calculation, or other action "based on" one or more of the stated conditions or values can, in practice, be based on additional conditions or values beyond those stated.

[0151] As used herein, "substantially" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0152] Furthermore, in order to clearly represent multiple layers and regions in the drawings, the thickness of each layer in the illustration is enlarged to clearly indicate the relative positions between the layers. When a part of a layer, film, region, plate, etc. is located "above" or "on" another part, this statement includes not only the case where it is "directly" above the other part, but also the case where there are other layers in between.

[0153] A semiconductor device refers to an electronic device that relies on the electrical characteristics of semiconductor materials to achieve specific functions. Common semiconductor devices are, for example, transistor devices, that is, electronic devices containing at least one transistor. The structures and types of transistors are numerous, and in the embodiments of the present disclosure, only the case where the transistor is a field-effect transistor or a transistor with a similar structure is taken as an example for description.

[0154] As Figure 1 and Figure 2 As shown, some embodiments of the present disclosure provide a semiconductor device 100. The semiconductor device 100 includes a first substrate 11 and at least one transistor 20 and an auxiliary carrier portion 30 that are synchronously transferred onto the first substrate 11.

[0155] The first substrate 11 is configured to carry the transistor 20 and the auxiliary carrier portion 30. The first substrate 11 can adopt a substrate with high thermal conductivity and high resistance value to ensure excellent heat dissipation capacity and electrical performance of the semiconductor device 100. Optionally, the first substrate 11 is a single-crystal silicon carbide substrate, a polycrystalline silicon carbide substrate, a polycrystalline aluminum nitride substrate, a polycrystalline diamond substrate, a graphite substrate, a multi-layer graphene substrate, a copper substrate, or a composite substrate formed by laminating multiple materials, etc. Among them, the single-crystal silicon carbide substrate includes: a high-purity semi-insulating single-crystal silicon carbide substrate, or a vanadium-doped silicon carbide substrate. Compared with the high-purity semi-insulating single-crystal silicon carbide substrate, the vanadium-doped silicon carbide substrate increases the insulation of silicon carbide by doping vanadium elements, and its cost is lower than that of the high-purity semi-insulating single-crystal silicon carbide substrate.

[0156] The auxiliary carrier portion 30 and the foregoing at least one transistor 20 are disposed on the first substrate 11. The orthographic projection of the auxiliary carrier portion 30 on the first substrate 11 is located outside the orthographic projection of the at least one transistor 20 on the first substrate 11, and the boundary of the orthographic projection of the auxiliary carrier portion 30 on the first substrate 11 partially coincides with the boundary of the orthographic projection of the at least one transistor 20 on the first substrate 11. That is, the auxiliary carrier portion 30 is formed beside the at least one transistor 20. In this way, taking the at least one transistor 20 as a whole, during the production process of transferring the at least one transistor 20 to the first substrate 11, it is beneficial for the auxiliary carrier portion 30 to support and protect the at least one transistor 20. The material and structure of the auxiliary carrier portion 30 can be selected and set according to actual needs, and the embodiments of the present disclosure do not limit this.

[0157] In the embodiments of the present disclosure, the transistor 20 is taken as an example of a High Electron Mobility Transistor (HEMT) for illustration, but it is not limited thereto. The HEMT is a heterojunction field effect transistor, and can also be referred to as a two-dimensional electron gas field effect transistor or a modulation-doped field effect transistor.

[0158] Please continue to refer to Figure 1 and Figure 2 , the transistor 20 includes: a semiconductor layer 23, and a gate 25, a source 26, and a drain 27 respectively formed on a side of the semiconductor layer 23 facing away from the first substrate 11. The semiconductor device 100 further includes a plurality of metal patterns 60. The plurality of metal patterns 60 are formed on a side of the auxiliary carrier portion 30 facing away from the first substrate 11. At least one metal pattern in the plurality of metal patterns is coupled to the gate 25 in the corresponding transistor 20, at least one metal pattern is coupled to the drain 27 in the corresponding transistor 20, and the metal pattern coupled to the gate 25 and the metal pattern coupled to the drain 27 are insulated from each other.

[0159] Optionally, the source 26 in the transistor 20 is coupled to at least one of the multiple metal patterns 60 described above, or to another metal layer. Moreover, the metal pattern or metal layer coupled to the source 26 is insulated from the metal pattern coupled to the gate 25 and the metal pattern coupled to the drain 27.

[0160] Here, the metal pattern 60 is used to transmit an electrical signal to the electrode (including the gate 25, the source 26, or the drain 27) coupled thereto in the transistor 20, and its pattern can be designed according to actual requirements, limited to facilitating the electrical coupling between the semiconductor device 100 and an external device or realizing a specific function of the semiconductor device 100. For example, the metal pattern 60 is a combination of one or more of a metal electrode, a metal wire, a bonding pad, or a solder pad.

[0161] In addition, the source 26 and the drain 27 in the transistor 20 have the same structure, and the two are only used to couple to different power supplies or signal sources. Therefore, according to the type of the transistor 20, the couplings between the source 26 and the drain 27 and external components can be interchanged according to actual situations.

[0162] In the embodiment of the present disclosure, the structure of the semiconductor device 100 is as described above, and there are various ways to synchronously transfer the transistor 20 and the auxiliary carrier 30 onto the first substrate 11. For example, the transistor 20 and the auxiliary carrier 30 are synchronously bonded onto the first substrate 11. Or, for another example, the first substrate 11 is fabricated on the surfaces of the transistor 20 and the auxiliary carrier 30, thereby realizing the synchronous transfer of the transistor 20 and the auxiliary carrier 30.

[0163] In some embodiments, the transistor 20 and the auxiliary carrier 30 are synchronously bonded onto the first substrate 11. Here, "bonding" means combining two different substances into one body through the atomic force. Correspondingly, the manufacturing method of the semiconductor device 100 includes: S100 to S700.

[0164] S100, as Figure 3 shown, provide a wafer 12, and fabricate a plurality of transistors 20 on the wafer 12. Then, the wafer 12 is cut along the thickness direction of the wafer 12 to obtain a plurality of device particles 201. Each device particle 201 includes one or more transistors 20. The transistor 20 includes: a second substrate 21, a semiconductor layer 23 epitaxially grown on the second substrate 21, and a gate 25, a drain 27, and a source 26 respectively formed on the semiconductor layer 23.

[0165] Here, the second substrate 21 in the transistor 20 is the part of the wafer 12 that exists within the device particle 201. The semiconductor layer 23 is epitaxially grown on the wafer 12, and a transition layer 22, that is, a buffer layer, is usually grown between the wafer 12 and the semiconductor layer 23. The transition layer 22 can be used to improve the lattice quality of the surface part of the wafer 12 to ensure the film formation quality of the semiconductor layer 23. The semiconductor layer 23 of the transistor 20 includes a channel layer 231 and a barrier layer 232 that are stacked in a direction away from the second substrate 21, and a heterojunction is formed between the barrier layer 232 and the channel layer 231.

[0166] It can be understood that in the actual production process of the semiconductor device 100, the wafer 12 can be provided in the form of a semiconductor wafer, that is, the transition layer and the semiconductor film have been grown on the surface of the wafer 12. Taking the gallium nitride wafer 12 as an example, as Figure 4 shown, the gallium nitride wafer 12 includes a substrate 121 and a gallium nitride layer 122 epitaxially grown on the substrate 121. The substrate 121 is, for example, a sapphire (Al2O3) substrate, a silicon (Si) substrate, or a silicon carbide (SiC) substrate. The surface part of the gallium nitride layer 122 can be used as the channel layer 231 in the transistor 20. In the embodiment of the present disclosure, the gallium nitride layer 122 is composed of the channel layer 231 and the transition layer 22, that is, the part of the gallium nitride layer 122 other than the channel layer 231, that is, the part on the side of the channel layer 231 close to the substrate 121 is the transition layer 22, that is, the buffer layer. By continuously growing a semiconductor film on the surface of the gallium nitride wafer 12, a barrier layer 232 can be formed. The barrier layer 232 is, for example, an aluminum gallium nitride (AlGaN) layer or an aluminum nitride (AlN) layer.

[0167] As Figure 3 and Figure 4 shown, the transistor 20 further includes a first passivation layer 24 formed on the surface of the semiconductor layer 23 facing away from the second substrate 21. The first passivation layer 24 includes a plurality of openings, and the gate 25, the source 26, and the drain 27 are respectively formed in the corresponding openings and are in direct contact with the barrier layer 232. The gate 25 of the transistor 20 forms a Schottky barrier with the barrier layer 232. In addition, it is also allowed to provide a gate insulating layer between the gate 25 and the barrier layer 232. The first passivation layer 24 and the gate insulating layer are made of insulating materials and can be prepared, for example, using inorganic insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride.

[0168] According to the physical properties of semiconductor materials, the band gaps of the barrier layer 232 and the channel layer 231 forming the heterojunction are different. Electrons will flow from the semiconductor with a wide band gap (i.e., the barrier layer 232) to the semiconductor with a narrow band gap (i.e., the channel layer 231), thereby forming a quantum well on the side of the narrow-bandgap semiconductor at the heterojunction contact surface. When the doping concentration of the wide-bandgap semiconductor is relatively high and the conduction band difference between the heterojunctions is relatively large, a very high potential barrier will be formed between the gate 25 and the barrier layer 232, thereby restricting the movement of free electrons in the quantum well in the direction perpendicular to the heterojunction contact surface. This quantum well is the two-dimensional electron gas (2DEG for short). The 2DEG is located on the surface of the channel layer 231 in contact with the barrier layer 232. By adjusting the size of the Schottky barrier between the gate 25 and the barrier layer 232, the concentration of 2DEG in the channel layer 231 can be controlled, thereby controlling the magnitude of the current in the channel layer 231.

[0169] S200, as Figure 5 shown, provide a support substrate 90, and bond the front surface S1 of at least one device particle 201 to the support substrate 90. In some of the following embodiments, the example of bonding two device particles 201 to the support substrate 90 is used for illustration.

[0170] Here, the support substrate 90 has a certain mechanical strength. The support substrate 90 is, for example, a silicon substrate or a glass substrate. The front surface S1 of the device particle 201 refers to the surface of the transistor 20 facing away from the second substrate 21, for example, the surface of the transistor 20 on the side where the gate 25 or the drain 27 is located. The back surface S2 of the device particle 201 refers to the surface opposite to its front surface S1, and is also the surface of the second substrate 21 in the transistor 20 facing away from the semiconductor layer 23.

[0171] Optionally, the surfaces of the gate 25, the source 26, and the drain 27 facing away from the semiconductor layer 23 are flush or substantially flush with the surface of the first passivation layer 24 facing away from the semiconductor layer 23. In this way, a relatively large contact area can be provided between the device particle 201 and the support substrate 90, thereby facilitating bonding the front surface of the device particle 201 to the support substrate 90 and achieving a better bonding effect therebetween.

[0172] The bonding between the above-mentioned device particle 201 and the support substrate 90 can be realized by direct bonding or bonding through a bonding layer.

[0173] In some embodiments, as Figure 5 shown, bonding the front surface of at least one device particle 201 to the support substrate 90 includes: forming a temporary bonding layer 91 on the support substrate 90; bonding the front surface of at least one device particle 201 to the temporary bonding layer 91.

[0174] Here, the temporary bonding layer 91 refers to a bonding layer that can be debonded after bonding, that is, the temporary bonding layer 91 can be removed when it is no longer needed in the subsequent process.

[0175] Optionally, the temporary bonding layer 91 is made of at least one of glass, silicon dioxide, or silicon nitride, and is formed on the support substrate 90 by a spin coating or vapor deposition process. In this way, the temporary bonding layer 91 can be removed by at least one of the processes such as laser treatment, heat treatment, chemical treatment, etching, grinding, or polishing when its presence is not required. Moreover, when the temporary bonding layer 91 is formed of the above materials, it can be ensured that the temporary bonding layer 91 will not be affected by the high-temperature environment in the subsequent process. The temperature of the high-temperature environment is, for example, ≥200 °C.

[0176] S300, as Figure 6 shown, an auxiliary support film 31 is formed on the surface of the support substrate 90 that is not covered by the device particles 201 and on the back surface S2 of the device particles 201.

[0177] When the temporary bonding layer 91 is formed on the support substrate 90, the auxiliary support film 31 is formed on the surface of the temporary bonding layer 91 that is not covered by the device particles 201.

[0178] The auxiliary support film 31 is used to support and protect the transistor 20 and can be formed of an insulating material with a certain mechanical strength, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon, silicon carbide, aluminum nitride, aluminum oxide, epoxy resin, polyimide, or benzocyclobutene. The auxiliary support film 31 can be formed by a vapor deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. The deposition thickness of the auxiliary support film 31 can be selected and set according to actual requirements.

[0179] Exemplarily, when the auxiliary support film 31 is formed by a chemical vapor deposition process, the deposition thickness D2 of the auxiliary support film 31 is greater than the minimum thickness D1 of the transistor 20, and the minimum thickness D1 of the transistor 20 refers to the thickness of the transistor 20 when the second substrate 21 and the transition layer 22 are not included.

[0180] S400, as Figure 7 shown, the auxiliary support film 31 and the device particles 201 are polished to obtain at least one transistor 20 and an auxiliary support portion 30 beside the at least one transistor 20. The polished surface of the auxiliary support portion 30 and the polished surface of the transistor 20 are in the same plane.

[0181] Here, the polishing-assisted carrier film 31 means that the auxiliary carrier film 31 is thinned and its surface is flattened by a polishing process. Since the auxiliary carrier film 31 is formed on the surface of the support substrate 90 that is not covered by the device particles 201 and on the back surface S2 of the device particles 201, during the process of polishing the auxiliary carrier film 31, in order to expose the transistors 20 in the device particles 201, the part of the auxiliary carrier film 31 located on the back surface S2 of the device particles 201 will be removed. In this way, during the process of polishing the auxiliary carrier film 31 and the device particles 201, the auxiliary carrier film 31 can support and protect the device particles 201, thereby reducing the implementation difficulty of the polishing process and being beneficial to improving production efficiency. Moreover, the obtained auxiliary carrier portion 30 after polishing is located beside the transistors 20 and can continuously provide auxiliary support and protection for the transistors 20 in subsequent processes.

[0182] In addition, the thinning of the auxiliary carrier film 31 can also be achieved by etching or grinding, etc., as long as the formed auxiliary carrier portion 30 and the exposed surface of the transistors 20 have good surface flatness.

[0183] It can be understood that the transistor 20 may only include a semiconductor layer 23 and a first passivation layer 24, a gate 25, a source 26, and a drain 27 located on the semiconductor layer 23. That is, the polished surface of the transistor 20 is the surface of the semiconductor layer 23 facing away from the gate 25, and the polished surface of the auxiliary carrier portion 30 is flush or approximately flush with the surface of the semiconductor layer 23 in the transistor 20 that faces away from the gate 25, as shown in, for example Figure 7 shown.

[0184] Alternatively, the transistor 20 further includes a second substrate 21 and a transition layer 22. That is, the polished surface of the transistor 20 is the polished surface of the second substrate 21. The polished surface of the auxiliary carrier portion 30 is flush or approximately flush with the polished surface of the second substrate 21 in the transistor 20, as shown in, for example Figure 8 shown. Here, compared with the back surface S2 of the device particles 201, the polished surface of the second substrate 21 is the surface after removing part of the base material. The thickness of the second substrate 21 removed by polishing can be set according to actual needs.

[0185] It should be added that, please combine Figure 4 、 Figure 7 and Figure 8Understand that taking the gallium nitride wafer of wafer 12 as an example, the gallium nitride layer 122 is epitaxially grown on the substrate 111. The lattice quality of the surface part of the gallium nitride layer 122 is good and can be used to form the channel layer 231 in the transistor 20. The lattice quality of the part of the gallium nitride layer 122 close to the substrate 121 (i.e., the transition layer 22) is poor, which easily results in poor thermal conductivity of the transition layer 22. Based on this, during the process of polishing the auxiliary carrier film 31, the transition layer 22 and the second substrate 21 in the transistor 12 are polished and removed, which can also effectively improve the heat dissipation capacity of the semiconductor device 100.

[0186] S500, as Figure 9 shown, provide the first substrate 11, and synchronously bond the polishing surfaces of the auxiliary carrier part 30 and the transistor 20 on the first substrate 11.

[0187] In some of the following embodiments, an example is given where the transistor 20 only includes the semiconductor layer 23 and the first passivation layer 24, the gate 25, the source 26, and the drain 27 located on the semiconductor layer 23 for illustration.

[0188] The structure of the first substrate 11 can be referred to as described in some of the foregoing embodiments. In addition, the auxiliary carrier part 30 and the transistor 20 are transferred to the first substrate 11 after being prepared. Based on this, when the cost of the wafer 12 used to prepare the transistor 20 is high, the first substrate 11 can be composed of a material or wafer with a relatively low cost. In addition, the polishing surface of the auxiliary carrier part 30 is flush or substantially flush with the polishing surface of the transistor 20, which can ensure that the bonding surfaces of the auxiliary carrier part 30 and the transistor 20 to be bonded have a high surface quality, thereby ensuring a good bonding effect between the two and the first substrate 11.

[0189] The bonding method between the auxiliary carrier part 30 and the transistor 20 and the first substrate 11 can be achieved by direct bonding or indirect bonding through a bonding layer.

[0190] Exemplarily, the auxiliary carrier part 30 and the transistor 20 are directly bonded to the first substrate 11. In this way, before direct bonding, the bonding surfaces of the auxiliary carrier part 30 and the transistor 20 to be bonded, as well as the bonding surface of the first substrate 11, can be surface-treated by plasma or ion beam or atomic beam, etc., so that there is an amorphous interface layer formed by plasma or ion beam or atomic beam treatment at the direct bonding interface between the auxiliary carrier part 30 and the transistor 20 and the first substrate 11. For example, the first substrate 11 is a polycrystalline silicon carbide substrate, and the exposed surface of the transistor 20 is a gallium nitride surface. In this way, after plasma treatment of the two, there will be an amorphous GaN and / or amorphous SiC interface layer at the direct bonding interface between the transistor 20 and the first substrate 11.

[0191] Exemplarily, the auxiliary carrier portion 30 and the transistor 20 are indirectly bonded to the first substrate 11.

[0192] Optionally, as Figure 10 shown, bonding the auxiliary carrier portion 30 and the transistor 20 to the first substrate 11 further includes: forming a bonding layer 40 on the first substrate 11, and bonding the auxiliary carrier portion 30 and the transistor 20 to the bonding layer 40. Here, the semiconductor layer 23 of the transistor 20 is in direct contact with the bonding layer 40, and the bonding layer 40 is a non-conductive bonding layer. The non-conductive bonding layer 40 can entirely cover the first substrate 11, or can be formed only within the bonding region of the first substrate 11. The bonding region can be the region of the first substrate 11 for bonding with the transistor 20, or can be the region of the first substrate 11 for bonding with the transistor 20 and the auxiliary carrier portion 30.

[0193] Optionally, as Figure 11 shown, bonding the auxiliary carrier portion 30 and the transistor 20 to the first substrate 11 further includes: forming a bonding layer 40 on the auxiliary carrier portion 30 and the transistor 20, and bonding the first substrate 11 to the bonding layer 40. Here, the semiconductor layer 23 of the transistor 20 is in direct contact with the bonding layer 40, and the bonding layer 40 is a non-conductive bonding layer.

[0194] The above bonding layer 40 can also have other setting methods. For example, the bonding layer 40 includes a first non-conductive bonding layer and a second non-conductive bonding layer. Thus, forming the first non-conductive bonding layer on the auxiliary carrier portion 30 and the transistor 20, forming the second non-conductive bonding layer on the first substrate 11, and then bonding the first non-conductive bonding layer and the second non-conductive bonding layer is also allowed. Taking the first substrate 11 as a polycrystalline diamond substrate and the exposed surface of the transistor 20 as a gallium nitride (GaN) surface as an example, a silicon nitride bonding layer (SiN) can be formed on the polycrystalline diamond substrate, and SiN can be formed on the GaN surface, so as to realize the bonding of GaN / SiN - SiN / diamond.

[0195] The above non-conductive bonding layer 40 can be prepared from materials such as non-conductive silicon (Si), silicon carbide (SiC), silicon nitride (SiN), silicon dioxide (SiO2), aluminum nitride (AlN), or aluminum oxide (Al2O3). Thus, using the non-conductive bonding layer 40 can not only enhance the bonding strength between the auxiliary carrier portion 30 and the transistor 20 and the first substrate 11 respectively, but also ensure that the transistor 20 will not have problems such as leakage current due to its existence, which is beneficial to ensuring the electrical performance of the semiconductor device 100.

[0196] In addition, when the transistor 20 further includes a second substrate 21 and a transition layer 22, the second substrate 21 of the transistor 20 is in direct contact with the bonding layer 40, and the bonding layer 40 can be a conductive bonding layer. The conductive bonding layer 40 can be prepared from a metal material, such as Ti, Cr, Ni, Cu, Au, etc. The second substrate 21 and the transition layer 22 are non-conductive materials. Therefore, using a conductive bonding layer for the bonding layer 40 will not affect the electrical performance of the semiconductor device 100 due to its presence.

[0197] S600, as Figure 12 shown, remove the support substrate 90.

[0198] When a temporary bonding layer 91 is formed on the support substrate 90, the above removal of the support substrate 90 also includes removing the temporary bonding layer 91. In addition, the removal of the support substrate 90 and the temporary bonding layer 91 can be achieved by processes such as etching, grinding, or polishing, but is not limited thereto. For example, depending on the materials used to form the support substrate 90 and the temporary bonding layer 91, their removal can also be achieved by laser or chemical or thermal slip peeling. When the support substrate 90 can be obtained intact, the support substrate 90 can also be reused.

[0199] In addition, during the process of removing the support substrate 90, the auxiliary carrier portion 30 can support and protect the transistor 20 from the side thereof, thereby reducing the difficulty of removing the support substrate 90 and further improving production efficiency.

[0200] S700, as Figure 13 shown, form a plurality of metal patterns 60 on the side of the auxiliary carrier portion 30 facing away from the first substrate 11, and make at least one of the plurality of metal patterns 60 be coupled to the gate 25, at least one metal pattern be coupled to the drain 27, and the metal pattern coupled to the gate 25 and the metal pattern coupled to the drain 27 be insulated from each other.

[0201] Optionally, the above plurality of metal patterns 60 further includes at least one metal pattern coupled to the source 26, and the metal pattern coupled to the source 26 is insulated from the metal pattern coupled to the gate 25 and the metal pattern coupled to the drain 27.

[0202] For ease of description, hereinafter, the metal pattern coupled to the gate 25 is taken as the first metal pattern 61, the metal pattern coupled to the source 26 is taken as the second metal pattern 62, and the metal pattern coupled to the drain 27 is taken as the third metal pattern 63 as an example for illustration.

[0203] Here, the first metal pattern 61, the second metal pattern 62, and the third metal pattern 63 are all patterns formed by using metal materials, and their patterns can be the same or different. The materials for preparing the first metal pattern 61, the second metal pattern 62, and the third metal pattern 63 can be metal materials with good conductivity, such as at least one of metals such as copper, aluminum, gold, platinum, tungsten, nickel, iridium, or cobalt.

[0204] The patterns of the first metal pattern 61, the second metal pattern 62, and the third metal pattern 63 can be designed according to actual needs. For example, the first metal pattern 61, the second metal pattern 62, or the third metal pattern 63 is a single-layer pattern, and this single-layer pattern can be designed as a combination of one or more of a metal electrode, a metal wire, a bonding pad, or a solder pad. Or, for another example, the first metal pattern 61, the second metal pattern 62, or the third metal pattern 63 is a multi-layer pattern provided on a multi-layer insulating film, and this multi-layer pattern can be designed as a combination of at least two of a capacitor, an inductor, or a multi-layer metal wire.

[0205] In addition, the metal pattern 60 is formed on the auxiliary carrier portion 30. The auxiliary carrier portion 30 is located beside the transistor 20. The auxiliary carrier portion 30 is formed of an insulating material, which can effectively insulate the metal pattern 60 and the semiconductor layer 23 in the transistor 20, thereby ensuring the electrical performance of the transistor 20.

[0206] It should be added that in the case where one device particle 201 is used to prepare one semiconductor device 100, referring to the preparation methods in some of the foregoing embodiments, only one device particle 201 is transferred onto the support substrate 90, and then a single semiconductor device 100 can be prepared. Or, referring to the preparation methods in some of the foregoing embodiments, multiple device particles 201 are transferred onto the support substrate 90, and then after the metal pattern 60 is prepared, as Figure 14 shown, a single semiconductor device 100 is obtained by cutting.

[0207] In some other embodiments, the transfer of the transistor 20 and the auxiliary carrier portion 30 is achieved by preparing a first substrate 11 on the surfaces of the transistor 20 and the auxiliary carrier portion 30. Correspondingly, the preparation method of the semiconductor device 100 includes S100' to S700'.

[0208] S100', as Figure 15 shown, provide a wafer 12, and prepare partial layers of multiple transistors 20 on the wafer 12, such as preparing the semiconductor layer 23 and the first passivation layer 24 of the transistor 20. Then, the wafer 12 is cut along the thickness direction of the wafer 12 to obtain multiple device particles 201'. Such a device particle 201' includes at least a second substrate 21, a transition layer 22, a semiconductor layer 23, and a first passivation layer 24 of one transistor 20. Here, the structures of the second substrate 21 and the transition layer 22 are the same as those described above.

[0209] Compared with the preparation process of S100 in some of the foregoing embodiments, in the embodiments of the present disclosure, only the preparation of the gate 25, source 26, and drain 27 in the transistor 20 is missing, and the rest can be referred to the relevant content in some of the foregoing embodiments and will not be elaborated. Correspondingly, the openings for accommodating the gate 25, source 26, and drain 27 on the first passivation layer 24 can be formed during the subsequent preparation of the gate 25, source 26, and drain 27.

[0210] It should be noted that the preparation sequence of the gate 25, source 26, and drain 27 in the transistor 20 can be adjusted according to the specific process temperature, provided that the temperature of the subsequent process does not damage or destroy the structure formed by the previous process. For example, if the source 26 and drain 27 have good high-temperature resistance characteristics, then S100' further includes: forming a plurality of openings in the first passivation layer 24, and correspondingly forming the source 26 and drain 27 of the transistor 20 in the plurality of openings. The gate 25 of the transistor 20 is prepared in a subsequent process as appropriate. In this way, it is convenient to batch-produce more transistors 20 on the wafer 12 at a lower cost and avoid damage to the prepared structure by high-temperature processes such as the subsequent formation process of the first substrate 11.

[0211] S200', as Figure 16 shown, provide a support substrate 90, and bond the front surface S1 of at least one device particle 201' to the support substrate 90. Here, the front surface of the device particle 201' is the surface of the first passivation layer 24 facing away from the semiconductor layer 23.

[0212] The support substrate 90 is, for example, a glass substrate or a silicon substrate. The device particle 201' can be directly bonded to the support substrate 90 or indirectly bonded to the support substrate 90 through a temporary bonding layer 91. In addition, the realization of the bonding between the device particle 201' and the support substrate 90 can be performed with reference to the relevant content of S200 in the foregoing embodiments.

[0213] In some of the following embodiments, an example of bonding one device particle 201' to the support substrate 90 is used for illustration.

[0214] S300', as Figure 17 shown in (a) of, form an auxiliary carrier film 31 on the surface of the support substrate 90 not covered by the device particle 201' and on the back surface of the device particle 201'.

[0215] In the case where a temporary bonding layer 91 is formed on the support substrate 90, the auxiliary carrier film 31 is formed on the surface of the temporary bonding layer 91 not covered by the device particle 201' and on the back surface of the device particle 201'.

[0216] For the materials and preparation process of the auxiliary carrier film 30, reference can be made to the relevant records in S300 in the foregoing embodiments.

[0217] S400', as Figure 17 shown in (b) of FIG., polish the auxiliary carrier film 31 and the device particles 201' to obtain at least one transistor 20 and an auxiliary carrier portion 30 located beside the at least one transistor 20. The polished surface of the auxiliary carrier portion 30 and the polished surface (i.e., the exposed surface) of the transistor 20 are in the same plane.

[0218] The transistor 20 obtained here refers to the structure of the transistor 20 prepared in S100', including some layers of the transistor 20. Polishing the device particles 201' further includes: exposing the surface of the semiconductor layer 23 of the transistor 20 in the device particles 201' close to the second substrate 21, or exposing the polished surface of the second substrate 21 of the transistor 20 in the device particles 201' ( Figure 17 not shown in FIG.).

[0219] For the polishing process of the auxiliary carrier film 31 and the structure of the auxiliary carrier portion 30, reference can be made to the relevant records in the foregoing embodiments.

[0220] S500', as Figure 17 shown in (c) of FIG., prepare a first substrate 11 on the polished surfaces of the auxiliary carrier portion 30 and the transistor 20.

[0221] The first substrate 11 can be prepared by a vapor deposition process, such as a chemical vapor deposition process or a physical vapor deposition process. The materials for preparing the first substrate 11 are, for example, polycrystalline silicon carbide, polycrystalline aluminum nitride, or polycrystalline diamond.

[0222] It can be understood that after polishing the auxiliary carrier film 31 and the device particles 201', the polished surface of the auxiliary carrier portion 30 and the polished surface of the semiconductor layer 23 or the second substrate 21 are in the same plane. Thus, depositing the first substrate 11 on a surface with a high flatness can ensure the film formation quality of the first substrate 11.

[0223] It should be added that in some examples, especially in the example where the polished surface of the transistor 20 is the surface of the semiconductor layer 23, as Figure 18As shown, a first substrate 11 is prepared on the polished surfaces of the auxiliary carrier portion 30 and the transistor 20, further including: forming a gas barrier layer 111 on the polished surfaces of the auxiliary carrier portion 30 and the transistor 20, and then forming the first substrate 11 on the surface of the gas barrier layer 111 facing away from the auxiliary carrier portion 30. The gas barrier layer 111 can be formed by using at least one of materials such as silicon (Si), silicon nitride (SiN), aluminum nitride (AlN), or silicon carbide (SiC). For example, the gas barrier layer 111 includes at least one of a silicon layer, a silicon nitride layer, an aluminum nitride layer, or a silicon carbide layer.

[0224] In the embodiment of the present disclosure, before depositing the first substrate 11, the gas barrier layer 111 is prepared in advance, and the gas barrier layer 111 can be used to prevent the gases (such as methane and hydrogen) used in the first substrate 11 deposition process from damaging or destroying the semiconductor layer 23.

[0225] In addition, for example, as Figure 19 shown, after the gas barrier layer 111 is formed on the polished surfaces of the auxiliary carrier portion 30 and the transistor 20, if the first substrate 11 is a polycrystalline diamond substrate formed by a chemical vapor deposition process, then a nanocrystalline diamond layer 112 with very small diamond grains will be formed first at the initial stage of the diamond growth process, and then as the diamond growth thickness increases, a microcrystalline diamond layer 113 will be formed. The thickness of the nanocrystalline diamond layer 112 is very thin, which is much smaller than the thickness of the microcrystalline diamond layer 113. Thus, the polycrystalline diamond substrate prepared by the chemical vapor deposition process is a laminate of the nanocrystalline diamond layer 112 and the microcrystalline diamond layer 113.

[0226] S600', as Figure 20 shown in (a) of

[0227] In the case where a temporary bonding layer 91 is formed on the support substrate 90, the above removal of the support substrate 90 also includes removing the temporary bonding layer 91. In addition, the removal of the support substrate 90 and the temporary bonding layer 91 can be achieved by processes such as etching, grinding, or polishing, but is not limited thereto. For example, according to the formation materials of the support substrate 90 and the temporary bonding layer 91, their removal can also be carried out by laser lift-off, thermal lift-off, or chemical lift-off. In the case where the support substrate 90 can be obtained intact, the support substrate 90 can also be reused repeatedly.

[0228] In addition, during the process of removing the support substrate 90, the auxiliary carrier portion 30 can support and protect the transistor 20 from the side, thereby reducing the difficulty of removing the support substrate 90 and further improving the production efficiency.

[0229] S700', as Figure 20As shown in (b) therein, a plurality of openings penetrating through both side surfaces are formed in the first passivation layer 24, and the gate 25, source 26, and drain 27 of the transistor 20 are correspondingly formed in the plurality of openings. Then, a plurality of metal patterns 60 are formed on the side of the auxiliary carrier portion 30 facing away from the first substrate 11. Thus, the semiconductor device 100 is obtained.

[0230] Herein, for the structure of the plurality of metal patterns 60 and the way of their arrangement, reference can be made to the relevant descriptions in some of the foregoing embodiments.

[0231] In summary, in the semiconductor device 100 according to the embodiment of the present disclosure, the transistor 20 or a partial layer of the transistor 20 (such as the semiconductor layer 23, etc.) can be prepared on the wafer 12 in advance, and then, with the aid of the support substrate 90, it is transferred to the first substrate 11 synchronously with the auxiliary carrier portion 30. The auxiliary carrier portion 30 is formed beside the transistor 20 and can provide auxiliary support and protection for the transistor 20 or the partial layer structure of the transistor 20 during the transfer process of the transistor 20, thereby effectively improving the process stability during the production of the semiconductor device 100.

[0232] The first substrate 11 is used to carry the transferred transistor 20 and the auxiliary carrier portion 30. The planar area of the first substrate 11 is generally larger than the orthographic projection area of the transistor 20 on the first substrate 11. That is to say, there is an area on the first substrate 11 that is not covered by the transistor 20; this area can be used to accommodate the auxiliary carrier portion 30 and fabricate other electronic components or for heat dissipation. This means that the preparation of the transistor 20 on the wafer 12 is not affected by the positions of other component elements such as the metal patterns 60 in the semiconductor device 100. In this way, during the process of batch fabricating the transistor 20 on the wafer 12, the semiconductor film on the wafer 12 (such as the gallium nitride layer 122 on the gallium nitride - wafer 12) only needs to reserve a very small passive area portion or no passive area portion needs to be reserved. Thus, the semiconductor film on the wafer 12 can be effectively utilized and fabricated into the channel layer 231 of the transistor 20 to ensure that the wafer 12 has a high area utilization rate, for example, the area utilization rate of the wafer 12 reaches 80% or more. Herein, the area utilization rate of the wafer 12 refers to the ratio of its available area to its total planar area, and the available area is the area that can be used to form the channel layer 231 in the transistor 20.

[0233] Based on this, the area ratio of the active region AR in the transistor 20 on the semiconductor layer 23 can be relatively large. This area ratio refers to the ratio of the orthographic projection area of the active region AR on the first substrate 11 to the orthographic projection area of the semiconductor layer 23 on the first substrate 11. The active region AR refers to the effective region when the transistor 20 operates; that is, the region in the semiconductor layer 23 of the transistor 20 used to form a conductive channel. Optionally, the value range of the area ratio of the active region AR in the transistor 20 on the semiconductor layer 23 is 80% - 100%; for example, it is 80%, 90% or 100%.

[0234] In addition, the first substrate 11 is formed of a material with a cost lower than that of wide bandgap semiconductor wafers such as gallium nitride, which is also beneficial to reducing the production cost of the semiconductor device 100. The first substrate 11 is formed of a material with a relatively high thermal conductivity. For example, under the condition that the temperature is 300K, the thermal conductivity of the first substrate 11 is greater than 200W / mK, which is also beneficial to improving the heat dissipation ability of the semiconductor device 100 or reducing the active region area of the semiconductor device 100.

[0235] To more clearly illustrate the structure of the semiconductor device 100 in some embodiments of the present disclosure, Figure 2 、 Figure 21 、 Figure 22 and Figure 23 respectively show the cross-sectional structures of four different semiconductor devices 100, and these four semiconductor devices 100 can be obtained by using the corresponding steps in the foregoing preparation method. Among them, compared with the semiconductor device 100 shown in Figure 2 , the transistor 20 in the semiconductor device 100 shown in Figure 21 includes a transition layer 22 and a second substrate 21, Figure 22 the semiconductor device 100 shown in Figure 23 also includes a bonding layer 40,

[0236] It should be added that the wafer used to prepare the transistor 20 is not limited to the gallium nitride wafer 12, and can also be a gallium arsenide wafer, a gallium oxide wafer or a wafer with similar properties.

[0237] Exemplarily, the wafer used to prepare the transistor 20 is a gallium arsenide wafer. In the thus-prepared transistor 20, the channel layer 231 of the semiconductor layer 23 is a gallium arsenide layer, and the barrier layer 232 can be a gallium aluminum arsenide (AlGaAs) layer. Here, the preparation of the transistor 20 on the gallium arsenide wafer is similar to the preparation of the transistor 20 on the gallium nitride wafer 12 described above, and will not be elaborated here.

[0238] Exemplarily, the wafer for fabricating the transistor 20 is a gallium oxide wafer. Thus, in the fabricated transistor 20, the channel layer 231 of the semiconductor layer 23 in the transistor 20 is a gallium oxide layer, and the barrier layer 232 can be an aluminum nitride layer or a gallium aluminum oxide layer. Here, the fabrication of the transistor 20 on the gallium oxide wafer is similar to the fabrication of the aforementioned transistor 20 on the gallium nitride wafer 12, and will not be elaborated here.

[0239] In addition, in some embodiments where the transistor 20 is a HEMT, the transistor 20 has a high electron mobility, and the thickness of the transistor 20 can be set to be relatively small, such as less than 10 μm. Exemplarily, as Figure 2 shown, the transistor 20 only includes a semiconductor layer 23, a first passivation layer 24, and a gate 25, a source 26, and a drain 27 respectively disposed in the openings of the first passivation layer 24. The thickness D of the transistor 20 is less than 5 μm, such as 3 μm, 2 μm, or 1 μm. This is conducive to realizing the thinning and lightening of the semiconductor device 100 and reducing the thermal resistance of the semiconductor device 100.

[0240] It should be noted that in the semiconductor device 100, the number of transistors 20 can be one or more.

[0241] In some embodiments, the number of transistors 20 is multiple. The multiple transistors 20 can be arranged in an array or in a row on the first substrate 11. In addition, there can be various implementations of the coupling between the metal pattern 60 and the transistor 20. For example, as Figure 1 shown, the gate 25 of each transistor 20 is coupled to at least one first metal pattern 61; the source 26 of each transistor 20 is coupled to a second metal pattern 62; the drain 27 of each transistor 20 is coupled to a third metal pattern 63. Or, for another example, as Figure 24 shown, each first metal pattern 61 is coupled to the gate 25 of at least one transistor 20; each second metal pattern 62 is coupled to the source 26 of at least one transistor 20; each third metal pattern 63 is coupled to the drain 27 of at least one transistor 20. The embodiments of the present disclosure do not limit this.

[0242] Exemplarily, as Figure 24 and Figure 25As shown, the semiconductor device 100 includes four transistors arranged side by side, and each transistor is represented by codes M1, M2, M3, and M4 respectively. Some electrodes in the transistors M1, M2, M3, and M4 are shared, which can improve the distribution density of the transistors. For example, the transistors M1 and M2 share a drain 27, the transistors M3 and M2 share a source 26, and the transistors M4 and M3 share a drain 27. In addition, the gates 25 in the transistors M1, M2, M3, and M4 are interconnected and can be coupled to the same first metal pattern 61. The sources 26 of the transistors M1 and M4 are located on the outside and can be respectively coupled to a second metal pattern 62. The source 26 of the transistor M2 is located between the gates 25 of the transistors M2 and M3 and can be coupled to other conductive parts, for example, coupled to a metal layer 80 located on the back surface of the first substrate 11 through a first via hole H1. The drains 27 of the transistors M1 and M4 are interconnected and can be coupled to the same third metal pattern 63.

[0243] For the convenience of description, in the following some embodiments, the semiconductor device 100 includes only one transistor 20 as an example for illustration. In the case where the number of transistors 20 in the semiconductor device 100 is multiple, the structure of the semiconductor device 100 can be adaptively changed according to the following relevant descriptions.

[0244] Exemplarily, as Figure 1 and Figure 2 shown, the source 26, gate 25, and drain 27 of the transistor 20 are strip-shaped and the three are parallelly distributed, and the gate 25 is located between the source 26 and the drain 27. The multiple metal patterns 60 in the semiconductor device 100 include two first metal patterns 61, one second metal pattern 62, and one third metal pattern 63. Among them, the two first metal patterns 61 are respectively located on both sides of the gate 25 and are coupled to the two ends of the gate 25 along the length direction. The second metal pattern 62 is located on the side of the source 26 away from the gate 25 and is coupled to the source 26. The third metal pattern 63 is located on the side of the drain 27 away from the gate 25 and is coupled to the drain 27.

[0245] Please continue to refer to Figure 2 , most of the first metal pattern 61, the second metal pattern 62, and the third metal pattern 63 are formed on the surface of the auxiliary carrier portion 30, that is, the orthographic projections of the first metal pattern 61, the second metal pattern 62, and the third metal pattern 63 on the first substrate 11 are located in the area of the first substrate 11 not covered by the semiconductor layer 23. Thus, in the process of batch manufacturing the semiconductor device 100, in the case where the wafer 12 is a gallium nitride wafer or a similar wide-bandgap semiconductor wafer with high cost, compared with the case where the metal pattern 60 is formed in the passive region of the semiconductor layer, the semiconductor device 100 adopting the above structure can have a lower production cost.

[0246] In some embodiments, as Figure 2 shown, the surface of the auxiliary carrier portion 30 facing away from the first substrate 11 is flush or substantially flush with the surface of the gate 25 or the drain 27 in the transistor 20 facing away from the first substrate 11. Optionally, the surfaces of the gate 25 and the drain 27 in the transistor 20 facing away from the first substrate 11 may be located or substantially located in the same plane. This is beneficial to form a metal pattern 60 with better flatness on the auxiliary carrier portion 30 to ensure the film forming quality of the metal pattern 60.

[0247] In the case where the surfaces of the gate 25 and the drain 27 in the transistor 20 facing away from the first substrate 11 are not in the same plane, the surface of the auxiliary carrier portion 30 facing away from the first substrate 11 may be flush or substantially flush with the surface that is the farthest from the first substrate 11 among the two.

[0248] In addition, in some examples, as Figure 2 shown, the transistor 20 only includes a semiconductor layer 23, a first passivation layer 24, a gate 25, a source 26, and a drain 27. The surface of the auxiliary carrier portion 30 close to the first substrate 11 and the surface of the semiconductor layer 23 close to the first substrate 11 are formed in the same polishing process and are flush or substantially flush with each other.

[0249] In other examples, as Figure 21 shown, the transistor 20 further includes a transition layer 22 and a second substrate 21 laminated on a side of the semiconductor layer 23 facing away from the gate 25. The surface of the auxiliary carrier portion 30 close to the first substrate 11 and the surface of the second substrate 21 close to the first substrate 11 are formed in the same polishing process and are flush or substantially flush with each other.

[0250] In some embodiments, the first substrate 11 is prepared by a chemical vapor deposition process. As Figure 20 shown, the surface of the auxiliary carrier portion 30 facing away from the first substrate 11 is flush or substantially flush with the surface of the first passivation layer 24 facing away from the first substrate 11. On this basis, the gate 25, the source 26, and the drain 27 are respectively formed in corresponding openings of the first passivation layer 24. The gate 25, the source 26, and the drain 27 may protrude or not protrude from the surface of the first passivation layer 24 facing away from the semiconductor layer 24.

[0251] In addition, in other embodiments, as Figure 26As shown, the transistor 20 further includes a second passivation layer 28. The second passivation layer 28 is formed on the surface of the first passivation layer 24 facing away from the semiconductor layer 23, and is located on the side of the gate 25, source 26, and drain 27 facing away from the semiconductor layer 23. The surface of the auxiliary carrier portion 30 facing away from the first substrate 11 is flush or substantially flush with the surface of the second passivation layer 28 facing away from the first substrate 11. The metal pattern 60 can be coupled to the gate 25, source 26, or drain 27 through corresponding openings in the second passivation layer 28.

[0252] Correspondingly, please understand in combination with the manufacturing method of the semiconductor device 100 in the foregoing some embodiments.

[0253] As Figure 27 shown, a plurality of transistors 20 are fabricated on the wafer 12, including: epitaxially growing a semiconductor layer 23 on the wafer 12; forming a first passivation layer 24 on the surface of the semiconductor layer 23 facing away from the wafer 12; forming a plurality of openings in the first passivation layer 24, and respectively forming a gate 25, a source 26, and a drain 27 in the plurality of openings; forming a second passivation layer 28 on the surfaces of the first passivation layer 24, the gate 25, the source 26, and the drain 27 facing away from the semiconductor layer 23.

[0254] As Figure 28 shown, bonding the front surface of the device particle 201 (201') to the support substrate 90 includes: bonding the surface of the second passivation layer 28 facing away from the gate 25 to the support substrate 90.

[0255] Finally, forming a plurality of metal patterns 60 on the side of the auxiliary carrier portion 30 facing away from the first substrate 11 and making the plurality of metal patterns 60 be correspondingly coupled to the transistor 20 further includes: forming a plurality of openings in the second passivation layer 28; forming a plurality of metal patterns 60 on the side of the auxiliary carrier portion 30 facing away from the first substrate 11, such that the plurality of metal patterns are correspondingly coupled to the gate 25, source 26, and drain 27 through the openings in the second passivation layer 28.

[0256] In the embodiments of the present disclosure, after fabricating the gate 25, source 26, drain 27, and the second passivation layer 28 of the transistor 20, then synchronously transferring the transistor 20 and the auxiliary carrier portion 30 onto the first substrate 11, the second passivation layer 28 can be used to effectively protect the gate 25, source 26, and drain 27 of the transistor 20, thereby avoiding damage to the gate 25, source 26, and drain 27 of the transistor 20 due to the transfer of the transistor 20.

[0257] In the foregoing some embodiments, the auxiliary carrier portion 30 is used to assist in supporting the transistor 20, and there can be various ways of arranging the auxiliary carrier portion 30 beside the transistor 20. For example, the auxiliary carrier portion 30 is disposed on at least two sides of the transistor 20.

[0258] Optionally, as shown in Figure 29 FIG. Figure 29 , the auxiliary supporting portion 30 is disposed on opposite sides of the transistor 20, and the auxiliary supporting portion 30 includes two independently provided sub-portions 31 and 32.

[0259] Optionally, as shown in Figure 30 FIG. Figure 30 , the auxiliary supporting portion 30 is disposed on adjacent sides of the transistor 20.

[0260] Optionally, as shown in Figure 31 FIG. Figure 31 , the auxiliary supporting portion 30 is disposed around the peripheral side of the transistor 20.

[0261] In addition, in order to ensure that the auxiliary supporting portion 30 can effectively support and protect the transistor 20, so as to improve the process stability during the production of the semiconductor device 100, the ratio of the orthographic projection area of the auxiliary supporting portion 30 and the transistor 20 in the semiconductor device 100 on the first substrate 11 can be controlled within a reasonable range.

[0262] Optionally, referring to Figures 29 - 31 FIG. Figures 29 - 31 , taking the orthographic projection area of the transistor 20 in the semiconductor device 100 on the first substrate 11 as the first area S1, and the orthographic projection area of the auxiliary supporting portion 30 on the first substrate 11 as the second area S2, then: For example, or 1.

[0263] In some embodiments, as shown in Figure 32 FIG. Figure 32 , the semiconductor device 100 further includes a heat dissipation insulating layer 50 formed on the surfaces of the auxiliary supporting portion 30 and the transistor 20 facing away from the first substrate 11. A metal pattern 60 is formed on the surface of the heat dissipation insulating layer 50 facing away from the auxiliary supporting portion 30, and the metal pattern 60 can be correspondingly coupled to the electrodes in the transistor 20 through the openings in the heat dissipation insulating layer 50.

[0264] Correspondingly, the manufacturing method of the semiconductor device 100 further includes: forming a heat dissipation insulating layer 50 on the surfaces of the auxiliary supporting portion 30 and the transistor 20 facing away from the first substrate 11, so that the aforementioned plurality of metal patterns 60 are formed on the surface of the heat dissipation insulating layer 50 facing away from the auxiliary supporting portion 30.

[0265] Here, the heat dissipation insulating layer 50 can be prepared and formed by using an insulating material with good heat dissipation ability. The heat dissipation insulating layer 50 is, for example, a diamond layer. Forming the metal pattern 60 on the surface of the heat dissipation insulating layer 50 facing away from the auxiliary supporting portion 30 can effectively conduct the heat generated during the operation of the transistor 20 out through the heat dissipation insulating layer 50, thereby effectively improving the heat dissipation ability of the semiconductor device 100.

[0266] Optionally, in some embodiments, as shown in Figure 33As shown, the positive projection area of the auxiliary bearing portion 30 on the first substrate 11 is smaller than the planar area of the first substrate 11. A part of the surface of the heat dissipation insulating layer 50 can also be in direct contact with the first substrate 11. That is, the heat dissipation insulating layer 50 can cover both the auxiliary bearing portion 30 and the surface of the first substrate 11 not covered by the auxiliary bearing portion 30, so that the positive projection of the auxiliary bearing portion 30 on the first substrate 11 is located within the positive projection of the heat dissipation insulating layer 50 on the first substrate 11. Thus, when the first substrate 11 has a high thermal conductivity, the heat dissipation insulating layer 50 is in direct contact with the first substrate 11 and can also conduct heat to the first substrate 11 to further improve the heat dissipation capacity of the semiconductor device 100.

[0267] In some embodiments, as Figure 34 shown, the semiconductor device 100 further includes: a metal layer 80 formed on the surface of the first substrate 11 facing away from the transistor 11. In the embodiments of the present disclosure, forming the metal layer 80 on the surface of the first substrate 11 facing away from the semiconductor layer 23 can utilize the metal layer 80 to further improve the heat dissipation capacity of the first substrate 11. The metal layer 80 can be made of a metal material with good heat dissipation capacity, such as at least one of copper, aluminum, platinum, tungsten, nickel, iridium, or cobalt.

[0268] Furthermore, as Figure 35 shown, the semiconductor device 100 further includes: a heat dissipation substrate 82 disposed on the side of the metal layer 80 facing away from the first substrate 11. The metal layer 80 can be welded to the heat dissipation substrate 82, for example, by using processes such as gold - tin soldering, copper - tin soldering, or nano - silver sintering. That is, there is a soldering layer 81 between the metal layer 80 and the heat dissipation substrate 82, and the material of the soldering layer 81 can be selected according to actual needs to ensure good soldering quality between the metal layer 80 and the heat dissipation substrate 82. Welding the metal layer 80 to the heat dissipation substrate 82 can utilize the heat dissipation substrate 82 to further improve the heat dissipation capacity of the semiconductor device 100.

[0269] Optionally, the heat dissipation substrate 82 is a substrate with a high thermal conductivity such as an aluminum substrate, a copper substrate, a diamond / metal composite substrate, a ceramic substrate, a rigid printed circuit board, or a flexible printed circuit board.

[0270] Correspondingly, the structure of the semiconductor device 100 is as shown above. Before obtaining the semiconductor device 100, its manufacturing method further includes: forming a metal layer 80 on the surface of the first substrate 11 facing away from the transistor 20; providing a heat dissipation substrate 82 and welding the metal layer 80 to the heat dissipation substrate 82.

[0271] It should be added that in some embodiments, in addition to heat dissipation, the metal layer 80 can also be used as a common electrode to provide a ground signal or a floating signal to the transistor 20 or other electronic components in the semiconductor device 100.

[0272] In some examples, according to the different types of the transistors 20, the metal layer 80 may be coupled to the source 26 or the drain 27 in the transistors 20.

[0273] Optionally, as Figure 36 shown, the semiconductor device 100 further includes at least one first via hole H1. The first via hole H1 penetrates at least the first substrate 11 and the semiconductor layer 23, and the orthographic projection of the first via hole H1 on the metal layer 80 is located within the orthographic projection of the corresponding source 26 of the transistor 20 on the metal layer 80. The metal layer 80 may be coupled to the corresponding source 26 through the first via hole H1.

[0274] Here, the layer structure that the first via hole H1 needs to penetrate is consistent with the layer structure between the metal layer 80 and the source 26. According to the different structures of the semiconductor device 100, the layer structure penetrated by the first via hole H1 may be different, which will not be elaborated here.

[0275] Correspondingly, before forming the metal layer 80, the manufacturing method of the semiconductor device 100 further includes: forming a first via hole H1 that penetrates at least the first substrate 11 and the semiconductor layer 23, and making the orthographic projection of the first via hole H1 on the first substrate 11 be located within the orthographic projection of the corresponding source 26 of the transistor 20 on the first substrate 11. In this way, after forming the metal layer 80 on the surface of the first substrate 11 facing away from the transistors 20, the metal layer 80 can be coupled to the corresponding source 26 through the first via hole H1.

[0276] Optionally, as Figure 37 shown, the transistor 20 includes a transition layer 22 and a second substrate 21. The semiconductor device 100 further includes a bonding layer 40 located between the first substrate 11 and the second substrate 21. The bonding layer 40 is a conductive bonding layer. The first via hole H1 includes a first sub-via hole H11 and a second sub-via hole H12 that are arranged in sections. Among them, the first sub-via hole H11 penetrates the second substrate 21, the transition layer 22 and the semiconductor layer 23, and the two ends of the first via hole H1 are respectively coupled to the source 26 and the conductive bonding layer 40. The second sub-via hole H12 penetrates the first substrate 11, and the two ends of the second sub-via hole H12 are respectively coupled to the conductive bonding layer 40 and the metal layer 80.

[0277] Correspondingly, in the method for manufacturing the semiconductor device 100, forming a first via hole H1 that at least penetrates the first substrate 11 and the semiconductor layer 23 includes: forming a first sub-via hole H11 that penetrates the second substrate 21, the transition layer 22, and the semiconductor layer 23, such that one end of the first sub-via hole H11 is in direct contact with the corresponding source electrode 26; forming a conductive bonding layer 40 on the polished surfaces of the auxiliary carrier part 20 and the transistor 20, such that the conductive bonding layer 40 is in direct contact with the other end of the first sub-via hole H11; bonding the first substrate 22 to the conductive bonding layer 40; forming a second sub-via hole H12 that penetrates the first substrate 11, such that one end of the second sub-via hole H12 is in direct contact with the conductive bonding layer 40; and forming a metal layer 80 on the first substrate 11, such that the metal layer 80 is in direct contact with the other end of the second sub-via hole H12. Thus, the preparation of the first via hole H1 is achieved.

[0278] As described above, the first via hole H1 is composed of the first sub-via hole H11 and the second sub-via hole H12, which can reduce the manufacturing difficulty of the first via hole H1 and ensure the electrical connection performance of the first via hole H1, especially for the case where the thicknesses of the first substrate 11 and the transistor 20 are relatively large.

[0279] In some other examples, the metal layer 80 can be correspondingly coupled to a certain metal pattern 60, for example, coupled to the second metal pattern 62. Thus, as Figure 38 shown, the semiconductor device 100 further includes at least one second via hole H2. The second via hole H2 at least penetrates the first substrate 11 and the auxiliary carrier part 30, and the orthographic projection of the second via hole H2 on the metal layer 80 is located within the orthographic projection of the corresponding metal pattern 60 on the first substrate 11. The metal layer 80 can be coupled to the corresponding metal pattern 60 through the second via hole H2.

[0280] Here, the layer structure that the second via hole H2 needs to penetrate is consistent with the layer structure between the metal layer 80 and the metal pattern 60. According to the different structures of the semiconductor device 100, the layer structure penetrated by the second via hole H2 can be different, which will not be elaborated here.

[0281] Correspondingly, before forming the metal layer 80, the method for manufacturing the semiconductor device 100 further includes: forming a second via hole H2 that at least penetrates the first substrate 11 and the auxiliary carrier part 30, and making the orthographic projection of the second via hole H2 on the metal layer 80 be located within the orthographic projection of the corresponding metal pattern 60 on the first substrate 11. Thus, after forming the metal layer 80 on the surface of the first substrate 11 facing away from the transistor 20, the metal layer 80 can be coupled to the corresponding metal pattern 60 through the second via hole H2.

[0282] Optionally, as Figure 39As shown, the transistor 20 includes a transition layer 22 and a second substrate 21. The semiconductor device 100 further includes a bonding layer 40 located between the first substrate 11 and the second substrate 21. The bonding layer 40 is a conductive bonding layer. The second viaduct H2 includes a third sub-viaduct H21 and a fourth sub-viaduct H22 that are arranged in segments. The third sub-viaduct H21 penetrates through the auxiliary carrier portion 30, and both ends of the third sub-viaduct H21 are respectively coupled to the metal pattern 60 and the conductive bonding layer 40. The fourth sub-viaduct H22 penetrates through the first substrate 11, and both ends of the fourth sub-viaduct H22 are respectively coupled to the conductive bonding layer 40 and the metal layer 80.

[0283] Correspondingly, in the manufacturing method of the semiconductor device 100, forming the second viaduct H2 that at least penetrates through the first substrate 11 and the auxiliary carrier portion 30 includes: forming the third sub-viaduct H21 that penetrates through the auxiliary carrier portion 30; forming the conductive bonding layer 40 on the polished surfaces of the auxiliary carrier portion 30 and the transistor 20 such that the conductive bonding layer 40 is in direct contact with one end of the third sub-viaduct H21; bonding the first substrate 11 to the conductive bonding layer 40; forming the fourth sub-viaduct H22 that penetrates through the first substrate 11 such that one end of the fourth sub-viaduct H22 is in direct contact with the conductive bonding layer 40; forming the metal layer 80 on the first substrate 11 such that the metal layer 80 is in direct contact with the other end of the fourth sub-viaduct H22. In this way, after forming the metal pattern 60 subsequently, making the metal pattern 60 be in direct contact with the other end of the third sub-viaduct H21 can realize the coupling between the metal pattern 60 and the conductive bonding layer 40 through the third sub-viaduct H21.

[0284] As described above, the second viaduct H2 is composed of the third sub-viaduct H21 and the fourth sub-viaduct H22, which can reduce the manufacturing difficulty of the second viaduct H2 and ensure the electrical connection performance of the second viaduct H2, especially for the case where the thicknesses of the first substrate 11 and the auxiliary carrier portion 30 are relatively large.

[0285] It should be added that the above-mentioned first viaduct H1, second viaduct H2, first sub-viaduct H11, second sub-viaduct H21, third sub-viaduct H21, and fourth sub-viaduct H22 all include through-holes and metal conductors filled in the through-holes. In the case where the first viaduct H1 or the second viaduct H2 is not arranged in segments, the metal conductors in the first viaduct H1 or the second viaduct H2 can be prepared with the same metal material as the metal layer 80 to simplify the manufacturing process of the semiconductor device 100.

[0286] In some embodiments, the metal pattern 60 is a planar electrode or a metal wire. On this basis, as Figure 40As shown, the semiconductor device 100 further includes: a plurality of bonding pads 70. The bonding pads 70 are formed on corresponding metal patterns 60, and the orthographic projection of the bonding pads 70 on the first substrate 11 is located in the area of the first substrate 11 that is not covered by the transistors 20.

[0287] Correspondingly, before obtaining the semiconductor device 100, the manufacturing method of the semiconductor device 100 further includes: forming at least one bonding pad 70 on the metal pattern 60 such that the orthographic projection of the bonding pad 70 on the first substrate 11 is located in the area of the first substrate 11 that is not covered by the transistors 20.

[0288] Here, the bonding pads 70 can be formed of a metal material with good conductivity and certain mechanical strength, such as at least one of gold, copper, aluminum, platinum, tungsten, nickel, iridium, or cobalt. The material of the bonding pads 70 can be the same as or different from the material of the metal patterns 60, either is acceptable.

[0289] Exemplarily, the material hardness of the bonding pads 70 is greater than the material hardness of the metal patterns 60. The bonding pads 70 are arranged in a boss shape on the surface of the corresponding metal patterns 60, which is convenient for bonding external metal leads on the surface of the bonding pads 70 to couple with external components using the metal leads, thereby realizing the transmission of electrical signals between the semiconductor device 100 and the external components. The external components are, for example, a packaging shell or an adapter substrate, etc.

[0290] To more clearly illustrate the structure of the semiconductor device 100 in some embodiments of the present disclosure, for example, the structure of the semiconductor device 100 when the metal pattern 60 is a multi-layer pattern, the following takes Figure 41 the semiconductor device 100 shown as an example for detailed description. In the semiconductor device 100, a passive matching circuit can be fabricated in the area of the first substrate 11 that is not covered by the transistors 20 and the auxiliary carrier 30 by using the multi-layer pattern of the metal pattern 60. Of course, it is also allowed to fabricate the passive matching circuit on the surface of the auxiliary carrier 30 facing away from the first substrate 11. The embodiments of the present disclosure do not limit this, and it can be selected according to actual needs. The passive matching circuit generally can be composed of at least one of a capacitor, an inductor, a resistor, a metal wire, and a metal via.

[0291] According to the coupling relationship between the metal pattern 60 and each electrode in the transistor 20, the metal pattern 60 includes: a first metal pattern 61 coupled to the gate 25, a second metal pattern 62 coupled to the source 26, and a third metal pattern 63 coupled to the drain 27. Correspondingly, the plurality of bonding pads 70 includes: at least one first bonding pad 71 formed on the first metal pattern 61, at least one second bonding pad 72 formed on the second metal pattern 62, and at least one third bonding pad 73 formed on the third metal pattern 63.

[0292] For example, please refer to Figure 41 , Figure 42 and Figure 43 , both the first metal pattern 61 and the third metal pattern 63 include two layers of patterns, and an insulating layer 32 is provided between the first layer pattern and the second layer pattern. Among them, the first layer pattern is formed on the first substrate 11, and the second layer pattern is formed on the side of the first layer pattern away from the first substrate 11, that is, on the surface of the insulating layer 32 away from the first substrate 11. Optionally, the insulating layer 32 may also be composed of the heat dissipation insulating layer 50 in some of the foregoing embodiments.

[0293] In addition, the second metal pattern 62 is a single-layer pattern, and the second metal pattern 62 is formed on the surface of the insulating layer 32 away from the first substrate 11. In this way, the second metal pattern 62 can be formed synchronously with the second layer patterns in the first metal pattern 61 and the third metal pattern 63.

[0294] As Figure 41 and Figure 42 shown, at least the following can be formed by using the first metal pattern 61: a first capacitor C1, a second capacitor C2, and a first inductor L1. Here, the first pole 611 of the first capacitor C1 and the first pole of the second capacitor C2 can be formed by the first layer pattern in the first metal pattern 61, and the second pole 612 of the first capacitor C1 and the second pole of the second capacitor C2 can be formed by the second layer pattern in the first metal pattern 61. The first inductor L1 is a trench inductor and can be formed by the second layer pattern in the first metal pattern 61. In addition, the interconnection between the first capacitor C1, the second capacitor C2, the first inductor L1 and the gate 25 in the transistor 20 can be realized through metal wires or metal vias. The first bonding pad 71 is formed on the second layer pattern of the first metal pattern 61.

[0295] As Figure 41 and Figure 43 shown, at least the following can be formed by using the third metal pattern 63: a first resistor R1 and a second inductor L2. Here, the first resistor R1 can be formed by the first layer pattern in the third metal pattern 63. The second inductor L2 is a trench inductor and can be formed by the second layer pattern in the third metal pattern 63. In addition, the coupling between the first resistor R1, the second inductor L2 and the drain 27 in the transistor 20 can be realized through metal wires or metal vias. The third bonding pad 73 is formed on the second layer pattern of the third metal pattern 63.

[0296] It should be added that the above passive matching circuit can also be coupled to a metal layer 80 provided on the first substrate 11 through a via penetrating the first substrate 11, so as to use the metal layer 80 to transmit a ground signal or a floating signal.

[0297] The embodiments of the present disclosure also provide an electronic device. AsFigure 44 As shown, the electronic device 1000 includes: at least one semiconductor device 100 as described in any of the foregoing embodiments. The electronic device is, for example, a monolithic microwave integrated circuit (MMIC), a power amplifier based on MMIC, a mixer, a detector, a modulator, a phase shifter, or a power adapter and other electronic products. The specific form of the electronic device in the embodiments of the present disclosure is not particularly limited.

[0298] Exemplarily, the electronic device 1000 is a power amplifier. Figure 44 And Figure 45 Two cross-sectional structures of the electronic device 1000 are schematically given, but not limited thereto.

[0299] As Figure 44 shown, the semiconductor device 100 includes a heat dissipation substrate 82. The electronic device 1000 further includes a metal lead 1001, an external pin 1002, and an insulating portion 1003. The insulating portion 1003 is formed of an insulating material, such as a ceramic material, on the exposed surface of the heat dissipation substrate 82. The external pin 1002 is disposed on the surface of the insulating portion 1003 facing away from the heat dissipation substrate 82. The metal pattern 60 or the bonding pad 70 in the semiconductor device 100 can be correspondingly coupled to the external pin 1002 through the metal lead 1001.

[0300] The structures of the metal lead 1001, the external pin 1002, and the insulating portion 1003 can be selected and set according to actual needs. The embodiments of the present disclosure do not limit this. Optionally, the insulating portion 1003 adopts an annular structure, and there is a gap between the first substrate 11 and other parts on the heat dissipation substrate 82 in the semiconductor device 1000 and the inner side wall of the insulating portion 1003. The external pin 1002 is composed of a hollowed-out metal sheet. The metal lead 1001 is prepared from a metal material with good conductivity and certain mechanical strength, and the metal material is, for example, at least one of gold, copper, aluminum, platinum, tungsten, nickel, iridium, or cobalt.

[0301] In some embodiments, as Figure 45 shown, the electronic device 1000 further includes a packaging cover plate 1004. The packaging cover plate 1004 can be buckled on the heat dissipation substrate 82 or the ceramic portion 1003. A part of the external pin 1002 extends out of the packaging cover plate 1004, which is convenient for realizing the coupling of the electronic device 1000 with external components.

[0302] In the embodiments of the present disclosure, the advantages of the electronic device 1000 are the same as those of the semiconductor device 100 in the foregoing some embodiments, and will not be elaborated herein.

[0303] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0304] As described above, this is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A first substrate, at least one transistor, an auxiliary carrier portion, and a plurality of metal patterns; wherein, The auxiliary carrier portion and the at least one transistor are disposed on the first substrate; the orthographic projection of the auxiliary carrier portion on the first substrate is located outside the orthographic projection of the at least one transistor on the first substrate, and a boundary of the orthographic projection of the auxiliary carrier portion on the first substrate partially coincides with a boundary of the orthographic projection of the at least one transistor on the first substrate; Each transistor of the at least one transistor includes: a semiconductor layer, and a gate, a source, and a drain located on a side of the semiconductor layer facing away from the first substrate; The plurality of metal patterns are formed on a side of the auxiliary carrier portion facing away from the first substrate; at least one metal pattern of the plurality of metal patterns is coupled to the gate, at least one metal pattern is coupled to the drain, and the metal pattern coupled to the gate and the metal pattern coupled to the drain are insulated from each other; Wherein, a surface of the auxiliary carrier portion facing away from the first substrate is flush or substantially flush with a surface of the at least one transistor facing away from the first substrate.

2. The semiconductor device according to claim 1, wherein The surface of the auxiliary carrier portion facing away from the first substrate is flush or substantially flush with a surface of the gate or the drain facing away from the first substrate.

3. The semiconductor device according to claim 1, wherein The transistor further includes: a first passivation layer located on a surface of the semiconductor layer facing away from the first substrate; the first passivation layer includes a plurality of openings, and the gate, the source, and the drain are respectively formed in corresponding openings; The surface of the auxiliary carrier portion facing away from the first substrate is flush or substantially flush with a surface of the first passivation layer facing away from the first substrate.

4. The semiconductor device according to claim 1, wherein The transistor further includes: a first passivation layer and a second passivation layer; both the first passivation layer and the second passivation layer include a plurality of openings; The first passivation layer is formed on a surface of the semiconductor layer facing away from the first substrate; the gate, the source, and the drain are respectively formed in corresponding openings in the first passivation layer; The second passivation layer is formed on a surface of the first passivation layer facing away from the semiconductor layer and is located on a side of the gate, the source, and the drain facing away from the semiconductor layer; The surface of the auxiliary carrier portion facing away from the first substrate is flush or substantially flush with a surface of the second passivation layer facing away from the first substrate; the metal pattern is coupled to the gate or the drain through a corresponding opening in the second passivation layer.

5. The semiconductor device according to claim 1, wherein Further comprising: A heat dissipation insulating layer; The heat dissipation insulating layer is formed on surfaces of the auxiliary carrier portion and the transistor facing away from the first substrate; the metal pattern is formed on a surface of the heat dissipation insulating layer facing away from the auxiliary carrier portion.

6. The semiconductor device according to claim 5, wherein The orthographic projection of the auxiliary carrier portion on the first substrate is located within the orthographic projection of the heat dissipation insulating layer on the first substrate; a partial surface of the heat dissipation insulating layer is in direct contact with the first substrate.

7. The semiconductor device according to claim 1, wherein Further comprising: A metal layer and at least one first via hole; wherein, The metal layer is formed on a surface of the first substrate facing away from the transistor; The first vias penetrate at least the first substrate and the semiconductor layer; a positive projection of the first vias on the metal layer is located within a positive projection of the source electrode in the corresponding transistor on the metal layer; The metal layer is coupled to the source electrode through the first vias.

8. The semiconductor device according to claim 1, wherein Further included are: A metal layer and at least one second via; wherein, The metal layer is formed on a surface of the first substrate facing away from the transistor; The second vias penetrate at least the first substrate and the auxiliary carrier portion; a positive projection of the second vias on the metal layer is located within a positive projection of the corresponding metal pattern on the first substrate; The metal layer is coupled to the metal pattern through the second vias.

9. The semiconductor device according to claim 7 or 8, characterized in that, Further included are: A heat dissipation substrate; The heat dissipation substrate is located on a side of the metal layer facing away from the first substrate; The metal layer is welded to the heat dissipation substrate.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that A surface of the auxiliary carrier portion close to the first substrate is flush or substantially flush with a surface of the semiconductor layer close to the first substrate; The semiconductor device further includes: a non-conductive bonding layer; The auxiliary carrier portion and the semiconductor layer of the at least one transistor are bonded to the first substrate through the non-conductive bonding layer.

11. The semiconductor device according to any one of claims 1 to 8, characterized in that The transistor further includes: a transition layer and a second substrate stacked on a side of the semiconductor layer facing away from the gate; a surface of the auxiliary carrier portion close to the first substrate is flush or substantially flush with a surface of the second substrate close to the first substrate; The semiconductor device further includes: a conductive bonding layer; The auxiliary carrier portion and the second substrate of the at least one transistor are bonded to the first substrate through the conductive bonding layer.

12. The semiconductor device according to any one of claims 1 to 8, characterized in that, Further included are: A gas barrier layer; The gas barrier layer is formed on surfaces of the auxiliary carrier portion and the at least one transistor close to the first substrate; the first substrate is formed on a surface of the gas barrier layer facing away from the auxiliary carrier portion.

13. The semiconductor device according to any one of claims 1 to 8, characterized in that, The semiconductor layer includes a channel layer and a barrier layer stacked in a direction away from the first substrate.

14. An electronic device, characterized in that, Included are: At least one semiconductor device according to any one of claims 1 to 13.

15. A method for manufacturing a semiconductor device, characterized in that, Included are: Providing a wafer, and fabricating a plurality of transistors or partial layers of a plurality of transistors on the wafer; A front surface of the transistor or its partial layer is the outermost surface facing away from the wafer; Cutting the wafer along a thickness direction of the wafer to obtain a plurality of device particles; one device particle includes at least one transistor or at least one partial layer of a transistor; Providing a support substrate, and bonding a front surface of at least one of the device particles to the support substrate; the front surface of the device particle is the front surface of the transistor or its partial layer; Forming an auxiliary carrier film on a surface of the support substrate not covered by the device particles and on a back surface of the device particles; Polish the auxiliary carrier film and the device particles to obtain the at least one transistor and the auxiliary carrier portion located beside the at least one transistor, and a polished surface of the auxiliary carrier portion and a polished surface of the at least one transistor are in the same plane; Provide a first substrate, and synchronously bond the polished surfaces of the auxiliary carrier portion and the at least one transistor onto the first substrate; or, fabricate a first substrate on the polished surfaces of the auxiliary carrier portion and the at least one transistor; Remove the support substrate; Form a plurality of metal patterns on a side of the auxiliary carrier portion facing away from the first substrate, and couple the plurality of metal patterns to the at least one transistor correspondingly; Obtain a semiconductor device.

16. The method for manufacturing a semiconductor device according to claim 15, wherein The transistor in the device particles at least includes: a second substrate and a semiconductor layer epitaxially grown on the second substrate; the second substrate is a part of the wafer located in the device particles; Polishing the device particles further includes: exposing a surface of the semiconductor layer in the at least one transistor close to the second substrate; or, exposing a polished surface of the second substrate in the at least one transistor.

17. The method for manufacturing a semiconductor device according to claim 16, wherein, The transistor in the device particles further includes: a first passivation layer, a gate, a source, a drain, and a second passivation layer; Fabricating a plurality of transistors or partial layers of a plurality of transistors on the wafer includes: epitaxially growing the semiconductor layer on the wafer; forming a first passivation layer on a surface of the semiconductor layer facing away from the wafer; forming a plurality of openings in the first passivation layer, and respectively forming the gate, the source, and the drain in the plurality of openings; forming a second passivation layer on surfaces of the first passivation layer, the gate, the source, and the drain facing away from the semiconductor layer; Bonding the front surface of the device particles onto the support substrate includes: bonding a surface of the second passivation layer facing away from the gate onto the support substrate; Forming a plurality of metal patterns on a side of the auxiliary carrier portion facing away from the first substrate, and coupling the plurality of metal patterns to the at least one transistor correspondingly further includes: forming a plurality of openings in the second passivation layer; forming a plurality of metal patterns on a side of the auxiliary carrier portion facing away from the first substrate, such that the plurality of metal patterns are coupled to the gate and the drain through the openings in the second passivation layer.

18. The method for manufacturing a semiconductor device according to claim 16, characterized in that, The transistor in the device particles further includes: a first passivation layer formed on a surface of the semiconductor layer facing away from the wafer; Fabricating a plurality of transistors or partial layers of a plurality of transistors on the wafer includes: epitaxially growing the semiconductor layer on the wafer; forming a first passivation layer on a surface of the semiconductor layer facing away from the wafer; Bonding the front surface of the device particles onto the support substrate includes: bonding a surface of the first passivation layer facing away from the semiconductor layer onto the support substrate; Form a plurality of metal patterns on a side of the auxiliary carrier portion facing away from the first substrate, and couple the plurality of metal patterns to the at least one transistor correspondingly. It further includes: forming a plurality of openings in the first passivation layer, and respectively forming a gate, a source, and a drain in the plurality of openings; forming a plurality of metal patterns on a side of the auxiliary carrier portion facing away from the first substrate, and coupling at least one of the plurality of metal patterns to the gate, at least one metal pattern to the drain, and insulating the metal pattern coupled to the gate from the metal pattern coupled to the drain.

19. The method for manufacturing a semiconductor device according to claim 18, wherein, Prepare a first substrate on a polished surface of the auxiliary carrier portion and the at least one transistor. It further includes: Form a gas barrier layer on a polished surface of the auxiliary carrier portion and the at least one transistor, where the gas barrier layer includes at least one layer of a silicon layer, a silicon nitride layer, an aluminum nitride layer, or a silicon carbide layer; Form the first substrate on a surface of the gas barrier layer facing away from the auxiliary carrier portion by using a chemical vapor deposition process or a physical vapor deposition process.

20. The method for manufacturing a semiconductor device according to claim 15, characterized in that, Form a plurality of metal patterns on a side of the auxiliary carrier portion facing away from the first substrate. It further includes: Form a heat dissipation insulating layer on a surface of the auxiliary carrier portion and the at least one transistor facing away from the first substrate; Form the plurality of metal patterns on a surface of the heat dissipation insulating layer facing away from the auxiliary carrier portion.

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