Electronic equipment including electronic modules and compensation circuits

Abstract

Electronic devices including an electronic module and a compensation circuit are disclosed. According to one aspect, an electronic device includes a power terminal, a voltage regulator connected to the power terminal, an electronic module connected to the voltage regulator, and a compensation circuit configured to receive an auxiliary current generated by the voltage regulator and equal to a first portion of an electronic module current. The compensation circuit includes a current source configured to provide a source current to a cold spot and a compensation stage connected to the power terminal and traversed by an intermediate current equal to a difference between the source current and the auxiliary current and a complementary current equal to an inverse multiplication factor of the first portion multiplied by the intermediate current.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of French Patent Application No. 2201616, filed on February 23, 2022, which is incorporated herein by reference. Technical Field

[0003] The implementations and embodiments of the present invention relate to systems on a chip, and more specifically to protecting such systems on a chip from external attacks of the Simple Power Analysis (“SPA”) type. Background Technology

[0004] System-on-a-chip (SoC) can become a target for attacks aimed at recovering security information, especially those carried out through power analysis or SPAS.

[0005] During operation, the power consumption of an on-chip system depends more or less on the operations it performs. SPA attacks involve analyzing these power consumption variations in order to specifically infer the operations performed and / or indications of their occurrence.

[0006] Therefore, in security applications, it is recommended to smooth power consumption as much as possible so that potential attackers will find it difficult to determine the activity of various components of the system-on-a-chip through SPA attacks.

[0007] French patent application number 19 / 14244 describes a solution to SPA attacks. The proposed solution describes an electronic device including a first-generation component connected to a power supply terminal of an electronic module, particularly a microprocessor. The module is configured to consume module current. A first generating component is configured to generate an auxiliary module current equal to a first portion of the corresponding module current for each module. The electronic device also includes a first stage connected to the power supply terminal, including at least one current source configured to provide a stage current greater than the sum of the maximum values ​​of each auxiliary module current. The device also includes a second generating component configured to generate an intermediate current equal to the difference between the stage current and a secondary current equal to the sum of the currents of each auxiliary module. The electronic device further includes a regulating stage connected to the power supply terminal, comprising a first branch configured to generate a reference potential from the intermediate current, and a second branch including a regulating component and a comparator component configured to voltage-drive the regulating component, such that the potential of the second branch is equal to the reference potential, obtained by multiplying the current flowing in the branch by an impedance equal to the first portion. The device also includes a terminal stage connected to the power supply terminal and configured to multiply the intermediate current by a multiplication factor equal to 1.

[0008] This device allows for the simple generation of multiple currents consumed by the power supply, the sum of which depends not on the current consumed by the electronic modules, but only theoretically on the current supplied by the current source stage. The sum of the consumed currents is relatively constant. Therefore, the consumption of the integrated circuits is smoothed out, and from the outside, this smoothed total consumption is greater than the sum of the maximum consumption of each module.

[0009] For good performance, it is important that the current smoothing component quickly follows the current drawn by the voltage regulator to optimally smooth the current delivered by the power supply.

[0010] However, the electronic device has several stages controlled by two amplifiers, which makes the device cluttered and generates additional delays and power consumption. These delays do not allow for a sufficiently fast response to smooth current in applications with high operating frequencies (e.g., on the order of 115 MHz) for the electronic modules. High frequencies cause more abrupt current surges between the slow and fast phases of the electronic module's activity. Compensating for the delay then results in peaks in the current delivered by the power supply, and thus generates characteristics of the electronic module's operation that can be used to perform consumption analysis attacks.

[0011] Therefore, a compensation circuit that is more sensitive to changes in the current drawn by the electronic module is needed. Summary of the Invention

[0012] According to one aspect, an electronic device is provided, comprising:

[0013] The power terminal is configured to be connected to a power source.

[0014] At least one voltage regulator is connected to the power supply terminal.

[0015] At least one electronic module, particularly a microprocessor, is connected to at least one voltage regulator and is configured to draw current from the power supply.

[0016] A compensation circuit, connected to the at least one voltage regulator and configured to receive an auxiliary current generated by the at least one voltage regulator, the auxiliary current being equal to a first portion of the electronic module current consumed by the at least one electronic module, the compensation circuit comprising:

[0017] A current source, connected to at least one voltage regulator to receive auxiliary current, is configured to provide a source current to the cold point that is greater than the maximum value of the electronic module current consumed by at least one electronic module.

[0018] Compensation levels include:

[0019] Both the first resistor and the second resistor have a first terminal connected to a power supply terminal. The first resistor has a resistance value equal to the resistance value of the second resistor multiplied by a multiplication factor. The first resistor also has a second terminal connected to a current source so that an intermediate current equal to the difference between the source current and the auxiliary current can pass through it.

[0020] A transistor having a drain connected to the second terminal of a second resistor and a source connected to a cold spot.

[0021] An operational amplifier is configured to control a transistor and has an inverting input connected to the second terminal of a first resistor and a non-inverting input connected to the second terminal of a second resistor, such that the second resistor is traversed by a complementary current equal to the intermediate current multiplied by a multiplication factor.

[0022] The compensation circuit is configured to consume the current flowing through the compensation stage in addition to the current drawn by the electronic module, so that the sum of the current drawn by the compensation circuit and the electronic module is constant.

[0023] This compensation circuit allows the current seen from the power supply terminals to be smoothed out in order to conceal the current drawn by the electronic module connected to at least one voltage regulator.

[0024] This compensation circuit comprises a limited number of stages, which allows it to improve its responsiveness to changes in current drawn by the electronic module, thereby reducing its power consumption and physical size. In particular, this compensation circuit allows for the avoidance of the replication error of the current mirror used in the electronic device described in French patent application number 19 / 14244. This compensation circuit is also inexpensive.

[0025] An electronic device may be provided, comprising a single voltage regulator and a single electronic module connected to the voltage regulator. Alternatively, an electronic device may be provided, comprising several voltage regulators and several electronic modules connected to various voltage regulators. A compensation circuit then has an input for each voltage regulator to receive auxiliary current generated by the various voltage regulators. A current source and a compensation stage are then connected to the various voltage regulators.

[0026] In an advantageous embodiment, the current source and compensation stage are connected to at least one regulator via a transistor controlled by an operational amplifier having an inverting input connected to the source of the transistor and a non-inverting input configured to receive the voltage delivered to the electronic module by the at least one regulator. The transistor and the amplifier allow a potential at the drain of the transistor that is identical to the potential between the at least one regulator and the at least one electronic module, thereby ensuring an auxiliary current consistent with the current supplied to the electronic module.

[0027] When an electronic device includes several voltage regulators and several electronic modules, the current source and compensation stage are connected to the various regulators through several parallel branches, each branch including a transistor controlled by an operational amplifier as described above.

[0028] Preferably, the compensation level includes:

[0029] A first transistor has a drain connected to a second terminal of a first resistor and a source connected to a current source, such that the second terminal of the first resistor is connected to the current source via the first transistor.

[0030] The second transistor has a drain connected to a second terminal of a second resistor and a source connected to the drain of the transistor, such that the second terminal of the second resistor is connected to the drain of the transistor via the second transistor.

[0031] The first transistor and the second transistor have gates configured to receive a fixed voltage that allows the first transistor and the second transistor to operate as a cascode circuit. This fixed voltage can be a voltage supplied to the electronic module by at least one regulator.

[0032] The first transistor allows the potential at the second terminal of the first resistor to vary freely according to the current flowing through the first resistor. The second transistor allows protection of the transistors in the compensation stage controlled by the operational amplifier from high voltage, and also allows the potential at the second terminal of the second resistor to vary freely according to the current flowing through the second resistor.

[0033] Advantageously, the current source includes at least one current mirror configured to generate a source current from a reference current. Therefore, the current source may include one or more current mirrors to generate the source current. When the current source includes several current mirrors, the latter can be activated or deactivated according to the desired value of the source current.

[0034] In an advantageous embodiment, the current source includes:

[0035] Reference branches include:

[0036] At least the reference transistor of the current mirror,

[0037] A common-source cascode transistor has a drain configured to receive a reference current and connected to the gate of a reference transistor, a source connected to the drain of the reference transistor, and a gate configured to receive a fixed voltage.

[0038] A transistor having a drain connected to the source of a reference transistor, a source connected to a cold spot, and a gate configured to receive a voltage delivered to an electronic module by at least one regulator.

[0039] The auxiliary current generation branch for each current mirror includes:

[0040] A replica transistor of a current mirror, the replica transistor having a gate connected to the gate of a reference transistor and configured to at least partially generate a source current.

[0041] A common-source, common-gate transistor has a drain connected to the second output of at least one regulator and a source connected to the drain of a replica transistor.

[0042] The selection transistor has a drain connected to the source of the replica transistor, a source connected to a cold spot, and a gate configured to be controlled by a selection signal.

[0043] For example, the reference current can be on the order of 5 μA. Each current mirror includes a reference transistor and a replica transistor that allows the reference current to be multiplied. The sum of the currents generated by each current mirror corresponds to the source current generated by the current source.

[0044] Each select transistor allows activation or deactivation of its associated current mirror in order to modify the value of the source current generated by the current source.

[0045] Advantageously, the common-source cascode transistor of each current mirror generation branch has a gate configured to receive a fixed voltage.

[0046] Preferably, the cascode transistor is common to each generation branch, and the current source also includes an operational amplifier having a non-inverting input connected to the drain of the reference transistor, an inverting input connected to the source of the common transistor, and an output connected to the gate of the transistor. The operational amplifier then allows the acquisition of the drain voltage of the replica transistor of the current mirror, which is the same as the voltage at the drain of the reference transistor of the current mirror. Therefore, a smaller common-source cascode transistor can be used, allowing for reduced parasitic capacitance, thereby making the compensation circuit more responsive to current changes. Attached Figure Description

[0047] Other advantages and features of the invention will become apparent upon examination of the detailed description and accompanying drawings of the non-limiting embodiments, wherein:

[0048] Figure 1 An electronic device including an electronic module and a voltage regulator is shown;

[0049] Figure 2 An electronic device with a current source is shown, the current source including a reference branch and at least one branch for generating current; and

[0050] Figure 3 An electronic device is shown that includes a single common transistor for each current generation branch, which is controlled by an operational amplifier. Detailed Implementation

[0051] Figure 1 An electronic device DIS, particularly a system-on-a-chip (SoC), including electronic modules, especially a microprocessor CPU, and an LDO voltage regulator are illustrated. The LDO regulator is configured to adapt the voltage VCC provided by the power supply ALIM to a desired voltage to power the microprocessor CPU. For example, the LDO regulator may be adapted to provide 1.2V to the microprocessor CPU from a 3V voltage generated by the power supply ALIM. The LDO voltage regulator may be a low-dropout type (also known as a "low-dropout regulator" or "LDO regulator").

[0052] The LDO voltage regulator has an input I1 connected to the power supply terminal BA of the electronic device DIS. The power supply terminal BA is configured to be connected to the power supply ALIM. The LDO regulator also has a first output O1 connected to the power supply terminal of the microprocessor CPU. In this way, the LDO voltage regulator is configured to extract the current I supplied by the power supply ALIM. vdd This current is then transferred to the microprocessor CPU. Current I vdd The value can vary depending on the operations that the microprocessor can perform.

[0053] The electronic device DIS also includes a compensation circuit JSCR, which is configured to draw current I from the power supply ALIM. JSCR This makes the total current I drawn from the power source... VCC It is constant, regardless of the value of the current Ivdd required by the microprocessor CPU.

[0054] Specifically, the compensation circuit JSCR includes a first input IN1 connected to the second output O2 of the LDO voltage regulator, and a second input IN2 connected to the power supply terminal BA of the electronic device DIS so as to be able to be connected to the power supply ALIM.

[0055] The second output O2 of the voltage regulator is configured to send an equal amount of I to the compensation circuit JSCR. vdd / 100 auxiliary current I aux That is, current I vdd One percent. For this purpose, the LDO voltage regulator may include a current mirror. The current mirror may then include a first branch with a first transistor of a given size, and a second branch with a second transistor of a size one hundred times smaller than the first transistor. The current mirror may also include a plurality of identical transistors connected in parallel on its first branch, the number of which is one hundred times greater than the number of identical transistors connected in parallel on its second branch.

[0056] Therefore, the LDO regulator is configured to draw the total current I. VDD The total current I VDDEqual to the current I required by the microprocessor VDD The value transmitted to the compensation circuit is equal to I. VDD / 100 current I aux sum.

[0057] The compensation circuit JSCR may include a first amplifier AMP_LDO configured to control the gate of a first PMOS transistor PCASLDO. The amplifier AMP_LDO includes an inverting input connected to the second output O2 of the LDO regulator via a first input IN1 of the compensation circuit, and also connected to the source of the transistor PCASLDO. The amplifier AMP_LDO also includes a non-inverting input connected to the first output O1 of the LDO regulator to receive a voltage vdd at the input of the microprocessor CPU. Therefore, the first amplifier AMP_LDO and the transistor PCASLDO allow the same potential to be obtained at the second output O2 of the LDO regulator as at the first output O1 of the LDO regulator, thereby ensuring the current I... vdd / 100 conforms to the current I supplied to the microprocessor CPU. vdd .

[0058] The compensation circuit JSCR also includes a current source SC, which has a first terminal connected to the drain of the transistor PCASLDO and a second terminal connected to the cold point, specifically ground GND. The current source SC is NMOS type and is therefore configured to generate an I²C value towards the cold point GND. set / 100 current I src Current I set The value was chosen to be greater than the current I. vdd The maximum value of the current I. src and current I set The ratio between them was chosen to be the ratio of the current I. aux and I vdd The ratios between them are the same. (The following is a combination of...) Figure 2 and Figure 3 An embodiment of this current source is described.

[0059] The compensation circuit JSCR also includes a compensation stage. The compensation stage includes an NMOS transistor, CASMINUS. The CASMINUS transistor has a gate connected to the first output of the LDO regulator to receive a fixed voltage that allows the CASMINUS transistor to operate as a cascode. This fixed voltage can be a voltage Vdd. The CASMINUS transistor also includes a source connected to the first terminal of a current source and the drain of the transistor PCASLDO.

[0060] The compensation stage CSTG includes a resistor R0 with a first terminal and a second terminal. The first terminal is connected to the second input IN2 of the compensation circuit JSCR to enable connection to the power supply ALIM, and the second terminal is connected to the drain of the transistor CASMINUS. The compensation stage also includes a resistor R1 with a first terminal connected to both the first terminal of resistor R0 and the second input IN2 of the compensation circuit JSCR to enable connection to the power supply ALIM. The value of resistor R1 is selected such that the ratio between resistor R1 and resistor R0 is proportional to the current I. aux and I vdd The ratios between them are the same, and are related to the current I. src and current I set The ratios between them are the same. For example, the value of resistor R1 is equal to R0 / 100. The CASMINUS transistor allows the potential at the second terminal of resistor R0 to vary freely according to the current flowing through resistor R0.

[0061] The compensation stage CSTG also includes an NMOS transistor, CASPLUS. CASPLUS has a gate connected to the first output of the LDO regulator to receive a fixed voltage that allows it to operate as a cascode source. This fixed voltage can be a voltage Vdd. CASPLUS also has a drain connected to the second terminal of resistor R1.

[0062] The compensation stage CSTG also includes an NMOS transistor LV. Transistor LV has a drain connected to the source of transistor CASPLUS and a source connected to a cold spot, specifically ground. Transistor CASPLUS allows protection of transistor LV from high voltages and allows the potential at the second terminal of resistor R1 to vary freely according to the current flowing through resistor R1.

[0063] The compensation stage CSTG also includes an operational amplifier AMP3, which has an inverting input connected to the second terminal of resistor R0 and a non-inverting input connected to the second terminal of resistor R1. Operational amplifier AMP3 also has an output connected to the gate of transistor LV to enable control of transistor LV. Therefore, amplifier AMP3 allows the same potential to be obtained at the second terminal of resistor R1 as at the second terminal of resistor R0.

[0064] In this way, resistor R0 is equal to (I set -I vdd The current I is 1 / 100 int Passing through, and resistor R1 is equal to I set -I vdd Current I SMT Pass through.

[0065] Therefore, the current I transmitted by the power supply ALIM VCC Equal to the current I required by the microprocessor CPU vdd The current I transmitted at the second output O2 of the LDO regulator vdd / 100 and the current I corresponding to the current flowing through resistor R0 int and the current I flowing through resistor R1 SMT The sum of the currents I JSCR The sum of the two. Therefore, the current I is expressed by the following formula. VCC :

[0066]

[0067] It has a value of 1.01*I set Current I VCC No longer dependent on the current I required by the microprocessor CPU vdd Therefore, it is constant.

[0068] The advantage of this JSCR compensation circuit is its relative simplicity, while allowing for smoothing of the current drawn from the power supply and reducing the current I required by the microprocessor CPU. vdd Respond to changes.

[0069] Figure 2 An electronic device DIS as described above according to a first embodiment is shown, which allows the generation of current I. src The current source SC is shown.

[0070] In this embodiment, the current source SC includes components for generating current I. src The reference branch BREF and at least one branch BGEN.

[0071] The reference branch includes an NMOS cascode transistor MCREF, and each current generation branch BGEN includes an NMOS cascode transistor MCDAC. Both transistors MCREF and MCDAC have gates configured to receive a fixed voltage vcas5u. The drain MCREF is configured to receive, for example, a reference current I of 5μA. ref .

[0072] The current source SC also includes a current mirror MIR for each current generation branch BGEN. Each current mirror MIR allows a reference current I. ref Multiply so as to obtain an output equal to I at the current source. set / 100 current I srcSpecifically, the generation branch includes an NMOS type transistor MMREF. This MMREF has a drain connected to the source of transistor MCREF, a gate connected to the drain of transistor MCREF, and a source connected to the drain of transistor MSREF in the reference branch. The MSREF also includes a source connected to a cold point (particularly ground) and a gate configured to receive a voltage Vdd!.

[0073] Each current generation branch includes an NMOS transistor MMDAC.<n:0> and NMOS transistor MSDAC<n:0> The transistor MMDAC in each current generation branch.<n:0> A transistor MCDAC has a gate connected to the gate of transistor MMREF and a gate connected to the same current generation branch.<n:0> The source and drain of the transistor, and the MSDAC transistor connected to the same current generation branch.<n:0> The drain and source of the current mirror. Therefore, each current mirror includes a reference branch transistor MMREF and a current generation branch transistor MMDAC.<n:0> .

[0074] MSDAC per transistor<n:0> With the option to receive the selection signal SEL<n:0> The gate of the mirror and the source connected to a cold spot, particularly ground. A selection signal allows various current mirrors (MIRs) to be activated or deactivated.

[0075] Then, the total current consumed by the compensation circuit is equal to the current generated by the current source SC, which is equal to I. set / 100 current I src The current consumed is the sum of the current consumed by operational amplifier AMP_LDO and operational amplifier AMP3. Therefore, the total current consumed is relatively low, which is advantageous, especially for products requiring high power consumption.

[0076] In addition, the bias current of amplifier AMP3 can be increased to improve the performance of compensation circuit JSCR.

[0077] Figure 3 An electronic device DIS as described above, according to a second embodiment, is shown, which allows the generation of an electronic device equal to I. set / 100 current I src The current source SC is shown.

[0078] The second embodiment differs from the first embodiment in that it includes a single common transistor MCDAC for each current generation branch. This MCDAC transistor is controlled by the operational amplifier AMP_CAS, rather than by the signal vcas5u.

[0079] Specifically, the operational amplifier AMP_CAS has a non-inverting input connected to the drain of the transistor MMREF and an inverting input connected to the drain of the transistor MMDAC.

[0080] In this way, the drain voltage of the transistor MMDAC is the same as the drain voltage of the transistor MCREF. Therefore, a smaller transistor MCDAC that allows for reduced parasitic capacitance can be used, making the compensation circuit more responsive to current changes I. vdd The responsiveness is stronger. The amplifier's bandwidth does not affect the compensation circuit because the current I... ref It is constant.

[0081] Then, the total current consumed by the compensation circuit is equal to the current I generated by the current source. set / 100, the sum of the current supplied to operational amplifier AMP_LDO, the current consumed by operational amplifier AMP3, and the current supplied to amplifier AMP_CAS (Iamp_cas). Compared to known compensation circuits, this total current is also relatively low.

[0082] Of course, the present invention is applicable to various variations and modifications that will be conceived by those skilled in the art. For example, an electronic device comprising several LDO voltage regulators and several electronic modules connected to the various voltage regulators can also be provided. The compensation circuit then has several inputs IN1 for the various voltage regulators to receive auxiliary current generated by the various regulators. The current source SC and the compensation stage CSTG are then connected to the various LDO regulators via several parallel branches connected to the inputs IN1, each branch including a transistor PCAS_LDO controlled by the operational amplifier AMP_LDO as described above.

Claims

1. An electronic device comprising: a power supply terminal configured to be connected to a power supply; at least one voltage regulator connected to the power supply terminal; at least one electronic module connected to the at least one voltage regulator and configured to consume an electronic module current from the power supply; and a compensation circuit connected to the at least one voltage regulator and configured to receive an auxiliary current, the auxiliary current being generated by the at least one voltage regulator and being equal to a first portion of the electronic module current consumed by the at least one electronic module, the compensation circuit comprising: a current source connected to the at least one voltage regulator so as to receive the auxiliary current and configured to provide, to a cold spot, a source current greater than a maximum value of the electronic module current consumed by the at least one electronic module; and a compensation stage comprising: a first resistor and a second resistor, both having a first terminal connected to the power supply terminal, the first resistor having a first resistance value equal to a second resistance value of the second resistor multiplied by an inverse of a multiplication factor of the first portion, the first resistor having a second terminal connected to the current source so as to be traversed by an intermediate current equal to a difference between the source current and the auxiliary current; a first transistor having a drain connected to the second terminal of the second resistor and a source connected to the cold spot; and a first operational amplifier configured to control the first transistor and having an inverting input connected to the second terminal of the first resistor and a non-inverting input connected to the second terminal of the second resistor, so that the second resistor is traversed by a complementary current equal to the intermediate current multiplied by the multiplication factor.

2. The device of claim 1, wherein the current source and the compensation stage are connected to the at least one voltage regulator via a second transistor controlled by a second operational amplifier, the second operational amplifier having an inverting input and a non-inverting input, the inverting input being connected to a source of the second transistor; the non-inverting input being configured to receive a voltage delivered by the at least one voltage regulator to the at least one electronic module.

3. The device of claim 1, wherein the compensation stage comprises: a third transistor having a drain connected to the second terminal of the first resistor and a source connected to the current source, so that the second terminal of the first resistor is connected to the current source via the third transistor; and a fourth transistor having a drain connected to the second terminal of the second resistor and a source connected to the drain of the first transistor, so that the second terminal of the second resistor is connected to the drain of the first transistor via the fourth transistor; the third transistor and the fourth transistor both having a gate configured to receive a fixed voltage allowing the third transistor and the fourth transistor to operate as common-source common-gate. ​ 4. The apparatus of claim 1, wherein the current source comprises at least one current mirror configured to generate the source current from a reference current.

5. The apparatus of claim 4, wherein the current source comprises: a reference leg comprising: a reference transistor of the at least one current mirror; a first cascode transistor having a drain configured to receive the reference current and connected to a gate of the reference transistor, a source connected to a drain of the reference transistor, and a gate configured to receive a fixed voltage; and a first select transistor having a drain connected to a source of the reference transistor, a source connected to the cold spot, and a gate configured to receive a voltage delivered to the at least one electronic module by the at least one voltage regulator; an auxiliary current generation leg for each current mirror comprising: a replica transistor of the current mirror having a gate connected to a gate of the reference transistor and configured to at least partially generate the source current; a second cascode transistor having a drain connected to a second output of the at least one voltage regulator and a source connected to a drain of the replica transistor; and a second select transistor having a drain connected to a source of the replica transistor and a source connected to the cold spot.

6. The apparatus of claim 5, wherein the second select transistor of the auxiliary current generation leg of each current mirror has a gate configured to be controlled by a select signal.

7. The apparatus of claim 5, wherein the second cascode transistor is common to each generation leg, the current source further comprising a third operational amplifier having a non-inverting input connected to the drain of the reference transistor, an inverting input connected to the source of the common second cascode transistor, and an output connected to the gate of the second cascode transistor.

8. An electronic apparatus comprising: a power supply terminal configured to be connected to a power supply; at least one voltage regulator connected to the power supply terminal; at least one electronic module connected to the at least one voltage regulator and configured to consume an electronic module current from the power supply; and a compensation circuit connected to the at least one voltage regulator and configured to receive an auxiliary current, the auxiliary current being generated by the at least one voltage regulator and equal to a first portion of the electronic module current consumed by the at least one electronic module, the compensation circuit comprising: a current source connected to the at least one voltage regulator so as to receive the auxiliary current and configured to provide a source current to a cold spot greater than a maximum of the electronic module current consumed by the at least one electronic module, wherein the current source comprises: at least one current mirror configured to generate the source current from a reference current; a reference leg; and an auxiliary current generation leg for each current mirror; and a compensation stage comprising: ​ a first resistor and a second resistor, both having a first terminal connected to the power supply terminal, the first resistor having a first resistance value equal to a second resistance value of the second resistor multiplied by an inverse of a multiplication factor of the first fraction, the first resistor having a second terminal connected to the current source so as to be traversed by an intermediate current equal to a difference between the source current and the auxiliary current; a first transistor having a drain connected to the second terminal of the second resistor and a source connected to the cold junction; and a first operational amplifier configured to control the first transistor and having an inverting input connected to the second terminal of the first resistor and a non-inverting input connected to the second terminal of the second resistor, so that the the second resistor being traversed by a complementary current equal to the intermediate current multiplied by the multiplication factor.

9. The device of claim 8, wherein the current source and the compensation stage are connected to the at least one voltage regulator via a second transistor controlled by a second operational amplifier, the second operational amplifier having an inverting input and a non-inverting input, the inverting input being connected to a source of the second transistor, the non-inverting input being configured to receive a voltage delivered by the at least one voltage regulator to the at least one electronic module.

10. The device of claim 9, wherein the compensation stage comprises: a third transistor having a drain connected to the second terminal of the first resistor and a source connected to the current source, so that the second terminal of the first resistor is connected to the current source via the third transistor; and a fourth transistor having a drain connected to the second terminal of the second resistor and a source connected to the drain of the first transistor, so that the second terminal of the second resistor is connected to the drain of the first transistor via the fourth transistor; the third transistor and the fourth transistor both having a gate configured to receive a fixed voltage allowing the third transistor and the fourth transistor to operate as common-source common-gate.

11. The device of claim 8, wherein the compensation stage comprises: a third transistor having a drain connected to the second terminal of the first resistor and a source connected to the current source, so that the second terminal of the first resistor is connected to the current source via the third transistor; and a fourth transistor having a drain connected to the second terminal of the second resistor and a source connected to the drain of the first transistor, so that the second terminal of the second resistor is connected to the drain of the first transistor via the fourth transistor; the third transistor and the fourth transistor both having a gate configured to receive a fixed voltage allowing the third transistor and the fourth transistor to operate as common-source common-gate.

12. The device of claim 8, wherein the reference branch comprises: a reference transistor of the at least one current mirror; ​ ​ a first cascode transistor having: a drain configured to receive the reference current and connected to a gate of the reference transistor; a source connected to a drain of the reference transistor; and a gate configured to receive a fixed voltage; and a first selection transistor having: a drain connected to the source of the reference transistor; a source connected to the cold spot; and a gate configured to receive a voltage delivered by the at least one voltage regulator to the at least one electronic module.

13. The apparatus of claim 12, wherein each auxiliary current generation leg comprises: a replica transistor of the current mirror having a gate connected to the reference leg and configured to at least partially generate the source current; a second cascode transistor having: a drain connected to a second output of the at least one voltage regulator; and a source connected to a drain of the replica transistor; and a second selection transistor having: a drain connected to a source of the replica transistor; 14. The apparatus of claim 13, wherein the second cascode transistor pair is common to each generation branch, the current source further comprising a third operational amplifier, the third operational amplifier having a non-inverting input connected to the drain of the reference transistor; a source connected to the cold spot; and a gate configured to be controlled by a selection signal. an inverting input connected to the source of the second cascode transistor common to the legs; and an output connected to the gate of the second cascode transistor.

15. An electronic apparatus comprising: a power supply terminal configured to be connected to a power supply; at least one voltage regulator connected to the power supply terminal; at least one electronic module connected to the at least one voltage regulator; and a compensation circuit connected to the at least one voltage regulator, the compensation circuit comprising: a current source connected to the at least one voltage regulator; and a compensation stage comprising: a first resistor and a second resistor each having a first terminal connected to the power supply terminal, wherein the first resistor has a second terminal connected to the current source; a first transistor having a drain connected to the second terminal of the second resistor and a source connected to a cold spot; a first operational amplifier having: an inverting input connected to the second terminal of the first resistor; a non-inverting input connected to the second terminal of the second resistor; and an output connected to a gate of the first transistor; a second transistor connecting the current source and the compensation stage to the at least one voltage regulator; and a second operational amplifier having: an output coupled to a gate of the second transistor; an inverting input connected to a source of the second transistor; and a non-inverting input configured to receive a voltage delivered by the at least one voltage regulator to the at least one electronic module.

16. The apparatus of claim 15, wherein the compensation stage comprises: a third transistor having a drain connected to the second terminal of the first resistor and a source connected to the current source, such that the second terminal of the first resistor is connected to the current source via the third transistor; and a fourth transistor having a drain connected to the second terminal of the second resistor and a source connected to the cold spot. a fourth transistor having a drain connected to the second terminal of the second resistor and a source connected to the drain of the first transistor, such that the second terminal of the second resistor is connected to the drain of the first transistor via the fourth transistor.

17. The apparatus of claim 15, wherein the current source comprises at least one current mirror configured to generate a source current from a reference current.

18. The apparatus of claim 17, wherein the current source comprises: a reference branch comprising: a reference transistor of the at least one current mirror; a first cascode transistor having a drain configured to receive the reference current and connected to a gate of the reference transistor, a source connected to a drain of the reference transistor, and a gate configured to receive a fixed voltage; and a first select transistor having a drain connected to a source of the reference transistor, a source connected to the cold spot, and a gate configured to receive a voltage delivered to the at least one electronic module by the at least one voltage regulator; for each current mirror, an auxiliary current generation branch comprising: a replica transistor of the current mirror having a gate connected to a gate of the reference transistor and configured to at least partially generate the source current; a second cascode transistor having a drain connected to a second output of the at least one voltage regulator and a source connected to a drain of the replica transistor; and a second select transistor having a drain connected to a source of the replica transistor and a source connected to the cold spot.

19. The apparatus of claim 18, wherein the second select transistor of the auxiliary current generation branch of each current mirror has a gate configured to be controlled by a select signal.

20. The apparatus of claim 18, wherein the second common-source common-gate transistor pair is common to each generation branch, the current source further comprising a third operational amplifier, the third operational amplifier having: a non-inverting input connected to the drain of the reference transistor; an inverting input connected to the source of the second cascode transistor common to the at least one voltage regulator; and an output connected to the gate of the second cascode transistor.

Images