Method for analyzing combined schedulability of integrated avionics system

Abstract

The application discloses a kind of combination schedulability analysis methods for integrated avionics system, comprising: using AADL, extension partition attribute set and resource attribute set, obtain the architecture model for integrated modular avionics system;The instantiation file aaxl2 is generated by instantiation to architecture model;By parsing and traversing instantiation file aaxl2, obtain the software and hardware information of integrated modular avionics system described by AADL;According to the mapping relationship between AADL and Cheddar ADL, the software and hardware information of integrated modular avionics system described by AADL is mapped to the software and hardware part in Cheddar ADL model, and Cheddar ADL model is obtained;In UPPAAL, the task scheduling strategy of extended time automaton modeling is utilized, and XML file is obtained;By parsing XML file, the task scheduling strategy described by extended time automaton is converted into sc script file;In cheddar, sc script file is called, and Cheddar ADL model is simulated, and the schedulability analysis result of integrated modular avionics system is obtained.

Description

Technical Field

[0001] This invention belongs to the field of requirements engineering for safety-critical software, and specifically relates to a method for combinatorial schedulability analysis of integrated avionics systems. Background Technology

[0002] A safety-critical system is a system whose failure would threaten human life, cause significant property damage, or severely harm the surrounding environment. Common safety-critical systems include flight control systems, aerospace vehicles, nuclear reactor monitoring systems, and critical care patient monitoring systems. Safety-critical software, as a component of a safety-critical system, directly or indirectly leads to a hazardous state if it fails. Therefore, safety, reliability, and real-time performance are fundamental requirements for these systems and software. Avionics systems fall under the category of safety-critical systems.

[0003] With the rapid development of information technology, microelectronics, and multimedia services, and the increasing complexity of the airspace environment, aircraft are placing increasing demands on and dependence on avionics systems. To meet the ever-complexing mission requirements of aircraft, the interaction between modules within Integrated Modular Avionics (IMA) systems has surged. However, with the widespread application of increasingly sophisticated interactive entertainment systems and more convenient service systems in new aircraft, the dramatic increase in the number of tasks within avionics systems poses a significant threat to their safety. Therefore, avionics systems are demanding higher levels of real-time performance and reliability.

[0004] For avionics systems, considering each scheduled execution entity (such as processes, partitions, and messages) within the system, if its maximum response time does not exceed its deadline, the system is considered schedulable. The analytical process for determining system schedulability is called schedulability analysis, which is the core of avionics system timing correctness verification and forms the basis for the reliability of avionics system timing operations. The ARINC 653 specification is a real-time operating system standard developed by the American Aeronautical Electronics Engineering Committee (AAEEC). It defines the behavioral logic of the operating system and the interface specifications for applications under the IMA architecture. To ensure the safe execution of various avionics functions, the ARINC 653 specification introduces the concept of partitions. Each partition contains an independent address space, context data, and real-time tasks; erroneous behavior in one partition cannot affect other partitions. The operating system divides time windows for each partition according to their different needs. Each partition will receive one or more time windows, referred to as time slices. Through extensive and in-depth research by many scholars, a mature two-level scheduling model has been formed in the IMA system: interval scheduling and intra-partition scheduling.

[0005] Current research has explored the use of AADL extended modeling and Cheddar simulation analysis for schedulability analysis of IMA systems. However, studies using AADL for IMA modeling haven't considered how to map partition modules with configured time attributes to Cheddar ADL and perform schedulability analysis after obtaining partition modules with task scheduling tables provided by different vendors. Furthermore, similar studies lack comprehensive analysis of resource constraints. Most research cases also consider traditional scheduling strategies, while in practice, it's necessary to solve for constraints related to task requirements and processor resources to derive custom scheduling algorithms. Therefore, the conversion of custom scheduling algorithms and the integration of tools can significantly improve the reliability and efficiency of model analysis. Summary of the Invention

[0006] Purpose of the invention: To address the problem of how to map partition modules with configured time attributes to Cheddar ADL and perform schedulability analysis, this invention proposes a method for combinatorial schedulability analysis of avionics systems, ensuring the real-time performance and reliability of avionics systems under complex task interaction scenarios.

[0007] Technical solution: A method for analyzing the combinatorial schedulability of integrated avionics systems, comprising the following steps:

[0008] Step 1: Using the attribute set of AADL, create a layered architecture model for integrated modular avionics systems; and using the appendix extension capability of AADL, extend the partition attribute set and resource attribute set of the layered architecture model for integrated modular avionics systems to obtain the architecture model for integrated modular avionics systems.

[0009] Step 2: Instantiate the architecture model obtained in Step 1 to generate an instantiation file aaxl2; by parsing and traversing the instantiation file aaxl2, obtain the hardware and software information of the integrated modular avionics system described by AADL.

[0010] Step 3: Based on the mapping relationship between AADL and Cheddar ADL, map the hardware and software information of the integrated modular avionics system described by AADL to the hardware and software parts in the Cheddar ADL model to obtain the Cheddar ADL model.

[0011] Step 4: By analyzing the specific parameters provided by the processor, partitions, and tasks of the integrated modular avionics system, the task scheduling strategy of the integrated modular avionics system is obtained. The task scheduling strategy is modeled in UPPAAL using an extended time automaton to obtain an XML file.

[0012] Step 5: Convert the task scheduling strategy described by the extended time automaton into an sc script file by parsing the XML file;

[0013] Step 6: In cheddar, call the sc script file to perform scheduling simulation on the Cheddar ADL model and obtain the scheduling analysis results of the integrated modular avionics system.

[0014] Furthermore, in step 1, the use of AADL's accessory extension capabilities to extend the partition attribute set and resource attribute set of the hierarchical architecture model for integrated modular avionics systems specifically includes: extending the partition attribute set according to the partition's acquisition of processor resources on the processor and the partition attribute configuration supported by Cheddar.

[0015] Based on the ARINC653 standard attribute set and resource constraints provided by AADL, the resource attribute set is expanded.

[0016] Furthermore, in step 3, the mapping relationship between AADL and Cheddar ADL is used to map the hardware and software information of the integrated modular avionics system described in AADL to the hardware and software parts in the Cheddar ADL model, thus obtaining the Cheddar ADL model. This specifically includes:

[0017] The integrated modular avionics system described in the AADL includes hardware and software information such as component information, attribute information, and binding relationships between components.

[0018] When partitions and tasks are scheduled hierarchically, the processor's scheduling policy is defined as hierarchical offline scheduling. The Supported_Scheduling_Protocols attribute in AADL is extended to configure the scheduling policies supported by the current component. Setting the processor's scheduling policy attribute to Schedule_Protocol => Hierarchical_Offline_Protocol indicates that the current processor adopts a hierarchical offline scheduling policy. Partition attributes are configured using the partition attribute set, and task attributes are configured using the Thread_Properties and Timing_Properties attribute sets. Simultaneously, resource allocation is defined within the partition using the Resource_Properties::critical_section attribute set. The hardware and software information of the integrated modular avionics system described in AADL is obtained, the component category is determined, and component mapping is performed according to the AADL-Cheddar ADL component mapping relationship to obtain the component. Attribute information and dependencies within the component are obtained, and attribute mapping is performed according to the AADL-Cheddar ADL attribute mapping relationship to obtain the component attributes. Finally, the partition and processor information bound to the current component is obtained, dependencies are generated, and the Cheddar ADL model is obtained.

[0019] When treating partitions as black boxes and only considering the scheduling of multiple partitions on the processor, there is no need to configure scheduling attributes. Instead, partition attributes are configured using the partition attribute set. Resource information attributes are defined in the parent component of the partition and mapped according to the mapping relationship between AADL and CheddarADL components to obtain the Cheddar ADL model.

[0020] Furthermore, the mapping relationship between AADL and Cheddar ADL components includes: Processor in AADL corresponds to Core & Processor in Cheddar ADL, Process / Thread Group in AADL corresponds to Address in Cheddar ADL, Thread in AADL corresponds to Task in Cheddar ADL, Data in AADL corresponds to Resource in Cheddar ADL, and Connection in AADL corresponds to Dependency in Cheddar ADL.

[0021] The mapping relationship between AADL and Cheddar ADL attributes includes: AADL's Scheduling_Protocol corresponds to Cheddar ADL's Scheduler Type; AADL's Preemptive_Scheduler corresponds to Cheddar ADL's Preemptive Type; AADL's Compute_Execution_Time / Execution_Time corresponds to Cheddar ADL's Capacity; AADL's Priority corresponds to Cheddar ADL's Priority; AADL's Deadline corresponds to Cheddar ADL's Deadline; AADL's Period corresponds to Cheddar ADL's Period; AADL's Dispatch_Absolute_Time corresponds to Cheddar ADL's Start Time; AADL's Dispatch_Protocol corresponds to Cheddar ADL's Task Type; AADL's Critical_Section corresponds to Cheddar ADL's Critical Section; AADL's Data_Concurrency_State corresponds to Cheddar ADL's State; and AADL's Concurrency_Control_Protocol corresponds to Cheddar ADL's Protocol.

[0022] Furthermore, the step of obtaining the partition and processor information bound to the current component and generating dependencies includes:

[0023] By indexing the two-level parent components, the bound virtual processor is obtained, and the partition component is bound to the virtual processor;

[0024] By indexing the first-level parent component, the bound partition address is obtained, and the task and resource components are bound to the partition address.

[0025] Furthermore, the attribute definitions of the resource information are located in the parent component of the partition and mapped according to the mapping relationship between AADL and CheddarADL components, including:

[0026] In the mapping relationship between AADL and Cheddar ADL components, the partition component process / thread group in AADL corresponds to the task component task in Cheddar ADL;

[0027] During the code conversion process, a partition component (address) is automatically generated, and the task is bound to the automatically generated address component.

[0028] Furthermore, in step 5, the process of converting the task scheduling strategy described by the extended time automaton into an sc script file by parsing the XML file includes:

[0029] Based on the code declaration, syntax rules, and grammar file editing syntax rules provided by the UPPAAL model, generate Lexer and Parser;

[0030] The XML file is parsed using the API provided by UPPAAL to obtain System information, Template information, and Declaration information; then, the generated Lexer and Parser are used to construct a parse tree; the System information includes instantiation information; the Template information includes specific parameter information of the thread time automaton and the scheduling policy time automaton; the Declaration information includes the thread structure, relevant variables required for scheduling, and declarations of predefined functions;

[0031] By using the Listener and Visitor provided by ANTLR4 to access the parse tree, relevant information about the task scheduling strategy described by the extended time automaton is obtained. XPath is used to identify the node set of the parse tree, and tree pattern matching is combined to generate an sc script file.

[0032] Furthermore, the generation of Lexer and Parser based on the code declaration, syntax rules, and grammar file editing syntax rules provided by the UPPAAL model official documentation includes:

[0033] Edit the C.g4 file provided by the official antlr4 website according to the code declaration and syntax rules of the UPPAAL model to obtain the UPPAAL.g4 file. Then, generate the Lexer and Parser in antlr4 based on UPPAAL.g4.

[0034] Furthermore, the step of using the Listener and Visitor provided by ANTLR4 to access the parse tree to obtain relevant information about the task scheduling strategy described by the extended temporal automaton, using XPath to identify the node set of the parse tree, and combining tree pattern matching to generate an sc script file specifically includes:

[0035] Use Listener to access the root node content of System, Template, and Declaration information in an XML file; use Visitor to access the child node content of the node to be retrieved.

[0036] Traverse all child nodes and perform matching in the parse tree. If a match is successful, map the content of the current node into an sc file format and write it out; if not, match the next type of node.

[0037] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0038] (1) This invention reads the instantiation file aaxl2 of the integrated modular avionics system and automatically generates Cheddar ADL code based on the mapping relationship between AADL and Cheddar ADL. This invention adds the mapping of partition attributes and resource attributes to the original mapping relationship between AADL and Cheddar ADL, and considers the binding of virtual processors and partitions, which makes up for the shortcomings of Cheddar in graphical modeling and improves modeling efficiency. Moreover, the use of AADL to expand the attribute set can model the system requirements in more detail.

[0039] (2) The present invention utilizes the UPPAAL time automaton to model the task scheduling strategy of the integrated modular avionics system. This method can verify the feasibility of the strategy in the early stage of modeling. The automatically generated sc script file after parsing can be used as the script file for the custom scheduling strategy in Cheddar, which solves the difficulty of manually writing sc files. This makes it easier to use the scheduling strategy in Cheddar to analyze the schedulability of the integrated modular avionics system and improve the safety and reliability of the integrated modular avionics system. All of the above transformations can be integrated into OSATE, providing an efficient integration tool for early system safety verification based on the model-driven development method. Attached Figure Description

[0040] Figure 1 A modular architecture diagram for a combined schedulability analysis method for integrated avionics systems;

[0041] Figure 2 This is a diagram of the structure of the instantiation file aaxl2 for integrated modular avionics systems.

[0042] Figure 3 Flowchart for converting AADL model components to Cheddar ADL model components;

[0043] Figure 4 Flowchart for pattern matching transformation sc script file. Detailed Implementation

[0044] The objects and functions of the present invention, as well as the methods for achieving these objects and functions, will be clarified by referring to exemplary embodiments. However, the present invention is not limited to the exemplary embodiments disclosed below; it can be implemented in various forms. The purpose of this specification is merely to help those skilled in the art to comprehensively understand the specific details of the invention.

[0045] Embodiments of the present invention will now be described with reference to the accompanying drawings.

[0046] like Figure 1 As shown, this embodiment discloses a method for combinatorial schedulability analysis of integrated avionics systems, including the following steps:

[0047] Step 1: Based on the requirements, model parameters, and the ARINC 653 standard attribute set provided by AADL, create a layered architecture model for integrated modular avionics systems. The ARINC 653 standard provides a specific plan for avionics system modeling, but considering the actual situation, the description of some attributes is not perfect. This embodiment utilizes AADL's powerful attribute set and appendix extension capabilities to extend the partition attribute set and resource attribute set describing resource constraints in the layered architecture model of integrated modular avionics systems in OSATE, describing the allocation and binding of resources in partitions and the system, thereby creating an architecture model for integrated modular avionics systems based on resource constraints.

[0048] Specifically, in this step, based on the partition's acquisition of processor resources on the processor and the partition attribute configuration supported by Cheddar, the partition attribute set Partition_Properties is expanded. This includes the partition execution time Execution_Time applies to(thread,process), where apply to indicates the components to which the current attribute is applicable; the time when the partition first acquires resources Dispatch_Absolute_Time applies to(thread,process); and whether the scheduling within and between partitions supports preemption Preemptive_type applies to(process,processor).

[0049] Specifically, in this step, based on the ARINC653 standard and resource constraints, the resource attribute set Resource_Properties is expanded, including resource size Resource_Size applies to(data) and resource allocation Critical_Section applies to(system,process,thread).

[0050] Step 2: Instantiate the architecture model obtained in Step 1 to generate an instantiation file aaxl2; the structure of the instantiation file aaxl2 is as follows. Figure 2 In line with the hierarchical modeling structure of the integrated modular avionics system, SystemInstance is the instantiation of the entire system. It stores the hardware and software information of the entire system in a tree structure. Processor defines processor resources, Process / Thread Group defines partition components, and Data defines resource components. According to the modeling requirements of the integrated modular avionics system, partitioning is a concept of temporal and spatial isolation. When each partition is bound to a processor, it should be bound to a separate virtual processor. Therefore, Processor contains the sub-component VirtualProcessor. Property defines the component's attribute categories, and value stores the parameter values ​​of the corresponding attributes. Each partition contains specific task threads and the resource data that the task needs to access. Inter-partition communication also requires access to resources; therefore, there is resource data at the same level as the partition.

[0051] The instantiated file aaxl2 is read using the API provided by osata.aadl2. By parsing and traversing the instantiated file aaxl2, the hardware and software information of the integrated modular avionics system described by AADL is obtained. This hardware and software information includes component information, attribute information, and binding relationships between components.

[0052] Step 3: The schedulability analysis in this embodiment combines the model code with the custom scheduling algorithm code and uses the simulation analysis function provided by Cheddar to analyze the schedulability of the system. Therefore, it is considered in two parts. The first part is about the mapping of the model code from AADL to Cheddar ADL.

[0053] By utilizing the mapping relationship between AADL code and Cheddar ADL code, the hardware and software information of the integrated modular avionics system described by AADL is mapped to the hardware and software parts in the Cheddar ADL model, and written into an xmlv3 file to obtain the Cheddar ADL model.

[0054] In this step, the mapping relationship between AADL code and Cheddar ADL code includes: mapping of scheduling attributes, mapping of partition attributes, mapping of resource attributes, and the original mapping relationship between AADL code and Cheddar ADL code. The original mapping relationship between AADL code and Cheddar ADL code includes: component mapping and component attribute mapping.

[0055] In this step, the hardware and software information of the integrated modular avionics system described in AADL is mapped to the hardware and software components in the Cheddar ADL model. This mainly includes two parts:

[0056] When considering hierarchical scheduling of partitions and tasks, partitions are treated as time- and space-isolated modules. One scheduling strategy is used between partitions, and a different strategy is used for tasks within a partition. Therefore, in hierarchical scheduling, the processor's scheduling strategy is defined as hierarchical offline scheduling, and the processor's scheduling strategy attribute is set to `Scheduling_Protocol => Hierarchical_Offline_Protocol`. In AADL, the `Supported_Scheduling_Protocols` attribute is extended to set the scheduling strategy within a partition. Partition attributes are configured using the `Partition_Properties` attribute set, and task attributes are configured using the `Thread_Properties` and `Timing_Properties` attribute sets. Simultaneously, within the partition, `Resource_Properties` is used... The `routerties::critical_section` defines resource allocation; it uses `osate.aadl2.instance` to obtain the hardware and software information of the integrated modular avionics system described in AADL, determines the component category, and maps the components according to the mapping relationship in Table 1. After obtaining the components, it obtains the attribute information and dependencies within the components and maps the attributes according to the mapping relationship in Table 2. After obtaining the component attributes, it generates the corresponding component attributes; at the same time, it is necessary to obtain the partition and processor information bound to the current component in order to generate dependencies. However, in the architecture model for integrated modular avionics systems modeled according to the ARINC653 standard, partition components are required to be bound to virtual processors in the processor. Therefore, when a partition component obtains the bound processor, it needs to index two levels of parent components, while task and resource components only need to index one level to obtain the address of the currently bound partition.

[0057] Table 1 Mapping relationship between AADL and Cheddar ADL components

[0058] AADL Cheddar ADL Processor Core & Processor Process / Thread Group Address Thread Task Data Resource Connection Dependency

[0059] Table 2 Mapping Relationship between AADL and Cheddar ADL Attributes

[0060]

[0061]

[0062] When a pre-configured partition task is obtained from the vendor, the partition is treated as a black box, and only the scheduling of multiple partitions on the processor is considered. Therefore, when the partition is considered as a black box, there is no need to configure scheduling properties when modeling the processor. Similarly, partition properties are configured using Partition_Properties, while the resource information properties are defined in the parent component of the partition. At this time, the partition component process / thread group in Table 1 should be mapped to the task component task in Cheddar ADL. At the same time, the partition component address is automatically generated during the code conversion process, and the mapped task is bound to the automatically generated address. Finally, the conversion code is written into xmlv3.

[0063] Using mapping relationships, as follows Figure 3 The model conversion method shown includes the following specific steps:

[0064] S310: Obtain the instantiated file aaxl2, and parse it using the API osate.aadl2 provided by OSATE, that is, obtain the root node through the getSystemInstance() interface;

[0065] S320: The getAllComponentInstances() interface retrieves all child components and stores them in the component list Component;

[0066] S330: Iterate through the list Component and get the component type getCategory();

[0067] S340: Determine whether the current component belongs to a certain type. For example, in the figure, take partition as an example. Determine whether the current component is a partition component Process. If yes, jump to S350; otherwise, return to S330.

[0068] S350: Calls cheddar_v3.2.jar to create a partition object Address_Space;

[0069] S360: Retrieve the values ​​of partition attributes defined in the integrated modular avionics system from the Component and write them as strings into the attribute field corresponding to the partition Address_Space;

[0070] S370: Create a new text object document, write the string from S360 into document, then iterate through all types of components and get their attribute values, write them into document, then create a new xmlv3 file, write the text content into the file, and the process ends.

[0071] Step 4: By analyzing the specific parameters provided by the processor, partitions and tasks of the integrated modular avionics system, the task scheduling strategy of the integrated modular avionics system can be obtained by using constraint solving. The task scheduling strategy is modeled in UPPAAL using extended time automata. Considering the standard format of scheduling algorithms in Cheddar, the corresponding identifiers and predefined functions are declared in UPPAAL to generate an XML file.

[0072] Step 5: Use the API model.core2 provided by UPPAAL to parse the XML file and convert the task scheduling strategy described by the extended time automaton into an sc script file; specific operations include:

[0073] Referring to the syntax rules provided by the official UPPAAL documentation, it can be seen that the syntax rules for system declarations, parameter definitions, and system definitions in UPPAAL are similar to those in C. Therefore, we first obtain the C.g4 file from the antlr4 official documentation. Then, according to the syntax rules provided by UPPAAL and the declaration rules for custom scheduling algorithms in Cheddar, we modify C.g4. For example, UPPAAL does not support declaring variables in the forCondition clause of a for statement. Therefore, according to the UPPAAL syntax rules, we modify "'forCondition:(forDeclaration|expression?)';'forExpression?';'forExpression?;'" in C.g4 to "'forCondition:expression';'forExpression';'forExpression;'", removing the variable declaration statement forDeclaration.

[0074] Simultaneously, modeling in UPPAAL requires considering the standard scheduling policy format specified by Cheddar and deterministic predefined functions. For example, the user-defined scheduler in Cheddar specifies the following four parts: The start section defines initial variables, The priority section calculates priorities, The election section selects the task to receive processor resources, and The task activation section activates the task. The first part uses custom identifiers `@start_section`...`@end_section` during modeling, while the other three parts are declared as functions in the code. Therefore, it is necessary to add `"StartSection:'@start_section';EndSection:'@end_section';"` to the g4 file to parse the identifiers `@start_section` and `@end_section` declared in the XML file. The modified grammar file is then saved as UPPAAL.g4. Antlr4 is then used to generate the Lexer and Parser.

[0075] The XML file contains three parts: System, Template, and Declaration. System defines the system model, which consists of one or more concurrent procedures, local and global variables, and channels. Template defines a time automaton used to test and update clocks, variables, record types, and call user-defined functions. Declaration contains global and local declarations used to define information such as clocks, channels, arrays, records, and predefined functions. The XML file model.core2 provided by UPPAAL is parsed as follows: The first part uses the API to obtain the contents of the System and Template sections. Specifically, getTemplate() is used to obtain Template information and getPropertyValue("system") is used to obtain System information. In other words, the instantiation information of the model definition is obtained from System, and the specific parameter information of the thread time automaton and the scheduling policy time automaton is obtained from Template. Then, the generated Lexer and Parser are used to analyze and generate a parse tree. The second part uses the API to obtain the contents of the Declaration section. Specifically, getPropertyValue("declaration") is used to obtain Declaration information. In other words, the thread structure, relevant variables required for scheduling, and declarations of predefined functions are obtained from Declaration. Similarly, the generated Lexer and Parser are used to analyze and generate a parse tree. In other words, the Lexer and Parser parse the information of each part and construct a parse tree to achieve code conversion.

[0076] Using the Listener and Visitor provided by ANTLR4, we can access the parse tree constructed by Lexer and Parser. Specifically, the Listener automatically accesses all nodes using a depth-first traversal, while the Visitor can access the subtree of the node that needs to be obtained. Therefore, we can use the Listener to obtain the root node content of the three main parts of the XML, and use the Visitor to access the content of specific child nodes, thereby obtaining relevant information about the task scheduling strategy.

[0077] Both Listener and Visitor access use Xpath.findALL to find the path, traverse all child nodes, use Parsetreepattern to mark the required child nodes, and use match to perform the matching. If the match is successful, the content of the current node is mapped to sc file format and written out. If the match is unsuccessful, the current node does not exist in the model, so the next type of node is matched.

[0078] like Figure 4As shown, the specific steps for accessing the parse tree and converting the code are as follows:

[0079] S510: Access the parse tree using the Visitor provided by antlr4;

[0080] S520: Use XPath to access a path node and obtain a subset of the parse tree to be processed. For example, taking " / statement / *" as an example, find all child nodes of the path "statement" in the parse tree.

[0081] S530: Store the byte points obtained by XPath in ParseTree and iterate through them;

[0082] S540: Determine whether a child node belongs to a certain type of declaration statement. For example, the selection statement is shown in the figure. If it belongs, jump to S550; otherwise, return to S530.

[0083] S550: Use ParseTreePattern to provide the label information of the current node, such as the if...else... declaration statement "if( <expression> ) <statement>else <statement>",in" <expression>"The expression to be evaluated is followed by the statement to be executed if the evaluation is successful, and else is followed by the statement to be executed if the evaluation fails."

[0084] S560: Based on the tree pattern given in S550, perform matching in the parse tree. If the match is successful, jump to S570. If the match is unsuccessful, it means that the current pattern statement does not exist. Then return to S520 to revisit the path node and match other statements.

[0085] S570: If a statement declaration given by ParseTreePattern is matched, use the getText() interface to retrieve the text from the declaration statement. <expression>The value is stored as a string structure;

[0086] S580: Convert the successfully matched statements above into statements according to the syntax rules specified by sc. At the same time, create a new text object and write the converted statements and the variable expressions obtained in S570 into the text object.

[0087] S590: Create an sc file, write the text content into the file for storage, generate a script file, and then the process ends.

[0088] Step 6: Cheddar provides traditional scheduling strategies, but in practical applications, task and partition scheduling needs to consider actual resource allocation. Start Cheddar from the OSATE tool and automatically import the xmlv3 file. If the Processor defines the attribute Schedule_Protocol => Hierarchical_Offline_Protocol describing the hierarchical scheduling strategy, then consider two-level scheduling analysis for tasks and processes. Therefore, define the scheduling attribute as a user-defined strategy in the Address Space, i.e., Scheduler_Type => Pipeline User Defined Protocol, and import the sc file. If the processor does not define a Schedule_Protocol attribute value, then define the scheduling attribute as a user-defined strategy in the Cheddar ADL component core, i.e., Scheduler_Type => Pipeline User Defined Protocol, and import the sc file. The schedulability results of the integrated modular navigation system with the custom scheduling strategy can then be analyzed.< / expression> < / expression> < / statement> < / statement> < / expression>

Claims

1. A method for analyzing the combinatorial schedulability of integrated avionics systems, characterized by: The steps include: Step 1: Using the attribute set of AADL, create a layered architecture model for integrated modular avionics systems; and using the appendix extension capability of AADL, extend the partition attribute set and resource attribute set of the layered architecture model for integrated modular avionics systems to obtain the architecture model for integrated modular avionics systems. Step 2: Instantiate the architecture model obtained in Step 1 to generate an instantiation file aaxl2; by parsing and traversing the instantiation file aaxl2, obtain the hardware and software information of the integrated modular avionics system described by AADL. Step 3: Based on the mapping relationship between AADL and Cheddar ADL, map the hardware and software information of the integrated modular avionics system described by AADL to the hardware and software parts in the Cheddar ADL model to obtain the Cheddar ADL model. Step 4: By analyzing the specific parameters provided by the processor, partitions, and tasks of the integrated modular avionics system, the task scheduling strategy of the integrated modular avionics system is obtained. The task scheduling strategy is modeled in UPPAAL using an extended time automaton to obtain an XML file. Step 5: Convert the task scheduling strategy described by the extended time automaton into an sc script file by parsing the XML file; Step 6: In cheddar, call the sc script file to perform scheduling simulation on the Cheddar ADL model and obtain the scheduling analysis results of the integrated modular avionics system.

2. The method for combinatorial schedulability analysis of integrated avionics systems according to claim 1, characterized in that: In step 1, the step of using AADL's attachment extension capabilities to extend the partition attribute set and resource attribute set of the hierarchical architecture model for integrated modular avionics systems specifically includes: extending the partition attribute set according to the partition's acquisition of processor resources on the processor and the partition attribute configuration supported by Cheddar. Based on the ARINC653 standard attribute set and resource constraints provided by AADL, the resource attribute set is expanded.

3. The method for combinatorial schedulability analysis of integrated avionics systems according to claim 1, characterized in that: In step 3, the mapping relationship between AADL and Cheddar ADL is used to map the hardware and software information of the integrated modular avionics system described in AADL to the hardware and software parts in the Cheddar ADL model, thus obtaining the Cheddar ADL model. This specifically includes: The integrated modular avionics system described in the AADL includes hardware and software information such as component information, attribute information, and binding relationships between components. When partitions and tasks are scheduled hierarchically, the processor's scheduling policy is defined as hierarchical offline scheduling. The Supported_Scheduling_Protocols attribute in AADL is extended to configure the scheduling policies supported by the current component. Setting the processor's scheduling policy attribute to Schedule_Protocol => Hierarchical_Offline_Protocol indicates that the current processor adopts a hierarchical offline scheduling policy. Partition attributes are configured using the partition attribute set, and task attributes are configured using the Thread_Properties and Timing_Properties attribute sets. Simultaneously, resource allocation is defined within the partition using the Resource_Properties::critical_section attribute set. The hardware and software information of the integrated modular avionics system described in AADL is obtained, the component category is determined, and components are mapped according to the AADL-Cheddar ADL component mapping relationship to obtain the components. Attribute information and dependencies within the components are obtained, and attribute mapping is performed according to the AADL-Cheddar ADL attribute mapping relationship to obtain the component attributes. The partition and processor information bound to the current component are obtained, dependencies are generated, and the Cheddar ADL model is obtained. When treating partitions as black boxes and only considering the scheduling of multiple partitions on the processor, there is no need to configure scheduling attributes. Instead, partition attributes are configured using the partition attribute set. Resource information attributes are defined in the parent component of the partition and mapped according to the mapping relationship between AADL and Cheddar ADL components to obtain the Cheddar ADL model.

4. The method for combinatorial schedulability analysis of integrated avionics systems according to claim 3, characterized in that: The mapping relationship between AADL and Cheddar ADL components includes: Processor in AADL corresponds to Core & Processor in Cheddar ADL, Process / Thread Group in AADL corresponds to Address in Cheddar ADL, Thread in AADL corresponds to Task in Cheddar ADL, Data in AADL corresponds to Resource in Cheddar ADL, and Connection in AADL corresponds to Dependency in Cheddar ADL. The mapping relationship between AADL and Cheddar ADL attributes includes: AADL's Scheduling_Protocol corresponds to Cheddar ADL's Scheduler Type; AADL's Preemptive_Scheduler corresponds to Cheddar ADL's Preemptive Type; AADL's Compute_Execution_Time / Execution_Time corresponds to Cheddar ADL's Capacity; AADL's Priority corresponds to Cheddar ADL's Priority; AADL's Deadline corresponds to Cheddar ADL's Deadline; AADL's Period corresponds to Cheddar ADL's Period; AADL's Dispatch_Absolute_Time corresponds to Cheddar ADL's Start Time; AADL's Dispatch_Protocol corresponds to Cheddar ADL's Task Type; AADL's Critical_Section corresponds to Cheddar ADL's Critical Section; AADL's Data_Concurrency_State corresponds to Cheddar ADL's State; and AADL's Concurrency_Control_Protocol corresponds to Cheddar ADL's Protocol.

5. The method for combinatorial schedulability analysis of integrated avionics systems according to claim 3, characterized in that: The step of obtaining the partition and processor information bound to the current component and generating dependency relationships includes: By indexing the two-level parent components, the bound virtual processor is obtained, and the partition component is bound to the virtual processor; By indexing the first-level parent component, the bound partition address is obtained, and the task and resource components are bound to the partition address.

6. The method for combinatorial schedulability analysis of integrated avionics systems according to claim 3, characterized in that: The attribute definitions of the resource information are located in the parent component of the partition and mapped according to the mapping relationship between AADL and Cheddar ADL components, including: In the mapping relationship between AADL and Cheddar ADL components, the process / thread group in AADL corresponds to the task in CheddarADL; During the code conversion process, an address component is automatically generated, and the task is bound to the automatically generated address component.

7. The method for combinatorial schedulability analysis of integrated avionics systems according to claim 1, characterized in that: In step 5, the process of converting the task scheduling strategy described by the extended time automaton into an sc script file by parsing the XML file includes: Based on the code declaration, syntax rules, and grammar file editing syntax rules provided by the UPPAAL model, generate Lexer and Parser; The XML file is parsed using the API provided by UPPAAL to obtain System information, Template information, and Declaration information; then, the generated Lexer and Parser are used to construct a parse tree; the System information includes instantiation information; the Template information includes specific parameter information of the thread time automaton and the scheduling policy time automaton; the Declaration information includes the thread structure, relevant variables required for scheduling, and declarations of predefined functions; By using the Listener and Visitor provided by ANTLR4 to access the parse tree, relevant information about the task scheduling strategy described by the extended time automaton is obtained. XPath is used to identify the node set of the parse tree, and tree pattern matching is combined to generate an sc script file.

8. The method for combinatorial schedulability analysis of integrated avionics systems according to claim 7, characterized in that: The process of generating Lexer and Parser based on the code declaration, syntax rules, and grammar file editing rules provided by the UPPAAL model and ANTLR4 official documentation includes: Edit the C.g4 file provided by the official antlr4 website according to the code declaration and syntax rules of the UPPAAL model to obtain the UPPAAL.g4 file. Then, generate the Lexer and Parser in antlr4 based on UPPAAL.g4.

9. The method for combinatorial schedulability analysis of integrated avionics systems according to claim 7, characterized in that: The process involves using the Listener and Visitor provided by ANTLR4 to access the parse tree, obtaining information related to the task scheduling strategy described by the extended temporal automaton, using XPath to identify the node set of the parse tree, and combining this with tree pattern matching to generate an sc script file. Specifically, this includes: Use Listener to access the root node content of System, Template, and Declaration information in an XML file; use Visitor to access the child node content of the node to be retrieved. Traverse all child nodes and perform matching in the parse tree. If a match is successful, map the content of the current node into an sc file format and write it out; if not, match the next type of node.

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