Surrounding contacts comprising a positioned metal silicide

Abstract

A conformally deposited metal liner for forming discrete wrap-around contact structures is located between pairs of gate structures and under the top of the gate structures. Block mask patterning is employed to protect transistors above the active area of the substrate while removing portions of the metal liner between the active area. A chamfering technique is employed to selectively remove other portions of the metal liner within the active area. After deposition and patterning of a dielectric layer and subsequent metallization, the metal silicide liner formed on the source / drain regions using the conformally deposited metal liner is electrically connected to the source / drain contact metal.

Description

Background Technology

[0001] This invention generally relates to the electrical, electronic and computer fields, and more particularly to field-effect transistors (FETs) including surrounding contacts and their fabrication.

[0002] As the size of various integrated circuit components shrinks, transistors such as field-effect transistors (FETs) have experienced significant improvements in performance and power consumption. These improvements can be primarily attributed to the reduction in the size of the components used within them, which typically translates into reduced capacitance, resistance, and increased current flow from the transistor. Metal-oxide-semiconductor field-effect transistors (MOSFETs) are well-suited for high-density integrated circuits. With the reduction in the size of MOSFETs and other devices, the sizes of the device's source / drain regions, channel region, and gate electrode also decrease.

[0003] FinFETs, nanosheets, and other FETs are under development for potential use in close-pitch applications. Nanosheet FETs comprise multiple channel layers, each separated by a gate stack comprising a conductive gate material layer and a gate dielectric layer. The gate stack surrounds all sides of the channel layers, forming a gate-all-around (GAA) structure. Epitaxial regions at the ends of the nanosheet channel layers form the source / drain regions of the nanosheet FET. Spacers are used to electrically isolate the gate of the nanosheet transistor from the source / drain regions. FinFETs have a three-dimensional non-planar configuration, including fin-like structures extending above a substrate. The substrate can include a semiconductor-on-insulator (SOI) substrate or a bulk semiconductor substrate. In some FinFETs, silicon fins are formed on the substrate using known techniques such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed in part by selectively etching a crystalline silicon layer down to its oxide or other insulating layer after photolithography. When using an SOI substrate, the source fin height is determined by the SOI thickness. In a bulk FinFET, the active fin height is typically set by the oxide thickness and the etched fin height.

[0004] Due to the aggressive scaling in advanced CMOS devices, the contribution of mid-process (MOL) contact resistance to total parasitic resistance is increasing. Silicide / source-drain interface resistance is likely the major contributor to total external parasitic resistance. Increasing the silicide contact length around the total source-drain surface can reduce the total contact resistance. Trench silicide (TS) pads covering the source-drain epitaxy as wraparound contacts (WACs) to reduce extended resistance may be important for designing advanced semiconductor devices. Conformal metallization processes using chemical vapor deposition (CVD) or atomic layer deposition (ALD) have been employed to form metal contacts. Summary of the Invention

[0005] According to one aspect of the invention, a method for forming a semiconductor structure including surrounding contacts is provided. The method includes conformally depositing a metal pad on a monolithic structure including first and second active regions, and field-effect transistors on the first and second active regions, including gate structures and epitaxial source / drain regions. A metal silicide pad is formed from the metal pad on the epitaxial source / drain regions and surrounds these regions. The method further includes protecting the first and second active regions with a patterned blocking mask, selectively removing the metal pad from the region between the first and second active regions exposed by the patterned blocking mask, and removing the patterned blocking mask. A protective mask is formed on the monolithic structure such that the epitaxial source / drain regions are completely beneath the top surface of the protective mask, exposing a portion of the metal pad above the first and second active regions. The exposed portions of the metal pad above the first and second active regions are selectively removed, and then the protective mask is removed.

[0006] Another method of forming a semiconductor structure including surrounding contacts includes obtaining a monolithic structure comprising first and second active regions; field-effect transistors on the first and second active regions, including gate structures, a gate cap above the gate structure, gate sidewall spacers on the sidewalls of the gate structure, and epitaxial source / drain regions between pairs of gate structures; and adjacent pads including a first pad portion on and surrounding the epitaxial source / drain regions and a metal pad extending between the first and second active regions and above the gate cap and gate sidewall spacers. The first and second active regions are protected by a patterned blocking mask. The metal pad is selectively removed from the region between the first and second active regions exposed by the patterned blocking mask, followed by removal of the patterned blocking mask. A protective mask is formed on the monolithic structure such that the top portions of the gate cap and gate sidewall spacers extend above the top surface of the protective mask, and the epitaxial source / drain regions are below the top surface of the protective mask. The metal liner is selectively removed from the top portion of the gate sidewall spacer and the gate cap, and the protective mask is also removed.

[0007] In another aspect of the invention, a semiconductor structure is provided, comprising a semiconductor substrate having a first active region and a second active region, a shallow trench isolation region between the first and second active regions, and a plurality of gate structures on the first active region. A first field-effect transistor on the first active region includes one of the gate structures on the first active region, a channel region, and a pair of epitaxial source / drain regions on opposite sides of the channel region, each epitaxial source / drain region being located between the pair of gate structures on the first active region. A metal silicide pad is adjacent to each epitaxial source / drain region. A dielectric layer extends over the semiconductor substrate and the first field-effect transistor. The semiconductor structure also includes metal pad portions adjacent to each metal silicide pad, each metal pad portion including a vertically extending portion located between the pair of gate structures on the first active region and extending over the source / drain region, and a horizontally extending portion located below the source / drain region of the first field-effect transistor and located between the shallow trench isolation region and the dielectric layer. The horizontally extending portion of each metal pad portion extends laterally beyond one of the source / drain regions of the first field-effect transistor.

[0008] According to another aspect, a semiconductor structure includes: a semiconductor substrate including a first active region and a second active region; a plurality of parallel gate structures extending across the semiconductor substrate; a first field-effect transistor on the first active region, the first field-effect transistor including one of the gate structures, a channel region, and a first epitaxial source / drain region on the opposite side of the channel region. Each epitaxial source / drain region is located between the first pair of gate structures. The semiconductor structure further includes a second field-effect transistor on a second active region, wherein the second field-effect transistor includes one of the gate structures, a channel region, and a second pair of epitaxial source / drain regions on the opposite side of the channel region, each epitaxial source / drain region being located between the second pair of gate structures. A dielectric pad surrounds the first and second field-effect transistors. A metal silicide layer surrounds each source / drain region of the first and second field-effect transistors. A conformal metal pad extends from and is adjacent to each metal silicide pad. Each conformal metal layer includes a vertically extending portion constrained between a pair of gate structures and extending vertically over one of the source / drain regions, the pair of gate structures extending vertically over the vertically extending portion of each conformal metal pad. Source / drain contact metals extend vertically through the dielectric layer and contact the metal silicide pad.

[0009] The techniques and structures disclosed herein can provide substantially beneficial technical effects. As examples only and not limitations, one or more embodiments may provide one or more of the following advantages:

[0010] ■ Features robust and easily integrated discrete surrounding contact elements;

[0011] ■ Reduce the number of extreme ultraviolet lithography (EUVL) levels;

[0012] ■ This avoids potential problems associated with inverted color patterning.

[0013] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention, which is read in conjunction with the accompanying drawings. Attached Figure Description

[0014] The following figures are presented by way of example only and not as a limitation, wherein, in all the views, the same reference numerals (where used) indicate the corresponding elements, and wherein:

[0015] Figure 1 This is a schematic top view showing selected components of a monolithic semiconductor structure;

[0016] Figure 1A It is along Figure 1 A schematic cross-sectional view taken by line X shows other components of the monolithic semiconductor structure;

[0017] Figure 1B It is along Figure 1 A schematic cross-sectional view taken by line Y shows other components of the monolithic semiconductor structure;

[0018] Figure 2A yes Figure 1A A schematic cross-sectional view of the structure shown after selective oxide etching;

[0019] Figure 2B yes Figure 1B A schematic cross-sectional view of the structure shown after selective oxide etching;

[0020] Figure 3A yes Figure 2A The diagram shows a schematic cross-sectional view of the structure after the removal of the contact etch stop layer (CESL);

[0021] Figure 3B yes Figure 2B The diagram shows a schematic cross-sectional view of the structure after the removal of the contact etch stop layer (CESL);

[0022] Figure 4A This is after forming a silicide pad around its source / drain region, such as Figure 3A A schematic cross-sectional view of the structure shown;

[0023] Figure 4B This is after the deposition of the metal liner, such as Figure 3B A schematic cross-sectional view of the structure shown;

[0024] Figure 5AIt is after depositing and patterning a blocking mask on it. Figure 4A A schematic cross-sectional view of the structure shown;

[0025] Figure 5B It is after depositing and patterning a blocking mask on it. Figure 4B A schematic cross-sectional view of the structure shown;

[0026] Figure 6A This occurs after selectively removing the metal pads between its active regions. Figure 5A A schematic cross-sectional view of the structure shown;

[0027] Figure 6B This occurs after selectively removing the metal pads between its active regions. Figure 5B A schematic cross-sectional view of the structure shown;

[0028] Figure 7A After removing the patterned blocking mask, such as Figure 7A A schematic cross-sectional view of the structure shown;

[0029] Figure 7B After removing the patterned blocking mask, such as Figure 6B A schematic cross-sectional view of the structure shown;

[0030] Figure 8A This is after depositing an organic planarization layer (OPL) and partially etching it back. Figure 7A A schematic cross-sectional view of the structure shown;

[0031] Figure 8B This is after depositing an organic planarization layer (OPL) and partially etching it back. Figure 7B A schematic cross-sectional view of the structure shown;

[0032] Figure 9A This is after selectively chamfering the metal pads on its gate, as... Figure 8A A schematic cross-sectional view of the structure shown;

[0033] Figure 9B This is after selectively chamfering the metal pads on its gate, as... Figure 8B A schematic cross-sectional view of the structure shown;

[0034] Figure 10A It is after removing OPL Figure 9A A schematic cross-sectional view of the structure shown;

[0035] Figure 10B It is after removing OPL Figure 9B A schematic cross-sectional view of the structure shown;

[0036] Figure 11AThis is after the interlayer dielectric (ILD) layer is deposited and planarized on top. Figure 10A A schematic cross-sectional view of the structure shown;

[0037] Figure 11B It is after the ILD layer is deposited and planarized on it, as Figure 10B A schematic cross-sectional view of the structure shown;

[0038] Figure 12A This is after the contact trenches are formed in the ILD layer, such as... Figure 11A A schematic cross-sectional view of the structure shown;

[0039] Figure 12B This is after the contact trenches are formed in the ILD layer, such as... Figure 11B A schematic cross-sectional view of the structure shown;

[0040] Figure 13A yes Figure 12A The diagram shows a schematic cross-sectional view of the structure after contact metallization.

[0041] Figure 13B yes Figure 12B The diagram shows a schematic cross-sectional view of the structure after contact metallization.

[0042] Figure 14A It is after flattening Figure 13A A schematic cross-sectional view of the structure shown; and

[0043] Figure 14B It is after flattening Figure 13B A schematic cross-sectional view of the structure shown.

[0044] It should be understood that, for simplicity and clarity, the components are shown in the figures. Common but well-known components that may be useful or necessary in commercially feasible embodiments may not be shown in order to facilitate a more unobstructed view of the illustrated embodiments. Detailed Implementation

[0045] The principles of the invention will be described herein in the context of illustrative embodiments. However, it should be understood that the specific embodiments and / or methods illustrated and described herein should be considered exemplary and not restrictive. Furthermore, based on the teachings herein, those skilled in the art will appreciate that many modifications within the scope of the claims can be made to the illustrated embodiments. That is, no limitation is intended or should be inferred with respect to the embodiments shown and described herein.

[0046] The accompanying drawings illustrate an exemplary sequence of steps that can be used to form a surround contact (WAC). While the disclosed method and the resulting structure relate to GAA nanosheet structures, the principles of the invention can also be applied to other FET structures, such as FinFETs.

[0047] like Figure 1 , 1A The exemplary monolithic structure 20 shown in 1B can be obtained during the fabrication process in which the GAA nanosheet structure is provided. Various techniques for fabricating this and similar structures are known in the art, and new techniques continue to be developed. The exemplary structure 20 includes pFETs and nFETs, each comprising a stack of alternating semiconductor channel layers 21 (in... Figure 1B (Seen in cross-section). The semiconductor channel layer 21 may be, for example, a silicon nanosheet. The nanosheet may be formed on a semiconductor-on-insulator substrate or a bulk semiconductor substrate, such as a bulk silicon substrate. A shallow trench isolation (STI) region 26 formed within the substrate 24 provides electrical isolation for an active region comprising an adjacent transistor or other device that may be formed on the substrate. In an exemplary embodiment, the active region 24A of the substrate 24 comprises a single-crystal silicon fin, although impurities may be present within the crystal structure. Single-crystal silicon wafers are commercially available and are characterized by a diamond cubic lattice structure. As is known in the art, the Miller index of the substrate is determined by the reciprocal of the number of points where the crystal planes of silicon intersect the principal crystal axes. The exemplary embodiments described herein relate to structures comprising doped or undoped (100) silicon as a substrate material.

[0048] In one or more exemplary embodiments, each semiconductor channel layer 21 has a thickness ranging from four to ten nanometers (4-10 nm). The number of semiconductor (channel) layers in the semiconductor layer stack can vary depending on the desired use and capabilities of the nanosheet transistor to be fabricated. The channel layers 21 may be substantially composed of single-crystal silicon layers that may include impurities, and in some embodiments are spaced six to twenty nanometers (6-20 nm). In some embodiments, the width of each semiconductor channel layer 21 is approximately twenty to fifty nanometers (20-50 nm), but this range should be considered exemplary and not limiting.

[0049] Fabrication of structure 20 may include replacing the sacrificial silicon-germanium layer (not shown) between channel layers 21 with a metal gate and a gate dielectric material, the metal gate and gate dielectric material being formed as shown in the figure. Figure 1 and 1BThe diagram schematically illustrates a gate-enclosed structure (gate stack) 28. Silicon and silicon-germanium layers can be epitaxially grown sequentially in alternating sequences to obtain a vertical stack with a desired number of silicon (channel) layers. The terms "epitaxical growth and / or deposition" and "epitaxically grown and / or deposited" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, wherein the grown semiconductor material has the same crystal properties as the semiconductor material on the deposition surface. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled, and the system parameters are set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves toward the crystal arrangement of the atoms on the deposition surface. Therefore, the epitaxial semiconductor material has the same crystal properties as the deposition surface on which the epitaxial semiconductor material is formed.

[0050] Gate structure 28 may have a thickness ranging from six to twenty nanometers (6-20 nm). The size range of the channel layer and gate structure should be considered exemplary and not limiting. A gate dielectric layer forms part of the gate stack 28, replacing the sacrificial silicon-germanium layer. The gate stack is adjacent to the silicon nanosheet channel layer 21 and extends down to the bottom dielectric isolation (BDI) layer 36 and / or the STI region 26. Non-limiting examples of suitable materials for the gate dielectric layer include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k gate dielectric materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials can also include dopants such as lanthanum and aluminum.

[0051] The gate dielectric layer can be formed by a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of the gate dielectric material can vary depending on the deposition process and the composition and amount of the high-k dielectric material used. In one exemplary embodiment, a high-k dielectric layer with a thickness of 2.5 nm is used. In some embodiments, the gate dielectric layer comprises multiple layers.

[0052] Source / drain regions 32P and 32N are epitaxially grown on the exposed edges of the silicon (channel) layer 21 and can be merged. The source / drain regions are electrically isolated from the substrate 24 via a bottom dielectric isolation (BDI) layer 36. As is known in the art, dopants can be introduced in situ within the source / drain regions 32 using suitable precursors. "In situ" means introducing a dopant that determines the conductivity type of the doped layer during a process step (e.g., epitaxial deposition) to form the doped layer. As used herein, the term "conductivity type" indicates whether the doped region is p-type or n-type. As used herein, "p-type" refers to the addition of an impurity to the intrinsic semiconductor, which creates a defect for valence electrons. Examples of p-type dopants, i.e., impurities, in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium. As used herein, "n-type" refers to the addition of an impurity that contributes free electrons to the intrinsic semiconductor. Examples of n-type dopants, i.e., impurities, in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus. Exemplary epitaxial growth processes suitable for forming silicon and / or silicon-germanium epitaxy include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The nFET region includes a transistor with n-type source / drain regions, while the pFET region includes p-type source / drain regions. The use of the BDI layer 36 is optional for the fabrication of nFET and pFET transistors as described herein.

[0053] The monolithic structure 20 also includes a contact etch stop layer (CESL), which forms a pad thereon after the source / drain epitaxy. In some embodiments, the CESL pad 37 is formed by depositing a conformal layer of silicon nitride, a low-k dielectric material (e.g., silicon-carbon-boron-nitrogen (SiCBN), silicon oxycarbide (SiOC), or silicon oxynitride-carbon (SiCON)) over and between the source-drain regions 32P and 32N.

[0054] Next, an interlayer dielectric layer (ILD) 38, such as silicon dioxide (SiO2) or any other material with similar functional properties, is formed on the source-drain region and the CESL pad 37 by chemical vapor deposition (CVD) or any other suitable deposition technique. Structure 20 further includes a dielectric gate sidewall spacer 42 and a gate cap 44, such as... Figure 1B As shown. The technique used to form such spacers and gate caps is known in the art. CESL pad 37 also extends on the gate sidewall spacers and gate caps. After planarizing the gate cap (where the gate cap layer is formed) and depositing the oxide filler, as... Figure 1A and 1B As shown, the above-mentioned components are embedded in the ILD layer 38.

[0055] refer to Figure 2A and 2BThe ILD layer 38 is selectively removed using, for example, wet hydrofluoric acid (HF) etching or any other suitable etching. The CESL pad 37 is then selectively removed to obtain, as... Figure 3A and Figure 3B Structure 30 is schematically shown in cross-section. In one or more embodiments, wet phosphoric acid etching or other suitable etching may be used to selectively remove the CESL pad 37.

[0056] The TS pad surrounding the source / drain regions 32P, 32N can be formed using CVD conformal deposition of a titanium (Ti) pad 46 or other suitable metal pads. An annealing step can be performed at or after this process stage, following the deposition of pad 46, to form a titanium silicide and / or titanium-based germanium silicide layer on the source / drain regions. The conformal film is understood to have a substantially uniform thickness. In some exemplary structures including nFET and pFET regions, annealing causes the source / drain regions within the nFET region to include a TiS2 layer, while a titanium germanium silicide (Ti(SiGe)2) layer is formed on the source / drain regions within the pFET region. The terms titanium silicide and metal silicide as used below are intended to include silicides formed on silicon or silicon-germanium. The thickness of the Ti pad 46 can be, for example, in the range of two to five nanometers (2 nm to 5 nm). Figure 4A and 4B As shown, the pads also extend over the STI region 26, the gate sidewall spacer 42, and the gate cap 44. This results in structure 40.

[0057] An organic planarization layer (OPL) 48 is deposited on structure 40 and patterned to form a barrier mask. According to embodiments of the invention, OPL 48 can be an organic polymer comprising carbon, hydrogen, and nitrogen. Non-limiting examples of OPL materials include JSRHM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL 102, or other similar materials commercially available from suppliers such as JSR, TOK, Sumitomo, and Rohm & Haas. OPL 48 can be deposited, for example, by spin coating, and excess material is etched back. Figure 5A and 5B As shown, the remaining portion of the OPL forms a barrier mask that extends over and protects the active region 24A on the substrate 24. The source / drain regions 32P, 32N, portions of the pad 46 surrounding the source / drain regions, and the gate structure on the active region are embedded within the patterned OPL and are thus protected. Figure 5AAs shown, the patterned OPL extends laterally across the source / drain regions, while exposing the horizontal portion of the titanium pad 46 between the pFET and nFET active regions. After the OPL is patterned, portions of the titanium pad 46 extending over the STI region 26 and gate structure 28 between the active regions are exposed in the resulting structure 50.

[0058] The exposed portions of the titanium pad 46 between the active regions 24A are selectively removed. Selective removal of the titanium-based material can be performed wet processes, such as using a sulfuric acid peroxide mixture (SPM) in combination with sulfuric acid and hydrogen peroxide. As used herein, the term "selective" in relation to a material removal process (e.g., etching) means that, with appropriate etchant selection, the material removal rate (i.e., etching rate) of the target material is greater than, and preferably much greater than, the removal rate of at least one other material exposed to the material removal process. Thus, it is possible to obtain... Figure 6A and 6B Structure 60 is schematically shown in a cross-section. Removing OPL 48 from structure 60 re-exposes the titanium-covered source / drain regions 32P, 32N and other structures above the active region 24A of the substrate 24. As shown... Figure 7A and 7B The structure 70 is schematically shown in the diagram. (For example...) Figure 7A As shown, the metal pads 46 now include horizontal segments 46A that extend partially over the STI region 26 and extend laterally beyond the lateral ends of the source / drain regions directly above them.

[0059] Another organic planarization layer 48' is deposited and etched back to obtain, as shown Figure 8A and 8B The structure 80 is shown schematically. OPL 48' may, but does not necessarily, include the same material as OPL 48 described above. It may be deposited in the same manner or using different techniques. Figure 8A and 8B As shown, the thickness of OPL 48' is sufficient to embed and protect the source / drain regions 32P, 32N, including the titanium (silicide) layer 48, within the OPL. A portion of the gate structure 28 and the gate sidewall spacer 42 extends above the top surface of the OPL. The titanium-covered gate cap 44 formed above the active region 24A is fully exposed. By providing sufficient uniformity to the recessed OPL 48' beneath the top surface of the gate cap 44 on the wafer on which the field-effect transistor is formed, a portion of the titanium layer 46 on the gate cap 44 is fully exposed, while the titanium (or silicide) on the epitaxial source / drain regions 32P, 32N is not exposed.

[0060] Selective titanium chamfering results in the removal of the exposed portion of the titanium liner 46 above the top surface of OPL 48'. As described above, selective removal of the titanium-based material can be performed using a wet process, for example, a sulfur peroxide mixture (SPM). Therefore, it is possible to obtain... Figure 9A and 9B Structure 90 is schematically shown in a cross-section. The remaining vertical portion 46B of the titanium pad abuts the gate sidewall spacer 42 and terminates below the gate cap 44. The gate structure 28, having a top portion abutting the gate cap 44, extends above the vertical portion 46B of the titanium layer 46.

[0061] The second OPL 48' can be removed by ashing or other suitable processes to obtain, as shown in the image. Figure 10A and 10B Structure 100 is schematically shown in a cross-section. The gasket 46 now comprises a plurality of discrete, adjacent segments, each segment including a metal silicide portion and a metal portion extending from the silicide portion. (See diagram below.) Figure 10A As shown, the titanium silicide portion of pad 46 surrounds the source / drain regions 32P, 32N. The laterally extending metal (non-silicide) portion 46A of pad 46 extends horizontally a limited distance from the sub-fin region beneath the bottom dielectric isolation layer 36 and above a portion of the STI region 26. As described above, the laterally extending portion 46A of pad 46 further extends laterally beyond the associated source / drain regions 32P, 32N of the field-effect transistor. Figure 10B As shown, the vertical portion 46B of the titanium pad 46 segment is located between the gate structures 28 pairs. Each vertical portion 46B includes a pair of metal segments adjacent to the gate sidewall spacers 42. The vertical portion 46B is completely located below the top surface of the gate structure 28 and the gate cap 44.

[0062] An interlayer dielectric (ILD) layer 52 is deposited on structure 90 and planarized. The ILD layer can be deposited using, for example, deposition techniques including, but not limited to, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), radio frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), and / or liquid source atomized chemical deposition (LSMCD), spin coating, sputtering, and / or electroplating. The ILD layer 52 may include, but is not limited to, low-k materials (e.g., k less than about 4.0), such as porous silicates, carbon-doped oxides, silicon dioxide, silicon oxynitride, carbon-doped silicon oxynitride (SiCOH) and their porous variants, silsesquioxanes, siloxanes, or other dielectric materials having a dielectric constant, for example, in the range of about 2 to about 4.

[0063] An interlayer dielectric (ILD) layer 52 is conformally deposited on structure 90 to fill the space between nFET and pFET elements on substrate 24. In one exemplary embodiment, the interlayer dielectric layer may, for example, comprise a conformal oxide, such as ALD silicon dioxide. In one or more embodiments, a flowable ILD material may be employed. For example, FCVD can be used to deposit a substantially carbon-free silicon oxide (SiO2) material. Flowable chemical vapor deposition (FCVD) provides a fluid-like film that flows freely into the trench-like geometry to provide bottom-up, void-free, and seamless filling. In some embodiments, other dielectric materials may be used alternatively, although etch selectivity should be provided between the ILD layer 52 and the gate sidewall spacers 42, gate cap 44, and metal silicide. The ILD layer 52 may optionally be cured using a variety of known curing techniques, including UV-assisted curing below 400°C. The resulting structure is then subjected to chemical mechanical planarization (CMP). This results in a structure as described above. Figure 11A and 11B The structure 110 is schematically shown in the figure, wherein a horizontal portion 46A of the metal pad 46 is positioned between the ILD layer 52 and the STI region 26.

[0064] The trench openings are typically formed in the ILD layer 52 using, for example, a known damascene technique. Photolithography and etching steps are performed after ILD layer deposition. Specifically, a photoresist (not shown) is applied to the ILD layer. The photoresist can be applied using any suitable technique, including but not limited to coating or spin coating techniques. A mask (not shown) is provided on the photoresist, patterned to define the shape of the trench openings and / or contact holes to be formed, and the mask pattern is transferred to the photoresist using a photolithography process, which creates recesses in the uncovered areas of the photoresist. The same recessed pattern is then created in the ILD dielectric layer using the patterned photoresist through conventional etching, typically used to form trenches and contact holes. Dry etching (e.g., reactive ion etching) can be used to form such trenches and contact holes. The etching selectively removes a portion of the ILD layer 52. After the trench openings 54 are formed, the photoresist can be stripped from the ILD layer by ashing or other suitable processes. Figure 12A and 12B As schematically shown, the resulting structure 120 can withstand wet cleaning.

[0065] After stripping the resist, the trench (via) openings are cleaned and then lined with, for example, a thin PVD (e.g., sputtered) titanium (Ti) layer (not shown). The Ti film serves as an adhesion layer and also reduces contact resistance with the underlying conductor by reducing interfacial oxides. Titanium nitride (TiN) (not shown) is subsequently deposited by sputtering or CVD. A contact metal layer 56, such as tungsten (W) or cobalt (Co), is conformally deposited on the structure, filling the trench 54 that forms the ILD layer 52 and directly contacting the metal silicide and / or metal germanium silicide layers formed from the metal pad 46 on the source / drain regions 32N, 32P. The vertical extension 46B of the pad also contacts the metal contact layer 56, as shown below. Figure 13B As shown. In some embodiments, the contact metal layer is a tungsten (W) layer deposited using a tungsten hexafluoride source with silane. For example, the tungsten layer can be deposited using chemical vapor deposition at a temperature between 300-400°C and using tungsten hexafluoride precursor chemicals. The contact material may alternatively include, for example, tantalum (Ta), aluminum (Al), platinum (Pt), gold (Au), titanium (Ti), palladium (Pd), or any combination thereof. The contact material can be deposited by, for example, CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering. After trench silicide metallization as described above, a result such as Figure 13A and 13B Structure 130 is shown schematically in the diagram.

[0066] A planarization process such as CMP is performed to remove any conductive material (overload) from the top surface of the structure. The thickness of the ILD layer 52 can also be reduced using CMP to achieve, as... Figure 14A and 14B Structure 140 is schematically shown in the diagram. (Example) Figure 14A As shown, metal silicide surrounds the source / drain regions 32P and 32N. (As...) Figure 14B As shown, the metal silicide surrounding the source / drain regions and the adjacent portion 46B of the pad 46 extending above the source / drain regions are located between the gate structures 28. All remaining portions of the pad 46 are located below the top surface of the gate structure 28. A semiconductor structure 140 including a gate-around-all-around (GAA) structure, surrounding source / drain contacts, and localized metal / silicide can be provided. Furthermore, the combination of barrier mask patterning and chamfering used to fabricate this structure avoids the need for inverse tone patterning.

[0067] The accompanying figures, as described above, depict exemplary processing steps / stages in the fabrication of the exemplary structure. While the overall fabrication method and the resulting structure are entirely novel, certain individual processing steps required to implement this method can utilize conventional semiconductor fabrication techniques and tools. These techniques and tools are already familiar to those skilled in the art, given the teachings herein. Furthermore, one or more processing steps and tools for fabricating semiconductor devices are described in numerous readily available publications, including, for example, James D. Plummer et al.'s "Silicon VLSI Technology: Fundamentals, Practice, and Modeling, First Edition, Prentice Hall, 2001" (incorporated herein by reference). It should be emphasized that while some individual processing steps are illustrated herein, these steps are merely illustrative, and those skilled in the art will be familiar with several equally suitable alternatives that will be applicable.

[0068] It should be understood that the various layers and / or regions shown in the accompanying drawings may not be drawn to scale. Furthermore, for ease of interpretation, one or more semiconductor layers of a type typically used in such integrated circuit devices or other layers may not be explicitly shown in a given figure. This does not imply that un-explicitly shown semiconductor layers or other layers are omitted in actual integrated circuit devices.

[0069] Considering the discussion so far, it will be understood that, in general, an exemplary method of forming a semiconductor structure including a surrounding contact includes conformally depositing a metal pad on a monolithic structure including first and second active regions 24A and field-effect transistors (FETs) on the first and second active regions. Figure 3A and 3B An exemplary monolithic structure 30 including a nanosheet FET is shown. The FET includes a gate structure 28 and epitaxial source / drain regions 32P and / or 32N. A metal silicide pad is formed from a metal pad on the epitaxial source / drain regions and surrounds the source / drain regions. Figure 5A and 5B As schematically shown, the first and second active regions are protected by a patterned blocking mask 48. A metal pad is selectively removed from the area exposed by the patterned blocking mask between the first and second active regions. After removing the patterned blocking mask 48, the desired result is obtained as shown in the diagram. Figure 7A and 7B The structure shown is 70. (As shown) Figure 8A and 8BSchematarily shown, a protective mask 48' is formed on a monolithic structure. The protective mask protects the epitaxial source / drain regions, which are completely located below the top surface of the protective mask. A portion of the metal pad 46 above the first and second active regions is exposed. The exposed portion of the metal pad 46 above the active regions is removed, followed by the removal of the protective mask 48'. Thus, as shown... Figure 10A and 10B The monolithic semiconductor structure 100 shown should be understood to be applicable to the nanosheet transistor shown and other types of FETs such as FinFETs.

[0070] In an exemplary embodiment, forming a protective mask includes depositing an organic planarization layer on a monolithic structure and etching back the organic planarization layer to expose the top portion of the gate structure 28 and the associated gate sidewall spacers 42 and gate cap 44. The method may include forming an interlayer dielectric layer 52 on the monolithic structure, patterning the interlayer dielectric layer, thereby exposing metal silicide pads on the epitaxial source / drain regions 32P, 32N, such as… Figure 12A and 12B As shown, there is a metal contact 56 formed within the interlayer dielectric layer and in direct contact with the metal silicide pad on the epitaxial source / drain region. Figure 13A and 13B An exemplary structure 130 after contact metallization is shown. In one or more exemplary embodiments, the monolithic structure 30 further includes a gate cap 44 and gate sidewall spacers 42 adjacent to the gate structure, wherein selectively removing a metal pad 46 over a top portion of the gate structure includes removing the metal pad from the gate cap and a portion of the gate sidewall spacers. In one or more embodiments, the monolithic structure includes a shallow trench isolation region 26, wherein selectively removing the metal pad 46 from the region between the first and second active regions includes removing the metal pad from the top surface of the shallow trench isolation region 26.

[0071] A semiconductor structure provided according to one or more embodiments includes a semiconductor substrate 24, which includes a first active region 24A and a second active region 24A, and a shallow trench isolation region 26 between the first active region and the second active region. A first field-effect transistor on the first active region includes a gate structure 28 on the first active region, a channel region (the region of layer 21 adjacent to the gate structure), and a pair of epitaxial source / drain regions 32P or 32N on opposite sides of the channel region. Each epitaxial source / drain region is located between a pair of gate structures on the first active region. Each epitaxial source / drain region of the first field-effect transistor is adjacent to a metal silicide pad (silicide portion of conformal metal layer 46). A dielectric layer 52 extends over the semiconductor substrate and the first field-effect transistor. A metal pad portion is adjacent to each metal silicide pad, respectively. Each metal pad portion includes a vertically extending portion 46B located between a pair of gate structures 28 on the first active region and extending over the source / drain region. The gate structure 28 on the first active region extends vertically above the vertical extension portion 46B. The horizontally extending metal pad portion 46A extends below the source / drain regions of the first field-effect transistor and is located between the shallow trench isolation region 26 and the dielectric layer 52. For example, as... Figure 14A As shown, the horizontal extension 46A of each metal pad portion extends laterally beyond one of the source / drain regions of the first field-effect transistor located directly thereon.

[0072] At least some of the above-described technologies can be implemented in integrated circuits. In forming integrated circuits, identical dies are typically fabricated on the surface of a semiconductor wafer in a repeating pattern. Each die includes the devices described herein and may include other structures and / or circuits. Individual dies are cut or sliced ​​from the wafer and then packaged into integrated circuits. Those skilled in the art will know how to cut wafers and package dies to produce integrated circuits.

[0073] Those skilled in the art will understand that the exemplary structures described above can be distributed as bare chips in their original form (i.e., a single wafer with multiple unpackaged chips), distributed in a packaged form, or incorporated as part of intermediate or final products that benefit from having nanosheets or other FET devices with surrounding contacts formed according to one or more exemplary embodiments.

[0074] Many techniques exist that are used by those skilled in the art to remove material at various stages of semiconductor structure formation. These processes are generally referred to as “etching” as used herein. Etching includes, for example, wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE) techniques, all of which are known techniques for removing selective material during semiconductor structure formation. Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid, and hydrogen peroxide. The techniques and applications of etching are readily understood by those skilled in the art; therefore, a more detailed description of these processes is not provided herein.

[0075] The embodiments described herein are intended to provide a general understanding of the various embodiments and are not intended to be used as a complete description of all elements and features of apparatuses and systems that may utilize the circuits and techniques described herein. Many other embodiments will become apparent to those skilled in the art from the teachings herein; other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of the invention. It should also be noted that in some alternative implementations, some steps of the exemplary method may occur in a different order than shown in the figures. For example, two steps shown consecutively may actually be performed substantially simultaneously, or certain steps may sometimes be performed in reverse order, depending on the functionality involved. The figures are also merely representative and not drawn to scale. Therefore, the specification and figures should be considered illustrative rather than restrictive.

[0076] In this document, if more than one embodiment is actually shown, the embodiments may be referred to individually and / or collectively as the term "embodiment" for convenience only and not to limit the scope of this application to any single embodiment or inventive concept. Therefore, although specific embodiments have been shown and described herein, it should be understood that arrangements achieving the same purpose may replace the shown one or more specific embodiments. Combinations of the foregoing embodiments, as well as other embodiments not specifically described herein, will become apparent to those skilled in the art from the teachings herein.

[0077] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including” as used in this specification specify the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Terms such as “above” and “below” and “vertical” are used to indicate the relative positioning of elements or structures with respect to each other, as opposed to relative height.

[0078] The corresponding structures, materials, actions, and equivalents of any means or steps plus functional elements in the following claims are intended to include any structures, materials, or actions for performing functions in combination with other claimed elements as specifically claimed. Various embodiments have been described for purposes of illustration and description, but are not intended to be exhaustive or limited to the forms disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The embodiments were chosen and described in order to best explain the principles and practical application, and to enable others skilled in the art to understand the various embodiments with various modifications suitable for the particular purpose contemplated.

[0079] An abstract is provided to conform to 37C.FR §1.72(b). It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen from the foregoing detailed description, various features have been grouped together in a single embodiment to facilitate the flow of this disclosure. This approach to disclosure should not be construed as reflecting an intention that the claimed embodiment requires more features than expressly recited in each claim. Rather, as reflected in the appended claims, the claimed subject matter may comprise fewer than all features of a single embodiment. Therefore, the following claims are thus incorporated into the detailed description, wherein each claim is independently claimed as a separate subject matter.

[0080] In light of the teachings provided herein, those skilled in the art will be able to conceive of other implementations and applications of the techniques and disclosed embodiments. Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the illustrative embodiments are not limited to those precise embodiments, and various other changes and modifications can be made therein by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A semiconductor structure, comprising: A semiconductor substrate, including a first active region and a second active region; Shallow trench isolation zone between the first active region and the second active region; Multiple gate structures on the first active region; A first field-effect transistor on the first active region, the first field-effect transistor including one of the gate structures on the first active region, a channel region and a pair of epitaxial source / drain regions on opposite sides of the channel region, each epitaxial source / drain region being located between a pair of gate structures on the first active region; Surrounding the metal silicide pad, which is adjacent to each epitaxial source / drain region of the first field-effect transistor; A dielectric layer extending over the semiconductor substrate and the first field-effect transistor; Metal pad portions, each adjacent to a metal silicide pad, and each metal pad portion comprising: The vertically extending portion is located between a pair of gate structures on the first active region and extends above the source / drain region; as well as The horizontal extension portion, located below the source / drain regions of the first field-effect transistor and between the shallow trench isolation region and the dielectric layer, extends laterally beyond one of the source / drain regions of the first field-effect transistor.

2. The semiconductor structure according to claim 1, further comprising: Multiple gate structures on the second active region; A second field-effect transistor on the second active region, the second field-effect transistor including one of the gate structures on the second active region, a channel region, and a pair of epitaxial source / drain regions on opposite sides of the channel region, each epitaxial source / drain region being located between a pair of gate structures, the dielectric layer extending over the second field-effect transistor; Surrounding the metal silicide pad, which is adjacent to each epitaxial source / drain region of the second field-effect transistor; Metal pad portions, each adjacent to a metal silicide pad of the second field-effect transistor, each metal pad portion comprising: A vertically extending portion is located between a pair of gate structures on the second active region and extends above the source / drain regions of the second field-effect transistor, wherein the gate structures on the second active region extend vertically above the vertically extending portion. as well as The horizontal extension portion, located below the source / drain regions of the second field-effect transistor and between the shallow trench isolation region and the dielectric layer, extends laterally beyond one of the source / drain regions of the second field-effect transistor.

3. The semiconductor structure according to claim 2, further comprising: Multiple vertically extending trenches within the dielectric layer; as well as The metal contacts the metal silicide pad within the trench and adjacent to the epitaxial source / drain regions of the first and second field-effect transistors.

4. The semiconductor structure according to claim 3, wherein, The first field-effect transistor and the second field-effect transistor are nanosheet transistors, and the epitaxial source / drain regions include doped polyhedral structures.

5. The semiconductor structure according to claim 3, wherein, The active region includes semiconductor fins.

6. The semiconductor structure of claim 5 further includes a bottom dielectric isolation layer below the first field-effect transistor and the second field-effect transistor, each metal pad portion extending above an edge portion of the bottom dielectric isolation layer.

7. The semiconductor structure of claim 1, further comprising a gate sidewall spacer on the sidewall of the gate structure, wherein the vertically extending portions of the metal pad portion are respectively adjacent to the gate sidewall spacer, and the gate structure on the first active region extends vertically above the vertically extending portions of the metal pad portion.

8. The semiconductor structure according to claim 7, wherein, The metal liner portion comprises titanium, and the first field-effect transistor is a nanosheet transistor or a FinFET transistor.

9. A semiconductor structure, comprising: A semiconductor substrate, including a first active region and a second active region; Multiple parallel gate structures extending across the semiconductor substrate; A first field-effect transistor on the first active region, the first field-effect transistor including one of the gate structures, a channel region and a first epitaxial source / drain region on the opposite side of the channel region, each epitaxial source / drain region being located between the first pair of gate structures; A second field-effect transistor on the second active region, the second field-effect transistor including one of the gate structures, a channel region and a second epitaxial source / drain region on the opposite side of the channel region, each epitaxial source / drain region being located between the second pair of gate structures; A dielectric layer encapsulates the first field-effect transistor and the second field-effect transistor; A metal silicide pad surrounds each of the source / drain regions; A conformal metal pad extends from and is adjacent to each metal silicide pad, each conformal metal pad including a vertically extending portion defined between one of the first pair and the second pair of gate structures and extending vertically over one of the source / drain regions, the first pair and the second pair of gate structures extending vertically over the vertically extending portion of each conformal metal pad. as well as The source / drain contact metal extends vertically through the dielectric layer and contacts the metal silicide pad.

10. The semiconductor structure according to claim 9, wherein, The channel region of each of the first and second transistors includes multiple vertically stacked channel layers.

11. The semiconductor structure according to claim 9, wherein, Each of the gate structures includes a gate sidewall spacer, and further, wherein the vertical extension of each conformal metal pad includes a pair of vertical segments, each vertical segment being adjacent to one of the gate sidewall spacers.

12. The semiconductor structure according to claim 11, wherein, Each conformal metal pad includes a horizontal segment that extends beneath the dielectric layer and laterally beyond one of the source / drain regions.

13. The semiconductor structure of claim 12, further comprising a shallow trench isolation region below the dielectric layer and laterally located between the first active region and the second active region, wherein a horizontal segment of each conformal metal pad extends between the dielectric layer and the shallow trench isolation region.

14. A method of forming a semiconductor structure including a surrounding contact, comprising: A metallic pad is conformally deposited on a monolithic structure, the monolithic structure comprising: The first active region and the second active region; and The field-effect transistors on the first and second active regions include a gate structure and an epitaxial source / drain region; A metal silicide pad is formed from the metal pad on and around the epitaxial source / drain region; The first and second active regions are protected with a patterned blocking mask; The metal pad is selectively removed from the area exposed by the patterned blocking mask between the first and second active regions; Remove the patterned blocking mask; A protective mask is formed on the monolithic structure such that the epitaxial source / drain regions are completely located below the top surface of the protective mask, and the portion of the metal pad located above the first active region and the second active region is exposed; Selectively remove the exposed portions of the metal pads above the first and second active regions; and Remove the protective mask.

15. The method according to claim 14, wherein, Forming the protective mask includes: An organic planarization layer is deposited on the monolithic structure; and The organic planarization layer is etched back, causing a portion of the gate structure to extend above the top surface of the protective mask.

16. The method of claim 15, further comprising: An interlayer dielectric layer is formed above the active region; Pattern the interlayer dielectric layer to expose the metal silicide pads on the epitaxial source / drain regions; A metal contact is formed within the interlayer dielectric layer, which directly contacts the metal silicide pad on the epitaxial source / drain region.

17. The method according to claim 16, wherein, The monolithic structure further includes a gate cap and a gate sidewall spacer adjacent to the gate structure. Further, selectively removing the exposed portion of the metal pad above the first active region and the second active region includes removing the metal pad from the top portion of the gate cap and the gate sidewall spacer.

18. The method according to claim 17, wherein, The monolithic structure includes a shallow trench isolation region between the first active region and the second active region, further wherein selectively removing the metal liner from the region between the first active region and the second active region includes removing the metal liner from the top surface of the shallow trench isolation region.

19. The method according to claim 18, wherein, The monolithic structure further includes a contact etch stop pad extending over the first active region, the second active region, and the shallow trench isolation region, and the method further includes: Remove the contact etch stop pad and replace it with the metal pad.

20. The method according to claim 18, wherein, The field-effect transistor includes a nanosheet transistor or a FinFET transistor.

21. The method according to claim 14, wherein, The field-effect transistor includes a nanosheet transistor or a FinFET transistor, and the epitaxial source / drain region includes a doped multifaceted semiconductor region. Further, the metal pad is conformally deposited such that the metal pad surrounds the doped multifaceted semiconductor region.

22. The method according to claim 21, wherein, The patterned blocking mask completely covers the epitaxial source / drain region and extends laterally beyond the epitaxial source / drain region.

23. The method of claim 22, wherein: The monolithic structure also includes a gate cap and a gate sidewall spacer adjacent to the gate structure; Forming the protective mask includes depositing an organic planarization layer on the monolithic structure and etching back the organic planarization layer to expose the top portion of the gate sidewall spacer and the gate cap; as well as Selectively removing the exposed portion of the metal pad above the first and second active regions includes removing the metal pad from the top portion of the gate sidewall spacer and the gate cap.

24. A method of forming a semiconductor structure including a surrounding contact, comprising: A monolithic structure is obtained, the monolithic structure comprising: First active region and second active region; Field-effect transistors located in the first active region and the second active region, the field-effect transistors including a gate structure, a gate cap above the gate structure, gate sidewall spacers on the sidewalls of the gate structure, and an epitaxial source / drain region between the gate structure pairs; and The adjacent pad includes a first pad portion on and around the epitaxial source / drain region and a metal pad extending between the first active region and the second active region and over the gate cap and the gate sidewall spacer. The first and second active regions are protected by a patterned blocking mask; The metal pad is selectively removed from the area exposed by the patterned blocking mask between the first and second active regions; Remove the patterned blocking mask; A protective mask is formed on the monolithic structure such that the top portions of the gate cap and the gate sidewall spacer extend above the top surface of the protective mask, and the epitaxial source / drain regions are below the top surface of the protective mask. Selectively remove the metal liner from the top portion of the gate cap and the gate sidewall spacer; and Remove the protective mask.

25. The method according to claim 24, wherein, The field-effect transistor includes a nanosheet transistor or a FinFET transistor, and the method further includes: A metal silicide pad is formed from the first pad portion; An interlayer dielectric layer is formed above the first active region and the second active region; Patterning the interlayer dielectric layer to expose the metal silicide pads on the epitaxial source / drain regions; and A metal contact is formed within the interlayer dielectric layer, which directly contacts the metal silicide pad on the epitaxial source / drain region.

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