Delay parameter determination method and apparatus, storage medium, and electronic device
By determining the clock signal setup time and target sampling delay in the DRAM design, the problem of DQ data acquisition errors caused by clock signal delay is solved, and automated delay parameter determination is achieved, ensuring the accuracy and efficiency of data acquisition.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-02-18
- Publication Date
- 2026-06-05
AI Technical Summary
In DRAM design, the clock signal is divided into four stages, which causes delays and leads to DQ data acquisition errors.
By determining the setup time of the clock signal in the memory and dividing it into multiple clock sub-signals, calculating the target sampling delay, determining the delay parameter of the DQ data signal relative to the clock signal, and using simulation technology to determine the simulation waveform, we can ensure that the DQ data is correctly acquired during the rising edge phase.
This enables accurate acquisition of DQ data in DRAM designs, avoiding the time-consuming and costly manual measurement, and improving the accuracy and efficiency of data acquisition.
Smart Images
Figure CN116665730B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a delay parameter determination method, a delay parameter determination device, a computer-readable storage medium, and an electronic device. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. Due to its advantages such as simple structure, high density, low power consumption, and low price, it has been widely used in the computer field and the electronics industry.
[0003] Typically, in DRAM design, the clock signal WCK is divided into four stages, and DQ (data I / O channel) data is acquired through these four stages.
[0004] However, in practical applications, due to the delay in the four-stage signals, there may be instances where incorrect DQ data is acquired.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] The purpose of this disclosure is to provide a method, apparatus, computer-readable storage medium, and electronic device for determining delay parameters, in order to solve the problem that clock sub-signals cannot effectively sample DQ data.
[0007] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of the invention.
[0008] According to a first aspect of this disclosure, a method for determining a delay parameter is provided, the method comprising: determining the setup time of a clock signal in a memory relative to a DQ data signal; dividing the clock signal into multiple clock sub-signals and determining a target sampling delay of the multiple clock sub-signals relative to the DQ data signal; and determining a delay parameter of the DQ data signal relative to the clock signal based on the target sampling delay and the setup time.
[0009] In one exemplary embodiment of this disclosure, the target sampling delay is the minimum sampling delay among the plurality of clock sub-signals relative to the DQ data signal.
[0010] In one exemplary embodiment of this disclosure, determining the target sampling delay of the plurality of clock sub-signals relative to the DQ data signal includes: determining the delay from the rising edge or falling edge of the DQ data signal to the rising edge of the corresponding clock sub-signal as the sampling delay of the clock sub-signal; and determining the minimum value among the sampling delays of the plurality of clock sub-signals as the target sampling delay.
[0011] In one exemplary embodiment of this disclosure, determining the target sampling delay includes: when the written DQ data signal is 1010 data and there are four clock sub-signals, determining the delay from the first rising edge of the DQ data signal to the first rising edge of the first clock sub-signal as the first sub-sampling delay of the first clock sub-signal; determining the delay from the first falling edge of the DQ data signal to the second rising edge of the second clock sub-signal as the second sub-sampling delay of the second clock sub-signal; determining the delay from the second rising edge of the DQ data signal to the third rising edge of the third clock sub-signal as the third sub-sampling delay of the third clock sub-signal; determining the delay from the second falling edge of the DQ data signal to the fourth rising edge of the fourth clock sub-signal as the fourth sub-sampling delay of the fourth clock sub-signal; and determining the minimum sub-sampling delay from the first sub-sampling delay, the second sub-sampling delay, the third sub-sampling delay, and the fourth sub-sampling delay as the target sampling delay.
[0012] In one exemplary embodiment of this disclosure, determining the delay parameter of the DQ data signal relative to the clock signal based on the target sampling delay and the setup time includes: determining the difference between the target sampling delay and the setup time as the delay parameter.
[0013] In one exemplary embodiment of this disclosure, the method further includes: generating a test netlist based on a memory design database, the test netlist including test parameters; performing simulation based on the test parameters to determine a simulation waveform; and determining the rising and falling edges of the DQ data signal and the rising edge of each clock sub-signal based on the simulation waveform.
[0014] In one exemplary embodiment of this disclosure, the setup time is determined based on simulation results of DQ samples.
[0015] According to a second aspect of this disclosure, a delay parameter determination apparatus is provided, the apparatus comprising: an setup time determination module for determining a setup time of a clock signal in a memory relative to a DQ data signal; a target sampling delay determination module for dividing the clock signal into multiple clock sub-signals and determining a target sampling delay of the multiple clock sub-signals relative to the DQ data signal; and a delay parameter determination module for determining a delay parameter of the DQ data signal relative to the clock signal based on the target sampling delay and the setup time.
[0016] In one exemplary embodiment of this disclosure, the target sampling delay is the minimum sampling delay among the plurality of clock sub-signals relative to the DQ data signal.
[0017] In one exemplary embodiment of this disclosure, the target sampling delay determination module is used to determine the delay from the rising edge or falling edge of the DQ data signal to the rising edge of the corresponding clock sub-signal, as the sampling delay of the clock sub-signal; and to determine the minimum value among the sampling delays of multiple clock sub-signals as the target sampling delay.
[0018] In one exemplary embodiment of this disclosure, the target sampling delay determination module is configured to, when the written DQ data signal is 1010 data and there are four clock sub-signals, determine the delay from the first rising edge of the DQ data signal to the first rising edge of the first clock sub-signal as the first sub-sampling delay of the first clock sub-signal; determine the delay from the first falling edge of the DQ data signal to the second rising edge of the second clock sub-signal as the second sub-sampling delay of the second clock sub-signal; determine the delay from the second rising edge of the DQ data signal to the third rising edge of the third clock sub-signal as the third sub-sampling delay of the third clock sub-signal; determine the delay from the second falling edge of the DQ data signal to the fourth rising edge of the fourth clock sub-signal as the fourth sub-sampling delay of the fourth clock sub-signal; and determine the minimum sub-sampling delay from the first sub-sampling delay, the second sub-sampling delay, the third sub-sampling delay, and the fourth sub-sampling delay as the target sampling delay.
[0019] In one exemplary embodiment of this disclosure, the delay parameter determination module is used to determine the difference between the target sampling delay and the establishment time as the delay parameter.
[0020] In one exemplary embodiment of this disclosure, the apparatus further includes: a simulation module, configured to generate a test netlist based on a memory design database, the test netlist including test parameters; perform simulation based on the test parameters to determine a simulation waveform; and a waveform determination module, configured to determine the rising or falling edge of the DQ data signal and the rising edge of each clock sub-signal based on the simulation waveform.
[0021] In one exemplary embodiment of this disclosure, the setup time determination module is used to determine the setup time based on the simulation results of the DQ sample.
[0022] According to a third aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described delay parameter determination method.
[0023] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described delay parameter determination method by executing the executable instructions.
[0024] The technical solution provided in this disclosure may include the following beneficial effects:
[0025] In the exemplary embodiments of this disclosure, on the one hand, the delay parameter of the DQ data signal can be determined by combining the target sampling delay of multiple clock sub-signals relative to the DQ data signal based on the setup time. In other words, the problem that the clock sub-signals cannot effectively sample DQ data is solved based on the actual setup time and target sampling delay. On the other hand, the delay parameter can be automatically determined, avoiding the time-consuming and costly problems caused by manual measurement.
[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:
[0028] Figure 1 The illustration schematically shows a structure in which a clock signal is divided into four clock sub-signals according to an exemplary embodiment of the present disclosure;
[0029] Figure 2 A flowchart illustrating a delay parameter determination method according to an exemplary embodiment of the present disclosure is shown schematically.
[0030] Figure 3 The illustration schematically shows a simulated waveform diagram of a DQ data signal and four clock sub-signals according to an exemplary embodiment of the present disclosure;
[0031] Figure 4 The diagram schematically illustrates waveforms of a DQ data signal and a clock signal according to an exemplary embodiment of the present disclosure;
[0032] Figure 5 A block diagram illustrating a delay parameter determination apparatus according to an exemplary embodiment of the present disclosure is shown schematically. Figure 1 ;
[0033] Figure 6 A block diagram illustrating a delay parameter determination apparatus according to an exemplary embodiment of the present disclosure is shown schematically. Figure 2 ;
[0034] Figure 7 The illustration schematically shows a module diagram of an electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation
[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.
[0036] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.
[0037] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.
[0038] Semiconductor memories are used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices and applications. A semiconductor memory comprises multiple memory cells in a memory array, each memory cell storing at least one bit of information. DRAM is an example of such a semiconductor memory. This solution is preferably used in DRAM. Therefore, the following description of embodiments is made with reference to DRAM as a non-limiting example.
[0039] In DRAM integrated circuit devices, especially in LPDDR5 (Low Power Double Data Rate SDRAM), refer to Figure 1 During the design process, the clock signal WCK is divided into four clock sub-signals: WCKR0, WCKF0, WCKR1, and WCKF1. Ideally, as long as there are write data signals aligned with these four clock sub-signals—namely, DQR0 aligned with WCKR0, DQF0 aligned with WCKF0, DQR1 aligned with WCKR1, and DQF1 aligned with WCKF1—DQ data can be correctly sampled under all four clock sub-signals. DQ data is transmitted via DQ signals, and the signal transmitted by each data pin (DQ PAD) of the DRAM is called the DQ signal.
[0040] However, in practice, due to differences between different devices, such as process variations, the four clock sub-signals WCKR0, WCKF0, WCKR1, and WCKF1 will have varying degrees of delay, and these delays are usually difficult to detect. If DQ data is sent according to the alignment described above under these circumstances, data sampling errors can easily occur at the rising edges of the four clock phases. Therefore, it is necessary to appropriately delay the transmission of the aforementioned DQR0, DQF0, DQR1, and DQF1 signals to ensure that DQ data can be correctly captured at the rising edge. The delay transmission parameter for the aforementioned DQ signals is the delay parameter tWCK2DQI that needs to be determined in this embodiment of the disclosure.
[0041] The method for determining delay parameters provided in the exemplary embodiments of this disclosure refers to... Figure 2 This may include the following steps:
[0042] Step S210: Determine the setup time of the clock signal in the memory relative to the DQ data signal;
[0043] Step S220: Divide the clock signal into multiple clock sub-signals and determine the target sampling delay of the multiple clock sub-signals relative to the DQ data signal;
[0044] Step S230: Determine the delay parameter of the DQ data signal relative to the clock signal based on the target sampling delay and setup time.
[0045] The delay parameter determination method provided in the exemplary embodiments of this disclosure can, on the one hand, determine the delay parameter of the DQ data signal by combining the target sampling delay of multiple clock sub-signals relative to the DQ data signal based on the setup time. In other words, it solves the problem that the clock sub-signals cannot effectively sample DQ data based on the actual setup time and target sampling delay, and ensures that the correct DQ data is collected. On the other hand, it can realize the automatic determination of the delay parameter, avoiding the time-consuming and costly problems caused by manual measurement.
[0046] In the exemplary embodiments of this disclosure, simulation of the DQ sample is required during the determination of the setup time and target sampling delay. (Refer to...) Figure 3 As shown, the simulation of DQ samples refers to detecting when a correct DQR0 value can be output when different DQ data signals DQIB and clock sub-signal WCKR0 are input. If the output DQR0 value is correct, then the corresponding input DQIB and WCKR0 can be used to determine the setup time t. setup Among them, the establishment time t setup It is the delay that allows the clock signal WCK to effectively acquire data.
[0047] It should be noted that the default value of the delay parameter tWCK2DQI is 0 during the DQ Sample simulation. Therefore, the actual delay parameter tWCK2DQI can be calculated based on the simulation results of DQ Sample.
[0048] In this practical application, DQ Sample directly receives DQIB and WCKR0. WCKR0 has no delay, and different clock sub-signals can obtain corresponding different setup times t. setup Therefore, DQ Sample simulation can obtain multiple setup times t. setup .
[0049] In practical applications, a test netlist can be generated based on the memory design database. This test netlist can include test parameters, such as the initial setup time t. setup It can also be the delay time and data type of the DQ data signal DQIB, or the delay times of multiple clock sub-signals WCKR0, WCKF0, WCKR1, and WCKF1, etc. Simulation can be performed based on the test parameters to determine the simulated waveform. (Refer to...) Figure 3The simulation waveform shows a DQ data signal DQIB and four clock sub-signals WCKR0, WCKF0, WCKR1, and WCKF1. It can be seen from the simulation waveform that the four clock sub-signals WCKR0, WCKF0, WCKR1, and WCKF1 are delayed relative to the DQ data signal DQIB.
[0050] Based on the above simulation waveform, the delay parameter tWCK2DQI of the DQ data signal DQIB relative to the clock signal WCK can be determined according to the embodiments of this disclosure.
[0051] In the exemplary embodiments of this disclosure, the establishment time t setup The timeout can be determined by the simulation results of the DQ Sample under different PVT (Pressure, Voltage, and Temperature). Typically, during the simulation of the DQ Sample, the clock sub-signal has no delay, therefore the setup time t... setup It can be considered equivalent to an initial value.
[0052] At the specific establishment time t setup During the determination process, multiple setup times t can be obtained from the DQ Sample simulation. setup Typically, the multiple setup times t obtained are... setup To improve data sampling speed and allow sufficient time for subsequent sampling, data can be established at multiple time points t, depending on the size of the data. setup Choose the minimum value as the setup time t setup Setup time t under different PVT conditions setup They are also different, therefore, the corresponding setup time t can be set according to the actual situation, such as the DRAM operating environment. setup .
[0053] Correspondingly, multiple clock sub-signals are obtained by simulating the actual circuit. Once the analog circuit is determined, the corresponding sub-sampling delay is derived from it. For example, by inputting a clock signal and running the analog circuit in a simulation environment, the delayed clock sub-signals can be obtained. By setting various parameters in the analog circuit, the corresponding delay parameters can be obtained through simulation. It should be noted that the accuracy of these delay parameters depends on the degree of simulation in the analog circuit. Generally speaking, the more parameters in the analog circuit, the more accurate the result; the higher the degree of simulation, the more accurate the delay parameters.
[0054] Assume that the analog circuit obtains the following results after simulation: Figure 3 The simulated waveforms shown can be used to determine the target sampling delay t of multiple clock sub-signals relative to the DQ data signal. mainIn an exemplary embodiment of this disclosure, the target sampling delay t main It can be the minimum sampling delay t among multiple clock sub-signals relative to the DQ data signal DQIB. min .
[0055] by Figure 3 Taking the four clock sub-signals WCKR0, WCKF0, WCKR1, and WCKF1 as an example, the target sampling delay t main It can be the minimum sampling delay t of the four clock sub-signals WCKR0, WCKF0, WCKR1, and WCKF1 relative to the DQ data signal DQIB. min .
[0056] In exemplary embodiments of this disclosure, such as Figure 3 As shown, the target sampling delay t of multiple clock sub-signals WCKR0, WCKF0, WCKR1, and WCKF1 relative to the DQ data signal DQIB is determined. main The process may include: determining the delay from the rising or falling edge of the DQ data signal DQIB to the rising edge of the corresponding clock sub-signal WCKR0, WCKF0, WCKR1, or WCKF1, and using this delay as the sampling delay t1, t2, t3, t4 of the clock sub-signal; and taking the minimum value t1 among the sampling delays t1, t2, t3, t4 of multiple clock sub-signals. min The target sampling delay t is determined to be... main Where t1 is the sampling delay corresponding to clock sub-signal WCKR0, t2 is the sampling delay corresponding to clock sub-signal WCKF0, t3 is the sampling delay corresponding to clock sub-signal WCKR1, and t4 is the sampling delay corresponding to clock sub-signal WCKF1.
[0057] Specifically, determine the target sampling delay t. main The process can be determined based on the data type of the DQ data signal DQIB. For example, if the written DQ data signal DQIB is 1010 data and the clock sub-signals are four WCKR0, WCKF0, WCKR1, and WCKF1, then... Figure 3As shown, the delay from the first rising edge of the DQ data signal DQIB to the rising edge of the first clock sub-signal WCKR0 is determined as the first sub-sampling delay t1 of the first clock sub-signal WCKR0; the delay from the first falling edge of the DQ data signal DQIB to the rising edge of the second clock sub-signal WCKF0 is determined as the second sub-sampling delay t2 of the second clock sub-signal WCKF0; the delay from the second rising edge of the DQ data signal DQIB to the rising edge of the third clock sub-signal WCKR1 is determined as the third sub-sampling delay t3 of the third clock sub-signal WCKR1; and the delay from the second falling edge of the DQ data signal DQIB to the rising edge of the fourth clock sub-signal WCKF1 is determined as the fourth sub-sampling delay t4 of the fourth clock sub-signal WCKF1.
[0058] It should be noted that the above example of DQIB being 1010 is just an example. In practical applications, the data type of DQIB can be set according to actual needs, such as 0101. Depending on the data type, the specific method for determining the subsampling delay will change accordingly. This exemplary implementation will not list them one by one.
[0059] In an exemplary embodiment of this disclosure, referring to Figure 4, after determining the target sampling delay t... main and establishment time t setup Then, based on the target sampling delay t main and establishment time t setup The delay parameter tWCK2DQI of the DQ data signal DQIB relative to the clock signal WCK is determined. For example, it could be that the target sampling is delayed by t main The difference t between the establishment time and the establishment time setup The delay parameter tWCK2DQI is determined to be t, i.e., tWCK2DQI = t main -t setup =t min -t setup .
[0060] It should be noted that the target sampling delay t main The determination process uses simulated waveforms. Therefore, the rising and falling edges of the DQ data signal DQIB, as well as the rising edges of each clock sub-signal WCKR0, WCKF0, WCKR1 and WCKF1, are all determined based on the simulated waveforms. The specific simulation process can be referred to existing simulation methods, and this embodiment will not elaborate on it.
[0061] In summary, the delay parameter determination method provided by the exemplary embodiments of this disclosure can determine the target sampling delay and setup time based on the rising and falling edges of the DQ data signal and the rising edges of multiple clock sub-signals by means of simulation, after obtaining the simulation waveform. Then, based on the target sampling delay and setup time, the delay parameter of the DQ data signal relative to the clock signal is determined, thereby realizing an automated means of determining delay parameters from the data simulation level.
[0062] It should be noted that although the steps of the method in this invention are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0063] Furthermore, in this example embodiment, a delay parameter determination apparatus is also provided. (Refer to...) Figure 5 The delay parameter determination device 500 may include: a setup time determination module 510, a target sampling delay determination module 520, and a delay parameter determination module 530, wherein:
[0064] The setup time determination module 510 can be used to determine the setup time of the clock signal in the memory relative to the DQ data signal;
[0065] The target sampling delay determination module 520 can be used to divide the clock signal into multiple clock sub-signals and determine the target sampling delay of the multiple clock sub-signals relative to the DQ data signal.
[0066] The delay parameter determination module 530 can be used to determine the delay parameter of the DQ data signal relative to the clock signal based on the target sampling delay and setup time.
[0067] In one exemplary embodiment of this disclosure, the target sampling delay is the minimum sampling delay among a plurality of clock sub-signals relative to the DQ data signal.
[0068] In one exemplary embodiment of this disclosure, the target sampling delay determination module 520 can be used to determine the delay from the rising edge or falling edge of the DQ data signal to the rising edge of the corresponding clock sub-signal, as the sampling delay of the clock sub-signal; and determine the minimum value among the sampling delays of multiple clock sub-signals as the target sampling delay.
[0069] In one exemplary embodiment of this disclosure, the target sampling delay determination module 520 can be used to determine, when the written DQ data signal is 1010 data and there are four clock sub-signals, the delay from the first rising edge of the DQ data signal to the rising edge of the first clock sub-signal is the first sub-sampling delay of the first clock sub-signal; the delay from the first falling edge of the DQ data signal to the rising edge of the second clock sub-signal is the second sub-sampling delay of the second clock sub-signal; the delay from the second rising edge of the DQ data signal to the rising edge of the third clock sub-signal is the third sub-sampling delay of the third clock sub-signal; the delay from the second falling edge of the DQ data signal to the rising edge of the fourth clock sub-signal is the fourth sub-sampling delay of the fourth clock sub-signal; and determine the minimum sub-sampling delay from the first sub-sampling delay, the second sub-sampling delay, the third sub-sampling delay, and the fourth sub-sampling delay as the target sampling delay.
[0070] In one exemplary embodiment of this disclosure, the delay parameter determination module 530 can be used to determine the difference between the target sampling delay and the setup time as a delay parameter.
[0071] In one exemplary embodiment of this disclosure, reference is made to Figure 6 The delay parameter determining device 500 further includes:
[0072] The simulation module 540 can be used to generate a test netlist based on the memory design database. The test netlist includes test parameters. Simulation is performed based on the test parameters to determine the simulation waveform.
[0073] The waveform determination module 550 can be used to determine the rising or falling edge of the DQ data signal and the rising edge of each clock sub-signal based on the simulated waveform.
[0074] In one exemplary embodiment of this disclosure, the setup time determination module 510 can be used to determine the setup time based on the simulation results of the DQ sample.
[0075] The specific details of the virtual modules of each delay parameter determination device mentioned above have been described in detail in the corresponding delay parameter determination methods, so they will not be repeated here.
[0076] It should be noted that although several modules or units of the delay parameter determination device have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.
[0077] In an exemplary embodiment of this disclosure, an electronic device capable of implementing the above-described method is also provided.
[0078] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”
[0079] The following reference Figure 7 To describe an electronic device 700 according to this embodiment of the present invention. Figure 7 The electronic device 700 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.
[0080] like Figure 7 As shown, the electronic device 700 is manifested in the form of a general-purpose computing device. The components of the electronic device 700 may include, but are not limited to: at least one processing unit 710, at least one storage unit 720, a bus 730 connecting different system components (including storage unit 720 and processing unit 710), and a display unit 740.
[0081] The storage unit 720 stores program code that can be executed by the processing unit 710, causing the processing unit 710 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 710 can perform actions such as... Figure 2 The steps shown are: S210, determining the setup time of the clock signal in the memory relative to the DQ data signal; S220, dividing the clock signal into multiple clock sub-signals and determining the target sampling delay of the multiple clock sub-signals relative to the DQ data signal; and S230, determining the delay parameter of the DQ data signal relative to the clock signal based on the target sampling delay and setup time.
[0082] Storage unit 720 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 7201 and / or cache memory 7202, and may further include a read-only memory (ROM) 7203.
[0083] The storage unit 720 may also include a program / utility 7204 having a set (at least one) program module 7205, such program module 7205 including but not limited to: an operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.
[0084] Bus 730 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.
[0085] Electronic device 700 can also communicate with one or more external devices 770 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 700, and / or with any device that enables electronic device 700 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 750. Furthermore, electronic device 700 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 760. As shown, network adapter 760 communicates with other modules of electronic device 700 via bus 730. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.
[0086] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.
[0087] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section of this specification.
[0088] According to embodiments of the present invention, a program product for implementing the above-described method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on a terminal device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.
[0089] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.
[0090] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.
[0091] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.
[0092] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages such as Java and C++, and conventional procedural programming languages such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).
[0093] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.
[0094] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0095] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.
Claims
1. A method for determining a delay parameter, characterized in that, The method includes: Determine the setup time of the clock signal in the memory relative to the DQ data signal; The clock signal is divided into multiple clock sub-signals, and the target sampling delay of the multiple clock sub-signals relative to the DQ data signal is determined; Based on the target sampling delay and the setup time, the delay parameter of the DQ data signal relative to the clock signal is determined; The target sampling delay is the minimum sampling delay among the plurality of clock sub-signals relative to the DQ data signal; The step of determining the target sampling delay of the plurality of clock sub-signals relative to the DQ data signal includes: The delay from the rising edge or falling edge of the DQ data signal to the rising edge of the corresponding clock sub-signal is determined and used as the sampling delay of the clock sub-signal; The minimum value among the sampling delays of the plurality of clock sub-signals is determined as the target sampling delay; Determining the target sampling delay includes: When the DQ data signal being written is 1010 data and there are four clock sub-signals, the delay from the first rising edge of the DQ data signal to the first rising edge of the first clock sub-signal is determined to be the first sub-sampling delay of the first clock sub-signal. The delay from the first falling edge of the DQ data signal to the rising edge of the second clock sub-signal is determined as the second sub-sampling delay of the second clock sub-signal; The delay from the second rising edge of the DQ data signal to the third rising edge of the clock sub-signal is determined as the third sub-sampling delay of the third clock sub-signal; The delay from the second falling edge of the DQ data signal to the rising edge of the fourth clock sub-signal is determined as the fourth sub-sampling delay of the fourth clock sub-signal; The minimum sub-sampling delay is determined from the first sub-sampling delay, the second sub-sampling delay, the third sub-sampling delay, and the fourth sub-sampling delay, and is taken as the target sampling delay.
2. The method according to claim 1, characterized in that, The step of determining the delay parameter of the DQ data signal relative to the clock signal based on the target sampling delay and the setup time includes: The difference between the target sampling delay and the establishment time is determined as the delay parameter.
3. The method according to any one of claims 1-2, characterized in that, The method further includes: A test netlist is generated based on the memory design database, and the test netlist includes test parameters. The simulation waveform is determined by performing a simulation based on the test parameters. The rising and falling edges of the DQ data signal, as well as the rising edge of each clock sub-signal, are determined based on the simulated waveform.
4. The method according to any one of claims 1-2, characterized in that, The establishment time was determined based on the simulation results of the DQ sample.
5. A device for determining delay parameters, characterized in that, The device includes: The setup time determination module is used to determine the setup time of the clock signal in the memory relative to the DQ data signal; The target sampling delay determination module is used to divide the clock signal into multiple clock sub-signals and determine the target sampling delay of the multiple clock sub-signals relative to the DQ data signal; The delay parameter determination module is used to determine the delay parameter of the DQ data signal relative to the clock signal based on the target sampling delay and the setup time. The target sampling delay is the minimum sampling delay among the plurality of clock sub-signals relative to the DQ data signal; The target sampling delay determination module is used to determine the delay from the rising edge or falling edge of the DQ data signal to the rising edge of the corresponding clock sub-signal, as the sampling delay of the clock sub-signal; and to determine the minimum value among the sampling delays of multiple clock sub-signals as the target sampling delay. The target sampling delay determination module is configured to, when the written DQ data signal is 1010 data and there are four clock sub-signals, determine the delay from the first rising edge of the DQ data signal to the first rising edge of the first clock sub-signal as the first sub-sampling delay of the first clock sub-signal; determine the delay from the first falling edge of the DQ data signal to the second rising edge of the second clock sub-signal as the second sub-sampling delay of the second clock sub-signal; determine the delay from the second rising edge of the DQ data signal to the third rising edge of the third clock sub-signal as the third sub-sampling delay of the third clock sub-signal; determine the delay from the second falling edge of the DQ data signal to the fourth rising edge of the fourth clock sub-signal as the fourth sub-sampling delay of the fourth clock sub-signal; and determine the minimum sub-sampling delay from the first sub-sampling delay, the second sub-sampling delay, the third sub-sampling delay, and the fourth sub-sampling delay as the target sampling delay.
6. The apparatus according to claim 5, characterized in that, The delay parameter determination module is used to determine the difference between the target sampling delay and the establishment time as the delay parameter.
7. The apparatus according to any one of claims 5-6, characterized in that, The device further includes: The simulation module is used to generate a test netlist based on the memory design database, the test netlist including test parameters; and to perform simulation based on the test parameters to determine the simulation waveform. The waveform determination module is used to determine the rising or falling edge of the DQ data signal and the rising edge of each clock sub-signal based on the simulated waveform.
8. The apparatus according to any one of claims 5-6, characterized in that, The setup time determination module is used to determine the setup time based on the simulation results of the DQ sample.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the delay parameter determination method according to any one of claims 1-4.
10. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the delay parameter determination method of any one of claims 1-4 by executing the executable instructions.