Pixel circuits and display panels

Abstract

This invention provides a pixel circuit and a display panel. The pixel circuit includes a light-emitting element, a current source, a switch, a reset circuit, a first driving circuit, and a second driving circuit. The current source, switch, and reset circuit are connected in series between the light-emitting element and a first reference voltage. The first driving circuit is coupled to the current source and the switch. The first driving circuit outputs a control signal to the current source based on a second reference voltage and a third reference voltage. The current source generates a driving current according to the control signal. The second driving circuit is coupled to the switch or coupled to the switch through the first driving circuit. The second driving circuit controls whether the switch is turned on or off according to a modulation signal.

Description

Technical Field

[0001] This invention relates to a pixel circuit and a display panel, and more particularly to a pixel circuit and a display panel driven by multiple modulations. Background Technology

[0002] Generally, display panels using sub-millimeter light-emitting diodes (Mini LEDs) can be driven using pulse-amplitude modulation (PAM). However, when displaying high brightness, the PAM driving method generates excessive drive current, causing the drive transistors to operate in the linear region, making the drive current difficult to control.

[0003] On the other hand, some applications can control the magnitude of the drive current by increasing the voltage across the drive transistor to operate in the saturation region. However, the aforementioned method of increasing the voltage will increase the power consumption of the display panel. Summary of the Invention

[0004] This invention provides a pixel circuit that can accurately control the drive current and reduce power consumption during operation.

[0005] The pixel circuit of this invention includes a light-emitting element, a current source, a switch, a reset circuit, a first driving circuit, and a second driving circuit. The current source and the switch are connected in series between the light-emitting element and a first reference voltage. The reset circuit, the current source, and the switch are connected in series between the light-emitting element and the first reference voltage. The first driving circuit is coupled to the current source and the switch. The first driving circuit outputs a control signal to the current source based on a second reference voltage and a third reference voltage. The current source generates a driving current according to the control signal. The second driving circuit is coupled to the switch or coupled to the switch through the first driving circuit. The second driving circuit controls whether the switch is turned on or off according to a modulation signal.

[0006] This invention also provides a display panel. The display panel includes a pixel array and a control circuit. The pixel array includes a plurality of pixel circuits as described above. The control circuit is coupled to the pixel array. The control circuit is used to provide a first reference voltage, a second reference voltage, a third reference voltage, and a modulation signal to the pixel array.

[0007] Based on the above, the pixel circuit and display panel of the present invention enable the driving current to have a fixed current magnitude through the first driving circuit, and control the period during which the driving current is enabled by controlling whether the switch is turned on or off through the second driving circuit. This allows for accurate control of the magnitude and output time of the driving current, thereby improving the brightness consistency of the display panel and reducing power consumption during operation.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a block diagram of a pixel circuit according to an embodiment of the present invention.

[0010] Figure 2A This is a circuit diagram of a pixel circuit according to an embodiment of the present invention.

[0011] Figure 2B This is a circuit diagram of a pixel circuit according to an embodiment of the present invention.

[0012] Figure 3 Based on the present invention Figure 2A A schematic diagram of the operation of the pixel circuit shown in the embodiment.

[0013] Figures 4A to 4E Based on the present invention Figure 3 A schematic diagram of the operation of the pixel circuit shown in the embodiment.

[0014] Figure 5 This is a circuit diagram of a pixel circuit according to another embodiment of the present invention.

[0015] Figure 6 Based on the present invention Figure 5 A schematic diagram of the operation of the pixel circuit shown in the embodiment.

[0016] Figures 7A to 7F Based on the present invention Figure 6 A schematic diagram of the operation of the pixel circuit shown in the embodiment.

[0017] Figure 8 This is a block diagram of a display panel according to an embodiment of the present invention.

[0018] [Symbol Explanation]

[0019] 100, 200A, 200B, 500, 800: Pixel circuits

[0020] 110, 210, 510: Light-emitting elements

[0021] 120, 220, 520: Current source

[0022] 130, 230, 530: Switches

[0023] 140, 240, 540: Reset circuit

[0024] 150, 250, 550: First drive circuit

[0025] 160, 260, 560: Second drive circuit

[0026] 261: Modulation Circuit

[0027] 80: Display panel

[0028] 810: Pixel Array

[0029] 820: Control Circuit

[0030] C1~C4: Capacitors

[0031] EM[n]: Emitted signal

[0032] F1~F2: Image frame period

[0033] N1~N6: Nodes

[0034] P_RT, P_CT, P_EM, P_TF, P_DT: Period

[0035] S1[n]: First control signal

[0036] S1[n+1]: First control signal of the subsequent stage

[0037] S2[n]: Second control signal

[0038] T1~T13: Transistors

[0039] t1~t7: Time

[0040] VDATA: Data signal

[0041] VDD, VSS, VREF~VREF3, VH, VL: Reference voltage

[0042] VGH, VGL, VSWEEP_H, VSWEEP_M, VSWEEP_L: Voltage levels

[0043] VSWEEP: Modulated signal Detailed Implementation

[0044] Some embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Component symbols used in the following description, when appearing in different drawings, are considered to be the same or similar components. These embodiments are only a part of the present invention and do not disclose all possible implementations of the invention. More precisely, these embodiments are merely examples within the scope of the present invention's patent application.

[0045] Figure 1 This is a block diagram of a pixel circuit according to an embodiment of the present invention. Please refer to... Figure 1The pixel circuit 100 can be applied to a display device (such as a display panel) using sub-millimeter light-emitting diodes (Mini LEDs). The display device may include a plurality of pixel circuits 100 arranged in an array and a control circuit to drive the pixel circuits 100 according to a plurality of signals and / or voltages provided by the control circuit.

[0046] exist Figure 1 In the illustrated embodiment, the pixel circuit 100 includes a light-emitting element 110, a current source 120, a switch 130, a reset circuit 140, a first driving circuit 150, and a second driving circuit 160. One end of the light-emitting element 110 is coupled to the current source 120, the switch 130, and the reset circuit 140. The other end of the light-emitting element 110 receives a reference voltage VDD.

[0047] The current source 120 and the switch 130 can be connected in series between the light-emitting element 110 and the reference voltage VSS. Specifically, in this embodiment (or as shown in Figure 2), the light-emitting element 110, the current source 120, and the switch 130 are connected in series sequentially between the reference voltage VDD and the reference voltage VSS. In some embodiments (such as...) Figure 5 In the embodiment, the light-emitting element 110, the switch 130 and the current source 120 are connected in series between the reference voltage VDD and the reference voltage VSS.

[0048] The reset circuit 140 can be connected in series with the current source 120 and the switch 130 between the light-emitting element 110 and the reference voltage VSS.

[0049] The first driving circuit 150 is coupled to the current source 120 and the switch 130. The first driving circuit 150 receives reference voltages VREF and VREF2. In this embodiment, the first driving circuit 150 outputs a control signal (not shown) to the current source 120 based on the reference voltages VREF and VREF2, causing the current source 120 to generate a driving current according to the control signal and allowing the driving current to flow through the light-emitting path formed by the light-emitting element 110, the current source 120, and the switch 130. That is, the first driving circuit 150 causes the current source 120 to generate a driving current with a fixed current value. This fixed current value is related to the reference voltages VREF and VREF2. In this embodiment, the first driving circuit 150 may be, for example, a pulse-amplitude modulation (PAM) circuit to control the magnitude of the driving current.

[0050] The second drive circuit 160 can be coupled to the first drive circuit 150 so that the switch 130 can be coupled through the first drive circuit 150. Figure 1 Or as shown in the embodiment of Figure 2. The second driving circuit 160 can receive the modulated signal VSWEEP. In some embodiments (such as...) Figure 5 In the embodiment, the second drive circuit 160 can be directly coupled to the switch 130.

[0051] The second driving circuit 160 can control whether the switch 130 is turned on or off based on the modulation signal VSWEEP. Specifically, the second driving circuit 160 can turn on the switch 130 based on the modulation signal VSWEEP having a first voltage range to conduct the light-emitting path through which the driving current flows. Furthermore, the second driving circuit 160 can turn off the switch 130 based on the modulation signal VSWEEP having a second voltage range to cut off the light-emitting path through which the driving current flows. In other words, the second driving circuit 160 can control the duration for which the light-emitting path is circulated based on the modulation signal VSWEEP. The aforementioned duration is related to the voltage variation amplitude of the modulation signal VSWEEP.

[0052] For example, when the voltage value of the modulation signal VSWEEP is in a first voltage range, switch 130 can be turned on. When the voltage value of the modulation signal VSWEEP is in a second voltage range, switch 130 can be turned off. When the voltage value of the modulation signal VSWEEP switches between the first voltage range and the second voltage range, switch 130 can switch between being on and off. In this embodiment, the second driving circuit 160 may be, for example, a pulse-width modulation (PWM) circuit to control the duration of the output driving current to further control the displayed grayscale value.

[0053] It is worth mentioning that by controlling the current value of the drive current through the first drive circuit 150 and controlling the enable time of the drive current through the second drive circuit 160, it is possible to avoid the current value of the drive current being too large, causing the current source 120 to operate in the linear region. Furthermore, the pixel circuit of this embodiment can accurately control the magnitude of the drive current and the output time (i.e., pulse width) without additional boosting or bucking of the current source 120, thereby reducing drive current errors to improve brightness consistency and reducing power consumption during operation.

[0054] Figure 2A This is a circuit diagram of a pixel circuit according to an embodiment of the present invention. Please refer to... Figure 2A The light-emitting element 210, current source 220, switch 230, reset circuit 240, first driving circuit 250 and second driving circuit 260 included in the pixel circuit 200A can be referred to the relevant description of the pixel circuit 100 and deduced by analogy, so they will not be repeated here.

[0055] The first terminal (i.e., the cathode) of the light-emitting element 210 is coupled to the current source 220 and the reset circuit 240. The second terminal (i.e., the anode) of the light-emitting element 210 receives the reference voltage VDD. In this embodiment, the light-emitting element 210 may be implemented, for example, as a sub-millimeter light-emitting diode.

[0056] The current source 220 may include a first transistor T1 (i.e., a driving transistor). In this embodiment, the first transistor T1 may be implemented, for example, as a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET). The control terminal (i.e., the gate terminal) of the first transistor T1 is coupled to the first driving circuit 250 at the first node N1. The first terminal (i.e., the source terminal) of the first transistor T1 is coupled to the first terminal (i.e., the cathode terminal) of the light-emitting element 210 and the reset circuit 240. The second terminal (i.e., the drain terminal) of the first transistor T1 is coupled to the switch 230.

[0057] Switch 230 may include a second transistor T2. In this embodiment, the second transistor T2 may be implemented, for example, as a PMOSFET. The control terminal (i.e., the gate terminal) of the second transistor T2 is coupled to the second drive circuit 260 at the second node N2. The first terminal (i.e., the source terminal) of the second transistor T2 is coupled to the second terminal (i.e., the drain terminal) of the first transistor T1. The second terminal (i.e., the drain terminal) of the second transistor T2 receives a reference voltage VSS.

[0058] The first driving circuit 250 may include a third transistor T3 to a sixth transistor T6 and a first capacitor C1. In this embodiment, the third transistor T3 to the sixth transistor T6 may be implemented, for example, as a PMOSFET. The control terminal (i.e., the gate terminal) of the third transistor T3 receives the light emission signal EM[n]. The first terminal (i.e., the source terminal) of the third transistor T3 is coupled to the first terminal (i.e., the source terminal) of the first transistor T1. The second terminal (i.e., the drain terminal) of the third transistor T3 is coupled to the third node N3. The control terminal (i.e., the gate terminal) of the fourth transistor T4 receives the subsequent first control signal S1[n+1]. The first terminal (i.e., the source terminal) of the fourth transistor T4 is coupled to the second terminal (i.e., the drain terminal) of the first transistor T1 and the first terminal (i.e., the source terminal) of the second transistor T2. The second terminal (i.e., the drain terminal) of the fourth transistor T4 is coupled to the first node N1.

[0059] Continuing the above description, the first terminal of the first capacitor C1 is coupled to the first node N1. The second terminal of the first capacitor C1 is coupled to the second terminal (i.e., the drain terminal) of the third transistor T3 at the third node N3. The control terminal (i.e., the gate terminal) of the fifth transistor T5 receives the second control signal S2[n]. The first terminal (i.e., the source terminal) of the fifth transistor T5 is coupled to the third node N3. The second terminal (i.e., the drain terminal) of the fifth transistor T5 receives the reference voltage VREF2. The control terminal (i.e., the gate terminal) of the sixth transistor T6 receives the first control signal S1[n]. The first terminal (i.e., the source terminal) of the sixth transistor T6 receives the reference voltage VL. The second terminal (i.e., the drain terminal) of the sixth transistor T6 is coupled to the first node N1.

[0060] The second driving circuit 260 may include a seventh transistor T7 to an eleventh transistor T11, a modulation circuit 261, a second capacitor C2, and a third capacitor C3. The modulation circuit 261 may include a twelfth transistor T12. In this embodiment, the seventh transistor T7 to the twelfth transistor T12 may be implemented, for example, as a PMOSFET. The first terminal of the second capacitor C2 is coupled to the control terminal (i.e., the gate terminal) of the second transistor T2 at the second node N2. The second terminal of the second capacitor C2 receives the light emission signal EM[n]. The control terminal (i.e., the gate terminal) of the seventh transistor T7 is coupled to the fourth node N4. The first terminal (i.e., the source terminal) of the seventh transistor T7 is coupled to the second node N2. The second terminal (i.e., the drain terminal) of the seventh transistor T7 receives a reference voltage VREF. The control terminal (i.e., the gate terminal) of the eighth transistor T8 receives a first control signal S1[n]. The first terminal (i.e., the source terminal) of the eighth transistor T8 receives a reference voltage VL. The second terminal (i.e., the drain terminal) of the eighth transistor T8 is coupled to the control terminal (i.e., the gate terminal) of the seventh transistor T7 at the fourth node N4. The control terminal (i.e., gate terminal) of the ninth transistor T9 receives the first control signal S1[n+1] from the subsequent stage. The first terminal (i.e., source terminal) of the ninth transistor T9 is coupled to the fourth node N4. The control terminal (i.e., gate terminal) and the first terminal (i.e., source terminal) of the tenth transistor T10 are coupled together and coupled to the second terminal (i.e., drain terminal) of the ninth transistor T9. The second terminal (i.e., drain terminal) of the tenth transistor T10 receives the data signal VDATA.

[0061] Continuing the above explanation, the first terminal of the third capacitor C3 is coupled to the fourth node N4. The second terminal of the third capacitor C3 is coupled to the fifth node N5. The control terminal (i.e., the gate terminal) of the eleventh transistor T11 receives the second control signal S2[n]. The first terminal (i.e., the source terminal) of the eleventh transistor T11 is coupled to the second terminal of the third capacitor C3 at the fifth node N5. The second terminal (i.e., the drain terminal) of the eleventh transistor T11 receives the reference voltage VH. The control terminal (i.e., the gate terminal) of the twelfth transistor T12 receives the modulation signal VSWEEP. The first terminal (i.e., the source terminal) of the twelfth transistor T12 is coupled to the fifth node N5. The second terminal (i.e., the drain terminal) of the twelfth transistor T12 receives the reference voltage VL.

[0062] In this embodiment, the seventh transistor T7 and the tenth transistor T10 are matched. Specifically, the seventh transistor T7 and the tenth transistor T10 have the same size, threshold voltage value, and other transistor-related parameters.

[0063] The reset circuit 240 may include a thirteenth transistor T13. In this embodiment, the thirteenth transistor T13 may be implemented, for example, as a PMOSFET. The control terminal (i.e., gate terminal) of the thirteenth transistor T13 receives a subsequent first control signal S1[n+1]. The first terminal (i.e., source terminal) of the thirteenth transistor T13 receives a reference voltage VREF. The second terminal (i.e., drain terminal) of the thirteenth transistor T13 is coupled to the first terminal (i.e., source terminal) of the first transistor T1, the first terminal (i.e., cathode terminal) of the light-emitting element 210, and the first terminal (i.e., source terminal) of the third transistor T3.

[0064] In some embodiments, the first transistor T1 through the thirteenth transistor T13 may be implemented, for example, as an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET). In some embodiments, the signal is inverted to the corresponding signal in this embodiment.

[0065] Figure 2B This is a circuit diagram of a pixel circuit according to an embodiment of the present invention. Please refer to... Figure 2B The light-emitting element 210, current source 220, switch 230, reset circuit 240, first driving circuit 250 and second driving circuit 260 included in the pixel circuit 200B can be referred to the relevant description of the pixel circuit 200A and deduced by analogy, so they will not be repeated here.

[0066] Compared to Figure 2AIn one embodiment, the modulation circuit 261 may include a fourth capacitor C4, and the twelfth transistor T12 may be replaced by the fourth capacitor C4. A first terminal of the fourth capacitor C4 is coupled to a fifth node N5. A second terminal of the fourth capacitor C4 receives the modulation signal VSWEEP.

[0067] Figure 3 Based on the present invention Figure 2A A schematic diagram of the operation of the pixel circuit shown in the embodiment. Figures 4A to 4E Based on the present invention Figure 3 A schematic diagram illustrating the operation of the pixel circuitry in the embodiment. Figure 3 In the diagram, the horizontal axis represents the operating time of the pixel circuit 200A, and the vertical axis represents the voltage value. In some embodiments, the operation of the pixel circuit 200B can be deduced by referring to the relevant description of the pixel circuit 200A, and therefore will not be repeated here.

[0068] For details regarding the operation of pixel circuit 200A during the reset phase in P_RT, please also refer to... Figure 3 as well as Figure 4A At time t1, during the first image frame period F1, the first control signal S1[n] and the second control signal S2[N] generate falling edges to be pulled from the disable voltage level VGH to the enable voltage level VGL, and the reset phase begins. At time t2, the reset phase ends.

[0069] In this embodiment, the reference signal VDD may be, for example, a first high-voltage source signal. The reference signal VSS may be, for example, a first low-voltage source signal or a ground signal. The reference signal VH may be, for example, a second high-voltage source signal. The reference signal VL may be, for example, a second low-voltage source signal or a ground signal. The disable voltage level VGH may be higher than the voltage values ​​of the reference signals VDD and / or VH, or may be, for example, a logic high level. The enable voltage level VGL may be lower than the voltage values ​​of the reference signals VSS and / or VL, or may be, for example, a logic low level. The reference signals VREF and VREF2 may be, for example, signals with different voltage values, and the aforementioned voltage values ​​may be within the range between the voltage values ​​of the reference signals VDD, VGH, and / or VH and the voltage values ​​of the reference signals VSS, VGL, and / or VL.

[0070] Specifically, during the reset phase P_RT (i.e., time t1 to t2), the subsequent first control signal S1[n+1] is disabled by a disable voltage level VGH to turn off the thirteenth transistor T13, the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10. The light emission signal EM[n] is disabled by a disable voltage level VGH to turn off the third transistor T3. The modulation signal VSWEEP is disabled by a disable voltage level VSWEEP_H to turn off the twelfth transistor T12. The first control signal S1[n] is enabled by an enable voltage level VGL to turn on the sixth transistor T6 and the eighth transistor T8, so that the voltages at the first node N1 and the fourth node N4 are respectively pulled to the reference voltage VL. The second control signal S2[N] is enabled by an enable voltage level VGL to turn on the fifth transistor T5 and the eleventh transistor T11, so that the voltage at the third node N3 is pulled to the reference voltage VREF2, and the voltage at the fifth node N5 is pulled to the reference voltage VH. Because the voltage at node N4 is pulled to the reference voltage VL, transistor T7 is turned on, causing the voltage at node N2 to be pulled to the reference voltage VREF, which in turn turns off transistor T2. Because the voltage at node N1 is pulled to the reference voltage VL, transistor T1 is turned on. During this period P_RT, the voltages at nodes N1 through N5 are reset respectively.

[0071] For details regarding the operation of pixel circuit 200A during the compensation phase in P_CT, please also refer to... Figure 3 as well as Figure 4B At time t2, the first control signal S1[n] generates a rising edge, pulling the enable voltage level VGL to the disable voltage level VGH. The subsequent first control signal S1[n+1] generates a falling edge, and the compensation phase begins. At time t3, the compensation phase ends.

[0072] In this embodiment, the modulation signal VSWEEP may have a triangular pulse or other ramp wave. The disable voltage level VSWEEP_H may be the same as the disable voltage level VGH. The enable voltage level VSWEEP_L may be the same as the enable voltage level VGL. In this embodiment, the modulation signal VSWEEP may be, for example, a signal shared with other pixel circuits, for use in a synchronous light-emitting display panel.

[0073] In detail, during the compensation phase P_CT (i.e., time t2 to t3), the subsequent first control signal S1[n+1] is enabled by the enable voltage level VGL to conduct the thirteenth transistor T13, the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10. At this time, the voltage at the fourth node N4 can be implemented as shown in the following formula (1). In formula (1), VN4 is the voltage at the fourth node N4, and VTH_T10 is the critical voltage value of the tenth transistor T10.

[0074] VN4=VDATA-|VTH_T10| Formula (1)

[0075] It should be noted that since the seventh transistor T7 and the tenth transistor T10 have the same critical voltage value, the critical voltage value of the seventh transistor T7 (i.e., VTH_T10 in formula (1)) is compensated to the fourth node N4 to ensure that the emission time is consistent under the same gray level and thus the emission brightness is consistent.

[0076] Continuing the above explanation, the voltage at the fourth node N4 turns off the seventh transistor T7. The voltage at the second node N2 is maintained at the reference voltage VREF to turn off the second transistor T2. The light emission signal EM[n] is disabled by the disable voltage level VGH to turn off the third transistor T3. The modulation signal VSWEEP is disabled by the disable voltage level VSWEEP_H to turn off the twelfth transistor T12. The first control signal S1[n] is disabled by the disable voltage level VGH to turn off the sixth transistor T6 and the eighth transistor T8. The second control signal S2[N] is enabled by the enable voltage level VGL to turn on the fifth transistor T5 and the eleventh transistor T11, so that the voltage at the third node N3 is pulled to the reference voltage VREF2 and the voltage at the fifth node N5 is pulled to the reference voltage VH. The first transistor T1 is turned on. At this time, the voltage at the first node N1 can be realized as shown in the following formula (2). In formula (2), VN1 is the voltage at the first node N1, and VTH_T2 is the critical voltage value of the first transistor T1.

[0077] VN1=VREF-|VTH_T1| Formula (2)

[0078] It should be noted that during this period, within P_CT, the thirteenth transistor T13, the first transistor T1, and the fourth transistor T4 are all turned on and connected sequentially to form a diode connection architecture, so that the critical voltage value of the first transistor T1 is compensated to the first node N1. Therefore, through the aforementioned connection architecture, it is possible to compensate itself (i.e., the first transistor T1) to improve the compensation accuracy.

[0079] For details regarding the operation of the pixel circuit 200A within the P_EM during the light-emitting phase, please also refer to... Figure 3 as well as Figure 4C , 4D At time t3, the first control signal S1[n+1] and the second control signal S2[N] of the subsequent stage generate rising edges, the light emission signal EM[n] generates a falling edge, and the modulation signal VSWEEP begins to generate triangular pulses to be linearly pulled from the disable voltage level VSWEEP_H to the enable voltage level VSWEEP_L, and the light emission stage begins. At time t4, the light emission stage ends.

[0080] In this embodiment, the light-emitting phase P_EM can be divided into a first period (times t3 to t3-1) and a second period (times t3-1 to t4). At time t3-1, the modulation signal VSWEEP has a voltage level VSWEEP_M to switch the conduction state of the seventh transistor T7 (e.g., from off to on). The voltage level VSWEEP_M is within the range between the disable voltage level VSWEEP_H and the enable voltage level VSWEEP_L.

[0081] In detail, such as Figure 3 as well as Figure 4C As shown, during the first period of the light-emitting phase P_EM (i.e., time t3 to t3-1), the subsequent first control signal S1[n+1] is disabled by a disable voltage level VGH to turn off the thirteenth transistor T13, the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10. The first control signal S1[n] is disabled by a disable voltage level VGH to turn off the sixth transistor T6 and the eighth transistor T8. The light-emitting signal EM[n] is enabled by an enable voltage level VGL to turn on the third transistor T3. The second control signal S2[N] is disabled by a disable voltage level VGH to turn off the fifth transistor T5 and the eleventh transistor T11. At this time, the voltage at the third node N3 is pulled to the difference between the reference voltage VDD and the voltage difference of the light-emitting element 210 (i.e., the current-resistance voltage drop (IR Drop)). The voltage change at the third node N3 is coupled to the first node N1 through the first capacitor C1 to turn on the first transistor T1 and generate a drive current. The voltage at the first node N1 can be realized as shown in the following formula (3). Formula (3) can be found in the relevant explanation of formula (2), where VLED is the voltage difference of the light-emitting element 210.

[0082] VN1=VREF-|VTH_T2|+(VDD-VLED-VREF2) Formula (3)

[0083] It should be noted that during the early stage of P_EM, the driving current flowing through the light-emitting element 210 is compensated for by the IR drop of the reference voltage VDD and transferred to the third node N3 to reduce the error of the driving current and improve the uniformity of brightness. At this time, the light-emitting element 210 can operate at the point of highest luminous efficiency to save power consumption. In addition, the driving current has a fixed current value, and the aforementioned current value is related to the difference between the reference voltage VREF and VREF2.

[0084] Continuing the above explanation, the modulation signal VSWEEP has a portion of triangular pulses to gradually turn on the twelfth transistor T12. The aforementioned portion of the triangular pulses is a linear waveform between the disable voltage level VSWEEP_H and the voltage level VSWEEP_M, causing the voltage at the fifth node N5 to gradually decrease. The voltage change at the fifth node N5 is coupled to the fourth node N4 through the third capacitor C3 to turn off the seventh transistor T7. The voltage change of the light-emitting signal EM[n] is coupled to the second node N2 through the second capacitor C2 to turn on the second transistor T2, thereby outputting a drive current to the light-emitting element 210.

[0085] like Figure 3 as well as Figure 4D As shown, during the second period of P_EM in the light-emitting phase (i.e., from time t3-1 to t4), the difference from the first period is that the modulation signal VSWEEP has another portion of triangular pulses to fully turn on the twelfth transistor T12. This other portion of the triangular pulses is a linear waveform between the voltage level VSWEEP_M and the enable voltage level VSWEEP_L, causing the voltage at the fifth node N5 to gradually decrease. The voltage change at the fifth node N5 is coupled to the fourth node N4 through the third capacitor C3 to turn on the seventh transistor T7. At this time, the voltage at the second node N2 is pulled to the reference voltage VREF to turn off the second transistor T2, thereby cutting off the drive current output to the light-emitting element 210.

[0086] In this embodiment, the modulation signal VSWEEP can control when the twelfth transistor T12 is turned on during the light-emitting phase P_EM, so as to further control when the drive current is cut off. That is, the modulation signal VSWEEP can control the light-emitting time of the light-emitting element 210 to accurately adjust the grayscale value.

[0087] For details regarding the operation of pixel circuit 200A within P_TF during the turn-off phase, please also refer to... Figure 3 as well as Figure 4EAt time t4, the light emission signal EM[n] and the modulation signal VSWEEP generate rising edges and begin the turn-off phase. At time t5, the first image frame period F1 is switched to the second image frame period F2. At time t6, the turn-off phase ends in the second image frame period F2.

[0088] Specifically, during the turn-off phase P_TF (i.e., times t4 to t6), the subsequent first control signal S1[n+1] is disabled by a disable voltage level VGH to turn off the thirteenth transistor T13, the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10. The light emission signal EM[n] is disabled by a disable voltage level VGH to turn off the third transistor T3. The modulation signal VSWEEP is disabled by a disable voltage level VSWEEP_H to turn off the twelfth transistor T12. The first control signal S1[n] is disabled by a disable voltage level VGH to turn off the sixth transistor T6 and the eighth transistor T8. The second control signal S2[N] is disabled by a disable voltage level VGH to turn off the fifth transistor T5 and the eleventh transistor T11. At this time, the voltage at the fourth node N4 is maintained at the voltage of P_EM in the previous period to turn on the seventh transistor T7. The voltage at the second node N2 is maintained at the reference voltage VREF to turn off the second transistor T2.

[0089] Figure 5 This is a circuit diagram of a pixel circuit according to another embodiment of the present invention. Please refer to... Figure 5 The light-emitting element 510, current source 520, switch 530, reset circuit 540, first driving circuit 550 and second driving circuit 560 included in the pixel circuit 500 can be referred to the relevant descriptions of pixel circuits 100 and 200A and deduced by analogy, so they will not be repeated here.

[0090] The first terminal (i.e., the cathode) of the light-emitting element 510 is coupled to the switch 530. The second terminal (i.e., the anode) of the light-emitting element 510 receives the reference voltage VDD.

[0091] The current source 520 may include a first transistor T1 (i.e., a drive transistor). In this embodiment, the first transistor T1 may be implemented, for example, as a PMOSFET. The control terminal (i.e., the gate terminal) of the first transistor T1 is coupled to the first drive circuit 550 at the first node N1. The first terminal (i.e., the source terminal) of the first transistor T1 is coupled to the third node N3. The second terminal (i.e., the drain terminal) of the first transistor T1 receives a reference voltage VSS.

[0092] Switch 530 may include a second transistor T2. In this embodiment, the second transistor T2 may be implemented, for example, as a PMOSFET. The control terminal (i.e., gate terminal) of the second transistor T2 is coupled to the first driving circuit 550 and the second driving circuit 560 at the second node N2. The first terminal (i.e., source terminal) of the second transistor T2 is coupled to the first terminal (i.e., cathode terminal) of the light-emitting element 510. The second terminal (i.e., drain terminal) of the second transistor T2 is coupled to the first terminal (i.e., source terminal) of the first transistor T1, the first driving circuit 550, and the reset circuit 540 at the third node N3.

[0093] The first driving circuit 550 may include a third transistor T3 to a fifth transistor T5 and a first capacitor C1 to a second capacitor C2. In this embodiment, the third transistor T3 may be implemented, for example, as an NMOSFET. The fourth transistor T4 and the fifth transistor T5 may be implemented, for example, as PMOSFETs. The control terminal (i.e., the gate terminal) of the third transistor T3 receives the light emission signal EM[n]. The first terminal (i.e., the source terminal) of the third transistor T3 receives the reference voltage VREF2. The second terminal (i.e., the drain terminal) of the third transistor T3 is coupled to a fourth node N4. The control terminal (i.e., the gate terminal) of the fourth transistor T4 is coupled to a second node N2. The first terminal (i.e., the source terminal) of the fourth transistor T4 is coupled to the second terminal (i.e., the drain terminal) of the third transistor T3 at the fourth node N4. The second terminal (i.e., the drain terminal) of the fourth transistor T4 is coupled to a first node N1.

[0094] Continuing the above description, the control terminal (i.e., gate terminal) of the fifth transistor T5 receives the first control signal S1[n]. The first terminal (i.e., source terminal) of the fifth transistor T5 is coupled to the first node N1. The second terminal (i.e., drain terminal) of the fifth transistor T5 receives the reference voltage VREF. The first terminals of the first capacitor C1 and the second capacitor C2 are both coupled to the third node N3. The second terminal of the first capacitor C1 is coupled to the fourth node N4. The second terminal of the second capacitor C2 receives the reference voltage VREF.

[0095] The second driving circuit 560 may include a sixth transistor T6 through an eleventh transistor T11 and a third capacitor C3. In this embodiment, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 may be implemented, for example, as NMOSFETs. The ninth transistor T9 and the eleventh transistor T11 may be implemented, for example, as PMOSFETs. The control terminal (i.e., the gate terminal) of the sixth transistor T6 is coupled to the fifth node N5. The first terminal (i.e., the source terminal) of the sixth transistor T6 receives a reference voltage VREF2. The second terminal (i.e., the drain terminal) of the sixth transistor T6 is coupled to the second node N2. The control terminal (i.e., the gate terminal) of the seventh transistor T7 receives a light emission signal EM[n]. The first terminal (i.e., the source terminal) of the seventh transistor T7 is coupled to the second node N2. The second terminal (i.e., the drain terminal) of the seventh transistor T7 receives a reference voltage VREF3. The control terminal (i.e., the gate terminal) of the eighth transistor T8 receives a light emission signal EM[n]. The first terminal (i.e., the source terminal) of the eighth transistor T8 receives a reference voltage VREF2. The second terminal (drain terminal) of the eighth transistor T8 is coupled to the control terminal (gate terminal) of the sixth transistor T6 at the fifth node N5. The control terminal (gate terminal) of the ninth transistor T9 receives the modulation signal VSWEEP. The first terminal (source terminal) of the ninth transistor T9 is coupled to the fifth node N5. The second terminal (drain terminal) of the ninth transistor T9 is coupled to the sixth node N6.

[0096] Continuing the above explanation, the first terminal of the third capacitor C3 is coupled to the second terminal (i.e., the drain terminal) of the ninth transistor T9 at the sixth node N6. The second terminal of the third capacitor C3 receives the reference voltage VREF2. The control terminal (i.e., the gate terminal) of the tenth transistor T10 receives the light emission signal EM[n]. The first terminal (i.e., the source terminal) of the tenth transistor T10 is coupled to the sixth node N6. The second terminal (i.e., the drain terminal) of the tenth transistor T10 is coupled to the first terminal (i.e., the source terminal) of the eleventh transistor T11. The control terminal (i.e., the gate terminal) of the eleventh transistor T11 receives the data signal VDATA. The second terminal (i.e., the drain terminal) of the eleventh transistor T11 receives the subsequent first control signal S1[n+1].

[0097] In this embodiment, the ninth transistor T9 and the eleventh transistor T11 are matched. Specifically, the ninth transistor T9 and the eleventh transistor T11 have the same size, threshold voltage value, and other transistor-related parameters.

[0098] The reset circuit 540 may include a twelfth transistor T12 and a thirteenth transistor T13. In this embodiment, the twelfth transistor T12 and the thirteenth transistor T13 may be implemented, for example, as PMOSFETs. The control terminal (i.e., the gate terminal) of the twelfth transistor T12 receives a second control signal S2[n]. The first terminal (i.e., the source terminal) of the twelfth transistor T12 is coupled to a third node N3. The second terminal (i.e., the drain terminal) of the twelfth transistor T12 receives a reference voltage VREF3. The control terminal (i.e., the gate terminal) of the thirteenth transistor T13 receives the second control signal S2[n]. The first terminal (i.e., the source terminal) of the thirteenth transistor T13 is coupled to a first node N1. The second terminal (i.e., the drain terminal) of the thirteenth transistor T13 receives the reference voltage VREF3.

[0099] In some embodiments, these transistors T1 to T13 may be implemented, for example, as another type of metal-oxide-semiconductor field-effect transistor, such as... Figure 5 The PMOSFET shown is replaced with an NMOSFET, and the NMOSFET is replaced with a PMOSFET. In some embodiments, the signal is reversed to the corresponding signal in this embodiment.

[0100] Figure 6 Based on the present invention Figure 5 A schematic diagram of the operation of the pixel circuit shown in the embodiment. Figures 7A to 7F Based on the present invention Figure 6 A schematic diagram illustrating the operation of the pixel circuitry in the embodiment. Figure 6 In the diagram, the horizontal axis represents the operation time of pixel circuit 500, and the vertical axis represents the voltage value.

[0101] For details regarding the operation of pixel circuit 500 during the reset phase in P_RT, please refer to [link / reference needed]. Figure 6 as well as Figure 7A At time t1, during the first image frame period F1, the second control signal S2[N] generates a rising edge to pull the enable voltage level VGL to the disable voltage level VG, and the reset phase begins. At time t2, the first image frame period F1 is switched to the second image frame period F2. At time t3, the reset phase ends.

[0102] Specifically, during the reset phase P_RT (i.e., time t1 to t3), the second control signal S2[N] is disabled by a disable voltage level VGH to turn off the twelfth transistor T12 and the thirteenth transistor T13. The light-emitting signal EM[n] is enabled by an enable voltage level VGH to turn on the third transistor T3, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10, so that the voltage at the fourth node N4 is pulled to the reference voltage VREF2, the voltage at the second node N2 is pulled to the reference voltage VREF3, and the voltage at the fifth node N5 is pulled to the reference voltage VREF2. Because the voltage at the second node N2 is pulled to the reference voltage VREF3, the second transistor T2 is turned off to prevent the light-emitting element 510 from emitting light, and the fourth transistor T4 is turned off. Because the voltage at the fifth node N5 is pulled to the reference voltage VREF2, the sixth transistor T6 is turned off. The data signal VDATA (not shown in the diagram) Figure 6 The eleventh transistor T11 is enabled by the enable voltage level VGL, so that the voltage at the sixth node N6 is the difference between the voltage level VGH and the critical voltage value of the tenth transistor T10. The modulation signal VSWEEP is disabled by the disable voltage level VSWEEP_H, so that the ninth transistor T9 is turned off. The first control signal S1[n] is disabled by the disable voltage level VGH, so that the fifth transistor T5 is turned off. At this time, the first transistor T1 is turned off.

[0103] For details regarding the operation of pixel circuit 500 during the compensation phase in P_CT, please also refer to... Figure 6 as well as Figure 7B At time t3, the first control signal S1[n] generates a falling edge to be pulled from the disable voltage level VGH to the enable voltage level VGL, and the compensation phase begins. At time t4, the compensation phase ends.

[0104] Specifically, during the compensation phase P_CT (i.e., time t3 to t4), the second control signal S2[N] is disabled by a disable voltage level VGH to turn off the twelfth transistor T12 and the thirteenth transistor T13. The light emission signal EM[n] is enabled by an enable voltage level VGH to turn on the third transistor T3, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10, causing the voltage at the fourth node N4 to be pulled to the reference voltage VREF2, the voltage at the second node N2 to be pulled to the reference voltage VREF3, and the voltage at the fifth node N5 to be pulled to the reference voltage VREF2. Because the voltage at the second node N2 is pulled to the reference voltage VREF3, the second transistor T2 and the fourth transistor T4 are turned off. Because the voltage at the fifth node N5 is pulled to the reference voltage VREF2, the sixth transistor T6 is turned off. The data signal VDATA is enabled by an enable voltage level VGL to turn on the eleventh transistor T11. The modulation signal VSWEEP is disabled by the disable voltage level VSWEEP_H to turn off the ninth transistor T9. The first control signal S1[n] is enabled by the enable voltage level VGL to turn on the fifth transistor T5, so that the voltage on the first node N1 is pulled to the reference voltage VREF. Since the voltage on the first node N1 is pulled to the reference voltage VREF, the first transistor T1 is turned on and operates as a source follower. At this time, the voltage on the third node N3 can be realized as shown in the following formula (4). In formula (4), VN3 is the voltage on the third node N3, and VTH_T1 is the critical voltage value of the first transistor T1.

[0105] VN3=VREF+|VTH_T1| Formula (4)

[0106] It should be noted that by operating the first transistor T1 as a source follower, the critical voltage value of the first transistor T1 (i.e., VTH_T1 in formula (4)) is compensated to the third node N3 to ensure that the emission time is consistent under the same gray level and thus the emission brightness is consistent.

[0107] For details regarding the operation of pixel circuit 500 during the data writing phase P_DT, please refer to [the relevant documentation / reference]. Figure 6 as well as Figure 7C At time t4, the first control signal S1[n+1] of the subsequent stage generates a falling edge, and the compensation phase begins. At time t5, the data writing phase ends.

[0108] During the data writing phase P_DT (i.e., time t4 to t5), the operation of pixel circuit 500 can be referenced to the operation of pixel circuit 500 during the reset phase P_RT. The difference is that the voltage on the sixth node N6 is gradually discharged to a specific voltage value, and can be implemented as shown in the following formula (5). In formula (5), VN6 is the voltage on the sixth node N6, and VTH_T11 is the critical voltage value of the eleventh transistor T11.

[0109] VN6=VDATA+|VTH_T11| Formula (5)

[0110] It should be noted that since the ninth transistor T9 and the eleventh transistor T11 have the same critical voltage value, the critical voltage value of the ninth transistor T9 (i.e., VTH_T11 in formula (5)) is compensated to the sixth node N6 to improve the compensation accuracy and simplify the architecture of the second drive circuit 560 (i.e., the PWM circuit).

[0111] For details regarding the operation of pixel circuit 500 during the light-emitting phase within P_EM, please also refer to... Figure 6 as well as Figure 7D , 7E At time t5, the first control signal S1[n] generates a rising edge, the light emission signal EM[n] generates a falling edge, and the modulation signal VSWEEP begins to generate a triangular pulse to be linearly pulled from the disable voltage level VSWEEP_H to the enable voltage level VSWEEP_L, thus initiating the light emission phase. At time t6, the light emission phase ends.

[0112] In this embodiment, the light-emitting phase P_EM can be divided into a first period (time t5 to t5-1) and a second period (time t5-1 to t6). At time t5-1, the modulation signal VSWEEP has a voltage level VSWEEP_M to switch the conduction state of the ninth transistor T9 (e.g., switching from on to off).

[0113] In detail, such as Figure 6 as well as Figure 7DAs shown, during the first period of the light-emitting phase P_EM (i.e., time t5 to t5-1), the second control signal S2[N] is disabled by a disable voltage level VGH to turn off the twelfth transistor T12 and the thirteenth transistor T13. The light-emitting signal EM[n] is disabled by a disable voltage level VGL to turn off the third transistor T3, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10. The data signal VDATA is disabled by a disable voltage level VGH to turn off the eleventh transistor T11. The first control signal S1[n] is disabled by a disable voltage level VGH to turn off the fifth transistor T5. At this time, the second transistor T2 and the first transistor T1 are turned off.

[0114] Continuing the above explanation, the modulation signal VSWEEP has a portion of triangular pulses to gradually turn on the ninth transistor T9. This portion of the triangular pulses is a linear waveform between the disable voltage level VSWEEP_H and the voltage level VSWEEP_M, so that the voltage on the fifth node N5 is gradually pulled up to the voltage on the sixth node N6. At this time, the sixth transistor T6 is turned off.

[0115] like Figure 6 as well as Figure 7E As shown, during the second period of P_EM in the light-emitting phase (i.e., from time t5-1 to t6), the difference from the first period is that the modulation signal VSWEEP has another part of triangular pulses to fully turn on the ninth transistor T9. The aforementioned other part of the triangular pulses is a linear waveform between the voltage level VSWEEP_M and the enable voltage level VSWEEP_L, so that the voltage on the fifth node N5 is pulled to the voltage on the sixth node N6 (i.e., the voltage shown in formula (5)).

[0116] It should be noted that when the ninth transistor T9 is fully turned on, the fifth node N5 and the sixth node N6 can quickly turn on the sixth transistor T6 through charge sharing. Accordingly, the turned-on sixth transistor T6 can avoid being affected by the critical voltage value of the sixth transistor T6 and operate quickly in the linear region, so that the voltage on the second node N2 is pulled to the reference voltage VREF2, achieving a rapid voltage boosting effect and accelerating the driving time of the light-emitting element 510.

[0117] Because the voltage at the second node N2 is pulled to the reference voltage VREF2, the second transistor T2 is turned on, so that the voltage at the third node N3 is the difference between the voltage level VDD and the voltage difference of the light-emitting element 510. Furthermore, the fourth transistor T4 is turned on. The voltage change at the third node N3 is coupled to the fourth node N4 through the first capacitor C1 to turn on the seventh transistor T7. At this time, the first node N1 and the fourth node N4 have the same voltage, so that the first transistor T1 is turned on to output drive current to the light-emitting element 510.

[0118] It should be noted that the voltage on the second node N2 can simultaneously turn on the second transistor T2 and the fourth transistor T4, and turn on the first transistor T1 through capacitive coupling, thus enabling a rapid output of drive current to drive the light-emitting element 510.

[0119] At this time, the voltage on the first node N1 can be realized as shown in the following formula (6). In formula (6), VN1 is the voltage on the first node N1, VTH_T1 is the critical voltage value of the first transistor T1, and VLED is the voltage difference of the light-emitting element 510.

[0120] VN1=VREF2+(VDD-VLED-VREF)-|VTH_T1| Formula (6)

[0121] During the later stages of P_EM, the driving current flowing through the light-emitting element 510 is compensated for by the IRDrop of the reference voltage VDD and transferred to the first node N1 to reduce driving current errors and improve brightness uniformity. At this time, the light-emitting element 510 can operate at its highest luminous efficiency point to save power consumption. Furthermore, the driving current has a fixed value, and this value is related to the difference between the reference voltages VREF and VREF2.

[0122] In this embodiment, the modulation signal VSWEEP can control when the sixth transistor T6 is turned on during the light-emitting phase P_EM so that the second transistor T2 and the fourth transistor T4 are simultaneously turned on through the voltage on the second node N2, thereby further controlling when the drive current is output. In other words, the modulation signal VSWEEP can control the light-emitting time of the light-emitting element 510 to accurately adjust the grayscale value.

[0123] For details regarding the operation of pixel circuit 500 within P_TF during the turn-off phase, please refer to [link / reference needed]. Figure 6 as well as Figure 7F At time t6, the second control signal S2[N] generates a falling edge, and the light emission signal EM[n] and the modulation signal VSWEEP generate rising edges, thus initiating the turn-off phase. At time t7, the second control signal S2[N] generates a rising edge, thus ending the turn-off phase.

[0124] Specifically, during the turn-off phase P_TF (i.e., time t6 to t7), the second control signal S2[N] is enabled with an enable voltage level VGL to turn on the twelfth transistor T12 and the thirteenth transistor T13, causing the voltage at the third node N3 to be pulled to the reference voltage VREF3, and the voltage at the first node N1 to be pulled to the reference voltage VREF3. Since the voltage at the first node N1 is pulled to the reference voltage VREF3, the first transistor T1 is turned off. The light emission signal EM[n] is enabled with an enable voltage level VGH to turn on the third transistor T3, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10, causing the voltage at the fourth node N4 to be pulled to the reference voltage VREF2, the voltage at the second node N2 to be pulled to the reference voltage VREF3, and the voltage at the fifth node N5 to be pulled to the reference voltage VREF2. Since the voltage at the second node N2 is pulled to the reference voltage VREF3, the second transistor T2 and the fourth transistor T4 are turned off. Because the voltage at node N5 is pulled to the reference voltage VREF2, transistor T6 is turned off. The data signal VDATA is enabled by the enable voltage level VGL to turn on transistor T11. The modulation signal VSWEEP is disabled by the disable voltage level VSWEEP_H to turn off transistor T9. The first control signal S1[n] is disabled by the disable voltage level VGL to turn off transistor T5.

[0125] Figure 8 This is a block diagram of a display panel according to an embodiment of the present invention. Please refer to... Figure 8 The display panel 80 includes a pixel array 810 and a control circuit 820. The control circuit 820 is coupled to the pixel array 810. The control circuit 820 can provide multiple reference voltages and control signals to the pixel array 810. The aforementioned voltages and signals may include reference voltages VDD, VSS, VREF, VREF2 and VREF3, modulation signal VSWEEP and signals S1[n], S1[n+1], S2[n], EM[n] and VDATA.

[0126] In this embodiment, the pixel array 810 may include a plurality of pixel circuits 800 arranged in an array. Each pixel circuit 800 can be described by analogy with the relevant description of the pixel circuit 100, and therefore will not be repeated here.

[0127] In summary, the pixel circuit and display panel of this invention can accurately control the brightness by controlling the magnitude and output time of the driving current through the PAM circuit (i.e., the first driving circuit) and the PWM circuit (i.e., the second driving circuit), respectively, thereby improving brightness uniformity and reducing power consumption during operation. In some embodiments, compensation using matched transistors in the PWM circuit can improve compensation accuracy, increase brightness uniformity, and simplify the configuration of the PWM circuit. In some embodiments, compensation of the critical voltage value of the current source (i.e., the driving transistor) can improve compensation accuracy, thereby increasing brightness uniformity.

[0128] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A pixel circuit, comprising: Light-emitting elements; A current source and a switch are connected in series between the light-emitting element and the first reference voltage; A reset circuit is connected in series with the current source and the switch between the light-emitting element and the first reference voltage. A first driving circuit, coupled to the current source and the switch, is used to output a control signal to the current source based on a second reference voltage and a third reference voltage, wherein the current source is used to generate a driving current according to the control signal; as well as A second driving circuit, coupled to the switch or coupled to the switch through the first driving circuit, is used to control whether the switch is turned on or off based on a modulation signal. The current source includes: A first transistor has a control terminal coupled to the first driving circuit at a first node, a first terminal of the first transistor coupled to a first terminal of the light-emitting element and the reset circuit, wherein a second terminal of the light-emitting element receives a fourth reference voltage. The switch includes: The second transistor has a control terminal coupled to the second driving circuit at the second node, a first terminal coupled to the second terminal of the first transistor, and the second terminal of the second transistor receiving the first reference voltage. The first driving circuit includes: The third transistor has a control terminal for receiving light emission signals, and the first terminal of the third transistor is coupled to the first terminal of the first transistor. The fourth transistor has a control terminal that receives a first control signal from a subsequent stage. The first terminal of the fourth transistor is coupled to the second terminal of the first transistor and the first terminal of the second transistor. The second terminal of the fourth transistor is coupled to the first node. A first capacitor has a first end coupled to the first node, and a second end of the first capacitor is coupled to the second end of the third transistor at a third node; A fifth transistor has a control terminal that receives a second control signal, a first terminal of the fifth transistor coupled to the third node, and a second terminal of the fifth transistor that receives the third reference voltage; and The sixth transistor has a control terminal that receives a first control signal, a first terminal that receives a fifth reference voltage, and a second terminal that is coupled to the first node.

2. The pixel circuit of claim 1, wherein the second driving circuit comprises: The second capacitor has a first end coupled to the second node, and the second end of the second capacitor receives the light emission signal. A seventh transistor has a first terminal coupled to the second node, and a second terminal of the seventh transistor receiving the second reference voltage; The eighth transistor has a control terminal that receives the first control signal, a first terminal that receives the fifth reference voltage, and a second terminal that is coupled to the control terminal of the seventh transistor at the fourth node. The ninth transistor has a control terminal that receives the first control signal from the subsequent stage, and the first terminal of the ninth transistor is coupled to the fourth node; The tenth transistor has a control terminal and a first terminal coupled to a second terminal of the ninth transistor, the second terminal of the tenth transistor receiving a data signal; The third capacitor has a first end coupled to the fourth node; The eleventh transistor has a control terminal that receives the second control signal, the first terminal of the eleventh transistor is coupled to the second terminal of the third capacitor at the fifth node, and the second terminal of the eleventh transistor receives the sixth reference voltage. as well as A modulation circuit having a first terminal coupled to the fifth node and a second terminal receiving the modulation signal.

3. The pixel circuit of claim 2, wherein the modulation circuit comprises: The twelfth transistor has a control terminal that receives the modulation signal, a first terminal of the twelfth transistor that is coupled to the fifth node, and a second terminal of the twelfth transistor that receives the fifth reference voltage. or A fourth capacitor has a first end coupled to the fifth node, and a second end of the fourth capacitor receives the modulation signal.

4. The pixel circuit of claim 2, wherein the seventh transistor and the tenth transistor are matched to each other.

5. The pixel circuit of claim 2, wherein the reset circuit comprises: The thirteenth transistor has a control terminal that receives the first control signal from the subsequent stage, a first terminal that receives the second reference voltage, and a second terminal that is coupled to the first terminal of the first transistor.

6. The pixel circuit of claim 5, wherein during the reset phase, the subsequent first control signal is disabled to turn off the thirteenth transistor, the fourth transistor, the ninth transistor, and the tenth transistor; the light emission signal is disabled to turn off the third transistor; the modulation signal is disabled to turn off the modulation signal; the first control signal is enabled to turn on the sixth transistor and the eighth transistor; the second control signal is enabled to turn on the fifth transistor and the eleventh transistor; the seventh transistor is turned on; the second transistor is turned off; and the first transistor is turned on.

7. The pixel circuit of claim 6, wherein during the compensation phase, the subsequent first control signal is enabled to turn on the thirteenth transistor, the fourth transistor, the ninth transistor, and the tenth transistor; the light emission signal is disabled to turn off the third transistor; the modulation signal is disabled to turn off the modulation circuit; the first control signal is disabled to turn off the sixth transistor and the eighth transistor; the second control signal is enabled to turn on the fifth transistor and the eleventh transistor; the seventh transistor is turned off; the second transistor is turned off; and the first transistor is turned on.

8. The pixel circuit of claim 7, wherein during a first period of the light-emitting phase, the subsequent first control signal is disabled to turn off the thirteenth transistor, the fourth transistor, the ninth transistor, and the tenth transistor; the light-emitting signal is enabled to turn on the third transistor; the modulation signal has a portion of a triangular pulse to gradually turn on the modulation circuit; the first control signal is disabled to turn off the sixth transistor and the eighth transistor; the second control signal is disabled to turn off the fifth transistor and the eleventh transistor; the seventh transistor is turned off; and the second transistor and the first transistor are turned on to output the drive current to the light-emitting element.

9. The pixel circuit of claim 8, wherein during the second period of the light-emitting phase, the subsequent first control signal is disabled to turn off the thirteenth transistor, the fourth transistor, the ninth transistor, and the tenth transistor; the light-emitting signal is enabled to turn on the third transistor; the modulation signal has a partial triangular pulse to fully turn on the modulation circuit; the first control signal is disabled to turn off the sixth transistor and the eighth transistor; the second control signal is disabled to turn off the fifth transistor and the eleventh transistor; the seventh transistor is turned on; the first transistor is turned on; and the second transistor is turned off to cut off the drive current output to the light-emitting element.

10. The pixel circuit of claim 9, wherein during the shutdown phase, the subsequent first control signal is disabled to shut down the thirteenth transistor, the fourth transistor, the ninth transistor, and the tenth transistor; the light emission signal is disabled to shut down the third transistor; the modulation signal is disabled to shut down the modulation circuit; the first control signal is disabled to shut down the sixth transistor and the eighth transistor; the second control signal is disabled to shut down the fifth transistor and the eleventh transistor; the seventh transistor is turned on; the first transistor is turned on; and the second transistor is turned off.

11. The pixel circuit of claim 1, wherein the current source comprises: The first transistor has a control terminal coupled to the first driving circuit at the first node. The switch includes: The second transistor has a control terminal coupled to the first driving circuit and the second driving circuit at a second node, a first terminal of the second transistor coupled to the first terminal of the light-emitting element, and a second terminal of the second transistor coupled to the first terminal of the first transistor, the first driving circuit, and the reset circuit at a third node. The second terminal of the first transistor receives the first reference voltage, and the second terminal of the light-emitting element receives the fourth reference voltage.

12. The pixel circuit of claim 11, wherein the first driving circuit comprises: The third transistor has a control terminal that receives a light emission signal, and a first terminal of the third transistor that receives the third reference voltage. A fourth transistor has a control terminal coupled to the second node, a first terminal of the fourth transistor coupled to the second terminal of the third transistor on the fourth node, and the second terminal of the fourth transistor coupled to the first node. The fifth transistor has a control terminal that receives a first control signal, a first terminal of the fifth transistor that is coupled to the first node, and a second terminal of the fifth transistor that receives the second reference voltage. A first capacitor has a first end coupled to the third node and a second end coupled to the fourth node; as well as A second capacitor has a first terminal coupled to the third node, and a second terminal of the second capacitor receives the second reference voltage.

13. The pixel circuit of claim 12, wherein the second driving circuit comprises: A sixth transistor has a first terminal that receives the third reference voltage and a second terminal that is coupled to the second node; The seventh transistor has a control terminal that receives the light emission signal, a first terminal of the seventh transistor that is coupled to the second node, and a second terminal of the seventh transistor that receives a seventh reference voltage. The eighth transistor has a control terminal that receives the light emission signal, a first terminal that receives the third reference voltage, and a second terminal that is coupled to the control terminal of the sixth transistor at the fifth node. The ninth transistor has a control terminal that receives the modulation signal, and the first terminal of the ninth transistor is coupled to the fifth node; A third capacitor has a first terminal at the sixth node and a second terminal of the ninth transistor, the second terminal of the third capacitor receiving the third reference voltage; The tenth transistor has a control terminal that receives the light emission signal, and the first terminal of the tenth transistor is coupled to the sixth node; as well as The eleventh transistor has a control terminal for receiving data signals. The first terminal of the eleventh transistor is coupled to the second terminal of the tenth transistor, and the second terminal of the eleventh transistor receives a first control signal from the subsequent stage.

14. The pixel circuit of claim 13, wherein the ninth transistor and the eleventh transistor are matched to each other.

15. The pixel circuit of claim 14, wherein the reset circuit comprises: The twelfth transistor has a control terminal that receives a second control signal, a first terminal of the twelfth transistor that is coupled to the third node, and a second terminal of the twelfth transistor that receives the seventh reference voltage. as well as The thirteenth transistor has a control terminal that receives the second control signal, a first terminal of the thirteenth transistor that is coupled to the first node, and a second terminal of the thirteenth transistor that receives the seventh reference voltage.

16. The pixel circuit of claim 15, wherein during the reset phase, the second control signal is disabled to turn off the twelfth and thirteenth transistors, the light emission signal is enabled to turn on the third, seventh, eighth, and tenth transistors, the data signal is enabled to turn on the eleventh transistor, the modulation signal is disabled to turn off the ninth transistor, the first control signal is disabled to turn off the fifth transistor, the fourth transistor is turned off, the sixth transistor is turned off, and the second and first transistors are turned off.

17. The pixel circuit of claim 16, wherein during the compensation phase and the data writing period, the second control signal is disabled to turn off the twelfth and thirteenth transistors, the light emission signal is enabled to turn on the third, seventh, eighth, and tenth transistors, the data signal is enabled to turn on the eleventh transistor, the modulation signal is disabled to turn off the ninth transistor, the first control signal is enabled to turn on the fifth transistor, the fourth transistor is turned off, the sixth transistor is turned off, the second transistor is turned off, and the first transistor is turned on.

18. The pixel circuit of claim 17, wherein during a first period of the light-emitting phase, the second control signal is disabled to turn off the twelfth and thirteenth transistors, the light-emitting signal is disabled to turn off the third, seventh, eighth, and tenth transistors, the data signal is disabled to turn off the eleventh transistor, the modulation signal has a portion of a triangular pulse to gradually turn on the ninth transistor, the first control signal is disabled to turn off the fifth transistor, the sixth transistor is turned off, and the second and first transistors are turned off.

19. The pixel circuit of claim 18, wherein during a second period of the light-emitting phase, the second control signal is disabled to turn off the twelfth and thirteenth transistors, the light-emitting signal is disabled to turn off the third, seventh, eighth, and tenth transistors, the data signal is disabled to turn off the eleventh transistor, the modulation signal has a portion of a triangular pulse to fully turn on the ninth transistor, the first control signal is disabled to turn off the fifth transistor, the sixth transistor is turned on, and the second and first transistors are turned on to output the drive current to the light-emitting element.

20. The pixel circuit of claim 19, wherein during the off-phase, the second control signal is enabled to turn on the twelfth and thirteenth transistors, the light emission signal is enabled to turn on the third, seventh, eighth, and tenth transistors, the data signal is enabled to turn on the eleventh transistor, the modulation signal is disabled to turn off the ninth transistor, the first control signal is disabled to turn off the fifth transistor, and the second and first transistors are turned off.

21. A display panel, comprising: A pixel array, comprising a plurality of pixel circuits as described in claim 1; as well as A control circuit, coupled to the pixel array, is used to provide the first reference voltage, the second reference voltage, the third reference voltage, and the modulation signal to the pixel array.

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