Method for reducing solder bridging in semiconductor package structures
By employing a double-layer connecting rib structure in the lead frame, the area of the metal layer after electroplating is reduced, solving the bridging problem in QFNP packaging and improving process yield and production efficiency.
Patent Information
- Application Number
- CN202310565208.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-05-18
- Publication Date
- 2025-11-07
- Estimated Expiration
- 2043-05-18
AI Technical Summary
In the process of Quad Flat No-Package (QFNP), the small spacing between adjacent pins leads to solder bridging, which poses a risk of short circuit in the finished product. Existing technologies are unable to effectively solve this problem.
The design adopts a lead frame and the connecting ribs use a double-layer structure of different sizes. The first cut removes the bottom ribs and only retains the connecting ribs. During subsequent electroplating, the metal layer adheres to the surface of the connecting ribs, reducing the area. The second cut reduces the phenomenon of tin adhesion.
It effectively reduces solder bridging, improves process yield and production efficiency, and avoids pin short circuit problems.
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Figure CN116682740B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor packaging process, and more particularly to a method for reducing tin bridging in a semiconductor package. BACKGROUND
[0002] Quad Flat No-lead Package (QFNP) is a popular trend in the semiconductor industry. QFNP has the advantages of small size, comparable to Chip Scale Package (CSP), low cost, high yield, and better coplanarity and heat dissipation for high speed and power management circuits. In addition, QFNP does not require leads on the four sides, thus providing better electrical performance than conventional packages with leads on the sides.
[0003] With the development of electronic technology and semiconductor packaging technology, semiconductor size is getting smaller and smaller, and the distance between the pins of integrated circuits is also getting smaller and smaller. The semiconductor structure of Quad Flat No-lead Package (QFNP) best meets this requirement. However, due to the smaller distance between adjacent pins, tin bridging often occurs, which poses a risk of short circuit in the finished product. The tin bridging occurs during the process of cutting a large-area packaging lead frame into individual semiconductor structures. The main reason is that in order to achieve good electrical connection of the pins on the circuit board, a layer of tin is attached to the surface of the pins by electroplating before the cutting process. The operation mode is shown in Figure 1A The partial enlarged view of the number of pins after the first cutting is shown in FIG. 2. The plurality of pins 91 are connected by the connecting portion 92, and the plurality of pins 91 are surrounded by the packaging adhesive 93. The width of the cutting path 94 is adjacent to the connecting portion 92, such as the upper and lower solid line areas in the figure. As shown in Figure 1B After the electroplating operation, a tin layer 95 is formed on the surface of the metal pins 91 and the connecting portion 92. The tin layer 95 is represented by diagonal lines in the figure. As can be seen in the figure, the tin layer 95 covers the entire connecting portion 92. The second cutting is to remove the connecting portion 92 along the cutting path 94. However, when the second cutting is performed, due to the small distance between the pins 91, the tin layer 95 on the surface of the connecting portion 92 has a large area. When the cutting blade cuts, the tin layer 95 with good ductility will also extend outward, causing some tin to adhere between the two adjacent pins 91, resulting in the tin bridging problem, which poses a risk of short circuit in the finished product. SUMMARY
[0004] The main purpose of the present application is to provide a method for reducing the occurrence of tin connection in semiconductor packaging structure, mainly reducing the area of the metal layer connected to the corresponding two pins after electroplating, so that the occurrence of tin connection can be greatly reduced when the second cutting is performed, thereby improving the process yield.
[0005] To achieve the foregoing purpose, the present application adopts the following technical scheme: the present application is a method for reducing the occurrence of tin connection in semiconductor packaging structure, comprising the following steps: using a completed packaging and uncut packaging lead frame, the packaging lead frame comprising a lead frame and a packaging adhesive covering the lead frame, the lead frame comprising a plurality of units, each unit comprising at least one die pad, a plurality of pins distributed around the die pad, and a connecting rib connected to the plurality of pins, the connecting rib being a double-layer structure with different sizes, namely a bottom layer rib and a connecting rib, the connecting rib being connected to the pins and the width of the connection being smaller than the maximum width of the pins; performing a first cutting to remove the bottom layer rib of the connecting rib, leaving only the connecting rib, each connecting rib still being connected to the pins; performing an electroplating operation to form a metal layer on the surface of the pins and the connecting rib; performing a second cutting to remove the connecting rib of the connecting rib to form a single semiconductor structure that has completed packaging.
[0006] As one of the preferred embodiments, at least one die is arranged in each die pad, and a plurality of lead wires are arranged to connect the dies and the corresponding pins.
[0007] As one of the preferred embodiments, the bottom layer rib and the connecting rib are in a stacked double-layer structure, the connecting rib being connected between the corresponding pins of two adjacent units, and the bottom layer rib being connected to a plurality of connecting ribs and a plurality of pins.
[0008] As one of the preferred embodiments, the width of the connecting rib connected to the pin is smaller than the width of the connection of the pin.
[0009] As one of the preferred embodiments, the metal layer is a tin layer or a tin alloy layer.
[0010] As one of the preferred embodiments, the lead frame has a first face and a second face opposite to each other, the connecting rib of the connecting rib being located on the first face, and the bottom layer rib being located on the second face, the cutting being performed from the direction of the second face.
[0011] Compared with the prior art, the method for reducing the tin adhesion of the semiconductor package structure in the application is to remove most of the connecting ribs by first cutting, only leaving small-area connecting ribs connected with the pins, so that the tin or tin alloy area of the metal layer is reduced during subsequent electroplating, for example, the metal layer is attached to the surface of the existing connecting part from a large area to a small area on the surface of the connecting rib, so that the tin adhesion phenomenon during cutting is reduced, the short circuit problem of the finished product is eliminated, the process yield and production efficiency are improved. BRIEF DESCRIPTION OF DRAWINGS
[0012] Figure 1A Enlarged view of the existing packaged lead frame after first cutting.
[0013] Figure 1B Enlarged view of the existing packaged lead frame after electroplating.
[0014] Figure 2 Perspective view of the packaged lead frame used in the application.
[0015] Figure 3 Cross-sectional view of the AA plane of Figure 2
[0016] Figure 4 Enlarged perspective view of the lead frame of the application.
[0017] Figure 5 Perspective view of the bottom view of the lead frame of the application.
[0018] Figure 6 Enlarged plan view of the connecting rib and pin connection of the application.
[0019] Figure 7 Flowchart of the application.
[0020] Figure 8 Bottom view of the packaged lead frame of the application.
[0021] Figure 9A Perspective view of the packaged lead frame of the application after first cutting.
[0022] Figure 9B Plan view of the packaged lead frame of the application after first cutting.
[0023] Figure 10 Plan view of the packaged lead frame of the application during electroplating.
[0024] Figure 11 Plan view of the packaged lead frame of the application after second cutting.
[0025] Explanation of main reference signs:
[0026] 91: pin; 92: connecting portion; 93: encapsulation adhesive; 94: cutting path; 95: tin layer
[0027] 10: package lead frame; 20: lead frame; 21: die pad; 22: pin; 23: connecting rib
[0028] 231: bottom layer rib; 232: connecting rib; 30: encapsulation adhesive; 40: die; 50: lead
[0029] 60: cutting path; 80: metal layer; 90: semiconductor structure; L1: connecting rib width
[0030] L2: maximum width; L3: connecting portion width DETAILED DESCRIPTION
[0031] The technical solutions of the present application will be described clearly and completely below in combination with specific embodiments and drawings. It should be noted that when a component is referred to as "mounted on or fixed on" another component, it means that it can be directly on the other component or there can be a middle component. When a component is referred to as "connected to" another component, it means that it can be directly connected to the other component or there can be a middle component. In the shown embodiments, the directions such as up, down, left, right, front and back are relative, and are used to explain the structure and movement of different components. When the components are in the positions shown in the drawings, these directions are appropriate. However, if the positions of the components change, it is considered that these directions will also change accordingly.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing specific embodiments only and is not intended to be limiting of the application. As used in the description herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0033] The method for reducing tin bridging of a semiconductor package structure of the present application uses a package lead frame 10 that has been completed and not cut. As shown in Figure 2 and 3 The package lead frame 10 includes a lead frame 20 and an encapsulation adhesive 30, and the lead frame 20 includes a plurality of units, each unit including a die pad 21, a plurality of pins 22 distributed around the die pad 21, and a connecting rib 23 connected to the plurality of pins 22. In Figure 2 and Figure 3In the embodiment, only four units are shown, and the actual number of units can be designed by the manufacturer. After cutting, each unit forms a semiconductor structure. The die pad 21 is provided with at least one die 40, and each die 40 is connected to the corresponding lead 22 through a plurality of leads 50. In the embodiment, the package lead frame 10 is manufactured by using the existing packaging process, and thus will not be described in detail. The lead frame 20 used in the present application is slightly different from the prior art, and will be described below.
[0034] As shown in Figure 4 and Figure 5 are enlarged views of the lead frame at different angles. The lead frame 20 includes a plurality of units. For ease of description, only one unit structure in the lead frame 20 is shown in the subsequent figures. The area shown by the imaginary line in the figure is the area covered by one unit. Each unit is composed of a die pad 21, a plurality of leads 22 distributed around the die pad 21, and a connecting rib 23 connected to the plurality of leads 22. The connecting rib 23 is a double-layer structure with different sizes, including a bottom layer rib 231 and a connecting rib 232. The connecting rib 232 is connected between the corresponding two leads 22 of adjacent two units, and the bottom layer rib 231 is connected to the plurality of connecting ribs 232 and the plurality of leads 22. The lead frame 20 has a first face and a second face opposite to each other. The first face is commonly referred to as the front face, which is the surface on which the die 40 is placed on the die pad 21, and is also the surface on which the lead 22 is connected to the lead 50 of the die 40. The connecting rib 232 is also formed on this face and connected between the adjacent two leads 22 (as shown in Figure 4 ). The second face is commonly referred to as the back face, and the bottom layer rib 231 is located on the second face (as shown in Figure 5 ). When cutting, the entire structure is flipped over and cut from the direction of the second face. In addition, as shown in Figure 6 , the connecting rib width L1 of the connecting rib 232 is smaller than the maximum width L2 of the lead 22. In the embodiment, the connecting rib width L1 of the connecting rib 232 connected to the lead 22 is even smaller than the connection width L3 of the lead 22. In the embodiment, the semi-etching method is used to process the lead frame 20 to form the shape of the connecting rib 232 and the shape of the lead 22. Because the connecting rib 232 has the smallest area, it helps to reduce the area of the subsequent electroplated layer.
[0035] Next, the method for reducing the occurrence of tin connection during cutting of a semiconductor package structure will be described in detail. As shown in Figure 7 , it is a flowchart of the present application, which includes the following steps:
[0036] Step 701, using the package lead frame 10 which has been completed encapsulation and not cut, the structure of the package lead frame 10 is as described above, the package lead frame 10 includes the lead frame 20 and the encapsulation adhesive 30 which is coated on the lead frame 20, the lead frame 20 includes a plurality of units, each unit includes a die pad 21, a plurality of pins 22 which are distributed around the die pad 21, and a plurality of connecting ribs 23 which are connected to the plurality of pins 22. The connecting rib 23 is a double-layer structure with different sizes, which is the bottom layer rib 231 and the connecting rib 232, the connecting rib 232 is connected to the pin 22 and the width of the connecting part is smaller than the maximum width of the pin 22. As shown in Figure 8 , it is the bottom view of the package lead frame 10, because the encapsulation adhesive 30 has been encapsulated on the lead frame 20, the second surface of the lead frame 20 only exposes the die pad 21, the plurality of pins 22 and the bottom layer rib 231, the imaginary line in the figure is the position and width of the predetermined cutting path 60.
[0037] Step 702, first cutting, cutting off the bottom layer rib 231 of the connecting rib 23, only leaving the connecting rib 232, each connecting rib 232 is still connected to the pin 22, as shown in Figure 9A and Figure 9B , after the first cutting along the cutting path 60, the pin 22 adjacent to the connecting rib 232 is also partially cut off, and finally only the connecting rib 232 is connected between the corresponding two pins 22.
[0038] Step 703, electroplating operation, forming a metal layer 80 on the surface of the pin 22 and the connecting rib 232. This operation must take the package lead frame 10 out and place it in the electroplating tank for electroplating, as shown in Figure 10 , a layer of metal layer 80 is formed on the exposed surface at the positions of the die pad 21, the pin 22 and the connecting rib 232, in this embodiment, the metal layer 80 is a tin layer or a tin alloy layer. As can be seen from the figure, because the width of the connecting rib 232 is smaller than the width of the pin 22, the metal layer 80 attached to the connecting rib 232 is much less than the existing method (as shown in Figure 1B ).
[0039] Step 704, second cutting, removing the connecting rib 232 of the connecting rib 23, forming a single semiconductor structure 90 which has been completed encapsulation. As shown in Figure 11 , using a cutting blade to completely cut off the package lead frame 10, also cutting off the connecting rib 32 and the encapsulation adhesive 30 here, forming a single semiconductor structure 90, the bottom of the semiconductor structure 90 only leaves the die pad 21 and the plurality of pins 22 which are distributed around. Because only a small area of the connecting rib 232 surface is attached with the metal layer 80 in the present application, when the second cutting (completely cutting) is performed, the small area of the metal layer 80 is not easy to be stretched and spread, so it is not easy to occur that the tin is adhered to the adjacent pin 22, therefore, the finished product processed by the method of the present application is not easy to occur the pin short circuit problem, the method of the present application can effectively solve the tin connection problem and improve the process yield.
[0040] In summary, the method for reducing tin adhesion in semiconductor packaging structure of the present application uses a lead frame with a special shape, i.e. the connecting rib connecting two adjacent leads is a double-layer structure with different sizes, which is beneficial to remove most of the structure in the first cutting, leaving only a small area of connecting rib connected with the lead, so as to reduce the tin plating area in subsequent plating, thereby reducing the tin adhesion phenomenon in cutting, eliminating the problem of signal short circuit of the finished product, and improving the process yield.
[0041] The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the embodiments of the present application. Any equivalent changes and modifications made in accordance with the scope of the patent application of the present application are covered by the patent scope of the present application.
Claims
1. A method of reducing stitch formation in a semiconductor package structure, the method comprising: The steps include: using a completed package and uncut package lead frame, the package lead frame including a lead frame and a package adhesive covering the lead frame, the lead frame including a plurality of units, each unit including at least one die pad, a plurality of pins distributed around the die pad, and a connecting rib connected to the plurality of pins, the connecting rib being a double-layer structure with different sizes, respectively a bottom rib and a connecting rib, the connecting rib being connected to the pins and the width of the connection being less than the maximum width of the pins; performing a first cutting to remove the bottom rib of the connecting rib, leaving only the connecting rib, each connecting rib still being connected to the pins; performing an electroplating operation to form a metal layer on the surface of the pins and the connecting rib; performing a second cutting to remove the connecting rib of the connecting rib to form a single semiconductor structure that has been packaged.
2. The method of claim 1, wherein the method further comprises: Each die pad is provided with at least one die, and a plurality of lead wires are provided to connect the die and the corresponding pins.
3. The method of claim 1, wherein the method further comprises: The bottom rib and the connecting rib are in a stacked double-layer structure, the connecting rib being connected between the corresponding pins of two adjacent units, and the bottom rib being connected to a plurality of connecting ribs and a plurality of pins.
4. The method of reducing stitch of a semiconductor package structure of claim 3, wherein, The width of the connecting rib connected to the pins is less than the width of the connection of the pins.
5. The method of claim 1, wherein the method further comprises: applying a flux to the semiconductor package structure. The metal layer is a tin layer or a tin alloy layer.
6. The method of reducing stitch of claim 1, wherein, The lead frame has a first surface and a second surface opposite to each other, the connecting rib of the connecting rib being located on the first surface, and the bottom rib being located on the second surface, and the cutting being performed from the direction of the second surface.
Citation Information
Patent Citations
Semiconductor packaging technology
CN104505346A
Semiconductor encapsulation frame
CN104505377A