An ESD protection diode and a preparation method thereof

Abstract

The present invention relates to the field of semiconductor device fabrication, and discloses an ESD protection diode and a fabrication method. The method includes the steps of: providing a plurality of shallow trench isolation regions on a substrate, including a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region, and a fourth shallow trench isolation region; providing a polysilicon layer on the second shallow trench isolation region and the third shallow trench isolation region; performing ion implantation between every two shallow trench isolation regions to obtain a first doped layer, a second doped layer, and a third doped layer on the substrate. The first doped layer and the third doped layer are adapted to conduct current, the second doped layer is the cathode of the PN junction, and the substrate is the anode of the PN junction. In the present invention, by covering the STI with POLY, since the POLY layer has a relatively thick thickness, which can effectively block ion (plus) implantation and serves as a blocking layer for plus implantation, plus will not hit the STI divot region during implantation, making the interface of the PN junction smoother and improving the voltage withstand or current withstand ability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device fabrication, and particularly to an ESD protection diode and a fabrication method thereof. Background Art

[0002] In the prior art, when fabricating a PN junction, a SAB (salicide block) layer is disposed on a shallow trench isolation region. The SAB layer is used to deposit an oxide layer on the surface of the active region to prevent the formation of silicide. In the PN junction structure of the prior art, the junction between AA and STI is usually covered with SAB. Subsequently, ion implantation is performed in the middle of the shallow trench isolation region, i.e., plus implantation, to form two doped layers, a P+ doped layer on both sides and an N+ doped layer in the middle. Plus implantation includes Pplus (P+) implantation and Nplus (N+) implantation. P+ is a heavily doped P-type ion, and N+ is a heavily doped N-type ion.

[0003] When performing plus implantation at the junction between AA and STI, since the wet etching in the process flow consumes the oxide film in the STI region, the oxide film at the junction between STI and AA is lower than that of AA, forming a recessed region, which is the divot region. Due to the existence of the divot region, the implanted ions in the divot region will be deeper than those in other AA regions during plus implantation, and a protruding plus region will be formed in the divot region, resulting in a spike. This protruding plus region makes the interface of the PN junction have a protruding part, seriously affecting the breakdown voltage of the PN junction.

[0004] Therefore, a new ESD protection diode and a fabrication method thereof are needed. Summary of the Invention

[0005] Therefore, the present invention provides an ESD protection diode and a fabrication method thereof, in an attempt to solve or at least alleviate the problems mentioned above.

[0006] According to a first aspect of the present invention, there is provided an ESD protection diode. The diode includes a substrate, on which a plurality of shallow trench isolation regions are disposed, including a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region, and a fourth shallow trench isolation region; a polysilicon layer is disposed on the second shallow trench isolation region and the third shallow trench isolation region; a first doped layer is disposed between the first shallow trench isolation region and the second shallow trench isolation region, a third doped layer is disposed between the third shallow trench isolation region and the fourth shallow trench isolation region, and a second doped layer is disposed between the second shallow trench isolation region and the third shallow trench isolation region. The first doped layer and the third doped layer are adapted to conduct current, the second doped layer is the cathode of the PN junction, and the substrate is the anode of the PN junction.

[0007] According to a second aspect of the present invention, a method for manufacturing an ESD protection diode is provided. The method includes the steps of: providing a plurality of shallow trench isolation regions on a substrate, including a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region, and a fourth shallow trench isolation region; providing a polysilicon layer on the second shallow trench isolation region and the third shallow trench isolation region; performing ion implantation between every two shallow trench isolation regions to obtain a first doped layer, a second doped layer, and a third doped layer on the substrate. The first doped layer and the third doped layer are adapted to conduct current, the second doped layer is the cathode of the PN junction, and the substrate is the anode of the PN junction.

[0008] Optionally, in the method according to the present invention, the cross-section of each shallow trench isolation region is the same trapezoid, the length of the upper base of the trapezoidal cross-section is longer than the lower base, and the two waists are equal.

[0009] Optionally, in the method according to the present invention, the polysilicon layer is a blocking layer for ion implantation, and the thickness of the polysilicon layer is greater than 1800 angstroms.

[0010] Optionally, in the method according to the present invention, the cross-sections of the polysilicon layers are the same, all being rectangles.

[0011] Optionally, in the method according to the present invention, performing ion implantation between every two shallow trench isolation regions to obtain a first doped layer, a second doped layer, and a third doped layer on the substrate includes: performing P-type ion implantation between the first shallow trench isolation region and the second shallow trench isolation region to obtain the first doped layer; performing P-type ion implantation between the third shallow trench isolation region and the fourth shallow trench isolation region to obtain the third doped layer; performing N-type ion implantation between the second shallow trench isolation region and the third shallow trench isolation region to obtain the second doped layer.

[0012] Optionally, in the method according to the present invention, the cross-sections of the first doped layer, the second doped layer, and the third doped layer are rectangles.

[0013] Optionally, in the method according to the present invention, the substrate includes a PWELL substrate.

[0014] Optionally, in the method according to the present invention, the substrate includes an NWELL substrate.

[0015] Optionally, in the method according to the present invention, performing ion implantation between every two shallow trench isolation regions to obtain a first doped layer, a second doped layer, and a third doped layer on the substrate includes: performing N-type ion implantation between the first shallow trench isolation region and the second shallow trench isolation region to obtain the first doped layer; performing N-type ion implantation between the third shallow trench isolation region and the fourth shallow trench isolation region to obtain the third doped layer; performing P-type ion implantation between the second shallow trench isolation region and the third shallow trench isolation region to obtain the second doped layer.

[0016] A method for manufacturing an ESD protection diode in the present invention, the method comprising the steps of: providing a plurality of shallow trench isolation regions on a substrate, including a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region, and a fourth shallow trench isolation region; providing a polysilicon layer on the second shallow trench isolation region and the third shallow trench isolation region; performing ion implantation between every two shallow trench isolation regions to obtain a first doped layer, a second doped layer, and a third doped layer on the substrate, the first doped layer and the third doped layer being adapted to conduct current, the second doped layer being the cathode of the PN junction, and the substrate being the anode of the PN junction. In the present invention, by covering the STI with POLY and replacing the original SAB, since the thickness of the POLY layer is relatively thick, exceeding 1800 angstroms It can effectively block ion (plus) implantation. As a blocking layer for plus implantation, plus will not hit the STI divot region during implantation, making the interface of the PN junction smoother and improving the voltage withstand or current withstand ability. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To achieve the above and related purposes, certain illustrative aspects are described herein in conjunction with the following description and drawings, which indicate various ways in which the principles disclosed herein can be practiced, and all aspects and their equivalent aspects are intended to fall within the scope of the claimed subject matter. The above and other objects, features, and advantages of the present disclosure will become more apparent by reading the following detailed description in conjunction with the drawings. Throughout the present disclosure, like reference numerals generally refer to like components or elements.

[0018] Figure 1 and Figure 2 shows a schematic diagram of the preparation of a PN junction in the prior art;

[0019] Figure 3 shows a schematic flow diagram of a method 300 for manufacturing an ESD protection diode according to an exemplary embodiment of the present invention;

[0020] Figure 4 shows a schematic cross-sectional view of an ESD protection diode according to an exemplary embodiment of the present invention;

[0021] Figure 5 shows a partial schematic diagram of an ESD protection diode prepared according to an exemplary embodiment of the present invention;

[0022] Figure 6 shows a schematic cross-sectional view of an ESD protection diode according to another exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be fully conveyed to those skilled in the art. The same reference numerals generally refer to the same components or elements.

[0024] Figure 1 and Figure 2 shows a schematic diagram of the preparation of a PN junction in the prior art. As Figure 1 shown, a plurality of shallow trench isolation regions (Shallow Trench Isolation, STI) are provided on the substrate. The substrate can be specifically implemented as a PWELL substrate, that is, a substrate implanted with p-type ions. The region on the substrate other than the shallow trench isolation region is the active area (active area, AA).

[0025] Subsequently, a SAB (salicide block) layer is provided on the middle shallow trench isolation region. The SAB layer is used to deposit an oxide layer on the surface of the active region so that silicide cannot be formed. In the PN junction structure in the prior art, the junction between the AA and the STI is usually covered with SAB.

[0026] Subsequently, ion implantation is performed in the middle of the shallow trench isolation region, that is, plus implantation, to form two side doped layers, a P+ doped layer and a middle N+ doped layer. Plus implantation includes Pplus (P+) implantation and Nplus (N+) implantation. P+ is a heavily doped p-type ion, and N+ is a heavily doped n-type ion.

[0027] Figure 1 In the PN junction shown, PWELL and N+ are the two ports of the diode. PWELL serves as the anode and N+ serves as the cathode. PWELL draws current through P+.

[0028] As Figure 2 shown, when plus implantation is performed at the junction between the AA and the STI, since the wet etching in the process flow will consume the oxide film in the STI region, the oxide film at the junction between the STI and the AA is lower than the AA, forming a recessed area, and this recessed area is the divot region.

[0029] Due to the existence of the divot region, the implanted ions in the divot region will be deeper than those in other AA regions during plus implantation, and a protruding plus region will be formed in the divot region, resulting in a spike. This protruding plus region makes the interface of the PN junction have a protruding place, seriously affecting the breakdown voltage of the PN junction.

[0030] To this end, the present invention proposes a method for manufacturing an ESD protection diode. Figure 3 FIG. 300 shows a schematic flow chart of a method for manufacturing an ESD protection diode according to an exemplary embodiment of the present invention.

[0031] As Figure 3 shown, a method 300 for manufacturing an ESD protection diode begins with step 310 of forming a plurality of shallow trench isolation regions on a substrate, including a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region, and a fourth shallow trench isolation region. The first shallow trench isolation region, the second shallow trench isolation region, the third shallow trench isolation region, and the fourth shallow trench isolation region are arranged in sequence on the substrate. The ESD protection diode, namely the TVS diode, is an electrostatic protection diode. The manufacturing method of the present invention is also applicable to other types of diodes.

[0032] The present invention manufactures an ESD protection diode, which includes a substrate, on which a plurality of shallow trench isolation regions are formed, including a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region, and a fourth shallow trench isolation region; a polysilicon layer is formed on the second shallow trench isolation region and the third shallow trench isolation region; a first doped layer is formed between the first shallow trench isolation region and the second shallow trench isolation region, a third doped layer is formed between the third shallow trench isolation region and the fourth shallow trench isolation region, and a second doped layer is formed between the second shallow trench isolation region and the third shallow trench isolation region. The first doped layer and the third doped layer are adapted to conduct current, the second doped layer is the cathode of the PN junction, and the substrate is the anode of the PN junction.

[0033] Figure 4 FIG. shows a schematic cross-sectional view of a PN junction according to an exemplary embodiment of the present invention. As Figure 4 shown, a plurality of shallow trench isolation regions 421-424 are formed on a substrate 410, including a first shallow trench isolation region 421, a second shallow trench isolation region 422, a third shallow trench isolation region 423, and a fourth shallow trench isolation region 424.

[0034] According to an embodiment of the present invention, the substrate 410 can be specifically implemented as a PWELL substrate.

[0035] The first shallow trench isolation region 421, the second shallow trench isolation region 422, the third shallow trench isolation region 423, and the fourth shallow trench isolation region 424 are distributed on the surface of the PWELL substrate. The cross-section of each shallow trench isolation region is trapezoidal, the length of the upper base of the trapezoidal cross-section is longer than that of the lower base, the two waists are equal, and the two base angles are equal. The cross-sections of each shallow trench isolation region are the same. The present invention does not limit the distance between adjacent two shallow trench isolation regions, which can be set as needed.

[0036] Return to Figure 3, Subsequently, step 320 is executed to form a polysilicon layer on the second shallow trench isolation region and the third shallow trench isolation region. According to an embodiment of the present invention, the polysilicon (POLY) layer serves as a blocking layer for subsequent ion implantation, and the thickness of the polysilicon layer is greater than 1800 angstroms

[0037] As Figure 4 shown, polysilicon layers 431 and 432 are formed on the second shallow trench isolation region 422 and the third shallow trench isolation region 423. The cross-sections of the polysilicon layers 431 and 432 are the same, both being rectangular, and the thickness of the cross-sections of the polysilicon layers 431 and 432 is greater than 1800 angstroms The present invention does not limit the specific length of the cross-sections of the polysilicon layers 431 and 432. The length of the cross-sections of the polysilicon layers 431 and 432 is greater than the length of the upper base of the trapezoidal cross-section of the shallow trench isolation region.

[0038] Returning to Figure 3 , Subsequently, step 330 is executed to perform ion implantation between every two shallow trench isolation regions to obtain a first doped layer, a second doped layer, and a third doped layer on the substrate. The first doped layer and the third doped layer are suitable for conducting current, the second doped layer is the cathode of the PN junction, and the substrate is the anode of the PN junction.

[0039] As Figure 4 shown, a first doped layer 441 is obtained by performing P-type ion implantation between the first shallow trench isolation region and the second shallow trench isolation region, and a third doped layer 443 is obtained by performing P-type ion implantation between the third shallow trench isolation region and the fourth shallow trench isolation region; an N-type ion implantation is performed between the second shallow trench isolation region and the third shallow trench isolation region to obtain a second doped layer 442. The present invention does not limit the sequence of constructing each doped layer, and they can be constructed separately or simultaneously.

[0040] According to an embodiment of the present invention, the first doped layer 441 and the third doped layer 443 have the same thickness, the same length, and the same rectangular cross-section. The cross-section of the second doped layer 442 is rectangular.

[0041] Figure 5 shows a partial schematic diagram of a PN junction prepared according to an exemplary embodiment of the present invention. As Figure 5 shown, in the present invention, by covering POLY on the STI and replacing the original SAB, since the thickness of the POLY layer is relatively thick, exceeding 1800 angstroms it can effectively block ion (plus) implantation. As a blocking layer for plus implantation, plus will not hit the STI divot region during implantation, making the interface of the PN junction smoother and improving the breakdown voltage or current-carrying capacity.

[0042] In the prior art, if there are some protrusions at the interface of the PN junction, it will seriously affect the breakdown voltage of the PN junction. In the present invention, POLY is used to replace SAB. POLY can be used as a blocking layer for plus implantation, so that plus will not hit the STI divot area. In this way, the interface of the PN junction will be more uniform, and the performance of the PN junction, i.e., the ESD DIODE performance, is improved. The ESD DIODE performance refers to the breakdown voltage ability of the ESD device, and the breakdown voltage ability is related to the over-current ability of the device.

[0043] Figure 6 FIG. shows a schematic cross-sectional view of a PN junction according to another exemplary embodiment of the present invention. As Figure 6 shown, the substrate 410 is specifically implemented as an NWELL substrate. When ion implantation is performed in the middle of every two shallow trench isolation regions to obtain a first doped layer, a second doped layer, and a third doped layer on the substrate, specifically: N-type ion implantation is performed in the middle of the first shallow trench isolation region and the second shallow trench isolation region to obtain the first doped layer, and N-type ion implantation is performed in the middle of the third shallow trench isolation region and the fourth shallow trench isolation region to obtain the third doped layer; P-type ion implantation is performed in the middle of the second shallow trench isolation region and the third shallow trench isolation region to obtain the second doped layer. The present invention does not limit the order of constructing each doped layer, and they can be constructed separately or simultaneously.

[0044] In the specification provided herein, a large number of specific details are set forth. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0045] Similarly, it should be understood that in order to streamline this disclosure and assist in understanding one or more of the various inventive aspects, in the foregoing description of the exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting an intention that: the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected by the following claims, the inventive aspects lie in less than all the features of the single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present invention.

[0046] Those skilled in the art should understand that the modules or units or groups of the devices in the examples disclosed herein may be arranged in the devices as described in this embodiment, or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or further divided into multiple sub-modules.

[0047] In addition, those skilled in the art will appreciate that although some of the embodiments described herein include certain features included in other embodiments and not others, combinations of features of different embodiments are meant to be within the scope of the present invention and form different embodiments.

[0048] As used herein, unless otherwise specified, the use of ordinal numbers such as "first", "second", "third", etc. to describe ordinary objects merely indicates different instances of similar objects and is not intended to imply that the objects so described must have a given order in time, space, ranking, or in any other manner.

[0049] Although the present invention has been described in terms of a limited number of embodiments, those skilled in the art within the present technology will appreciate that other embodiments can be contemplated within the scope of the present invention as thus described. In addition, it should be noted that the language used in this specification has been principally selected for readability and teaching purposes rather than for the purpose of explaining or limiting the subject matter of the present invention. Thus, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. For the scope of the present invention, the disclosure of the present invention is illustrative and not restrictive, and the scope of the present invention is defined by the appended claims.

Claims

1. An ESD protection diode, the diode comprising a substrate, on which a plurality of shallow trench isolation regions are provided, including a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region and a fourth shallow trench isolation region; A polysilicon layer is provided on the second shallow trench isolation region and the third shallow trench isolation region; the polysilicon layer is a barrier layer for ion implantation, the thickness of the polysilicon layer is greater than 1800 angstroms; the cross-sections of the polysilicon layer are the same, all being rectangular, and the length of the cross-section is greater than the length of the upper base of the trapezoidal cross-section of the shallow trench isolation region; A first doped layer is provided between the first shallow trench isolation region and the second shallow trench isolation region, a third doped layer is provided between the third shallow trench isolation region and the fourth shallow trench isolation region, and a second doped layer is provided between the second shallow trench isolation region and the third shallow trench isolation region. The first doped layer and the third doped layer are adapted to conduct current, the second doped layer is the cathode of the PN junction, and the substrate is the anode of the PN junction.

2. A method for manufacturing an ESD protection diode, the method comprising the steps of: Providing a plurality of shallow trench isolation regions on a substrate, including a first shallow trench isolation region, a second shallow trench isolation region, a third shallow trench isolation region and a fourth shallow trench isolation region; Providing a polysilicon layer on the second shallow trench isolation region and the third shallow trench isolation region; the polysilicon layer is a barrier layer for ion implantation, the thickness of the polysilicon layer is greater than 1800 angstroms; the cross-sections of the polysilicon layer are the same, all being rectangular, and the length of the cross-section is greater than the length of the upper base of the trapezoidal cross-section of the shallow trench isolation region; Performing ion implantation between every two shallow trench isolation regions to obtain a first doped layer, a second doped layer and a third doped layer on the substrate. The first doped layer and the third doped layer are adapted to conduct current, the second doped layer is the cathode of the PN junction, and the substrate is the anode of the PN junction.

3. The method according to claim 2, wherein, The cross-section of each shallow trench isolation region is the same trapezoid, the length of the upper base of the trapezoidal cross-section is longer than the lower base, and the two waists are equal.

4. The method according to claim 2, wherein The performing ion implantation between every two shallow trench isolation regions to obtain a first doped layer, a second doped layer and a third doped layer on the substrate includes: Performing P-type ion implantation between the first shallow trench isolation region and the second shallow trench isolation region to obtain the first doped layer; Performing P-type ion implantation between the third shallow trench isolation region and the fourth shallow trench isolation region to obtain the third doped layer; Performing N-type ion implantation between the second shallow trench isolation region and the third shallow trench isolation region to obtain the second doped layer.

5. The method according to claim 4, wherein, The cross-sections of the first doped layer, the second doped layer and the third doped layer are rectangular.

6. The method according to any one of claims 2-5, wherein, The substrate includes a PWELL substrate.

7. The method according to any one of claims 2-5, wherein The substrate includes an NWELL substrate.

8. The method according to claim 7, wherein The performing ion implantation between every two shallow trench isolation regions to obtain a first doped layer, a second doped layer and a third doped layer on the substrate includes: Performing N-type ion implantation between the first shallow trench isolation region and the second shallow trench isolation region to obtain the first doped layer; Performing N-type ion implantation between the third shallow trench isolation region and the fourth shallow trench isolation region to obtain the third doped layer; P-type ion implantation is performed between the second shallow trench isolation region and the third shallow trench isolation region to obtain a second doped layer.

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