Display panel

Abstract

The present application provides a display panel, which includes a power management circuit, a control circuit, a data driving circuit, a delay circuit, and a common electrode. The power management circuit is used to power on the control circuit and the data driving circuit according to an input voltage signal. The power management circuit generates a common voltage signal according to the input voltage signal. After the data driving circuit is powered on, the power management circuit generates a power-on signal. The control circuit generates a first control signal according to the power-on signal. The delay circuit is turned on according to the first control signal to transmit the common voltage signal to the common electrode through the delay circuit. After the control circuit and the data driving circuit are powered on, the delay circuit is turned on according to the first control signal to transmit the common voltage signal to the common electrode through the delay circuit, so that the power-on completion timing of the control circuit and the data driving circuit is earlier than the power-on completion timing of the common electrode, thereby avoiding white flashing when the display panel is turned on.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] Display technology has always been one of the important research directions in electronic devices. At present, the market demand for high-refresh, low-power, low-cost Indium Gallium Zinc Oxide Thin Film Transistor (IGZO-TFT) is increasing. The driving circuit design on the traditional single-crystal silicon (a-Si) display panel is that the power-on timing of the common voltage signal precedes the data signal and timing control signal when the power is turned on. However, due to the high electron mobility of IGZO-TFT, the data signal will incorrectly charge the pixel unit of the display panel when the power is turned on, resulting in the technical problem of the display panel flashing white when it is turned on. Summary of the Invention

[0003] The present application discloses a display panel, which can solve the technical problem of white flashing when the display panel is turned on.

[0004] The present application provides a display panel, which includes a power management circuit, a control circuit, a data driving circuit, a delay circuit and a common electrode. The power management circuit is electrically connected to the control circuit and the data driving circuit respectively. The power management circuit is used to power on the control circuit and the data driving circuit according to an input voltage signal. The power management circuit is also electrically connected to the common electrode through the delay circuit. The power management circuit generates a common voltage signal according to the input voltage signal. After the data driving circuit is powered on, the power management circuit generates a power-on signal. The control circuit generates a first control signal according to the power-on signal. The delay circuit is turned on according to the first control signal to transmit the common voltage signal to the common electrode through the delay circuit.

[0005] After the control circuit and the data driving circuit are powered on, the delay circuit is turned on according to the first control signal to transmit the common voltage signal to the common electrode through the delay circuit, so that the power-on completion timing of the control circuit and the data driving circuit is earlier than the power-on completion timing of the common electrode, thereby avoiding the display panel flashing white when it is turned on.

[0006] Optionally, the delay circuit includes a first switch unit and a second switch unit, the control end of the first switch unit is used to receive the first control signal, the first end of the first switch unit is electrically connected to the ground end, the second end of the first switch unit is electrically connected to the control end of the second switch unit and the first end of the second switch unit, and is used to receive the common voltage signal, and the second end of the second switch unit is electrically connected to the common electrode.

[0007] Optionally, the delay circuit also includes a first resistor and a second resistor, one end of the first resistor is used to receive the first control signal, and the other end of the first resistor is electrically connected to the control end of the first switch unit; one end of the second resistor is electrically connected to the first end of the second switch unit, and the other end of the second resistor is electrically connected to the control end of the second switch unit.

[0008] Optionally, the first switch unit is an N-type metal semiconductor oxide transistor, and the second switch unit is a P-type metal semiconductor oxide transistor.

[0009] Optionally, the display panel further includes a discharge circuit, which is electrically connected to the common electrode. The discharge circuit is configured to be turned on according to the second control signal generated by the power management circuit and the input voltage signal to electrically connect the common electrode to the ground terminal through the discharge circuit.

[0010] Optionally, the discharge circuit includes a third switch unit and a fourth switch unit, the control end of the third switch unit is used to receive the second control signal, the first end of the third switch unit is electrically connected to the ground end and electrically connected to the first end of the fourth switch unit, the second end of the third switch unit is electrically connected to the control end of the fourth switch unit and is used to receive the input voltage signal, and the second end of the fourth switch unit is electrically connected to the ground end and electrically connected to the common electrode.

[0011] Optionally, the discharge circuit also includes a third resistor, a fourth resistor, a fifth resistor and a sixth resistor, one end of the third resistor is used to receive the input voltage signal, and the other end of the third resistor is electrically connected to the control end of the fourth switch unit; one end of the fourth resistor is electrically connected to the second end of the fourth switch unit, and the other end of the fourth resistor is electrically connected to the fifth resistor and one end of the sixth resistor; the other end of the fifth resistor is electrically connected to the ground end; and the other end of the sixth resistor is electrically connected to the common electrode.

[0012] Optionally, the display panel has a power-on stage. When the display panel is in the power-on stage, the voltage value of the second control signal starts to rise from 0V under the influence of the input voltage signal, and when it is less than the voltage threshold, the third switch unit is cut off and the fourth switch unit is turned on to discharge the residual charge on the common electrode to the ground through the discharge circuit.

[0013] Optionally, the display panel has a shutdown stage. When the display panel is in the shutdown stage, the voltage value of the second control signal begins to decrease, and when it is less than the voltage threshold, the third switch unit is turned off and the fourth switch unit is turned on to discharge the charge of the common electrode to the ground through the discharge circuit.

[0014] Optionally, the third switch unit and the fourth switch unit are N-type metal semiconductor oxide transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0016] Figure 1 A schematic diagram of a display panel frame provided in one embodiment of the present application.

[0017] Figure 2 This is a possible power-on timing waveform diagram provided by this application.

[0018] Figure 3 A schematic diagram of a delay circuit provided in one embodiment of the present application.

[0019] Figure 4 A schematic diagram of a delay circuit provided in another embodiment of the present application.

[0020] Figure 5 A schematic top view of an electronic device provided in one embodiment of the present application.

[0021] Explanation of the accompanying symbols: input voltage signal-VIN, common voltage signal-VCOM, power-on signal-Reset, data signal-source, timing signal-CLK, first control signal-C1, second control signal-C2, control end-G, first end-S, second end-D, ground end-GND, display panel-1, power management circuit-11, control circuit-12, data driving circuit-13, delay circuit-14, first switch unit-T1, second switch unit-T2, first resistor-R1, second resistor-R2, common electrode-15, discharge circuit-16, third switch unit-T3, fourth switch unit-T4, third resistor-R3, fourth resistor-R4, fifth resistor-R5, sixth resistor-R6, electronic device-2, housing-21. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] This application provides a display panel 1, see Figure 1 , Figure 1 The display panel 1 includes a power management circuit 11, a control circuit 12, a data driver circuit 13, a delay circuit 14, and a common electrode 15. The power management circuit 11 is electrically connected to the control circuit 12 and the data driver circuit 13, respectively. The power management circuit 11 is configured to power on the control circuit 12 and the data driver circuit 13 according to an input voltage signal VIN. The power management circuit 11 is also electrically connected to the common electrode 15 through the delay circuit 14. The power management circuit 11 generates a common voltage signal VCOM according to the input voltage signal VIN. After the data driver circuit 13 is powered on, the power management circuit 11 generates a power-on signal Reset. The control circuit 12 generates a first control signal C1 according to the power-on signal Reset. The delay circuit 14 is turned on according to the first control signal C1 to transmit the common voltage signal VCOM to the common electrode 15 through the delay circuit 14.

[0024] It should be noted that the input voltage signal VIN is generally provided by a power supply, which may be external to the display panel 1 or a power supply provided by the display panel 1 itself, and this application does not impose any restrictions thereon. When the display panel 1 is powered on, the input voltage signal VIN first causes the power management circuit 11 to boost the voltage. The power management circuit 11 generates the common voltage signal VCOM and provides a power-on voltage signal to the control circuit 12 and the data driver circuit 13 to power on the control circuit 12 and the data driver circuit 13. After the control circuit 12 is powered on, it is used to control the scan driver circuit to generate a scan signal to turn on the pixel circuits of the display panel 1 row by row. The control circuit 12 is also used to generate a timing control signal to control the data driver circuit 13 to generate a data signal source, so that the data signal source charges the display unit in the turned-on pixel circuit. The display panel 1 generally also includes a liquid crystal layer, the common electrode 15 is arranged on one side of the liquid crystal layer, and an electrode plate is also provided on the other side of the liquid crystal layer and is used to receive the data signal source, so as to control the loaded voltage on both sides of the liquid crystal layer to control the liquid crystal molecules in the liquid crystal layer, thereby realizing the control of the liquid crystal layer over light and completing the display function of the display panel 1.

[0025] Please also refer to Figure 2 , Figure 2 This is a possible power-on timing waveform diagram provided by this application. Figure 2 As shown, in the related art, the input voltage signal VIN is boosted by the power management circuit 11, and the power management circuit 11 generates the common voltage signal VCOM, which is directly transmitted to the common electrode 15, so that the power-on timing of the common electrode 15 precedes the power-on timing of the data driver circuit 13. The timing signal CLK is used to drive the thin-film transistors in the corresponding row pixel circuit of the display panel 1 to turn on, so as to charge the data signal source into the pixel unit. When the display panel 1 uses a single-crystal silicon power-on circuit, the high electron mobility of the IGZO-TFT can easily cause the data signal source generated by the data driver circuit 13 to be incorrectly charged. As a result, when the display panel 1 is powered on, the light emitted by the backlight source in the display panel 1 can directly pass through the liquid crystal layer, resulting in a white display screen when the display panel 1 is powered on. This is the technical problem of the display panel 1 flashing white when powered on.

[0026] In this embodiment, the delay circuit 14 is provided in the path between the common electrode 15 and the power management circuit 11. The power management circuit 11 will still generate the common voltage signal VCOM after the input voltage signal VIN is boosted for the power management circuit 11. However, it is necessary to turn on the delay circuit 14 according to the first control signal C1 generated by the control circuit 12 after the control circuit 12 and the data driving circuit 13 are powered on, so as to transmit the common voltage signal VCOM to the common electrode 15 through the delay circuit 14, thereby completing the power-on of the common electrode 15, so that the power-on timing of the common electrode 15 is later than the power-on timing of the data driving circuit 13, thereby solving the technical problem of white flashing when the display panel 1 is turned on with a lower cost and a simple circuit.

[0027] It can be understood that in this embodiment, after the control circuit 12 and the data driving circuit 13 are powered on, the delay circuit 14 is turned on according to the first control signal C1 to transmit the common voltage signal VCOM to the common electrode 15 through the delay circuit 14, so that the power-on completion timing of the control circuit 12 and the data driving circuit 13 is earlier than the power-on completion timing of the common electrode 15, thereby avoiding the display panel 1 flashing white when it is turned on.

[0028] It should be noted that while the common voltage signal VCOM is transmitted to the common electrode 15 through the delay circuit 14, the control circuit 12 also controls the scan drive circuit to generate a scan signal. In other words, the common electrode 15 and the scan drive circuit are powered on at the same time, and the power-on timing is later than that of the data drive circuit 13 to prevent the data signal source from being charged incorrectly.

[0029] In a possible implementation, please refer to Figure 3 , Figure 3 Schematic diagram of a delay circuit provided in one embodiment of the present application. The delay circuit 14 includes a first switch unit T1 and a second switch unit T2. The control terminal G of the first switch unit T1 is used to receive the first control signal C1. The first terminal S of the first switch unit T1 is electrically connected to the ground terminal GND. The second terminal D of the first switch unit T1 is electrically connected to the control terminal G of the second switch unit T2 and the first terminal S of the second switch unit T2, and is used to receive the common voltage signal VCOM. The second terminal D of the second switch unit T2 is electrically connected to the common electrode 15.

[0030] Specifically, the first switch unit T1 is turned on when the first control signal C1 is applied, and the second switch unit T2 is turned on when the ground terminal GND is applied. In this embodiment, when the display panel 1 is turned on, after the power management circuit 11 generates the common voltage signal VCOM, before the control circuit 12 and the data driving circuit 13 are powered on, that is, before the control circuit 12 generates the first control signal C1, the first switch unit T1 and the second switch unit T2 are turned off; when the control circuit 12 and the data driving circuit 13 are powered on, the control circuit 12 generates the first control signal C1, and the first switch unit T1 is turned on when the first control signal C1 is applied. The ground terminal GND pulls down the voltage of the control terminal G of the second switch unit T2 through the first switch unit T1, thereby turning on the second switch unit T2, and transmitting the common voltage signal VCOM to the common electrode 15 through the second switch unit T2, thereby powering on the common electrode 15.

[0031] It is understood that in this embodiment, by configuring the first switch unit T1 and the second switch unit T2, the power-on timing of the common electrode 15 is achieved later than the power-on timing of the control circuit 12 and the data drive circuit 13. In other possible embodiments, the delay circuit 14 can also have other circuit designs, as long as it does not affect the power-on timing of the common electrode 15 being later than the power-on timing of the control circuit 12 and the data drive circuit 13, and this application is not limited to this.

[0032] In one possible implementation, please refer again to Figure 3 The delay circuit 14 further includes a first resistor R1 and a second resistor R2, one end of the first resistor R1 is used to receive the first control signal C1, and the other end of the first resistor R1 is electrically connected to the control end G of the first switch unit T1; one end of the second resistor R2 is electrically connected to the first end S of the second switch unit T2, and the other end of the second resistor R2 is electrically connected to the control end G of the second switch unit T2.

[0033] In this embodiment, the first resistor R1 is a 0 ohm resistor, and the second resistor R2 has a resistance value of 10 kilo-ohms. It should be noted that the first resistor R1 being a 0 ohm resistor does not mean that its resistance value is 0, but rather that its resistance value is very small, so as to bridge the control circuit 12 and the control terminal G of the first switch unit T1; the second resistor R2 serves to limit current and divide voltage. It is understood that in other possible embodiments, the resistance value of the first resistor R1 has an error range of ±1%, and the resistance value of the second resistor R2 has an error range of ±5%. This application does not limit the specific values ​​of the resistance values ​​of the first resistor R1 and the second resistor R2.

[0034] In a possible implementation, please refer to Figure 4 , Figure 4 Schematic diagram of a delay circuit provided in another embodiment of the present application. The display panel 1 further includes a discharge circuit 16, which is electrically connected to the common electrode 15. The discharge circuit 16 is configured to be turned on according to the second control signal C2 generated by the power management circuit 11 and the input voltage signal VIN, so as to electrically connect the common electrode 15 to the ground terminal GND through the discharge circuit 16.

[0035] It should be noted that, under normal circumstances, the display panel 1 has a power-on stage and a power-off stage. Before the display panel 1 is powered on, or after the display panel 1 is powered off, a certain amount of charge may remain on the common electrode 15 and not be released, resulting in the display panel 1 flashing white the next time it is powered on.

[0036] It can be understood that in this embodiment, the second control signal C2 and the input voltage signal VIN can be used to determine whether the display panel 1 is in the power-on stage or in the power-off stage, so as to turn on the discharge circuit 16 at the right time, and electrically connect the common electrode 15 to the ground terminal GND through the discharge circuit 16 to release the residual charge on the common electrode 15, thereby avoiding the display panel 1 from flashing white when it is turned on.

[0037] In one possible implementation, please refer again to Figure 4The discharge circuit 16 includes a third switch unit T3 and a fourth switch unit T4, the control end G of the third switch unit T3 is used to receive the second control signal C2, the first end S of the third switch unit T3 is electrically connected to the ground end GND and electrically connected to the first end S of the fourth switch unit T4, the second end D of the third switch unit T3 is electrically connected to the control end G of the fourth switch unit T4 and is used to receive the input voltage signal VIN, and the second end D of the fourth switch unit T4 is electrically connected to the ground end GND and electrically connected to the common electrode 15.

[0038] Specifically, the third switch unit T3 is turned on when the second control signal C2 is applied, and the fourth switch unit T4 is turned on when the input voltage signal VIN is applied. In one possible embodiment, the display panel 1 has a power-on phase. When the display panel 1 is in the power-on phase, the voltage value of the second control signal C2 begins to rise from 0V under the influence of the input voltage signal VIN, and when it is less than a voltage threshold, the third switch unit T3 is turned off and the fourth switch unit T4 is turned on, so that the residual charge on the common electrode 15 is discharged to the ground terminal GND through the discharge circuit 16.

[0039] In this embodiment, when the display panel 1 just enters the power-on stage, the voltage value of the second control signal C2 is usually 0V, and the voltage value of the input voltage signal VIN is usually greater than 0V. When the input voltage signal VIN is loaded into the power management circuit 11, the input voltage signal VIN pulls up the voltage value of the second control signal C2. The voltage value of the second control signal C2 starts to rise from 0V under the influence of the input voltage signal VIN, but the boost of the power management circuit 11 is not yet completed, so that the voltage value of the second control signal C2 generated by the power management circuit 11 is low and less than the voltage threshold, so that the third switch unit T3 is turned off, and the fourth switch unit T4 is turned on under the loading of the input voltage signal VIN, thereby discharging the residual charge of the common electrode 15 to the ground terminal GND through the discharge circuit 16. After the power management circuit 11 completes the voltage boost, the voltage value of the second control signal C2 generated by the power management circuit 11 is greater than or equal to the voltage threshold, causing the third switch unit T3 to turn on, thereby lowering the voltage value of the control terminal G of the fourth switch unit T4, thereby turning off the fourth switch unit T4. Subsequently, the common voltage signal VCOM is transmitted to the common electrode 15 via the second switch unit T2, powering the common electrode 15. It can be understood that in this embodiment, during the power-on phase of the display panel 1, the charge remaining in the common electrode 15 after the previous power-off is released, thereby preventing the display panel 1 from flashing white when it turns on.

[0040] In one possible embodiment, the display panel 1 has a shutdown stage. When the display panel 1 is in the shutdown stage, the voltage value of the second control signal C2 begins to decrease and is less than the voltage threshold, the third switch unit T3 is turned off and the fourth switch unit T4 is turned on to discharge the charge of the common electrode 15 to the ground terminal GND through the discharge circuit 16.

[0041] It can be understood that in this embodiment, when the display panel 1 enters the shutdown stage, the voltage value of the second control signal C2 begins to decrease and is less than the voltage threshold, the third switch unit T3 is turned off, and the fourth switch unit T4 is turned on under the loading of the input voltage signal VIN to discharge the charge of the common electrode 15 to the ground terminal GND through the discharge circuit 16, thereby achieving simultaneous rapid discharge of the common electrode 15, the control circuit 12 and the data driving circuit 13.

[0042] It can be understood that, through the configuration of the third switch unit T3 and the fourth switch unit T4, the residual charge of the common electrode 15 is released and the charge is rapidly discharged simultaneously with the control circuit 12 and the data driving circuit 13. In other possible implementations, the discharge circuit 16 can also have other circuit designs, as long as they do not affect the release of the residual charge of the common electrode 15 and the rapid discharge simultaneously with the control circuit 12 and the data driving circuit 13, and this application is not limited thereto.

[0043] In one possible implementation, please refer again to Figure 4 The discharge circuit 16 further includes a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, one end of the third resistor R3 is used to receive the input voltage signal VIN, and the other end of the third resistor R3 is electrically connected to the control end G of the fourth switch unit T4; one end of the fourth resistor R4 is electrically connected to the second end D of the fourth switch unit T4, and the other end of the fourth resistor R4 is electrically connected to the fifth resistor R5 and one end of the sixth resistor R6; the other end of the fifth resistor R5 is electrically connected to the ground end GND; and the other end of the sixth resistor R6 is electrically connected to the common electrode 15.

[0044] In this embodiment, the resistance value of the third resistor R3 is 10 kilo-ohms, the fourth resistor R4 and the sixth resistor R6 are 0-ohm resistors, and the resistance value of the fifth resistor R5 is 1 kilo-ohm. It should be noted that the introduction of the 0-ohm resistor is described above and will not be repeated in this application; the third resistor R3 and the fifth resistor R5 play the role of current limiting and voltage dividing. It is understandable that in other possible embodiments, the resistance value error range of the fourth resistor R4 and the sixth resistor R6 is ±1%, and the resistance value error range of the third resistor R3 and the fifth resistor R5 is ±5%. This application does not limit the specific numerical values ​​of the resistance values ​​of the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6.

[0045] In a possible implementation, the first switch unit T1 , the third switch unit T3 , and the fourth switch unit T4 are N-type metal semiconductor oxide transistors, and the second switch unit T2 is a P-type metal semiconductor oxide transistor.

[0046] In this embodiment, the first switch unit T1, the third switch unit T3, and the fourth switch unit T4 are N-type metal semiconductor oxide transistors, and the second switch unit T2 is a P-type metal semiconductor oxide transistor. In other words, applying a high-level voltage to the control terminals G of the first switch unit T1, the third switch unit T3, and the fourth switch unit T4 can turn on the first switch unit T1, the third switch unit T3, and the fourth switch unit T4, and applying a low-level voltage to the control terminal G of the second switch unit T2 can turn on the second switch unit T2. Conversely, applying a low-level voltage to the control terminals G of the first switch unit T1, the third switch unit T3, and the fourth switch unit T4 can turn off the first switch unit T1, the second switch unit T2, the third switch unit T3, and the fourth switch unit T4, and applying a high-level voltage to the control terminal G of the second switch unit T2 can turn off the second switch unit T2. It should be noted that the high level and low level mentioned in this application are relative values, that is, signals relatively higher or lower than a certain potential are regarded as high-level voltage signals or low-level voltage signals.

[0047] It is understood that in this embodiment, the common voltage signal VCOM is a high-level voltage signal greater than 0V. In other possible embodiments, when the common voltage signal VCOM is a low-level voltage signal less than 0V, the first switch unit T1, the third switch unit T3, and the fourth switch unit T4 can also be P-type metal semiconductor oxide transistors, and the second switch unit T2 can also be an N-type metal semiconductor oxide transistor, whose on- and off-voltages are complementary to those of the N-type metal semiconductor oxide transistors. At the same time, the voltage values ​​of the first control signal C1, the second control signal C2, and the input voltage signal VIN should also be adjusted accordingly. On this basis, as long as it does not affect the design objectives of the delay circuit 14 and the discharge circuit 16, the present application does not limit the types of the first switch unit T1, the second switch unit T2, the third switch unit T3, and the fourth switch unit T4.

[0048] This application also provides an electronic device 2, please refer to Figure 5 , Figure 5 This is a schematic top view of an electronic device according to one embodiment of the present application. The electronic device 2 includes a housing 21 and the display panel 1 described above. The housing 21 is used to support the display panel 1. For details, please refer to the above description of the display panel 1, which will not be repeated here.

[0049] It should be noted that the electronic device 2 in the implementation manner of the present application can be an electronic device 2 such as a television, a mobile phone, a smart phone, a tablet computer, an e-reader, a wearable portable device, a laptop computer, etc., which can communicate with a data transfer server through the Internet. The data transfer server can be an instant messaging server, an SNS (Social Networking Services) server, etc., and the implementation manner of the present application does not limit this.

[0050] It can be understood that in this embodiment, after the control circuit 12 and the data driving circuit 13 are powered on, the delay circuit 14 is turned on according to the first control signal C1 to transmit the common voltage signal VCOM to the common electrode 15 through the delay circuit 14, so that the power-on completion timing of the control circuit 12 and the data driving circuit 13 is earlier than the power-on completion timing of the common electrode 15, thereby avoiding the white flash when the electronic device 2 is turned on.

[0051] This document uses specific examples to illustrate the principles and implementation methods of this application. The description of the above implementation methods is only used to help understand the core idea of ​​this application. At the same time, for those skilled in the art, based on the idea of ​​this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on this application.

Claims

1. A display panel, characterized in that: The display panel includes a power management circuit, a control circuit, a data driving circuit, a delay circuit, and a common electrode. The power management circuit is electrically connected to the control circuit and the data driving circuit, respectively. The power management circuit is used to power on the control circuit and the data driving circuit according to an input voltage signal. The power management circuit is also electrically connected to the common electrode through the delay circuit. The power management circuit generates a common voltage signal according to the input voltage signal. After the data driving circuit is powered on, the power management circuit generates a power-on signal. The control circuit generates a first control signal according to the power-on signal. The delay circuit is turned on according to the first control signal to transmit the common voltage signal to the common electrode through the delay circuit. In which, the delay circuit includes a first switch unit and a second switch unit, the control end of the first switch unit is used to receive the first control signal, the first end of the first switch unit is electrically connected to the ground end, the second end of the first switch unit is electrically connected to the control end of the second switch unit and the first end of the second switch unit, and is used to receive the common voltage signal, and the second end of the second switch unit is electrically connected to the common electrode.

2. The display panel according to claim 1, wherein The delay circuit also includes a first resistor and a second resistor, one end of the first resistor is used to receive the first control signal, and the other end of the first resistor is electrically connected to the control end of the first switch unit; one end of the second resistor is electrically connected to the first end of the second switch unit, and the other end of the second resistor is electrically connected to the control end of the second switch unit.

3. The display panel according to claim 1, wherein The first switch unit is an N-type metal semiconductor oxide transistor, and the second switch unit is a P-type metal semiconductor oxide transistor.

4. The display panel according to claim 1, wherein: The display panel further includes a discharge circuit electrically connected to the common electrode. The discharge circuit is configured to be turned on according to a second control signal generated by the power management circuit and the input voltage signal to electrically connect the common electrode to a ground terminal through the discharge circuit.

5. The display panel according to claim 4, wherein: The discharge circuit includes a third switch unit and a fourth switch unit, the control end of the third switch unit is used to receive the second control signal, the first end of the third switch unit is electrically connected to the ground end and electrically connected to the first end of the fourth switch unit, the second end of the third switch unit is electrically connected to the control end of the fourth switch unit and is used to receive the input voltage signal, and the second end of the fourth switch unit is electrically connected to the ground end and electrically connected to the common electrode.

6. The display panel according to claim 5, wherein: The discharge circuit also includes a third resistor, a fourth resistor, a fifth resistor and a sixth resistor, one end of the third resistor is used to receive the input voltage signal, and the other end of the third resistor is electrically connected to the control end of the fourth switch unit; one end of the fourth resistor is electrically connected to the second end of the fourth switch unit, and the other end of the fourth resistor is electrically connected to the fifth resistor and one end of the sixth resistor; the other end of the fifth resistor is electrically connected to the ground end; and the other end of the sixth resistor is electrically connected to the common electrode.

7. The display panel according to claim 5, wherein: The display panel has a power-on stage. When the display panel is in the power-on stage, the voltage value of the second control signal starts to rise from 0V under the influence of the input voltage signal, and when it is less than the voltage threshold, the third switch unit is turned off and the fourth switch unit is turned on to discharge the residual charge on the common electrode to the ground terminal through the discharge circuit.

8. The display panel according to claim 5, wherein: The display panel has a shutdown stage. When the display panel is in the shutdown stage, the voltage value of the second control signal begins to decrease, and when it is less than the voltage threshold, the third switch unit is turned off and the fourth switch unit is turned on to discharge the charge of the common electrode to the ground end through the discharge circuit.

9. The display panel according to claim 5, wherein: The third switch unit and the fourth switch unit are N-type metal semiconductor oxide transistors.

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