A contact pad structure and method of manufacturing the same

Abstract

Embodiments of the present application disclose a contact pad structure and a manufacturing method thereof. The contact pad structure comprises a substrate, a plurality of first contact pads arranged on a first region of the substrate, a first dielectric layer arranged on the substrate and covering the plurality of first contact pads, the first dielectric layer forming a recess between two adjacent first contact pads, an etching stop layer arranged on the first dielectric layer and filling part of the recess, the etching stop layer being provided with a first gap in each recess, and a second dielectric layer arranged on the etching stop layer, the second dielectric layer filling the recess and being provided with a second gap in the recess. In this way, the parasitic capacitance between adjacent contact pads can be reduced, thereby improving the interference problem between the contact pads.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a contact pad structure and its manufacturing method. Background Technology

[0002] Semiconductor integrated circuit technology has continuously advanced over time, with each new generation of manufacturing processes producing products with smaller and more complex circuit designs than the previous generation. The number and density of functional components on each chip area must continuously increase due to product innovation needs, which naturally leads to smaller geometric dimensions of each component and smaller distances between components and / or circuits, resulting in more severe interference problems. Summary of the Invention

[0003] This invention discloses a contact pad structure and its manufacturing method. By setting gaps in the material layer between adjacent contact pads, the parasitic capacitance between adjacent contact pads is reduced, thereby improving the interference problem between them.

[0004] In one aspect, embodiments of the present invention disclose a contact pad structure, comprising:

[0005] Substrate;

[0006] Multiple first contact pads are disposed on a first region of the substrate;

[0007] A first dielectric layer is disposed on the substrate and covers the plurality of first contact pads, wherein the first dielectric layer forms a recess between two adjacent first contact pads;

[0008] An etch stop layer is disposed on the first dielectric layer and fills part of the recesses, wherein the etch stop layer has a first gap in each of the recesses;

[0009] A second dielectric layer is disposed on the etch stop layer, the second dielectric layer fills the depression, and a second void is provided in the depression.

[0010] Optionally, a portion of the first dielectric layer and a portion of the etch stop layer are sandwiched between each of the first gaps and any of the first contact pads, along the direction of the plane where the substrate is located.

[0011] Optionally, a portion of the first dielectric layer, a portion of the etch stop layer, and a portion of the second dielectric layer are sandwiched between each of the second gaps and any of the first contact pads along the direction of the plane where the substrate is located.

[0012] Optionally, the material composition of the etch stop layer is different from the material composition of the second dielectric layer.

[0013] Optionally, each of the first contact pads includes:

[0014] Dielectric pattern;

[0015] A conductive pattern is disposed on the dielectric pattern, wherein the plane containing the upper surface of the dielectric pattern is located on the side away from the substrate relative to the plane containing the bottom surface of the recess.

[0016] Optionally, the plane containing the upper surface of the dielectric pattern is located on the side away from the substrate relative to the first gap.

[0017] Optionally, each of the second gaps is located on the side away from the substrate relative to each of the first gaps, and the plane containing the upper surface of the conductive pattern is located on the side away from the substrate relative to the second gaps.

[0018] Optionally, the material composition of the dielectric pattern differs from that of the substrate.

[0019] Optionally, the etch stop layer and / or the second dielectric layer are sandwiched between the first gap and the second gap.

[0020] Optionally, it also includes:

[0021] A plurality of second contact pads are disposed on a second region of the substrate, wherein the spacing between two adjacent second contact pads is smaller than the spacing between two adjacent first contact pads;

[0022] The first dielectric layer also covers the plurality of second contact pads and fills the space between the plurality of second contact pads.

[0023] In another aspect, embodiments of the present invention disclose a method for manufacturing a contact pad structure, comprising:

[0024] Provide substrate;

[0025] A plurality of first contact pads are formed on a first region of the substrate;

[0026] A first dielectric layer is formed on the substrate, the first dielectric layer covers the plurality of first contact pads, and the first dielectric layer forms a recess between two adjacent first contact pads;

[0027] An etch stop layer is formed on the first dielectric layer, and the etch stop layer fills a portion of the recesses and forms a first void in each of the recesses;

[0028] A second dielectric layer is formed on the etch stop layer, the second dielectric layer fills the depression, and a second void is formed in the depression.

[0029] Optionally, the step of forming the first dielectric layer on the substrate further includes:

[0030] A first original dielectric layer is formed on the substrate, the first original dielectric layer covers the plurality of first contact pads, and the first original dielectric layer forms an original recess between two adjacent first contact pads;

[0031] The first original dielectric layer is etched back to remove a portion of the first dielectric layer used to form the original depression, resulting in the first dielectric layer and the depression.

[0032] Optionally, prior to the step of forming the first dielectric layer on the substrate, the method further includes:

[0033] A plurality of second contact pads are formed on a second region of the substrate, wherein the spacing between two adjacent second contact pads is smaller than the spacing between two adjacent first contact pads;

[0034] The first dielectric layer also covers the plurality of second contact pads and fills the spaces between the plurality of second contact pads. Optionally, the plurality of first contact pads and the plurality of second contact pads are formed together by a patterning process of a stacked structure formed on the substrate.

[0035] Optionally, a portion of the first dielectric layer and a portion of the etch stop layer are sandwiched between each of the first gaps and any of the first contact pads, along the direction of the plane where the substrate is located.

[0036] Optionally, a portion of the first dielectric layer, a portion of the etch stop layer, and a portion of the second dielectric layer are sandwiched between each of the second gaps and any of the first contact pads along the direction of the plane where the substrate is located.

[0037] Optionally, the material composition of the etch stop layer is different from the material composition of the second dielectric layer.

[0038] Optionally, the step of forming a plurality of first contact pads on a first region of the substrate includes:

[0039] A dielectric pattern is formed on a first region of the substrate;

[0040] A conductive pattern is formed on the dielectric pattern, wherein the plane containing the upper surface of the dielectric pattern is located on the side away from the substrate relative to the plane containing the bottom surface of the recess.

[0041] Optionally, the plane containing the upper surface of the dielectric pattern is located on the side away from the substrate relative to the first gap.

[0042] Optionally, each of the second gaps is located on the side away from the substrate relative to each of the first gaps, and the plane containing the upper surface of the conductive pattern is located on the side away from the substrate relative to the second gaps.

[0043] The contact pad structure and manufacturing method disclosed in this invention have the following advantages compared with the prior art:

[0044] (1) By setting a first gap in the etch stop layer material between two adjacent contact pads and a second gap in the material of the second dielectric layer between two adjacent contact pads, the parasitic capacitance between two adjacent contact pads can be reduced, thereby reducing the interference problem between two adjacent contact pads.

[0045] (2) The material between two adjacent contact pads is provided with a first gap and a second gap at the same time, so as to realize the combination of gaps, which can reduce the parasitic capacitance between two adjacent contact pads to a greater extent and further reduce the interference problem between two adjacent contact pads. Attached Figure Description

[0046] The accompanying drawings provide a more in-depth understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0047] Figures 1 to 5 This is a schematic diagram of the processing structure of a contact pad structure disclosed in an embodiment of the present invention. Figure 6 This is a schematic diagram of a contact pad structure disclosed in an embodiment of the present invention. Figure 2 for Figure 1 The following is a schematic diagram of the processing structure. Figure 3 for Figure 2 The following is a schematic diagram of the processing structure. Figure 4 for Figure 3 The following is a schematic diagram of the processing structure. Figure 5 for Figure 4 The subsequent processing structure diagram, and Figure 6 for Figure 5 The following is a structural diagram.

[0048] The annotations in the attached figures are explained as follows:

[0049] 10 substrates

[0050] 10BS bottom surface

[0051] 10TS upper surface

[0052] 12 dielectric layers

[0053] 12A dielectric pattern

[0054] 12B dielectric pattern

[0055] 14 Barrier Layers

[0056] 14A Obstacle Pattern

[0057] 14B obstacle pattern

[0058] 16 conductive layers

[0059] 16A conductive pattern

[0060] 16B conductive pattern

[0061] 18 First dielectric layer

[0062] 18A Part 1

[0063] 18B Part 2

[0064] 20 Etching Stop Layer

[0065] 20A Part 1

[0066] 20B Part 2

[0067] 22 Second dielectric layer

[0068] 22A Part 1

[0069] 22B Part 2

[0070] 24 contact structure

[0071] 91 Patterning Process

[0072] 92-cycle etching process

[0073] BS1 bottom surface

[0074] BS2 bottom surface

[0075] D1 Vertical direction

[0076] D2 Horizontal Direction

[0077] DS1 spacing

[0078] DS2 spacing

[0079] G1 Interval Space

[0080] G2 Interval Space

[0081] PD1 First Contact Pad

[0082] PD2 Second Contact Pad

[0083] RC1 dent

[0084] RC2 dent

[0085] R1 Zone 1

[0086] R2 Second District

[0087] ST stacked structure

[0088] TS1 upper surface

[0089] TS2 upper surface

[0090] TS3 upper surface

[0091] TS4 upper surface

[0092] V1 First Gap

[0093] V2 Second Gap Detailed Implementation

[0094] To enable those skilled in the art to further understand the embodiments of the present invention, several preferred embodiments are listed below, and the technical solutions and desired effects of the embodiments are described in detail with reference to the accompanying drawings. Those skilled in the art can, without departing from the spirit of the embodiments of the present invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0095] The terms “forming” or “setting” are used below to describe the act of applying a layer of material to a target object. These terms are intended to describe any feasible layer forming technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0096] Please see Figure 6 . Figure 6 This is a schematic diagram of a contact pad structure disclosed in an embodiment of the present invention. Figure 6 As shown, the contact pad structure disclosed in this embodiment includes: a substrate 10, a first dielectric layer 18, a second dielectric layer 22, an etch stop layer 20, at least two first contact pads PD1, a first gap V1, and a second gap V2. The substrate 10 may include a first region R1 and a second region R2, and a plurality of first contact pads PD1 are disposed on the first region R1 of the substrate 10.

[0097] The first region R1 and the second region R2 can be adjacent regions on the substrate that do not overlap.

[0098] A first dielectric layer 18 is disposed on the substrate 10 and covers a plurality of first contact pads PD1, and the first dielectric layer 18 has a recess RC2 located between two adjacent first contact pads PD1. An etch stop layer 20 is disposed on the first dielectric layer 18 and partially located in the recess RC2, and a first gap V1 is disposed in the etch stop layer 20 and located in the recess RC2. A second dielectric layer 22 is disposed on the etch stop layer 20 and partially located in the recess RC2, and a second gap V2 is disposed in the second dielectric layer 22 and located in the recess RC2. By forming a gap in the material layer located between adjacent first contact pads PD1, the parasitic capacitance between adjacent first contact pads PD1 can be reduced, thereby improving interference problems between them (e.g., but not limited to signal interference problems).

[0099] Through the above embodiments, the present invention provides a first gap in the etch stop layer material between two adjacent contact pads and a second gap in the material of the second dielectric layer between two adjacent contact pads, thereby achieving a combination of gaps. This can reduce the parasitic capacitance between two adjacent contact pads to a greater extent and further reduce the interference problem between two adjacent contact pads.

[0100] In some embodiments, the substrate 10 may comprise a single layer or multiple layers of material, such as a dielectric layer, a substrate, or a substrate and a dielectric layer disposed thereon, but is not limited thereto. The dielectric layer may comprise oxide dielectric materials (e.g., but not limited to silicon oxide), nitride dielectric materials (e.g., but not limited to silicon nitride), oxynitride dielectric materials (e.g., but not limited to silicon oxynitride), carbonitride dielectric materials (e.g., but not limited to silicon carbonitride), or other suitable dielectric materials. The substrate may comprise a semiconductor substrate, such as a silicon substrate, a silicon-germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials, but is not limited thereto. Furthermore, active elements, passive elements, and / or other circuits (not shown) may be formed on the substrate, and the first contact pad PD1 may be electrically connected to the elements and / or circuits on the substrate via other lines, but is not limited thereto. In some embodiments, the first contact pad PD1 may be disposed in the edge region of the integrated circuit structure, so the first contact pad PD1 may be regarded as an edge contact pad, but is not limited thereto.

[0101] In some embodiments, the first contact pad PD1, the first dielectric layer 18, the etch stop layer 20 and the second dielectric layer 22 described above may be disposed on the upper surface 10TS of the substrate 10, and the upper surface 10TS and the lower surface 10BS of the substrate 10 may be two opposing surfaces of the substrate 10 in the vertical direction D1. Therefore, the vertical direction D1 may be regarded as the thickness direction of the substrate 10, but is not limited thereto. In this document, the distance in the vertical direction D1 between a relatively high position and / or component and the upper surface 10TS of the substrate 10 may be greater than the distance in the vertical direction D1 between a relatively low position and / or component and the upper surface 10TS of the substrate 10. The lower part or bottom of each component may be closer to the upper surface 10TS of the substrate 10 in the vertical direction D1 than its upper part or top. Another component above a component may be considered relatively far from the upper surface 10TS of the substrate 10 in the vertical direction D1, and another component below a component may be considered relatively close to the upper surface 10TS of the substrate 10 in the direction D1. Furthermore, the upper surface of a component may include, but is not limited to, the topmost surface of that component in the vertical direction D1, and the bottom surface of a component may include, the bottommost surface of that component in the vertical direction D1.

[0102] In some embodiments, the contact pad structure may include two or more first contact pads PD1 disposed on the substrate 10. The multiple first contact pads PD1 may be arranged separately from each other in a horizontal direction D2 that is substantially orthogonal to the vertical direction D1. Each first contact pad PD1 may have substantially the same structure and size, and the multiple first contact pads PD1 may be arranged along the horizontal direction D2 with substantially equal spacing, but this is not a limitation. In some embodiments, each first contact pad PD1 may include multiple layers of material, for example, each first contact pad PD1 may include a dielectric pattern 12A, a barrier pattern 14A, and a conductive pattern 16A stacked in the vertical direction D1, but this is not a limitation. In each first contact pad PD1, a conductive pattern 16A may be disposed on top of a dielectric pattern 12A in the vertical direction D1, and a barrier pattern 14A may be sandwiched between the dielectric pattern 12A and the conductive pattern 16A in the vertical direction D1 and directly contact the dielectric pattern 12A and the conductive pattern 16A. The dielectric pattern 12A, the barrier pattern 14A, and the conductive pattern 16A may be disposed correspondingly to each other in the vertical direction D1 and have substantially the same projected pattern and / or projected area in the vertical direction D1, but this is not a limitation. In some embodiments, the dielectric pattern 12A may include an oxide dielectric material, a nitride dielectric material, or other suitable dielectric material, and the material composition of the dielectric pattern 12A may be different from the material composition of the substrate 10 to avoid damage to the substrate 10 during the manufacturing process of forming the first contact pad PD1, but this is not a limitation. The barrier pattern 14A may include titanium nitride, tantalum nitride or other suitable conductive barrier materials, while the conductive pattern 16A may include copper, aluminum, tungsten, molybdenum, alloys of the above materials, composite layer structures or other suitable conductive materials.

[0103] In this embodiment of the invention, the horizontal direction can be considered as the direction along the plane where the substrate is located, and the vertical direction can be considered as the normal direction along the plane where the substrate is located.

[0104] The first dielectric layer 18 may comprise an oxide dielectric material or other suitable dielectric material, and the first dielectric layer 18 may have a recess RC2. The recess RC2 may be located in the spacer G1 between two adjacent first contact pads PD1, and the spacer G1 is not filled by the first dielectric layer 18. In some embodiments, the first dielectric layer 18 may cover the upper surface of each first contact pad PD1, the sidewalls of each first contact pad PD1, and the upper surface 10TS of the substrate 10, and the first dielectric layer 18 covering the upper surface 10TS of the substrate 10 may have the lowest surface area (e.g., the lowest upper surface) relative to other portions of the first dielectric layer 18. Furthermore, the etch stop layer 20 may comprise a nitride dielectric material or other suitable dielectric material, the second dielectric layer 22 may comprise an oxide dielectric material or other suitable dielectric material, and the material composition of the etch stop layer 20 may differ from the material composition of the first dielectric layer 18 and the material composition of the second dielectric layer 22. In some embodiments, the etch stop layer 20 may be conformally disposed on the upper surface of the first dielectric layer 18 and in direct contact with the upper surface of the first dielectric layer 18. Therefore, a portion of the etch stop layer 20 may be disposed in the recess RC2 of the first dielectric layer 18, and the recess RC2 is not completely filled by the etch stop layer 20. A second dielectric layer 22 may be disposed on the upper surface of the etch stop layer 20 and in direct contact with the upper surface of the etch stop layer 20, and a portion of the second dielectric layer 22 may be disposed in the recess RC2 of the first dielectric layer 18. By controlling the condition of the recess RC2, such as controlling the depth, aspect ratio, or other structural characteristics of the recess RC2 in the vertical direction D1, it is possible to easily form a first void V1 in the etch stop layer 20 during the step of forming the etch stop layer 20, and the first void V1 is easily formed in the etch stop layer 20 located in the recess RC2. Furthermore, since the recess RC2 is not completely filled by the etch stop layer 20, it is relatively easy to form a second gap V2 in the second dielectric layer 22 located in the recess RC2 when the second dielectric layer 22 is formed on the etch stop layer 20. In some embodiments, the first gap V1 and the second gap V2 may each include an air gap or other types of gap structures, and the first gap V1 and the second gap V2 are separated from each other, but this is not a limitation.

[0105] In some embodiments, the bottom surface BS2 of the recess RC2 may be lower than the upper surface TS1 of the dielectric pattern 12A in each first contact pad PD1 in the vertical direction D1, and the first gap V1 may be lower than the upper surface TS1 of the dielectric pattern 12A in the vertical direction D1, but is not limited thereto. Furthermore, in some embodiments, the second gap V2 may be above the first gap V1 in the vertical direction D1, and the second gap V2 may be lower than the upper surface TS2 of the conductive pattern 16A in each first contact pad PD1 in the vertical direction D1, but is not limited thereto. In some embodiments, the first gap V1 and the second gap V2 may be surrounded by the etch stop layer 20 and the second dielectric layer 22, respectively. Therefore, a portion of the first dielectric layer 18 and a portion of the etch stop layer 20 may be sandwiched in the horizontal direction D2 between the first gap V1 and one of the plurality of first contact pads PD1 (e.g., the dielectric pattern 12A of this first contact pad PD1). Conversely, a portion of the first dielectric layer 18, a portion of the etch stop layer 20, and a portion of the second dielectric layer 22 may be sandwiched in the horizontal direction D2 between the second gap V2 and one of the plurality of first contact pads PD1 (e.g., the dielectric pattern 12A, barrier pattern 14A, and / or conductive pattern 16A of this first contact pad PD1). In some embodiments, the first gap V1 may not be completely covered by the etch stop layer 20 and may be directly connected to the first dielectric layer 18 and / or the second dielectric layer 22, and the second gap V2 may not be completely covered by the second dielectric layer 22 and may be directly connected to the etch stop layer 20, but this is not a limitation. In some embodiments, the contact structure 24 may penetrate the second dielectric layer 22, the etch stop layer 20, and the first dielectric layer 18 to contact the corresponding first contact pad PD1 to form an electrical connection.

[0106] In some embodiments, the contact pad structure may further include a plurality of second contact pads PD2 disposed on the second region R2 of the substrate 10, and the spacing between two adjacent second contact pads PD2 is smaller than the spacing between two adjacent first contact pads PD1. That is, the plurality of second contact pads PD2 may be arranged in a relatively close manner on the substrate 10. For example, the spacing DS2 between two adjacent second contact pads PD2 in the horizontal direction D2 may be smaller than the spacing DS1 between two adjacent first contact pads PD1 in the horizontal direction D2. In some embodiments, the spacing DS1 may be considered as the distance between two adjacent first contact pads PD1 in the horizontal direction D2 and / or the length of the gap space G1 between two adjacent first contact pads PD1 in the horizontal direction D2, while the spacing DS2 may be considered as the distance between two adjacent second contact pads PD2 in the horizontal direction D2 and / or the length of the gap space G2 between two adjacent second contact pads PD2 in the horizontal direction D2, and no contact pads are disposed in the gap space G1 and the gap space G2, but this is not a limitation.

[0107] In some embodiments, each second contact pad PD2 may include multiple layers of material. For example, each second contact pad PD2 may include a dielectric pattern 12B, a barrier pattern 14B, and a conductive pattern 16B stacked in the vertical direction D1, but this is not a limitation. In each second contact pad PD2, the conductive pattern 16B may be disposed on top of the dielectric pattern 12B in the vertical direction D1, and the barrier pattern 14B may be sandwiched between the dielectric pattern 12B and the conductive pattern 16B in the vertical direction D1 and directly contact the dielectric pattern 12B and the conductive pattern 16B. The dielectric pattern 12B, the barrier pattern 14B, and the conductive pattern 16B may be correspondingly disposed in the vertical direction D1 and have substantially the same projected pattern and / or projected area in the vertical direction D1, but this is not a limitation. Furthermore, in some embodiments, the first contact pad PD1 and the second contact pad PD2 can be formed together using the same manufacturing process. Therefore, the material composition of the dielectric pattern 12B, the barrier pattern 14B, and the conductive pattern 16B can be the same as that of the dielectric pattern 12A, the barrier pattern 14A, and the conductive pattern 16A, respectively. The upper surface TS3 of the dielectric pattern 12B can be substantially equal in height to the upper surface TS1 of the dielectric pattern 12A, and the upper surface TS4 of the conductive pattern 16B can be substantially equal in height to the upper surface TS2 of the conductive pattern 16A, but this is not a limitation.

[0108] Furthermore, the aforementioned first dielectric layer 18, etch stop layer 20, and second dielectric layer 22 may also be partially disposed on the second region R2 of the substrate 10. That is, the first portion 18A and the second portion 18B of the first dielectric layer 18 may be disposed on the first region R1 and the second region R2 of the substrate 10, respectively; the first portion 20A and the second portion 20B of the etch stop layer 20 may be disposed on the first region R1 and the second region R2 of the substrate 10, respectively; and the first portion 22A and the second portion 22B of the second dielectric layer 22 may be disposed on the first region R1 and the second region R2 of the substrate 10, respectively. The first dielectric layer 18 (e.g., the second portion 18B) may cover a plurality of second contact pads PD2, and the space between two second contact pads PD2 (e.g., the spacer G2) may be filled by the first dielectric layer 18. Since the space G2 between adjacent second contact pads PD2 is small, the first dielectric layer 18 can fill the space G2 without forming a depression in the space G2. Therefore, the second portion 20B of the etch stop layer 20 and the second portion 22B of the second dielectric layer 22 will not be formed in the space G2 between adjacent second contact pads PD2.

[0109] Please see Figures 1 to 6This invention discloses a method for manufacturing a contact pad structure, comprising the following steps: At least two first contact pads PD1 are formed on a first region R1 of a substrate 10. A first dielectric layer 18 is formed on the substrate 10, covering a plurality of first contact pads PD1, and the first dielectric layer 18 has a recess RC2 located between two adjacent first contact pads PD1. An etch stop layer 20 is formed on the first dielectric layer 18, a portion of which is located in the recess RC2, and a first void V1 is formed in the etch stop layer 20 and located in the recess RC2. A second dielectric layer 22 is formed on the etch stop layer 20, a portion of which is located in the recess RC2, and a second void V2 is formed in the second dielectric layer 22 and located in the recess RC2.

[0110] To further explain, the manufacturing method of the contact pad structure in this embodiment may include, but is not limited to, the following steps. For example... Figure 1 As shown, a stacked structure ST can be formed on the first region R1 and the second region R2 of the substrate 10. The stacked structure ST may include a dielectric layer 12, a barrier layer 14, and a conductive layer 16 stacked in the vertical direction D1. The dielectric layer 12 may include an oxide dielectric material, a nitride dielectric material, or other suitable dielectric material; the barrier layer 14 may include titanium nitride, tantalum nitride, or other suitable conductive barrier materials; and the conductive layer 16 may include copper, aluminum, tungsten, molybdenum, alloys of the above materials, composite layer structures, or other suitable conductive materials. Then, as... Figures 1 to 2 As shown, a patterning process 91 can be performed on the stacked structure ST to form a plurality of first contact pads PD1 and a plurality of second contact pads PD2 on the first region R1 and the second region R2 of the substrate 10, respectively. A spacing space G1 is formed between the plurality of first contact pads PD1, and a spacing space G2 is formed between the plurality of second contact pads PD2. In other words, in some embodiments, the plurality of first contact pads PD1 and the plurality of second contact pads PD2 can be formed together by patterning the stacked structure ST formed on the substrate 10 using the patterning process 91. At least a portion of the dielectric layer 12 can be patterned by the patterning process 91 to become dielectric patterns 12A and 12B, at least a portion of the barrier layer 14 can be patterned by the patterning process 91 to become barrier patterns 14A and 14B, and at least a portion of the conductive layer 16 can be patterned by the patterning process 91 to become conductive patterns 16A and 16B, but this is not a limitation.

[0111] Then, as Figure 3As shown, a first dielectric layer 18 can be formed on the substrate 10 to cover each first contact pad PD1 and each second contact pad PD2. In other words, the first dielectric layer 18 is formed after the step of forming the first contact pads PD1 and the second contact pads PD2. In some embodiments, the first contact pads PD1 may be formed on the substrate 10 without forming the second contact pads PD2, depending on the design requirements. In some embodiments, since the spacing between adjacent second contact pads PD2 is small and the spacing between adjacent first contact pads PD1 is large, the second portion 18B of the first dielectric layer 18 can substantially fill the space between adjacent second contact pads PD2 (e.g., the spacer space G2), while the first portion 18A of the first dielectric layer 18 will not fill the space between adjacent first contact pads PD1 (e.g., the spacer space G1) and will form a recess RC1 between adjacent first contact pads PD1. Then, as Figures 3 to 4 As shown, in some embodiments, the first dielectric layer 18 may be selectively etched back 92 after its formation to remove a portion of the first dielectric layer 18 and adjust the recess RC1. In some embodiments, the etch-back process 92 may thin the thickness of a second portion 18B of the first dielectric layer 18, but the second portion 18B of the first dielectric layer 18 still covers the upper surface of each second contact pad PD2 after the etch-back process 92. Furthermore, the etch-back process 92 may reduce the thickness of the first dielectric layer 18 located on each first contact pad PD1 and adjust the depth of the recess RC1 in the vertical direction D1, for example, by reducing the distance between the bottom surface BS1 of the recess RC1 and the substrate 10. For example, the recess RC1 may become a recess RC2 after the etch-back process 92, and the distance between the bottom surface BS2 of the recess RC2 and the substrate 10 in the vertical direction D1 may be smaller than the distance between the bottom surface BS1 of the recess RC1 and the substrate 10 in the vertical direction D1.

[0112] Then, as Figures 3 to 5 As shown, an etch stop layer 20 can be formed after the etch-back process 92. The etch stop layer 20 can be conformally formed on the upper surface of the first dielectric layer 18, and a portion of the etch stop layer 20 can be formed in the recess RC2. Due to the influence of the recess RC2 of the first dielectric layer 18 and / or the process conditions for forming the etch stop layer 20 (e.g., but not limited to film deposition rate, process temperature, etc.), a first void V1 can be formed in the etch stop layer 20 formed in the recess RC2, so that the recess RC2 is not completely filled by the etch stop layer 20. Then, as... Figure 6 As shown, a second dielectric layer 22 can be formed on the upper surface of the etch stop layer 20. Since the recess RC2 is not filled by the etch stop layer 20, a second void V2 can be formed in the second dielectric layer 22 formed in the recess RC2 by controlling the process conditions for forming the second dielectric layer 22 (e.g., but not limited to film deposition rate, process temperature, etc.).

[0113] Furthermore, in some embodiments, gaps (not shown) can be formed in the first dielectric layer 18 located between adjacent second contact pads PD2 using a suitable manufacturing process to reduce the parasitic capacitance between adjacent second contact pads PD2. However, since the spacing between adjacent first contact pads PD1 is relatively large, it is generally not easy to directly form gaps in the first dielectric layer 18 between adjacent first contact pads PD1. Therefore, between adjacent first contact pads PD1, a first gap V1 and a second gap V2 can be formed in the etch stop layer 20 and the second dielectric layer 22 using the manufacturing method described above to reduce the parasitic capacitance between adjacent first contact pads PD1.

[0114] In some embodiments, the contact structure 24 described above may be formed after the second dielectric layer 22 is formed, and through the above... Figure 3 The back etch process 92 shown can reduce the thickness of the first dielectric layer 18 and improve the etching damage and / or other negative effects on the first contact pad PD1 when forming the opening of the corresponding contact structure 24, thereby improving the relevant manufacturing yield, but is not limited thereto.

[0115] In summary, the contact pad structure and manufacturing method disclosed in the embodiments of the present invention can respectively provide a first gap and a second gap in different material layers between adjacent first contact pads, thereby reducing the parasitic capacitance between adjacent first contact pads and thus improving the interference problem between them.

[0116] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A contact pad structure, characterized by, Comprising: a substrate; a plurality of first contact pads disposed on a first region of the substrate; a first dielectric layer disposed on the substrate and covering the plurality of first contact pads, the first dielectric layer forming a recess between any two adjacent first contact pads; an etch stop layer disposed on the first dielectric layer and filling part of the recess, the etch stop layer being provided with a first void in each of the recesses; a second dielectric layer disposed on the etch stop layer, the second dielectric layer filling the recess and being provided with a second void in each of the recesses; a contact structure on the first contact pad.

2. The contact pad structure of claim 1, wherein, Each of the first voids is sandwiched between any one of the first contact pads and a part of the first dielectric layer and a part of the etch stop layer along a direction of a plane on which the substrate lies.

3. The contact pad structure of claim 1, wherein, Each of the second voids is sandwiched between any one of the first contact pads and a part of the first dielectric layer, a part of the etch stop layer and a part of the second dielectric layer along the direction of the plane on which the substrate lies.

4. The contact pad structure of claim 1, wherein, The material composition of the etch stop layer is different from that of the second dielectric layer.

5. The contact pad structure of claim 1, wherein, Each of the first contact pads comprises: a dielectric pattern; a conductive pattern disposed on the dielectric pattern, wherein a plane on which an upper surface of the dielectric pattern lies is located on a side away from the substrate relative to a plane on which a bottom surface of the recess lies.

6. The contact pad structure of claim 5, wherein, The plane on which the upper surface of the dielectric pattern lies is located on a side away from the substrate relative to the first void.

7. The contact pad structure of claim 5, wherein, Each of the second voids is located on a side away from the substrate relative to each of the first voids, and a plane on which an upper surface of the conductive pattern lies is located on a side away from the substrate relative to the second void.

8. The contact pad structure of claim 5, wherein, The material composition of the dielectric pattern is different from that of the substrate.

9. The contact pad structure of claim 1, wherein, The first void and the second void are sandwiched by the etch stop layer and / or the second dielectric layer.

10. The contact pad structure of claim 1, wherein, Further comprising: a plurality of second contact pads disposed on a second region of the substrate, wherein a spacing between any two adjacent second contact pads is smaller than a spacing between any two adjacent first contact pads; the first dielectric layer further covering the plurality of second contact pads and filling a space between the plurality of second contact pads.

11. A method of manufacturing a contact pad structure, characterized by: Comprising: providing a substrate; forming a plurality of first contact pads on a first region of the substrate; forming a first dielectric layer on the substrate, the first dielectric layer covering the plurality of first contact pads, and the first dielectric layer forming a recess between any two adjacent first contact pads; forming an etch stop layer on the first dielectric layer and filling part of the recess and forming a first void in each of the recesses; forming a second dielectric layer on the etch stop layer, the second dielectric layer filling the recess and forming a second void in each of the recesses.

12. The method of manufacturing a contact pad structure of claim 11, wherein, The step of forming a first dielectric layer on the substrate further comprises: forming a first original dielectric layer on the substrate, the first original dielectric layer covering the plurality of first contact pads, and the first original dielectric layer forming an original recess between any two adjacent first contact pads; performing a back-etching process on the first original dielectric layer to remove a portion of the first dielectric layer for forming a part of the original recess, to obtain the first dielectric layer and the recess.

13. The method of manufacturing a contact pad structure of claim 11, wherein, Before the step of forming the first dielectric layer on the substrate, further comprising: forming a plurality of second contact pads on the second region of the substrate, wherein a spacing between any two adjacent second contact pads is smaller than a spacing between any two adjacent first contact pads. The first dielectric layer further covers the plurality of second contact pads and fills the space between the plurality of second contact pads.

14. The method of manufacturing a contact pad structure of claim 13, wherein, The plurality of first contact pads and the plurality of second contact pads are formed by a patterning process on a stack structure formed on the substrate.

15. The method of manufacturing a contact pad structure of claim 11, wherein, Each of the first voids and any of the first contact pads are sandwiched by a part of the first dielectric layer and a part of the etch-stop layer along a direction of a plane on which the substrate lies.

16. The method of manufacturing a contact pad structure of claim 11, wherein, Each of the second voids and any of the first contact pads are sandwiched by a part of the first dielectric layer, a part of the etch-stop layer, and a part of the second dielectric layer along a direction of a plane on which the substrate lies.

17. The method of manufacturing a contact pad structure of claim 11, wherein, The material composition of the etch-stop layer is different from that of the second dielectric layer.

18. The method of manufacturing a contact pad structure of claim 11, wherein, The step of forming the plurality of first contact pads on the first region of the substrate comprises: forming a dielectric pattern on the first region of the substrate; forming a conductive pattern on the dielectric pattern, wherein a plane on which an upper surface of the dielectric pattern lies is located on a side away from the substrate relative to a plane on which a bottom surface of the recess lies.

19. The method of manufacturing a contact pad structure of claim 18, wherein, The plane on which the upper surface of the dielectric pattern lies is located on a side away from the substrate relative to the first void.

20. The method of manufacturing a contact pad structure of claim 18, wherein, Each of the second voids is located on a side away from the substrate relative to each of the first voids, and a plane on which an upper surface of the conductive pattern lies is located on a side away from the substrate relative to the second voids.

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