Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method of the semiconductor structure comprises the steps of providing a substrate; forming a channel bulge structure on the substrate, wherein the channel bulge structure comprises a channel bulge part and a first sacrificial layer on the channel bulge part; forming a pseudo gate structure crossing the channel bulge structure, wherein the pseudo gate structure covers part of the top and the side wall of the channel bulge structure; after the pseudo gate structure is formed, the pseudo gate structure and the first sacrificial layer at the bottom of the pseudo gate structure are sequentially removed, and the removal selection ratio between the first sacrificial layer and the channel protruding part is larger than the removal selection ratio between the pseudo gate structure and the channel protruding part. According to the embodiment of the invention, the first sacrificial layer can reduce the probability that the top of the channel lug boss is damaged in the process of removing the pseudo gate structure; and the removal selection ratio between the first sacrificial layer and the channel lug boss is greater than the removal selection ratio between the pseudo gate structure and the channel lug boss, so that the damage probability of the top of the channel lug boss can be reduced in the process of removing the first sacrificial layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.

[0003] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. Compared to planar transistors, three-dimensional transistors offer stronger gate control over the channel and better suppress short-channel effects, but this also correspondingly increases the difficulty and complexity of integrated circuit manufacturing.

[0004] However, the performance of semiconductor structures still needs to be improved. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel bump structure on the substrate, the channel bump structure including a channel bump portion and a first sacrificial layer located on the channel bump portion; forming a pseudo-gate structure spanning the channel bump structure, the pseudo-gate structure covering a portion of the top and a portion of the sidewalls of the channel bump structure; after forming the pseudo-gate structure, sequentially removing the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure, wherein the removal selectivity ratio between the first sacrificial layer and the channel bump portion is greater than the removal selectivity ratio between the pseudo-gate structure and the channel bump portion.

[0007] Optionally, the step of forming the channel protrusion structure on the substrate includes: forming a channel protrusion material layer on the substrate; forming a first sacrificial material layer on the channel protrusion material layer; and patterning the channel protrusion material layer and the first sacrificial material layer to form the channel protrusion and the first sacrificial layer.

[0008] Optionally, the step of forming a first sacrificial material layer on the channel protrusion material layer includes: depositing an initial first sacrificial material layer on the channel protrusion material layer; and modifying the initial first sacrificial material layer to form a first sacrificial material layer.

[0009] Optionally, multiple initial first sacrificial material layers are deposited and stacked on the channel protrusion material layer; the multiple initial first sacrificial material layers are modified to form multiple stacked first sacrificial material layers.

[0010] Optionally, in the step of forming the first sacrificial material layer on the channel protrusion material layer, the steps of depositing the initial first sacrificial material layer and the modification treatment are performed alternately to form a stacked multilayer first sacrificial material layer.

[0011] Optionally, multiple layers of first sacrificial material are stacked on the channel protrusion material layer, and the density of the first sacrificial material layer closest to the channel protrusion material layer is greater than the density of the first sacrificial material layers of the other layers.

[0012] Optionally, the process of forming the first sacrificial material layer on the channel protrusion material layer includes a deposition process, and the deposition process used to form the first sacrificial material layer closest to the channel protrusion material layer includes a plasma chemical deposition process or an atomic layer deposition process.

[0013] Optionally, in the step of depositing an initial first sacrificial material layer on the channel protrusion material layer, the material of the initial first sacrificial material layer includes one or more of silicon nitride, silicon, and silicon oxynitride.

[0014] Optionally, the modification process can be carried out by doping, and the dopant ions include carbon ions.

[0015] Optionally, the doping process includes an ion implantation process, wherein the process parameters of the ion implantation process include an implantation dose of 1E15 atoms per square centimeter to 1E16 atoms per square centimeter.

[0016] Optionally, after forming the first sacrificial material layer on the channel protrusion material layer and before patterning the channel protrusion material layer and the first sacrificial material layer, the method further includes performing a first annealing treatment on the first sacrificial material layer.

[0017] Optionally, the process parameters for the first annealing treatment include: an annealing temperature of 900 degrees Celsius to 1000 degrees Celsius and an annealing time of 10 minutes to 30 minutes.

[0018] Optionally, in the step of forming the channel protrusion structure, the channel protrusion includes a plurality of channel layers suspended on the substrate and spaced apart longitudinally, and the channel protrusion structure further includes a second sacrificial layer located between adjacent channel layers and between the channel layers and the substrate; in the step of sequentially removing the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure, the removal selectivity ratio between the first sacrificial layer and the channel layer is greater than the removal selectivity ratio between the pseudo-gate structure and the channel layer.

[0019] Optionally, after removing the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure in sequence, the method further includes: removing the second sacrificial layer; and after removing the second sacrificial layer, performing a second annealing process on the channel layer.

[0020] Optionally, in the step of performing a second annealing treatment on the channel layer, the channel layer is subjected to a second annealing treatment in an atmosphere containing deuterium or an inert gas. The process parameters of the second annealing treatment include: an annealing temperature of 400 degrees Celsius to 700 degrees Celsius and an annealing time of 1 minute to 30 minutes.

[0021] Optionally, in the step of forming the channel protrusion structure, the thickness of the topmost channel layer is greater than the thickness of the channel layers in the remaining layers.

[0022] Optionally, in the step of removing the first sacrificial layer at the bottom of the pseudo-gate structure, the removal selectivity ratio between the first sacrificial layer and the channel protrusion is greater than 5:1.

[0023] Optionally, after forming the pseudo-gate structure, before sequentially removing the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure, the method further includes: forming a first sidewall on the sidewall of the pseudo-gate structure, the first sidewall covering part of the sidewall and part of the top of the first sacrificial layer; in the step of removing the first sacrificial layer at the bottom of the pseudo-gate structure, retaining the first sacrificial layer at the bottom of the first sidewall, the first sacrificial layer at the bottom of the first sidewall serving as a second sidewall, the dielectric constant of the second sidewall being less than the dielectric constant of the first sidewall.

[0024] Optionally, an anisotropic dry etching process can be used to remove the first sacrificial layer at the bottom of the pseudo-gate structure.

[0025] Optionally, the material of the first sacrificial layer includes one or both of low-k dielectric materials and ultra-low-k dielectric materials.

[0026] Optionally, the material of the first sacrificial layer includes one or more of silicon carbide, silicon carbonitride, and silicon carbonitride.

[0027] Optionally, the material of the first sacrificial layer includes a carbon-containing dielectric material, and the molar ratio of carbon element to the material corresponding to the first sacrificial layer is 0.01 to 0.15.

[0028] Accordingly, embodiments of the present invention also provide a semiconductor structure, including: a substrate; a channel bump structure located on the substrate, the channel bump structure including a channel bump portion; and a gate structure spanning the channel bump portion and covering the top and sidewalls of the channel bump portion.

[0029] Optionally, the channel protrusion includes a plurality of channel layers suspended on the substrate and spaced apart longitudinally, wherein the thickness of the topmost channel layer is greater than or equal to the thickness of the channel layers of the other layers.

[0030] Optionally, the semiconductor structure further includes: a second sidewall located on top of the channel protrusion structure and covering a portion of the height of the gate structure; and a first sidewall covering the sidewall of the gate structure exposed by the second sidewall and the top of the second sidewall, wherein the dielectric constant of the first sidewall is greater than that of the second sidewall.

[0031] Optionally, the material of the second sidewall includes one or both of low-k dielectric materials and ultra-low-k dielectric materials.

[0032] Optionally, the material of the second sidewall includes one or more of silicon carbide, silicon carbonitride, and silicon carbonitride.

[0033] Optionally, the material of the second sidewall includes a carbon-containing dielectric material, and the molar ratio of carbon to the material of the second sidewall is 0.01 to 0.15.

[0034] Optionally, the height of the second sidewall ranges from 15 nanometers to 35 nanometers along the normal direction of the top surface of the substrate.

[0035] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0036] In the semiconductor structure formation method provided by this embodiment of the invention, a channel bump structure is formed on the substrate. The channel bump structure includes a channel bump portion and a first sacrificial layer located on the channel bump portion. A dummy gate structure is formed across the channel bump structure. After forming the dummy gate structure, the dummy gate structure and the first sacrificial layer at the bottom of the dummy gate structure are removed sequentially. The removal selectivity ratio between the first sacrificial layer and the channel bump portion is greater than the removal selectivity ratio between the dummy gate structure and the channel bump portion. Since the first sacrificial layer covers the channel bump portion, during the removal of the dummy gate structure, the first sacrificial layer... A sacrificial layer can protect the top of the channel protrusion, thereby reducing the probability of damage to the top of the channel protrusion during the removal of the dummy gate structure. Moreover, during the removal of the first sacrificial layer, since the removal selectivity ratio between the first sacrificial layer and the channel protrusion is greater than the removal selectivity ratio between the dummy gate structure and the channel protrusion, it is beneficial to reduce the probability of damage to the top of the channel protrusion during the removal of the first sacrificial layer. Therefore, the semiconductor structure formation method provided by the embodiments of the present invention is beneficial to reducing weak points in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0037] In an optional embodiment, after forming the pseudo-gate structure and before sequentially removing the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure, the method further includes: forming a first sidewall on the sidewall of the pseudo-gate structure, the first sidewall covering part of the sidewall and part of the top of the first sacrificial layer; in the step of removing the first sacrificial layer at the bottom of the pseudo-gate structure, retaining the first sacrificial layer at the bottom of the first sidewall as a second sidewall; the dielectric constant of the second sidewall is smaller than that of the first sidewall, which is beneficial to reducing the leakage current and parasitic capacitance of the semiconductor structure and improving the AC performance of the semiconductor structure, thereby further improving the performance of the semiconductor structure. Attached Figure Description

[0038] Figures 1 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0039] Figure 14 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0040] In the manufacturing process of semiconductor devices, a dummy gate structure is typically formed first, which spans the channel protrusion and covers part of the top and sidewalls of the channel protrusion. Then, other films are formed (for example, source and drain doped layers are formed in the channel protrusion structures on both sides of the dummy gate structure, and an interlayer dielectric layer covering the source and drain doped layers is formed on the substrate on the side of the dummy gate structure). After the other films are formed, the dummy gate structure is removed, and a gate structure is formed at the location of the dummy gate structure.

[0041] Because the selectivity for removal between the material corresponding to the pseudo-gate structure and the material corresponding to the channel protrusion is relatively small, the top of the channel protrusion is easily damaged during the removal of the pseudo-gate structure, which in turn leads to the formation of weak points in the semiconductor structure and affects the performance of the semiconductor structure.

[0042] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel bump structure on the substrate, the channel bump structure including a channel bump portion and a first sacrificial layer located on the channel bump portion; forming a pseudo-gate structure spanning the channel bump structure, the pseudo-gate structure covering a portion of the top and a portion of the sidewalls of the channel bump structure; after forming the pseudo-gate structure, sequentially removing the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure, wherein the removal selectivity ratio between the first sacrificial layer and the channel bump portion is greater than the removal selectivity ratio between the pseudo-gate structure and the channel bump portion.

[0043] In the semiconductor structure formation method provided by this embodiment of the invention, a channel bump structure is formed on the substrate. The channel bump structure includes a channel bump portion and a first sacrificial layer located on the channel bump portion. A dummy gate structure is formed across the channel bump structure. After forming the dummy gate structure, the dummy gate structure and the first sacrificial layer at the bottom of the dummy gate structure are removed sequentially. The removal selectivity ratio between the first sacrificial layer and the channel bump portion is greater than the removal selectivity ratio between the dummy gate structure and the channel bump portion. Since the first sacrificial layer covers the channel bump portion, during the removal of the dummy gate structure, the first sacrificial layer... A sacrificial layer can protect the top of the channel protrusion, thereby reducing the probability of damage to the top of the channel protrusion during the removal of the dummy gate structure. Moreover, during the removal of the first sacrificial layer, since the removal selectivity ratio between the first sacrificial layer and the channel protrusion is greater than the removal selectivity ratio between the dummy gate structure and the channel protrusion, it is beneficial to reduce the probability of damage to the top of the channel protrusion during the removal of the first sacrificial layer. Therefore, the semiconductor structure formation method provided by the embodiments of the present invention is beneficial to reducing weak points in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0044] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0045] Figures 1 to 13 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0046] refer to Figure 1 Provides a base of 100.

[0047] Substrate 100 is used to provide a process platform for subsequent process manufacturing.

[0048] In this embodiment, substrate 100 is used to form a field-effect transistor. As an example, substrate 100 is used to form a fully enclosed gate transistor. In other embodiments, the substrate can also be used to form a fin field-effect transistor, a forksheet transistor, a complementary field-effect transistor (CFET), etc.

[0049] In this embodiment, the substrate 100 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0050] refer to Figures 2 to 4 and in conjunction with references Figure 1 A channel protrusion structure 110 is formed on the substrate 100 (e.g., Figure 4 As shown, the channel protrusion structure 110 includes a channel protrusion 111 and a first sacrificial layer 112 located on the channel protrusion 111.

[0051] The channel protrusion structure 110 provides a process basis for forming a pseudo-gate structure that covers part of the top and part of the sidewalls of the channel protrusion structure 110.

[0052] The channel protrusion 111 is used to provide a process basis for forming the first sacrificial layer 112.

[0053] The first sacrificial layer 112 is used to occupy a portion of the space for the subsequent formation of the gate structure.

[0054] refer to Figure 4 In this embodiment, in the step of forming the channel protrusion structure 110, the channel protrusion portion 111 includes a plurality of channel layers 113 suspended on the substrate 100 and spaced apart in the longitudinal direction, and the channel protrusion structure 110 also includes a second sacrificial layer 114 located between adjacent channel layers 113 and between the channel layers 113 and the substrate 100.

[0055] Longitudinal refers to the direction along the normal to the top surface of the base 100.

[0056] The channel layer 113 is used as a conductive channel for the fully enclosed gate field-effect transistor, and the second sacrificial layer 114 is used to support the channel layer 113, thereby providing a process basis for the subsequent implementation of the spaced floating arrangement of the channel layer 113. The second sacrificial layer 114 is also used to occupy space for the gate structure to be formed later.

[0057] It should be noted that the material of the channel layer 113 may include silicon, germanium, silicon germanide, etc.

[0058] As an example, the channel layer 113 is made of silicon, and the second sacrificial layer 114 is made of silicon germanide. During the subsequent removal of the second sacrificial layer 114, the etching selectivity of silicon germanide and silicon is relatively high. Therefore, by setting the material of the second sacrificial layer 114 to silicon germanide and the material of the channel layer 113 to silicon, the impact of the removal process of the second sacrificial layer 114 on the channel layer 113 can be effectively reduced, thereby improving the quality of the channel layer 113 and thus contributing to improved semiconductor device performance. In other embodiments, the channel layer material may also be silicon germanide, and the second sacrificial layer material may be silicon accordingly.

[0059] Specifically, in the step of forming the channel protrusion structure 110, the thickness of the topmost channel layer 113 is greater than the thickness of the channel layers 113 of the other layers.

[0060] In the step of forming the channel protrusion structure 110, the thickness of the top channel layer 113 is greater than that of the other channel layers 113. This makes it easier for the thickness of the top channel layer 113 to still meet the process requirements after the dummy gate structure and the first sacrificial layer 112 are removed. This also makes it easier to make the top channel layer 113 thicker, thereby making the top channel layer 113 have better resistance to deformation.

[0061] Since the first sacrificial layer 112 covers the channel protrusion 111, the first sacrificial layer 112 can protect the top of the channel protrusion 111 during the removal of the dummy gate structure, thereby reducing the probability of damage to the top of the channel protrusion 111 during the removal of the dummy gate structure.

[0062] The first sacrificial layer 112 is also used to provide a process basis for the subsequent formation of the second sidewall.

[0063] In this embodiment, the step of forming the channel protrusion structure 110 on the substrate 100 includes: as follows Figure 1 As shown, a channel protrusion material layer 111' is formed on the substrate 100; as Figures 2 to 3 As shown, a first sacrificial material layer 112' is formed on the material layer 111' of the channel protrusion; as Figure 4As shown, a patterned channel protrusion material layer 111′ and a first sacrificial material layer 112′ are used to form the channel protrusion 111 and the first sacrificial layer 112.

[0064] First, the channel protrusion material layer 111′ and the first sacrificial material layer 112′ are formed sequentially, and then the channel protrusion material layer 111′ and the first sacrificial material layer 112′ are patterned, which helps to reduce the difficulty of forming the channel protrusion 111 and the first sacrificial layer 112.

[0065] In this embodiment, the step of forming a first sacrificial material layer 112' on the channel protrusion material layer 111' includes: as follows Figure 2 As shown, an initial first sacrificial material layer 112″ is deposited on the material layer 111′ of the channel protrusion; as Figure 3 As shown, the initial first sacrificial material layer 112″ is modified to form the first sacrificial material layer 112′.

[0066] First, an initial first sacrificial material layer 112″ is deposited on the material layer 111′ of the channel protrusion, and then the initial first sacrificial material layer 112″ is modified, which helps to reduce the difficulty of forming the first sacrificial material layer 112′.

[0067] In one specific embodiment, a multilayer initial first sacrificial material layer 112″ is deposited and stacked on the channel protrusion material layer 111′ (e.g., Figure 2 (As shown); the multilayer initial first sacrificial material layer 112″ is modified to form a stacked multilayer first sacrificial material layer 112′ (as shown). Figure 3 (As shown).

[0068] The deposition and stacking of multiple initial first sacrificial material layers 112″ on the channel protrusion material layer 111′ facilitates the improvement of the quality of the initial first sacrificial material layer 112″ closest to the channel protrusion material layer 111′, thereby improving the interface performance between the initial first sacrificial material layer 112″ and the channel protrusion material layer 111′, and correspondingly also improving the interface performance between the first sacrificial material layer 112′ and the channel protrusion material layer 111′.

[0069] Furthermore, modifying the multi-layer initial first sacrificial material layer 112″ to form a stacked multi-layer first sacrificial material layer 112′ also helps to reduce the process cost of forming the first sacrificial material layer 112′.

[0070] In another specific embodiment, in the step of forming a first sacrificial material layer on the channel protrusion material layer, the steps of depositing an initial first sacrificial material layer and the modification treatment are performed alternately to form a stacked multilayer first sacrificial material layer.

[0071] Alternating between depositing the initial first sacrificial material layer and performing modification treatment to form stacked multi-layer first sacrificial material layers is beneficial to improving the uniformity of element distribution in the first sacrificial material layer, thereby improving the quality of the first sacrificial material layer and making it easier to reduce the difficulty of subsequent removal of the first sacrificial material layer.

[0072] It should be noted that in other embodiments, the first sacrificial material layer can also be formed directly on the channel protrusion material layer, for example, by epitaxial production.

[0073] In this embodiment, multiple layers of first sacrificial material 112' are stacked on the channel protrusion material layer 111', and the density of the first sacrificial material layer 112' closest to the channel protrusion material layer 111' is greater than the density of the other layers of first sacrificial material 112'.

[0074] The density of the first sacrificial material layer 112' closest to the channel protrusion material layer 111' is greater than that of the other layers, which is beneficial to improving the interface performance between the first sacrificial material layer 112' and the channel protrusion material layer 111'.

[0075] Specifically, the process of forming the first sacrificial material layer 112' on the channel protrusion material layer 111' includes a deposition process, and the deposition process used to form the first sacrificial material layer 112' closest to the channel protrusion material layer 111' includes plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0076] The deposition process used to form the first sacrificial material layer 112′ closest to the channel protrusion material layer 111′ includes plasma chemical deposition or atomic layer deposition, which makes the density of the first sacrificial material layer 112′ closest to the channel protrusion material layer 111′ greater than the density of the first sacrificial material layer 112′ of the other layers.

[0077] In this embodiment, the modification is performed through a doping process, and the doping ions include carbon ions.

[0078] Typically, the material of the pseudo-gate structure includes polycrystalline silicon, which is modified through a doping process. The doping ions include carbon ions, which helps to make the material properties of the first sacrificial material layer 112′ different from those of the pseudo-gate structure. This makes it easier for the removal selectivity ratio between the first sacrificial layer 112 and the channel protrusion 111 to be greater than that between the pseudo-gate structure and the channel protrusion 111.

[0079] Specifically, the doping process includes ion implantation, and the process parameters of the ion implantation process include: an implantation dose of 1E15 atoms per square centimeter to 1E16 atoms per square centimeter.

[0080] Modifying the initial first sacrificial material layer 112″ through ion implantation helps to reduce the impact on other film layers (e.g., the protrusion material layer 111′).

[0081] As an example, ion implantation processes can include plasma immersion ion implantation (PIII) or conventional ion implantation processes.

[0082] It should be noted that the implantation dose of the ion implantation process should not be too small. By appropriately increasing the implantation dose, the concentration of carbon ions in the first sacrificial material layer 112′ is not too low, thereby improving the removal selectivity between the first sacrificial layer 112 and the channel protrusion 111. Conversely, the implantation dose should not be too large, as this helps to prevent the concentration of carbon ions in the first sacrificial material layer 112′ from becoming too high, thereby reducing the lattice mismatch rate between the first sacrificial material layer 112′ and the channel protrusion material layer 111′, and also reducing the probability of other film layers being affected by the ion implantation process (e.g., reducing the probability of the channel protrusion 111 being contaminated by carbon ions). Therefore, in this embodiment, the implantation dose of the ion implantation process is between 1E15 atoms per square centimeter and 1E16 atoms per square centimeter.

[0083] In this embodiment, in the step of depositing an initial first sacrificial material layer 112″ on the channel protrusion material layer 111′, the material of the initial first sacrificial material layer 112″ includes one or more of silicon nitride, silicon, and silicon oxynitride.

[0084] Silicon nitride, silicon, and silicon oxynitride are commonly used materials in semiconductor processes and are relatively easy to obtain, which helps to reduce process costs.

[0085] As an example, the material of the initial first sacrificial material layer 112″ includes silicon nitride.

[0086] When the initial first sacrificial material layer 112″ is made of silicon nitride and is modified by ion implantation, it is beneficial to improve the uniformity of dopant ion distribution in the first sacrificial material layer 112′.

[0087] In this embodiment, multiple layers of first sacrificial material 112' are stacked on the channel protrusion material layer 111', and the density of the first sacrificial material layer 112' closest to the channel protrusion material layer 111' is greater than the density of the other layers of first sacrificial material 112'.

[0088] The density of the first sacrificial material layer 112' closest to the channel protrusion material layer 111' is greater than that of the other layers, which is beneficial to improving the interface performance between the first sacrificial material layer 112' and the channel protrusion material layer 111'.

[0089] It should be noted that the thickness of the first sacrificial layer 112 along the normal direction of the top surface of the substrate 100 should not be too small or too large. If the thickness of the first sacrificial layer 112 is too small, it may result in poor protection of the top of the channel protrusion 111 during the removal of the dummy gate structure; moreover, it may increase the difficulty of forming the first sacrificial layer 112. If the thickness of the first sacrificial layer 112 is too large, it may increase the difficulty of forming the channel protrusion structure 110. Therefore, in this embodiment, the thickness of the first sacrificial layer 112 is 15 nanometers to 35 nanometers.

[0090] In this embodiment, the material of the first sacrificial layer 112 includes one or both of low-k dielectric materials and ultra-low-k dielectric materials.

[0091] Low-k dielectric materials refer to dielectric materials with a relative permittivity of less than 3.9, while ultra-low-k dielectric materials refer to dielectric materials with a relative permittivity of less than 2.6.

[0092] Typically, the material of the channel protrusion 111 includes silicon, germanium, silicon germanide, etc., and the material of the first sacrificial layer 112 includes one or two of low-k dielectric materials and ultra-low-k dielectric materials. This is beneficial because the material characteristics of the first sacrificial layer 112 are different from those of the channel protrusion 111, thereby facilitating a larger removal selectivity between the first sacrificial layer 112 and the channel protrusion 111. Consequently, the removal selectivity between the first sacrificial layer 112 and the channel protrusion 111 is greater than that between the pseudo-gate structure and the channel protrusion 111.

[0093] As an example, the material of the first sacrificial layer 112 includes one or more of silicon carbide, silicon carbonitride, and silicon carbonitride.

[0094] Silicon carbide, silicon carbonitride, and silicon carbonitride are commonly used low-k dielectric materials in semiconductor processes. They are readily available, which helps reduce process costs.

[0095] It should be noted that the material of the first sacrificial layer 112 includes a carbon-containing dielectric material, and the molar ratio of carbon in the material corresponding to the first sacrificial layer 112 should not be too low or too high. If the molar ratio of carbon in the material corresponding to the first sacrificial layer 112 is too low, the removal selectivity between the first sacrificial layer 112 and the channel protrusion 111 is likely to be greater than the removal selectivity between the pseudo-gate structure and the channel protrusion 111, resulting in poor performance in reducing damage to the top of the channel protrusion 111 during the removal of the first sacrificial layer 112. If the molar ratio of carbon in the material corresponding to the first sacrificial layer 112 is too high, the lattice mismatch rate between the first sacrificial layer 112 and the channel protrusion 111 is likely to increase, and the probability of other film layers being affected by the ion implantation process is also likely to increase (e.g., increasing the probability of the channel protrusion 111 being contaminated by carbon ions). Therefore, in this embodiment, the material of the first sacrificial layer 112 includes a carbon-containing dielectric material, and the molar ratio of carbon element to the material corresponding to the first sacrificial layer 112 is 0.01 to 0.15.

[0096] In this embodiment, after the first sacrificial material layer 112' is formed on the channel protrusion material layer 111' and before the patterned channel protrusion material layer 111' and the first sacrificial material layer 112' are patterned, the first sacrificial material layer 112' is further subjected to a first annealing process.

[0097] After the first sacrificial material layer 112' is formed on the channel protrusion material layer 111', the initial first sacrificial material layer 112'' is modified. After the first sacrificial material layer 112'' is formed, before the patterned channel protrusion material layer 111' and the first sacrificial material layer 112'' are patterned, the first sacrificial material layer 112'' is subjected to a first annealing treatment. This is beneficial for activating doped ions (carbon ions) and repairing lattice defects caused by the doping process, thereby enabling the first sacrificial material layer 112'' to recrystallize and thus improving the quality of the first sacrificial material layer 112''.

[0098] In this embodiment, the process parameters for the first annealing treatment include: an annealing temperature of 900 degrees Celsius to 1000 degrees Celsius and an annealing time of 10 minutes to 30 minutes. As an example, the first annealing treatment includes a spike annealing process.

[0099] It should be noted that the annealing temperature of the first annealing treatment should not be too low or too high. If the annealing temperature of the first annealing treatment is too low, the effect of activating dopant ions and repairing lattice defects will be poor; if the annealing temperature of the first annealing treatment is too high, it will have an adverse effect on the device performance of the semiconductor device. Therefore, in this embodiment, the annealing temperature of the first annealing treatment is 900 degrees Celsius to 1000 degrees Celsius.

[0100] It should also be noted that the annealing time for the first annealing process should not be too short or too long. If the annealing time is too short, the effect of activating dopant ions and repairing lattice defects may be poor; if the annealing time is too long, the diffusion range of dopant ions may be too large, thereby affecting the performance of the semiconductor device. In this embodiment, the annealing time for the first annealing process is 10 to 30 minutes.

[0101] refer to Figure 5 and Figure 6 This forms a pseudo-gate structure 120 that spans the channel protrusion structure 110 (e.g., Figure 6 As shown, the pseudo-gate structure 120 covers part of the top and part of the sidewalls of the channel protrusion structure 110.

[0102] The pseudo-gate structure 120 is used to reserve space for the subsequent formation of the gate structure.

[0103] In this embodiment, the pseudo gate structure 120 includes: a pseudo gate layer 122, and a pseudo gate dielectric layer 121 located between the pseudo gate layer 122 and the channel protrusion structure 110.

[0104] As an example, the dummy gate layer 122 is made of polysilicon, and the dummy gate dielectric layer 121 comprises one or both of silicon oxide and silicon oxynitride. In other embodiments, the dummy gate layer may comprise other suitable materials, such as amorphous silicon. The dummy gate dielectric layer may comprise other suitable dielectric materials.

[0105] In this embodiment, the step of forming the pseudo-gate structure 120 includes: as follows Figure 5 As shown, a pseudo-gate material layer 120' is formed on the substrate 100, and the pseudo-gate material layer 120' covers the sidewalls and top of the channel protrusion structure 110; as Figure 6 As shown, a portion of the pseudo-gate material layer 120′ is removed so that the remaining pseudo-gate material layer 120′ spans the channel protrusion 111 and serves as the pseudo-gate structure 120.

[0106] As an example, since a first sacrificial layer 112 is formed on the channel protrusion 111, the first sacrificial layer 112 occupies a portion of the space for the subsequent formation of the gate structure. Accordingly, the height of the dummy gate structure 120 located on the channel protrusion structure 110 can be reduced to avoid the total height of the subsequently formed gate structure being too high.

[0107] In this embodiment, after forming the pseudo-gate structure 120, before sequentially removing the pseudo-gate structure 120 and the first sacrificial layer 112 at the bottom of the pseudo-gate structure 120, the method further includes: forming a first sidewall 131 on the sidewall of the pseudo-gate structure 120 (e.g., ...). Figure 6 As shown), the first sidewall 131 covers part of the sidewall and part of the top of the first sacrificial layer 112.

[0108] The first sidewall 131 serves as an etching mask for the subsequent formation of the second sidewall, and together with the dummy gate structure 120, serves as an etching mask for the subsequent formation of source and drain grooves. The first sidewall 131 also serves to protect the dummy gate structure 120 and the sidewalls of the subsequently formed gate structure.

[0109] The first sidewall 131 can be a single-layer structure or a multi-layer structure. The material of the first sidewall 131 is a dielectric material. As an example, the first sidewall 131 is a single-layer structure, and the material of the first sidewall 131 is silicon nitride.

[0110] refer to Figures 7 to 9 and in conjunction with references Figure 6 In this embodiment, after forming the first sidewall 131, before sequentially removing the dummy gate structure 120 and the first sacrificial layer 112 at the bottom of the dummy gate structure 120, the method further includes: removing the channel protrusions 110 on both sides of the dummy gate structure 120 to form source / drain grooves 140 (e.g., Figure 6 and Figure 7 (As shown); along the direction perpendicular to the sidewall of the pseudo-gate structure 120, a portion of the width of the second sacrificial layer 114 is removed laterally via the source / drain groove 140, forming inner trenches (not shown) between the channel layers 113 and between the channel layers 113 and the substrate 100; inner sidewalls 150 are formed in the inner trenches (as shown). Figure 8 (as shown); after forming the inner sidewall 150, a source / drain doped layer 141 is formed in the source / drain groove (as shown). Figure 9 (As shown).

[0111] The source / drain recess 140 provides spatial location for the formation of the source / drain doped layer 141. During device operation, the source / drain doped layer 141 serves as a source or drain, providing a source of charge carriers.

[0112] It is understood that the source / drain doped layer 141 contains doped ions. As an example, the doped ions in the source / drain doped layer 141 are N-type ions. In other embodiments, the doped ions in the source / drain doped layer are P-type ions.

[0113] The inner groove is used to provide space for the formation of the inner sidewall 150.

[0114] The inner wall 150 is used to isolate the source / drain doped layer 141 from the subsequently formed gate structure, and also to increase the distance between the source / drain doped layer 141 and the gate structure, thereby helping to reduce the parasitic capacitance between the source / drain doped layer 141 and the gate structure.

[0115] As an example, the material of the inner wall 150 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material.

[0116] refer to Figure 10 In this embodiment, after forming the source / drain doped layer 141, before sequentially removing the dummy gate structure 120 and the first sacrificial layer 112 at the bottom of the dummy gate structure 120, the method further includes: forming a contact etch stop layer (CESL) (not shown) covering the source / drain doped layer 141, the contact etch stop layer also covering the sidewalls and top of the dummy gate structure 120; after forming the contact etch stop layer, forming an interlayer dielectric layer 160 covering the source / drain doped layer 141 on the substrate 100 on the side of the dummy gate structure 120, the interlayer dielectric layer 160 also covering the contact etch stop layer, as well as the sidewalls and top of the dummy gate structure 120; and planarizing the interlayer dielectric layer 160 to remove the interlayer dielectric layer 160 above the top of the dummy gate structure 120.

[0117] The contact etch stop layer is used to increase the stress of the source / drain doped layer 141.

[0118] Interlayer dielectric layer 160 is used to achieve electrical isolation between adjacent semiconductor devices.

[0119] It should be noted that the material of the interlayer dielectric layer 160 is a dielectric material. As an example, the material of the interlayer dielectric layer 160 is silicon oxide.

[0120] Specifically, during the planarization process of the interlayer dielectric layer 160, the contact etch stop layer above the top of the pseudo gate structure 120 is also removed.

[0121] refer to Figure 11 After forming the pseudo gate structure 120, the pseudo gate structure 120 and the first sacrificial layer 112 at the bottom of the pseudo gate structure 120 are removed sequentially. The removal selection ratio between the first sacrificial layer 112 and the channel protrusion 111 is greater than the removal selection ratio between the pseudo gate structure 120 and the channel protrusion 111.

[0122] Since the first sacrificial layer 112 covers the channel protrusion 111, it can protect the top of the channel protrusion 111 during the removal of the dummy gate structure 120, thereby reducing the probability of damage to the top of the channel protrusion 111 during the removal of the dummy gate structure 120. Moreover, during the removal of the first sacrificial layer 112, since the removal selectivity ratio between the first sacrificial layer 112 and the channel protrusion 111 is greater than that between the dummy gate structure 120 and the channel protrusion 111, it is beneficial to reduce the probability of damage to the top of the channel protrusion 111 during the removal of the first sacrificial layer 112. Therefore, the semiconductor structure formation method provided by the embodiments of the present invention is beneficial to reducing weak points in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0123] It is understandable that the pseudo gate structure 120 and the first sacrificial layer 112 at the bottom of the pseudo gate structure 120 are removed in sequence, so that an opening 170 is formed at the position of the pseudo gate structure 120 and the first sacrificial layer 112 at the bottom of the pseudo gate structure 120, and the opening 170 exposes the channel protrusion 111.

[0124] In this embodiment, in the step of forming the channel protrusion structure 110, the channel protrusion 111 includes a plurality of channel layers 113 suspended on the substrate 100 and spaced apart longitudinally. Since the removal selectivity ratio between the first sacrificial layer 112 and the channel protrusion 111 is greater than the removal selectivity ratio between the pseudo gate structure 120 and the channel protrusion 111, it is beneficial to reduce the probability of damage to the top channel layer 113 during the removal of the first sacrificial layer 112. That is, the thickness of the top channel layer 113 is thicker, which makes it easier to meet the process requirements, thereby making the top channel layer 113 have better resistance to deformation. Therefore, it is also beneficial to reduce the degree of bending of the top channel layer 113 towards the substrate 100 when it is bent towards the substrate 100 by the stress of the source / drain doped layer 141.

[0125] It should be noted that the removal selectivity ratio between the first sacrificial layer 112 and the channel protrusion 111 should not be too small. If the removal selectivity ratio between the first sacrificial layer 112 and the channel protrusion 111 is too small, the effect of reducing damage to the top of the channel protrusion 111 during the removal of the first sacrificial layer 112 will be poor. Therefore, in this embodiment, in the step of removing the first sacrificial layer 112 at the bottom of the pseudo-gate structure 120, the removal selectivity ratio between the first sacrificial layer 112 and the channel protrusion 111 is greater than 5:1.

[0126] In this embodiment, in the step of forming the channel protrusion structure 110, the channel protrusion portion 111 includes a plurality of channel layers 113 suspended on the substrate 100 and spaced apart longitudinally, and the channel protrusion structure 110 further includes a second sacrificial layer 114 located between adjacent channel layers 113 and between the channel layers 113 and the substrate 100. Correspondingly, in the step of sequentially removing the dummy gate structure 120 and the first sacrificial layer 112 at the bottom of the dummy gate structure 120, the removal selectivity ratio between the first sacrificial layer 112 and the channel layer 113 is greater than the removal selectivity ratio between the dummy gate structure 120 and the channel layer 113.

[0127] In this embodiment, we continue to refer to Figure 11After forming the pseudo-gate structure 120, before sequentially removing the pseudo-gate structure 120 and the first sacrificial layer 112 at the bottom of the pseudo-gate structure 120, the method further includes: forming a first sidewall 131 on the sidewall of the pseudo-gate structure 120, the first sidewall 131 covering part of the sidewall and part of the top of the first sacrificial layer 112. Correspondingly, in the step of removing the first sacrificial layer 112 at the bottom of the pseudo-gate structure 120, the first sacrificial layer 112 at the bottom of the first sidewall 131 is retained, and the first sacrificial layer 112 at the bottom of the first sidewall 131 serves as a second sidewall 132, the dielectric constant of the second sidewall 132 being less than the dielectric constant of the first sidewall 131.

[0128] Before removing the first sacrificial layer 112 at the bottom of the dummy gate structure 120, a first sidewall 131 is formed on the sidewall of the dummy gate structure 120. The first sidewall 131 covers part of the sidewall and part of the top of the first sacrificial layer 112, so that when the first sacrificial layer 112 at the bottom of the dummy gate structure 120 is removed, the first sacrificial layer 112 at the bottom of the first sidewall 131 can be retained, and the retained first sacrificial layer 112 serves as the second sidewall 132. The dielectric constant of the second sidewall 132 is less than that of the first sidewall 131, which helps to reduce the leakage current and parasitic capacitance of the semiconductor structure and improve the AC performance of the semiconductor structure, thereby further improving the performance of the semiconductor structure.

[0129] In this embodiment, the material of the first sacrificial layer 112 includes one or both of low-k dielectric materials and ultra-low-k dielectric materials. Correspondingly, the material of the second sidewall 132 also includes one or both of low-k dielectric materials and ultra-low-k dielectric materials.

[0130] The material of the second sidewall 132 includes one or both of low-k dielectric materials and ultra-low-k dielectric materials, which is beneficial to further reduce the parasitic capacitance of the semiconductor structure and improve the AC performance of the semiconductor structure.

[0131] As an example, the material of the first sacrificial layer 112 includes one or more of silicon carbide, silicon carbonitride, and silicon carbonitride. Correspondingly, the material of the second sidewall 132 also includes one or more of silicon carbide, silicon carbonitride, and silicon carbonitride.

[0132] In one specific embodiment, when the material of the second sidewall 132 is silicon carbide or silicon carbonitride and the material of the channel layer 113 is silicon, the lattice mismatch between silicon carbide and silicon, and between silicon carbonitride and silicon, results in a higher potential barrier between silicon carbide and silicon, and between silicon carbonitride and silicon. This leads to a lower flow rate of charge carriers passing through the interfaces of silicon carbide and silicon carbonitride materials, which is beneficial for further reducing the leakage current of the semiconductor structure. Moreover, compared with the interface of silicon nitride material, the interface of silicon carbide or silicon carbonitride material has poorer smoothness, resulting in greater resistance to the thermal diffusion of doped ions in the source / drain doped layer 141, thereby reducing the diffusion rate of doped ions in the source / drain doped layer 141 into the conductive channel.

[0133] Moreover, compared with silicon nitride, silicon carbide and silicon carbonitride have better elasticity, so that when the top channel layer 113 is bent toward the substrate 100 under the stress of the source / drain doped layer 141, the second sidewall 132, which is made of silicon carbide or silicon carbonitride, can stretch the top channel layer 113 toward the side away from the substrate 100, thereby improving the degree of bending of the top channel layer 113 toward the substrate 100.

[0134] Specifically, an anisotropic dry etching process is used to remove the first sacrificial layer 112 at the bottom of the pseudo gate structure 120.

[0135] Anisotropic dry etching process has high etching precision and better control over the profile, which helps to reduce the probability of damage to the first sidewall 131 and the first sacrificial layer 112 at the bottom of the first sidewall 131 during the removal of the first sacrificial layer 112 at the bottom of the pseudo gate structure 120.

[0136] In this embodiment, the thickness of the first sacrificial layer 112 is 15 nanometers to 35 nanometers. Correspondingly, the height of the second sidewall 132 ranges from 15 nanometers to 35 nanometers along the normal direction of the top surface of the substrate 100.

[0137] refer to Figure 12 In this embodiment, after removing the pseudo gate structure 120 and the first sacrificial layer 112 at the bottom of the pseudo gate structure 120 in sequence, the method further includes: removing the second sacrificial layer 114; after removing the second sacrificial layer 114, the channel layer 113 is subjected to a second annealing process.

[0138] Understandably, removing the second sacrificial layer 114 forms a through-channel 171 located between the channel layers 113 and between the channel layers 113 and the substrate 110.

[0139] After removing the second sacrificial layer 114, the channel layer 113 is subjected to a second annealing process, which helps to reduce dangling bonds in the channel layer 113 and repair interface defects in the channel layer 113, thereby improving the carrier mobility and reliability of the semiconductor device.

[0140] In this embodiment, in the step of performing a second annealing treatment on the channel layer 113, the channel layer 113 is subjected to a second annealing treatment in an atmosphere containing deuterium or an inert gas. The process parameters of the second annealing treatment include: an annealing temperature of 400 degrees Celsius to 700 degrees Celsius and an annealing time of 1 minute to 30 minutes.

[0141] It should be noted that the annealing temperature of the second annealing process should not be too low or too high. If the annealing temperature of the second annealing process is too low, the effect of reducing dangling bonds in the channel layer 113 and repairing interface defects in the channel layer 113 will be poor. If the annealing temperature of the second annealing process is too high, the thermal budget will be too large, which will lead to excessively high process costs. Moreover, it will also increase the probability of damage to the interface of the channel layer 113, which will adversely affect the device performance of the semiconductor device. Therefore, in this embodiment, the annealing temperature of the second annealing process is 400 degrees Celsius to 700 degrees Celsius.

[0142] It should also be noted that the annealing time for the second annealing process should not be too short or too long. If the annealing time for the second annealing process is too short, the effect of reducing dangling bonds in the channel layer 113 and repairing interface defects in the channel layer 113 may be poor. If the annealing temperature for the second annealing process is too high, the thermal budget may be too large, which may lead to excessively high process costs. Moreover, it may also increase the probability of damage to the interface of the channel layer 113, which may adversely affect the device performance of the semiconductor device. Therefore, in this embodiment, the annealing time for the second annealing process is 1 minute to 30 minutes.

[0143] refer to Figure 13 In this embodiment, after removing the dummy gate structure 120 and the first sacrificial layer 112 at the bottom of the dummy gate structure 120 in sequence, the method further includes forming a gate structure 175 in the opening 170.

[0144] The gate structure 175 is the device gate structure. When the device is working, the gate structure 175 is used to control the opening and closing of the conductive channel.

[0145] The gate structure 175 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0146] The gate dielectric layer is used to isolate the gate electrode layer from the channel protrusion 111.

[0147] The gate dielectric layer is made of one or more of the following dielectric materials: hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicate oxide (HfSiO), hafnium nitride silicate (HfSiON), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2), and lanthanum oxide (La2O3).

[0148] In this embodiment, the gate structure 175 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or it may only include a work function layer.

[0149] Accordingly, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0150] Specifically, after the channel layer 113 undergoes a second annealing process, a gate structure 175 is formed in the opening 170. In the step of forming the gate structure 175, the gate structure 175 is also filled in the through-slot 171 so that the gate structure 175 surrounds the channel layer 113. The gate structure 175 located in the longitudinal direction between adjacent channel layers 113 and between adjacent channel layers 113 and the substrate 110 serves as an inner gate structure 176.

[0151] Accordingly, the present invention also provides a semiconductor structure. (See reference) Figure 14 The semiconductor structure includes: a substrate 500; a channel bump structure 510 located on the substrate 500, the channel bump structure 510 including a channel bump portion 511; and a gate structure 520 spanning the channel bump portion 511 and covering the top and sidewalls of the channel bump portion 511.

[0152] The substrate 500 is used to provide a process platform for the formation of semiconductor structures.

[0153] In this embodiment, the substrate 500 is used to form a field-effect transistor. As an example, the substrate 500 is used to form a fully enclosed gate transistor. In other embodiments, the substrate can also be used to form a fin field-effect transistor, a fork-gate transistor, a complementary field-effect transistor, etc.

[0154] In this embodiment, the substrate 500 includes a substrate (not shown), which is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0155] The channel bump structure 510 provides a process basis for forming a gate structure 520 that spans the channel bump 511 and covers the top and sidewalls of the channel bump 511.

[0156] In this embodiment, the channel protrusion 511 includes a plurality of channel layers 513 suspended on the substrate 500 and spaced apart along the longitudinal direction, and the thickness of the top channel layer 513 is greater than or equal to the thickness of the channel layers 513 of the other layers.

[0157] Longitudinal refers to the direction along the normal to the top surface of the base at 500.

[0158] Multiple channel layers 513, suspended on the substrate 500 and spaced longitudinally, serve as conductive channels for a fully enclosed gate field-effect transistor.

[0159] The thickness of the top channel layer 513 is greater than or equal to the thickness of the channel layers 513 in the other layers. That is, the thickness of the top channel layer 513 is relatively thick, which is beneficial to ensure that the thickness of the top channel layer 513 meets the process requirements, thereby making the top channel layer 513 more resistant to deformation. Therefore, it is also beneficial to reduce the degree of bending of the top channel layer 513 towards the substrate 500 when it is bent towards the substrate 500 under the stress of the source / drain doped layer 541.

[0160] As an example, the channel layer 513 is made of silicon. In other embodiments, the channel layer may also be made of silicon germanide.

[0161] In this embodiment, the semiconductor structure further includes: a source / drain doped layer 541 located on the substrate 500 on both sides of the gate structure 520 and connected to both ends of the channel layer 513; an inner sidewall 550 located between the gate structure 520 and the source / drain doped layer 541; a contact etch stop layer (not shown) covering the top of the source / drain doped layer 541 and the sidewall of the gate structure 520; and an interlayer dielectric layer 560 located on the substrate 100 on the side of the gate structure 520, the interlayer dielectric layer 560 also covering the source / drain doped layer 541 and the contact etch stop layer.

[0162] When the device is in operation, the source and drain doped layers 541 are used as the source or drain to provide a source of charge carriers.

[0163] It is understood that the source / drain doped layer 541 contains doped ions. As an example, the doped ions in the source / drain doped layer 541 are N-type ions. In other embodiments, the doped ions in the source / drain doped layer 541 are P-type ions.

[0164] The inner wall 550 is used to isolate the source / drain doped layer 541 from the back gate structure 520, and also to increase the distance between the source / drain doped layer 541 and the gate structure 520, thereby helping to reduce the parasitic capacitance between the source / drain doped layer 541 and the gate structure 520.

[0165] The contact etch stop layer is used to increase the stress of the source / drain doped layer 541.

[0166] The interlayer dielectric layer 560 is used to achieve electrical isolation between adjacent semiconductor devices.

[0167] It should be noted that the material of the interlayer dielectric layer 560 is a dielectric material. As an example, the material of the interlayer dielectric layer is silicon oxide.

[0168] As an example, the material of the inner wall 550 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material.

[0169] The gate structure 520 is the device gate structure. When the device is working, the gate structure 520 is used to control the opening and closing of the conductive channel.

[0170] The gate structure 520 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) covering the gate dielectric layer.

[0171] The gate dielectric layer is used to isolate the gate electrode layer from the channel protrusion 111.

[0172] The gate dielectric layer is made of one or more of the following dielectric materials: hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicate oxide (HfSiO), hafnium nitride silicate (HfSiON), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), aluminum oxide (Al2O3), silicon oxide (SiO2), and lanthanum oxide (La2O3).

[0173] In this embodiment, the gate structure 520 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or it may only include a work function layer.

[0174] Accordingly, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0175] In this embodiment, the semiconductor structure further includes: a second sidewall 532, located on top of the channel bump structure 510 and covering a portion of the height of the gate structure 520; and a first sidewall 531, covering the sidewall of the gate structure 520 exposed by the second sidewall 532 and the top of the second sidewall 532, wherein the dielectric constant of the first sidewall 531 is greater than the dielectric constant of the second sidewall 532.

[0176] The second sidewall 532 and the first sidewall 531 are used to jointly protect the sidewalls of the gate structure 520.

[0177] The second sidewall 532 is located on top of the channel protrusion structure 510 and covers a portion of the height of the sidewall of the gate structure 520. Moreover, the dielectric constant of the second sidewall 532 is smaller than that of the first sidewall 531, which helps to reduce the leakage current and parasitic capacitance of the semiconductor structure and improve the AC performance of the semiconductor structure, thereby further improving the performance of the semiconductor structure.

[0178] In this embodiment, the material of the second sidewall 532 includes one or both of low-k dielectric materials and ultra-low-k dielectric materials.

[0179] Low-k dielectric materials refer to dielectric materials with a relative permittivity of less than 3.9, while ultra-low-k dielectric materials refer to dielectric materials with a relative permittivity of less than 2.6.

[0180] The material of the second sidewall 532 includes one or both of low-k dielectric materials and ultra-low-k dielectric materials, which is beneficial to further reduce the parasitic capacitance of the semiconductor structure and improve the AC performance of the semiconductor structure.

[0181] As an example, the material of the second sidewall 532 includes one or more of silicon carbide, silicon carbonitride, and silicon carbonitride.

[0182] Silicon carbide, silicon carbonitride, and silicon carbonitride are commonly used low-k dielectric materials in semiconductor processes. They are readily available, which helps reduce process costs.

[0183] In one specific embodiment, when the material of the second sidewall 532 is silicon carbide or silicon carbonitride and the material of the channel layer 513 is silicon, the lattice mismatch between silicon carbide and silicon, and between silicon carbonitride and silicon, results in a higher potential barrier between silicon carbide and silicon, and between silicon carbonitride and silicon. This leads to a lower flow rate of charge carriers passing through the interfaces of silicon carbide and silicon carbonitride materials, thereby further reducing the leakage current of the semiconductor structure. Moreover, compared with the interface of silicon nitride material, the interface of silicon carbide or silicon carbonitride material has poorer smoothness, resulting in greater resistance to the thermal diffusion of doped ions in the source / drain doped layer 541, thereby reducing the diffusion rate of doped ions in the source / drain doped layer 541 into the conductive channel.

[0184] Moreover, compared with silicon nitride, silicon carbide and silicon carbonitride have better elasticity, so that when the top channel layer 513 is bent toward the substrate 500 under the stress of the source / drain doped layer 541, the second sidewall 532, which is made of silicon carbide or silicon carbonitride, can stretch the top channel layer 513 toward the side away from the substrate 500, thereby helping to improve the degree of bending of the top channel layer 513 toward the substrate 500.

[0185] It should be noted that the material of the second sidewall 532 includes a carbon-containing dielectric material, and the molar ratio of carbon in the material corresponding to the second sidewall 532 should not be too low or too high. If the molar ratio of carbon in the material corresponding to the second sidewall 532 is too low, the effect of reducing damage to the top of the channel protrusion 511 during the formation of the second sidewall 532 will be poor; if the molar ratio of carbon in the material corresponding to the second sidewall 532 is too high, the lattice mismatch rate between the second sidewall 532 and the channel protrusion 511 will be increased. Therefore, in this embodiment, the material of the second sidewall 532 includes a carbon-containing dielectric material, and the molar ratio of carbon in the material corresponding to the second sidewall 532 is 0.01 to 0.15.

[0186] It should be noted that the height of the second sidewall 532 along the normal direction of the top surface of the substrate 500 should not be too small or too large. If the height of the second sidewall 532 is too small, it will be more difficult to form the second sidewall 532. Since the second sidewall 532 is formed by retaining the first sacrificial layer (not shown) at the bottom of the first sidewall 531, and the channel protrusion structure 510 is formed by a patterned channel protrusion material layer (not shown) and a first sacrificial material layer (not shown), if the height of the second sidewall 532 is too large, it will be more difficult to form the channel protrusion structure 510. Therefore, in this embodiment, the height of the second sidewall 532 along the normal direction of the top surface of the substrate 500 ranges from 15 nanometers to 35 nanometers.

[0187] The first sidewall 531 is used as an etching mask for forming the second sidewall 532.

[0188] The first sidewall 531 can be a single-layer structure or a multi-layer structure. The material of the first sidewall 531 is a dielectric material. As an example, the first sidewall 531 is a single-layer structure, and the material of the first sidewall 531 is silicon nitride.

[0189] In this embodiment, the channel protrusion 511 includes a plurality of channel layers 513 suspended on the substrate 500 and spaced apart in the longitudinal direction; correspondingly, the gate structure 520 also surrounds the channel layers 513, and the gate structure 520 located in the longitudinal direction between adjacent channel layers 513 and between adjacent channel layers 513 and the substrate 510 serves as an inner gate structure 526.

[0190] It should be noted that the semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.

[0191] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A channel protrusion structure is formed on the substrate, the channel protrusion structure including a channel protrusion portion and a first sacrificial layer located on the channel protrusion portion; A pseudo-gate structure is formed that spans the channel protrusion structure, the pseudo-gate structure covering part of the top and part of the sidewall of the channel protrusion structure; After the pseudo-gate structure is formed, the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure are removed sequentially. The removal selectivity ratio between the first sacrificial layer and the channel protrusion is greater than the removal selectivity ratio between the pseudo-gate structure and the channel protrusion.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the channel protrusion structure on the substrate includes: A material layer with channel protrusions is formed on the substrate; A first sacrificial material layer is formed on the material layer of the protruding part of the channel; The channel protrusion material layer and the first sacrificial material layer are graphically represented to form the channel protrusion and the first sacrificial layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The step of forming a first sacrificial material layer on the channel protrusion material layer includes: An initial first sacrificial material layer is deposited on the material layer of the channel protrusion; The initial first sacrificial material layer is modified to form a first sacrificial material layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, A multilayer initial first sacrificial material layer is deposited and stacked on the material layer of the channel protrusion; The multilayer initial first sacrificial material layer is modified to form a stacked multilayer first sacrificial material layer.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of forming a first sacrificial material layer on the channel protrusion material layer, the steps of depositing an initial first sacrificial material layer and the modification treatment are performed alternately to form a stacked multilayer first sacrificial material layer.

6. The method for forming a semiconductor structure as described in claim 2, characterized in that, Multiple layers of first sacrificial material are stacked on the channel protrusion material layer, and the density of the first sacrificial material layer closest to the channel protrusion material layer is greater than the density of the first sacrificial material layers of the other layers.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process of forming a first sacrificial material layer on the channel protrusion material layer includes a deposition process, and the deposition process used to form the first sacrificial material layer closest to the channel protrusion material layer includes a plasma chemical deposition process or an atomic layer deposition process.

8. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of depositing an initial first sacrificial material layer on the channel protrusion material layer, the material of the initial first sacrificial material layer includes one or more of silicon nitride, silicon, and silicon oxynitride.

9. The method for forming a semiconductor structure as described in claim 3, characterized in that, The modification is performed by a doping process, and the doping ions include carbon ions.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The doping process includes an ion implantation process, and the process parameters of the ion implantation process include an implantation dose of 1E15 atoms per square centimeter to 1E16 atoms per square centimeter.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming the first sacrificial material layer on the channel protrusion material layer, and before patterning the channel protrusion material layer and the first sacrificial material layer, the method further includes: performing a first annealing treatment on the first sacrificial material layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The process parameters for the first annealing treatment include: an annealing temperature of 900 degrees Celsius to 1000 degrees Celsius and an annealing time of 10 minutes to 30 minutes.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the channel protrusion structure, the channel protrusion includes a plurality of channel layers suspended on the substrate and spaced apart in the longitudinal direction, and the channel protrusion structure also includes a second sacrificial layer located between adjacent channel layers and between the channel layers and the substrate; In the step of sequentially removing the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure, the removal selection ratio between the first sacrificial layer and the channel layer is greater than the removal selection ratio between the pseudo-gate structure and the channel layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, After sequentially removing the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure, the process further includes: removing the second sacrificial layer; and after removing the second sacrificial layer, performing a second annealing process on the channel layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of performing a second annealing treatment on the channel layer, the channel layer is subjected to a second annealing treatment in an atmosphere containing deuterium or an inert gas. The process parameters of the second annealing treatment include: an annealing temperature of 400 degrees Celsius to 700 degrees Celsius and an annealing time of 1 minute to 30 minutes.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the channel protrusion structure, the thickness of the topmost channel layer is greater than the thickness of the channel layers in the remaining layers.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of removing the first sacrificial layer at the bottom of the pseudo-gate structure, the removal selectivity ratio between the first sacrificial layer and the channel protrusion is greater than 5:

1.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the pseudo-gate structure is formed, before the pseudo-gate structure and the first sacrificial layer at the bottom of the pseudo-gate structure are removed in sequence, the method further includes: forming a first sidewall on the sidewall of the pseudo-gate structure, wherein the first sidewall covers part of the sidewall and part of the top of the first sacrificial layer; In the step of removing the first sacrificial layer at the bottom of the pseudo-gate structure, the first sacrificial layer at the bottom of the first sidewall is retained, and the first sacrificial layer at the bottom of the first sidewall serves as the second sidewall, wherein the dielectric constant of the second sidewall is less than that of the first sidewall.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, An anisotropic dry etching process is used to remove the first sacrificial layer at the bottom of the pseudo-gate structure.

20. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first sacrificial layer includes one or both of low-k dielectric materials and ultra-low-k dielectric materials.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The material of the first sacrificial layer includes one or more of silicon carbide, silicon carbonitride, and silicon carbonitride.

22. The method for forming a semiconductor structure as described in claim 20, characterized in that, The material of the first sacrificial layer includes a carbon-containing dielectric material, and the molar ratio of carbon element to the material corresponding to the first sacrificial layer is 0.01 to 0.

15.

23. A semiconductor structure, characterized in that, include: Base; A channel protrusion structure is located on the substrate, and the channel protrusion structure includes a channel protrusion portion; A gate structure that spans the channel protrusion and covers the top and sidewalls of the channel protrusion.

24. The semiconductor structure as claimed in claim 23, characterized in that, The channel protrusion includes multiple channel layers suspended on the substrate and spaced apart longitudinally, with the thickness of the top channel layer being greater than or equal to the thickness of the channel layers in the other layers.

25. The semiconductor structure as described in claim 23 or 24, characterized in that, The semiconductor structure also includes: The second sidewall is located at the top of the channel protrusion structure and covers a portion of the height of the gate structure. A first sidewall covers the sidewall of the gate structure exposed by the second sidewall and the top of the second sidewall, wherein the dielectric constant of the first sidewall is greater than that of the second sidewall.

26. The semiconductor structure as described in claim 25, characterized in that, The material of the second sidewall includes one or both of low-k dielectric materials and ultra-low-k dielectric materials.

27. The semiconductor structure as claimed in claim 26, characterized in that, The material of the second sidewall includes one or more of silicon carbide, silicon carbonitride, and silicon carbonitride.

28. The semiconductor structure as claimed in claim 26, characterized in that, The material of the second sidewall includes a carbon-containing dielectric material, and the molar ratio of carbon to the corresponding material of the second sidewall is 0.01 to 0.

15.

29. The semiconductor structure as claimed in claim 25, characterized in that, Along the normal direction of the top surface of the substrate, the height of the second sidewall ranges from 15 nanometers to 35 nanometers.

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