Display panel and display device
By setting the voltage of the common electrode to the pulse valley value, the parasitic capacitive coupling effect between the vertical scan line and the common electrode is solved, thus improving the display quality of the display panel.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU CHINA STAR OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2023-09-15
- Publication Date
- 2026-06-26
AI Technical Summary
In the design of gate drivers using thin-film flip-chip packaging, the parasitic capacitance between the vertical traces of the scan lines and the common electrode causes a coupling effect, affecting the product quality of the display panel.
By setting the voltage of the common electrode to the pulse valley value that turns off the switching transistor, the parasitic capacitance between the common electrode and the second scan line is reduced, thereby reducing the coupling effect between the scan line and the common electrode.
The coupling effect of parasitic capacitance between the vertical scan line traces and the common electrode on the pixels has been improved, thus enhancing the display effect of the display panel.
Smart Images
Figure CN117518657B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology
[0002] As panel products gradually move towards narrower bezels and higher resolutions, the application of ultra-narrow bezels (less than 5.5mm and less than 1mm) and other ultra-high-definition LCD displays is injecting new vitality into the panel industry.
[0003] In related technologies, a design using a thin-film flip-chip package for the gate driver is employed, placing the drive signals for the scan lines and data lines on the same side. This reduces the width of the left and right sides of the LCD, achieving an ultra-narrow bezel effect. However, in this thin-film flip-chip design, because there are traces perpendicular to the scan lines within the pixel, and parasitic capacitance exists between these traces and the common electrode, the coupling effect of this parasitic capacitance on the pixel causes crosstalk in the display panel, affecting the product quality of the display panel.
[0004] Therefore, how to reduce the parasitic capacitance between the vertical traces of the scan line and the common electrode is a problem that urgently needs to be solved in this field. Summary of the Invention
[0005] Embodiments of the present invention provide an array substrate and a display panel to solve the technical problem of the coupling effect of parasitic capacitance between the vertical traces of the scan lines and the common electrode on the pixels.
[0006] To solve the above problems, the technical solution provided by the present invention is as follows:
[0007] In a first aspect, embodiments of this application provide an array substrate, comprising: a substrate; a common electrode layer disposed on the substrate, including a common electrode and a plurality of first scan lines extending along a first direction; and a wiring layer disposed on the common electrode layer, including a plurality of second scan lines extending along a second direction, the second direction intersecting the first direction, each second scan line being electrically connected to a corresponding first scan line, the second scan lines being used to transmit scan signals, the potential of the scan signals including pulse peak values and pulse valley values; wherein, the common electrode has the pulse valley value.
[0008] In one embodiment, a plurality of first scan lines are arranged sequentially along the second direction, and a plurality of second scan lines are arranged along the first direction. Each second scan line includes a first segment and a second segment that are electrically connected. The width of the second segment is smaller than the width of the first segment. The second segment of each second scan line is electrically connected to the corresponding first scan line.
[0009] In one embodiment, the common electrode layer further includes multiple connecting lines, each of which is connected in parallel with the first segment of the corresponding second scan line, and each of the connecting lines is spaced apart from the common electrode and the first scan line.
[0010] In one embodiment, the common electrode includes a plurality of first sub-electrodes and second sub-electrodes, wherein the orthographic projection of each second sub-electrode on the substrate at least partially overlaps with the orthographic projection of the second segment of the corresponding second scan line on the substrate.
[0011] In one embodiment, each second scan line further includes a third segment electrically connected to the first segment and the second segment, the third segment being located between the first segment and the second segment, the width of the third segment being less than the width of the first segment and greater than the width of the second segment.
[0012] In one embodiment, the wiring layer further includes multiple data lines for transmitting the data signal, and the data lines are spaced apart from the second scan line.
[0013] In one embodiment, the array substrate is further provided with a plurality of sub-pixels, the plurality of sub-pixels are arranged in rows and columns, each data line is electrically connected to a sub-pixel in a corresponding sub-pixel column, and the plurality of sub-pixels located in the same column are alternately electrically connected to two adjacent data signal lines in units of every two sub-pixels.
[0014] In one embodiment, each first scan line is electrically connected to a corresponding second scan line, and each second scan line is electrically connected to two adjacent first scan lines.
[0015] In one embodiment, the array substrate further includes a pixel electrode layer, the pixel electrode layer including pixel electrodes, the orthographic projection of the pixel electrodes on the substrate covering the orthographic projection of the data line on the substrate, and the orthographic projection of the pixel electrodes on the substrate at least partially covering the orthographic projection of the common electrode on the substrate.
[0016] Secondly, embodiments of this application also provide a display panel, including an array substrate as described in any of the preceding embodiments.
[0017] The beneficial effects of this invention are as follows: by setting the voltage on the common electrode to the pulse valley value that turns off the switching transistor, the parasitic capacitance between the common electrode and the second scan line is reduced during most of the pixel's operation, thereby reducing the coupling effect of the parasitic capacitance between the second scan line and the common electrode on the pixel, and improving the technical problem in related technologies where the coupling effect of the parasitic capacitance between the vertical trace of the scan line and the common electrode on the pixel affects the display panel display. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0019] Appendix Figure 1 This is a schematic diagram of the array substrate in one embodiment of the present invention;
[0020] Appendix Figure 2 This is a schematic diagram illustrating an abnormal display of a display panel in the related technology of the present invention;
[0021] Appendix Figure 3 This is a circuit diagram of a pixel in the related technology of the present invention;
[0022] Appendix Figure 4 This is a schematic diagram of the structure of the common electrode layer of the array substrate in one embodiment of the present invention;
[0023] Appendix Figure 5 for Figure 1 A cross-sectional view along the AA' direction;
[0024] Appendix Figure 6 This is a schematic diagram of the structure of the second scan line in one embodiment of the present invention. Detailed Implementation
[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0026] In related technologies, a design using a thin-film flip-chip package for the gate driver is employed, placing the drive signals for the scan lines and data lines on the same side. This reduces the width of the left and right sides of the LCD, achieving an ultra-narrow bezel effect. However, in this thin-film flip-chip design, traces perpendicular to the scan lines exist within the pixel. These vertical traces and the common electrode have parasitic capacitance. This parasitic capacitance between the vertical traces and the common electrode causes coupling effects on the pixels, resulting in crosstalk in the display panel and affecting its product quality.
[0027] Embodiments of the present invention provide an array substrate and a display panel to solve the technical problem that the coupling effect of parasitic capacitance between the vertical traces of the scan lines and the common electrode on the pixels affects the display of the display panel.
[0028] In a first aspect, embodiments of this application provide an array substrate, such as Figure 1 As shown, the array substrate includes a substrate 10, a common electrode layer, and a wiring layer.
[0029] The common electrode layer is disposed on the substrate 10. The common electrode layer includes a common electrode 31 and a plurality of first scan lines 32 extending along a first direction X. The common electrode 31 and the first scan lines 32 are spaced apart and insulated. The wiring layer is disposed on the common electrode layer. The wiring layer includes a plurality of second scan lines 42 extending along a second direction Y, which intersects with the first direction X. Each second scan line 42 is electrically connected to a corresponding first scan line 32. The first scan lines 32 and the second scan lines 42 are used to transmit scan signals. The potential of the scan signal includes a pulse peak value and a pulse valley value. The common electrode 31 has the pulse valley value.
[0030] Understandably, in the above embodiments, the scanning signal is used to control the conduction of the switching transistor T in the corresponding pixel to determine the writing of the data signal. For example, when the scanning signal is a peak pulse, the switching transistor T is turned on, and the data signal is written to the pixel electrode 51 of the liquid crystal capacitor. When the scanning signal is a valley pulse, the writing of the data signal stops. During the entire operation of the pixel, data signal writing only occurs for a small portion of the time, such as during the data writing phase. In other phases, such as the light emission phase, the switching transistor T is turned off, i.e., the scanning signal is a valley pulse. Therefore, setting the voltage of the common electrode 31 to the valley pulse value reduces the parasitic capacitance between the common electrode 31 and the second scan line 42 (vertical scan line), thereby reducing the coupling effect of the parasitic capacitance between the second scan line 42 and the common electrode 31 on the pixel and improving the technical problem.
[0031] In this embodiment, by making the voltage on the common electrode 31 the pulse valley value that turns off the switching transistor T, the parasitic capacitance between the common electrode 31 and the second scan line 42 is reduced during most of the pixel's operation. This reduces the coupling effect of the parasitic capacitance between the second scan line 42 and the common electrode 31 on the pixel, and improves the technical problem in related technologies where the coupling effect of the vertical trace of the scan line and the parasitic capacitance between the common electrode 31 on the pixel affects the display panel display.
[0032] like Figure 1 , Figure 3 As shown, the array substrate includes a plurality of pixel units arranged in an array, a second scan line 42, a first scan line 32, and a data line 41. Each pixel unit includes a pixel electrode 51 and a switching transistor T. Specifically, the second scan line 42 is located between adjacent columns of pixel units arranged along the width direction (first direction X) of the array substrate and extends along the length direction (second direction Y) of the array substrate. The first scan line 32 is located between adjacent rows of pixel units arranged along the length direction (second direction Y) of the array substrate and extends along the width direction (first direction X) of the array substrate. The data line 41 is located on a column of pixel units arranged along the width direction (first direction X) of the array substrate and extends along the length direction (second direction Y) of the array substrate. The second scan line 42 is electrically connected to at least one first scan line 32. Specifically, the second scan line 42 can be electrically connected to 1, 2, 3, ... n first scan lines 32. Those skilled in the art can adjust this as needed, and this application does not impose specific limitations here. The source s of the switching transistor T is electrically connected to the data line 41, the gate g of the switching transistor T is electrically connected to the first scan line 32, and the drain d of the switching transistor T is electrically connected to the pixel electrode 51.
[0033] During the driving process of the array substrate, the scan signal is transmitted to the corresponding first scan line 32 through the second scan line 42, and then loaded onto the gate g of the switching transistor T, causing the switching transistor T to conduct. The data signal is loaded onto the source s of the switching transistor T through the data line 41. The liquid crystal capacitor Clc is composed of the pixel electrode 51 disposed on the array substrate and the common electrode 31 disposed on the color filter substrate 10 (not shown in the figure), the common electrode 31 being A-COM; the storage capacitor Cst is composed of the pixel electrode 51 and the common electrode 31 disposed on the array substrate; the parasitic capacitance Cvgp is composed of the second scan line 42 and the common electrode 31; and the parasitic capacitance Chgp is composed of the first scan line 32 and the pixel electrode 51. When the scan signal causes the switching transistor T to be in the conducting state, the data signal is loaded onto the pixel electrode 51 of the liquid crystal capacitor Clc through the drain d of the switching transistor T. When the voltage applied between the liquid crystal capacitors Clc changes, the deflection direction of the liquid crystal molecules in the liquid crystal layer (not shown in the figure) also changes, thereby controlling the light transmittance through the pixel unit and thus controlling the display brightness of each pixel unit. When the parasitic capacitance between the common electrode 31 and the second scan line 42 is large, the coupling effect of the parasitic capacitance between the vertical trace of the scan line and the common electrode 31 on the pixel causes crosstalk in the display panel, affecting the product quality of the display panel. This application reduces the parasitic capacitance between the common electrode 31 and the second scan line 42 during most of the pixel's operation by setting the voltage on the common electrode 31 to the valley value of the pulse that turns off the switching transistor T. This reduces the coupling effect of the parasitic capacitance between the second scan line 42 and the common electrode 31 on the pixel, thereby improving the technical problem in related technologies where the coupling effect of the parasitic capacitance between the vertical trace of the scan line and the common electrode 31 on the pixel affects the display panel.
[0034] like Figure 1 , Figure 6 As shown, in one embodiment, a plurality of first scan lines 32 are arranged sequentially along the second direction Y, and a plurality of second scan lines 42 are arranged along the first direction X. To reduce the coupling between the second scan lines 42 and the common electrode 31, each second scan line 42 includes an electrically connected first segment 421 and a second segment 422. The width of the second segment 422 is smaller than the width of the first segment 421. The second segment 422 of each second scan line 42 is electrically connected to the corresponding first scan line 32. It is understood that, due to the reduced width of the second segment 422, the coupling capacitance between it and the common electrode 31 will decrease.
[0035] Understandably, the first segment 421 can be directly electrically connected to the second segment 422, that is, the width of the second scan line 42 can be directly reduced from the width of the first segment 421 to the width of the second segment 422. Alternatively, multiple buffer structures can be set between the first segment 421 and the second segment 422 to gradually reduce the width of the second scan line 42 from the width of the first segment 421 to the width of the second segment 422, thereby ensuring the strength and stability of the second scan line 42.
[0036] In some embodiments, each of the second scan lines 42 further includes a third segment 423 electrically connected to the first segment 421 and the second segment 422. The third segment 423 is located between the first segment 421 and the second segment 422, and the width of the third segment 423 is smaller than the width of the first segment 421 and larger than the width of the second segment 422. It is understood that by setting the third segment 423, a sudden drop in the width of the second scan line 42 can be avoided, ensuring the strength and stability of the second scan line 42. In some other embodiments, the second scan line 42 may also include a fourth segment, a fifth segment, a sixth segment, etc., with progressively decreasing widths, to gradually reduce the width of the second scan line 42. Those skilled in the art can set these as needed, and this application does not impose any limitations on this.
[0037] In some embodiments, the width of the first segment 421 gradually decreases at the end near the third segment 423. This is understood to make the transition between the first segment 421 and the third segment 423 smoother, further preventing a sudden drop in the width of the second scan line 42. For the same reason, the width of the third segment 423 also gradually decreases at the end near the second segment 422, to make the transition between the third segment 423 and the second segment 422 smoother, further preventing a sudden drop in the width of the second scan line 42.
[0038] like Figure 1 , Figure 4 , Figure 5As shown, in one embodiment, the common electrode layer further includes multiple connecting lines 33, each of which is spaced apart from the common electrode 31 and the first scan line 32. The orthographic projection of each connecting line 33 onto the array substrate is located within the orthographic projection range of the first segment 421 of the corresponding second scan line 42 onto the array substrate. Furthermore, each connecting line 33 is connected in parallel with the first segment 421 of the corresponding second scan line 42, and each connecting line 33 is spaced apart from the common electrode 31 and the first scan line 32. It is understood that the connecting line 33 and the second scan line 42 are not on the same film layer, and their electrical connection requires vias. Therefore, vias are provided between the connecting line 33 and the first segment 421 of the corresponding second scan line 42 to achieve their electrical connection. To achieve the parallel connection of the first segment 421 and the connecting line 33, both ends of the first segment 421 need to be electrically connected to the connecting line 33 respectively; therefore, corresponding vias are provided at both ends of the first segment 421. Understandably, the above settings can reduce the resistance of the first segment 421. By setting the corresponding connecting line 33 at the beginning of the first segment 421 of the second scan line 42, the resistance of the second scan line 42 can be significantly reduced, preventing the voltage drop of the scan signal on the second scan line 42 from being too large.
[0039] In one embodiment, the second scan line 42 is located between two adjacent pixel units to avoid affecting the aperture ratio of the pixels. The common electrode 31 includes a plurality of first sub-electrodes 311 and second sub-electrodes 312. The second sub-electrodes 312 are located between two adjacent pixel units, and the orthographic projection of each second sub-electrode 312 on the substrate 10 at least partially overlaps with the orthographic projection of the second segment 422 of the corresponding second scan line 42 on the substrate 10. When the voltage on the second scan line 42 changes, the second scan line 42 and the second sub-electrodes 312 are coupled, generating parasitic capacitance, which affects the deflection of the liquid crystal, thereby causing the display panel to display abnormalities, such as light leakage. Figure 2 (and other situations.)
[0040] In this application, by making the voltage on the common electrode 31 the valley value of the pulse that turns off the switching transistor T, specifically, by making the voltage on the second sub-electrode 312 the pulse value, the parasitic capacitance between the second sub-electrode 312 and the second scan line is reduced during most of the pixel's operation. This reduces the coupling effect of the parasitic capacitance between the second scan line 42 and the second sub-electrode 312 on the pixel, and improves the technical problem in related technologies where the coupling effect of the vertical trace of the scan line and the parasitic capacitance between the second sub-electrode 312 on the pixel affects the display panel display.
[0041] In one embodiment, the wiring layer further includes multiple data lines 41 for transmitting the data signal, and the data lines 41 are spaced apart from the second scan line 42. It is understood that the wiring layer may also include the source and drain of a switching transistor T, with the source of the transistor electrically connected to the data lines 41.
[0042] In one embodiment, the array substrate is further provided with a plurality of sub-pixels arranged in rows and columns. Each data line 41 is electrically connected to a sub-pixel in a corresponding sub-pixel column, and the plurality of sub-pixels in the same column are alternately electrically connected to two adjacent data lines 41 in units of every two sub-pixels. Each first scan line 32 is electrically connected to a corresponding second scan line 42, and each second scan line 42 is electrically connected to two adjacent first scan lines 32.
[0043] Understandably, in this embodiment, the number of data lines 41 is twice the number of columns of the sub-pixel, and the number of second scan lines 42 is half the number of rows of the sub-pixel. Therefore, the charging time of the sub-pixel can be doubled, and the sub-pixel has sufficient charging time, thereby enabling the display panel of this embodiment to achieve a higher resolution.
[0044] In one embodiment, the array substrate further includes a pixel electrode layer, the pixel electrode layer including a pixel electrode 51, the orthographic projection of the pixel electrode 51 on the substrate 10 covering the orthographic projection of the data line 41 on the substrate 10, and the orthographic projection of the pixel electrode 51 on the substrate 10 at least partially covering the orthographic projection of the common electrode 31 on the substrate 10.
[0045] In this embodiment of the application, the array substrate further includes a first insulating layer 21 and a second insulating layer 22. The first insulating layer 21 is disposed between the wiring layer and the common electrode layer, and the second insulating layer 22 is disposed between the pixel electrode layer and the data wiring layer. Specifically, the materials of the first insulating layer 21 and the second insulating layer 22 can be organic resin materials or inorganic insulating materials, such as at least one of silicon oxide, silicon nitride, and combinations thereof, or other materials with low dielectric constants. Using materials with low dielectric constants and relatively increasing the thickness of the first insulating layer 21 and the second insulating layer 22 helps to increase the distance between the first scan line 32 and the pixel electrode 51, the distance between the data line 41 and the pixel electrode 51, and the distance between the second scan line 42 and the common electrode 31. Therefore, the parasitic capacitance Chgp between the first scan line 32 and the pixel electrode 51, the parasitic capacitance between the data line 41 and the pixel electrode 51, and the parasitic capacitance Cvgp between the second scan line 42 and the common electrode 31 are all greatly reduced. At the same time, since organic resin materials and the like have low dielectric constants, the parasitic capacitances mentioned above can be further reduced, which helps to improve the display effect.
[0046] Secondly, embodiments of this application also provide a display panel, including an array substrate as described in any of the preceding embodiments. The array substrate includes a substrate 10, a common electrode layer, and a wiring layer.
[0047] The common electrode layer is disposed on the substrate 10. The common electrode layer includes a common electrode 31 and a plurality of first scan lines 32 extending along a first direction X. The common electrode 31 and the first scan lines 32 are spaced apart and insulated. The wiring layer is disposed on the common electrode layer. The wiring layer includes a plurality of second scan lines 42 extending along a second direction Y, which intersects with the first direction X. Each second scan line 42 is electrically connected to a corresponding first scan line 32. The first scan lines 32 and the second scan lines 42 are used to transmit scan signals. The potential of the scan signal includes a pulse peak value and a pulse valley value. The common electrode 31 has the pulse valley value.
[0048] Understandably, in the above embodiments, the scanning signal is used to control the conduction of the switching transistor T in the corresponding pixel to determine the writing of the data signal. For example, when the scanning signal is a peak pulse, the switching transistor T is turned on, and the data signal is written to the pixel electrode 51 of the liquid crystal capacitor. When the scanning signal is a valley pulse, the writing of the data signal stops. During the entire operation of the pixel, data signal writing only occurs for a small portion of the time, such as during the data writing phase. In other phases, such as the light emission phase, the switching transistor T is turned off, i.e., the scanning signal is a valley pulse. Therefore, setting the voltage of the common electrode 31 to the valley pulse value reduces the parasitic capacitance between the common electrode 31 and the second scan line 42 (vertical scan line), thereby reducing the coupling effect of the parasitic capacitance between the second scan line 42 and the common electrode 31 on the pixel and improving the technical problem.
[0049] In this embodiment, by making the voltage on the common electrode 31 the pulse valley value that turns off the switching transistor T, the parasitic capacitance between the common electrode 31 and the second scan line 42 is reduced during most of the pixel's operation. This reduces the coupling effect of the parasitic capacitance between the second scan line 42 and the common electrode 31 on the pixel, and improves the technical problem in related technologies where the coupling effect of the vertical trace of the scan line and the parasitic capacitance between the common electrode 31 on the pixel affects the display panel display.
[0050] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.
Claims
1. An array substrate, characterized in that, include: substrate; A common electrode layer is disposed on the substrate and includes a common electrode and a plurality of first scan lines extending along a first direction; A trace layer, disposed on the common electrode layer, includes multiple second scan lines extending along a second direction, the second direction intersecting the first direction, each second scan line being electrically connected to a corresponding first scan line, the second scan line being used to transmit scan signals, the potential of the scan signal including pulse peak value and pulse valley value; The common electrode has the pulse valley value; Multiple first scan lines are arranged sequentially along the second direction, and multiple second scan lines are arranged along the first direction. Each second scan line includes a first segment and a second segment that are electrically connected. The width of the second segment is smaller than the width of the first segment. The second segment of each second scan line is electrically connected to the corresponding first scan line.
2. The array substrate according to claim 1, characterized in that, The common electrode layer also includes multiple connecting lines, each of which is connected in parallel with the first segment of the corresponding second scan line, and each of which is spaced apart from the common electrode and the first scan line.
3. The array substrate according to claim 1, characterized in that, The common electrode includes a plurality of first sub-electrodes and second sub-electrodes, wherein the orthographic projection of each second sub-electrode on the substrate at least partially overlaps with the orthographic projection of the second segment of the corresponding second scan line on the substrate.
4. The array substrate according to claim 1, characterized in that, Each second scan line further includes a third segment electrically connected to the first segment and the second segment, the third segment being located between the first segment and the second segment, the width of the third segment being less than the width of the first segment and greater than the width of the second segment.
5. The array substrate according to claim 1, characterized in that, The wiring layer also includes multiple data lines used to transmit data signals, and the data lines are spaced apart from the second scan lines.
6. The array substrate according to claim 5, characterized in that, The array substrate is further provided with a plurality of sub-pixels, and the plurality of sub-pixels are arranged in rows and columns. Each data line is electrically connected to a sub-pixel in a corresponding sub-pixel column, and the plurality of sub-pixels located in the same column are alternately electrically connected to two adjacent data lines in units of every two sub-pixels.
7. The array substrate according to claim 6, characterized in that, Each of the first scan lines is electrically connected to a corresponding second scan line, and each of the second scan lines is electrically connected to two adjacent first scan lines.
8. The array substrate according to claim 5, characterized in that, The array substrate further includes a pixel electrode layer, which includes pixel electrodes. The orthographic projection of the pixel electrodes on the substrate covers the orthographic projection of the data line on the substrate, and the orthographic projection of the pixel electrodes on the substrate at least partially covers the orthographic projection of the common electrode on the substrate.
9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-8.