A semiconductor device, a manufacturing method thereof, and an electronic device

Abstract

The application provides a semiconductor device and a preparation method thereof and an electronic device, the device comprising: a substrate, the substrate comprising a test area and a device area, wherein the substrate comprises a semiconductor substrate, an ohmic contact layer formed on the semiconductor substrate, and an insulating layer formed between the ohmic contact layer and the semiconductor substrate in the test area, or the substrate comprises a semiconductor substrate, an insulating layer formed in the semiconductor substrate in the test area, and a part of the semiconductor substrate above the insulating layer in the test area serving as the ohmic contact layer; a conductive test pattern formed on the ohmic contact layer in the test area, used for measuring the contact resistivity of the ohmic contact layer to characterize the contact resistivity of the semiconductor substrate for the side in contact with the metal; and an epitaxial structure layer formed on the substrate, the epitaxial structure layer being provided with an opening exposing the conductive test pattern. The semiconductor device of the application can directly measure the substrate side contact resistivity on the device, and the measurement accuracy is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] With the continuous development of science and technology, various vertical cavity surface emitting lasers (VCSELs) and light-emitting diodes (LEDs) have been widely used in optical communication, optical interconnection and optical storage, bringing great convenience to people's lives.

[0003] In the performance research of semiconductor devices such as VCSELs and LEDs, the ohmic contact characteristics between metal and semiconductor have always been a key focus for researchers. Excellent ohmic contact characteristics are crucial for improving the performance and characterization of the electrical properties of semiconductor devices. Among them, substrate-side contact resistivity is an important parameter characterizing the quality of the ohmic contact between the metal electrode and the semiconductor.

[0004] In related technologies, two methods are often used to measure substrate-side contact resistivity: Method one involves directly etching the product wafer down to the substrate surface and fabricating a transmission line model (TLM) or circular transmission line model (CTLM) or other related conductivity test patterns on it for measurement; Method two involves using a co-wafer, the surface of which is made of the same material with the same doping concentration as the substrate, and fabricating a TLM or CTLM or other related conductivity test patterns on the co-wafer for measurement. However, while Method one can directly measure the substrate-side contact resistivity of semiconductor devices, it often has a large error and cannot obtain accurate results; while Method two is an indirect measurement method, which cannot directly obtain the actual substrate-side contact resistivity of semiconductor devices, and its structure cannot be applied to the epitaxial structure of actual semiconductor devices. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, the present invention provides a semiconductor device, comprising:

[0007] A substrate, the substrate including a test region and a device region, wherein the substrate includes a semiconductor substrate, an ohmic contact layer formed on the semiconductor substrate, and an insulating layer formed in the test region between the ohmic contact layer and the semiconductor substrate, or the substrate includes a semiconductor substrate, an insulating layer formed in the semiconductor substrate in the test region, wherein the portion of the semiconductor substrate located in the test region and above the insulating layer serves as the ohmic contact layer;

[0008] A conductivity test pattern is formed on the ohmic contact layer within the test area to measure the contact resistivity of the ohmic contact layer, thereby characterizing the contact resistivity of the semiconductor substrate on the side that contacts the metal.

[0009] An epitaxial structure layer is formed on the substrate, and an opening is formed in the epitaxial structure layer to expose the conductive test pattern.

[0010] For example, a semiconductor material layer is formed between the ohmic contact layer and the semiconductor substrate, and the insulating layer is obtained by processing the semiconductor material layer located in the test area.

[0011] For example, the semiconductor material layer is made of at least one of the following: Al x Ga 1-x As, Si, Ge, SiGe, SiC, SiGeC, and graphene, wherein x is greater than or equal to 0.97; the processing of the semiconductor material layer located in the test area includes oxidation or doping.

[0012] For example, when the semiconductor material layer located in the test area is subjected to the oxidation treatment, a trench is also formed in the edge region of the test area in the substrate, the trench penetrating at least the ohmic contact layer and the insulating layer.

[0013] For example, the ohmic contact layer is made of the same material as the semiconductor substrate and has the same doping concentration.

[0014] This application also provides a method for fabricating a semiconductor device, the method comprising:

[0015] A semiconductor substrate is provided, the semiconductor substrate including a test region and a device region;

[0016] A semiconductor material layer and an ohmic contact layer are sequentially formed on the semiconductor substrate;

[0017] An epitaxial structure layer is formed on the ohmic contact layer;

[0018] The epitaxial structure layer within the test area is etched away to form an opening that exposes the ohmic contact layer;

[0019] An insulating layer is obtained by processing the semiconductor material layer within the test area;

[0020] A conductive test pattern is formed on the ohmic contact layer within the test area. The conductive test pattern is used to measure the contact resistivity of the ohmic contact layer to characterize the contact resistivity of the semiconductor substrate on the side that is in contact with the metal.

[0021] For example, the process of processing the semiconductor material layer in the test area to obtain an insulating layer includes:

[0022] A trench is formed at the edge region of the test area, the trench penetrating at least the ohmic contact layer and the semiconductor material layer. The insulating layer is obtained by oxidizing the semiconductor material layer within the test area through the trench; or...

[0023] The insulating layer is obtained by doping the semiconductor material layer in the test area.

[0024] For example, the method further includes forming a buffer layer on the semiconductor substrate before forming the semiconductor material layer.

[0025] For example, the ohmic contact layer is made of the same material as the semiconductor substrate and has the same doping concentration.

[0026] Another aspect of this application provides a method for fabricating a semiconductor device, the method comprising:

[0027] A semiconductor substrate is provided, the semiconductor substrate including a test region and a device region;

[0028] An epitaxial structure layer is formed on the semiconductor substrate;

[0029] The epitaxial structure layer within the test area is etched away to form an opening exposing the semiconductor substrate;

[0030] The portion of the semiconductor substrate exposed in the opening below the surface of the semiconductor substrate is processed to form an insulating layer, wherein the portion of the semiconductor substrate located within the test area and above the insulating layer serves as an ohmic contact layer;

[0031] A conductive test pattern is formed on the ohmic contact layer within the test area. The conductive test pattern is used to measure the contact resistivity of the ohmic contact layer to characterize the contact resistivity of the semiconductor substrate on the side that is in contact with the metal.

[0032] Exemplarily, processing the portion of the semiconductor substrate below the surface exposed in the opening to form an insulating layer includes:

[0033] The portion of the semiconductor substrate below the surface exposed in the opening is doped to form the insulating layer.

[0034] In another aspect, the present invention provides an electronic device comprising the aforementioned semiconductor device or a semiconductor device prepared by the aforementioned preparation method.

[0035] The semiconductor device and its fabrication method, as well as the electronic device of the present invention, have an insulating layer formed below the ohmic contact layer in the test area, and a conductive test pattern formed on the ohmic contact layer in the test area. The contact resistivity of the ohmic contact layer is measured by the conductive test pattern to characterize the contact resistivity of the semiconductor substrate on the side that contacts the metal. This allows for direct measurement of the contact resistivity on the substrate side (the side of the semiconductor substrate that contacts the metal) on the semiconductor device, effectively controlling the thickness of the ohmic contact layer in the test area, greatly reducing measurement errors, improving the measurement accuracy of contact resistivity, and accurately reflecting the actual process level without affecting the current flow in the device area. Attached Figure Description

[0036] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0037] In the attached image:

[0038] Figure 1A A schematic diagram of a transmission line model is shown;

[0039] Figure 1B A schematic diagram of a circular transmission line model is shown;

[0040] Figure 1C A cross-sectional schematic diagram of a semiconductor device related to the technology is shown;

[0041] Figures 2A-2J A cross-sectional schematic diagram of the semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of the present invention is shown.

[0042] Figure 2K A top view of a semiconductor device according to a specific embodiment of the present invention is shown;

[0043] Figures 3A-3F A cross-sectional schematic diagram of the semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to another specific embodiment of the present invention is shown.

[0044] Figure 4 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of the present invention is shown;

[0045] Figure 5 A flowchart illustrating a method for fabricating a semiconductor device according to another specific embodiment of the present invention is shown;

[0046] Figure 6 A schematic diagram of an electronic device according to an embodiment of the present invention is shown. Detailed Implementation

[0047] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be construed as having the meaning consistent with their meaning in the relevant field and / or the context of this specification, and shall not be interpreted in an ideal or overly formal sense, unless expressly defined herein.

[0053] To fully understand this invention, detailed steps and structures will be set forth in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0054] like Figure 1A , Figure 1B and Figure 1C As shown, Figure 1A A schematic diagram of a transmission line model is shown. Figure 1B A schematic diagram of a circular transmission line model is shown. Figure 1C A cross-sectional schematic diagram of a semiconductor device related to this technology is shown. In the research of related semiconductor devices, excellent ohmic contact characteristics are crucial for improving the performance and characterizing the electrical properties of the semiconductor device. Among these, substrate-side contact resistivity is an important parameter characterizing the quality of the ohmic contact between the metal electrode and the semiconductor. In related technologies, one of the following two methods is often used to measure the substrate-side contact resistivity of semiconductor devices.

[0055] Method one involves directly etching the substrate onto the product wafer and fabricating a TLM or circular transmission line model (CTLM) and other relevant conductivity test patterns on it for measurement. The TLM and CTLM patterns are shown below. Figure 1A and Figure 1B As shown. The inventors of this application discovered that although the above-mentioned method one can directly measure the substrate-side contact resistivity of semiconductor devices, it cannot obtain accurate results. Taking the TLM algorithm as an example, the TLM algorithm has the following relationship:

[0056]

[0057] Where R T R is the total resistance. S For semiconductor sheet resistors, R C Let W be the contact resistance, and W and L be the width and distance between the metal parts. The actual measured total resistance R is... T An error δ is unavoidable. If the error is taken into account, the above equation should be:

[0058]

[0059] In TLM calculation methods, we have:

[0060]

[0061] L T ρ is the distance the electric current travels in the metal. c This refers to the contact resistivity we need to measure and calculate. Considering errors, we have:

[0062]

[0063] Substituting the above formula into the formula for calculating contact resistivity, we get:

[0064]

[0065] Discarding the second-order minterms in the above equation, we get:

[0066]

[0067] The first term on the right side of the equation is ρ when error is not considered. c The expression, the second term on the right-hand side of the equation, is the contact resistivity ρ. c The error X is denoted as:

[0068]

[0069] When the resistivity ρ of the material is constant, we have:

[0070]

[0071] d is the thickness of the contact layer in the ohmic contact. Substituting the above formula into the expression for the error X, we get:

[0072]

[0073] From the above equation, we can see that the contact resistivity ρ c The error X is directly proportional to the thickness d of the contact layer; the larger d is, the larger the error X is.

[0074] Based on the above calculations, in practice, when the semiconductor thickness is around 5 μm, the final error X < 1 × 10⁻⁶. -7 Ω·cm -2 This is compared to the contact resistivity itself, which is on the order of 1×10⁻⁶. -7 Ω·cm -2 This is acceptable, but when the semiconductor thickness increases to 50μm or even 100μm, the final error X will increase to the order of 1×

[0075] 10 -6 Ω·cm -2 This is even an order of magnitude larger than the contact resistivity itself, and such a measurement result would be completely unreliable. The calculation method for CTLM is the same as that for TLM, and will not be repeated here. The error in the result is also proportional to the thickness of the contact layer. Therefore, although Method 1 can directly measure the substrate-side contact resistivity of semiconductor devices, it often contains a non-negligible error and cannot obtain accurate measurement results.

[0076] Method two involves using a co-surface substrate. The surface of the co-surface substrate is made of the same material with the same doping concentration as the substrate. TLM or CTLM conductivity test patterns are fabricated on the co-surface substrate for measurement. The TLM and CTLM patterns are shown below. Figure 1A and Figure 1B As shown. Figure 1C As shown, the thickness of the contact layer is controlled by forming an undoped insulating layer to reduce measurement errors. However, this insulating layer also prevents current from flowing vertically. Therefore, Method 2 cannot be applied to normal semiconductor device structures as a direct measurement scheme, meaning that the actual substrate-side contact resistivity of the semiconductor device cannot be measured.

[0077] In summary, both Method 1 and Method 2 in the related technologies have defects in measuring the substrate-side contact resistivity of semiconductor devices, resulting in inaccurate measurement results.

[0078] Therefore, in view of the aforementioned technical problems, the present invention proposes a semiconductor device comprising:

[0079] A substrate, the substrate including a test region and a device region, wherein the substrate includes a semiconductor substrate, an ohmic contact layer formed on the semiconductor substrate, and an insulating layer formed in the test region between the ohmic contact layer and the semiconductor substrate, or the substrate includes a semiconductor substrate, an insulating layer formed in the semiconductor substrate in the test region, wherein the portion of the semiconductor substrate located in the test region and above the insulating layer serves as the ohmic contact layer;

[0080] A conductivity test pattern is formed on the ohmic contact layer within the test area to measure the contact resistivity of the ohmic contact layer, thereby characterizing the contact resistivity of the semiconductor substrate on the side that contacts the metal.

[0081] An epitaxial structure layer is formed on the substrate, and an opening is formed in the epitaxial structure layer to expose the conductive test pattern.

[0082] An insulating layer is formed beneath the ohmic contact layer in the test area, and a conductive test pattern is formed on the ohmic contact layer within the test area. The contact resistivity of the ohmic contact layer is measured using the conductive test pattern to characterize the contact resistivity of the semiconductor substrate on the side that contacts the metal. This allows for direct measurement of the substrate-side contact resistivity on the semiconductor device, effectively controlling the thickness of the ohmic contact layer in the test area, significantly reducing measurement errors, improving the accuracy of contact resistivity measurement, accurately reflecting the actual process level, and without affecting the current flow in the device area.

[0083] Example 1

[0084] Below, refer to the following: Figure 2J and Figure 3F The semiconductor device of the present invention will be described in detail.

[0085] In one example, such as Figure 2J As shown, the semiconductor device of the present invention includes a substrate, which includes a test region and a device region. It should be noted that the division between the test region and the device region can be made according to actual conditions and is not limited in the embodiments of the present invention; it is merely illustrated by example.

[0086] In one example, such as Figure 2J As shown, the substrate includes a semiconductor substrate 200. Exemplarily, the semiconductor substrate 200 is a bulk silicon substrate, which can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form the semiconductor substrate 200 have been described herein, any material that can be used as the semiconductor substrate 200 falls within the spirit and scope of the invention. In this embodiment, the semiconductor substrate 200 can be a GaAs substrate. In other embodiments, the semiconductor substrate 200 can also be any other suitable substrate. Exemplarily, the semiconductor substrate 200 can have a P-type conductivity type or an N-type conductivity type; in this embodiment, an N-type conductivity type semiconductor substrate 200 is used as an example. For example, metal electrodes for the device region may also be formed on the surface of the semiconductor substrate 200 away from the epitaxial structure layer 204.

[0087] In one example, such as Figure 2J As shown, a buffer layer 201 is also formed on the semiconductor substrate 200 to reduce defects in the epitaxial layers grown above the buffer layer. The buffer layer 201 may have the same material as the semiconductor substrate 200, and it can be lattice-matched with the semiconductor substrate 200, thereby reducing the migration of defects in the semiconductor substrate 200 to the buffer layer, and further, it helps to reduce the migration of defects in the semiconductor substrate 200 to other epitaxial layers on the buffer layer. Exemplarily, the buffer layer 201 can be formed using an epitaxial growth process or a suitable technique. In this embodiment, the buffer layer 201 can be formed using any of several methods in the epitaxial growth process, non-limiting examples including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). In one example, such as... Figure 2J As shown, a semiconductor material layer 202 is formed on the buffer layer 201 within the device region. Exemplarily, the semiconductor material layer 202 can be formed using epitaxial growth processes or suitable techniques. In this embodiment, the semiconductor material layer 202 can be formed using any of several methods in epitaxial growth processes, non-limiting examples including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). Exemplarily, the semiconductor material layer 202 is made of Al. x Ga 1-x As (where x is greater than or equal to 0.97). For example, the thickness of the semiconductor material layer 202 ranges from 20nm to 100nm. It should be noted that the material and thickness range of the semiconductor material layer 202 can be selected according to the actual situation.

[0088] In one example, such as Figure 2J As shown, an insulating layer 208 is formed on the buffer layer 201 within the test area. Exemplarily, the insulating layer 208 can be formed using oxidation processes known to those skilled in the art, such as furnace tube oxidation, rapid thermal annealing (RTO), or in-situ steam oxidation (ISSG). Exemplarily, the insulating layer 208 is used to limit the thickness through which current flows, i.e., to limit the thickness of the contact layer used for ohmic contact to the thickness of the ohmic contact layer 203. The error in the measured contact resistivity is positively correlated with the contact layer of the ohmic contact, thereby allowing the error in the measured contact resistivity to be controlled within a certain range.

[0089] In one example, such as Figure 2J As shown, ohmic contact layers 203 are formed in both the test region and the device region. The ohmic contact layer 203 in the test region covers the insulating layer 208, and the ohmic contact layer 203 in the device region covers the semiconductor material layer 202. Exemplarily, the ohmic contact layer 203 can be formed using epitaxial growth processes or suitable techniques. In this embodiment, the ohmic contact layer 203 can be formed using any of several methods in epitaxial growth processes, including, but not limited to, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). Exemplarily, the ohmic contact layer 203 is used to form ohmic contacts with metal electrodes, etc.

[0090] For example, the ohmic contact layer 203 has the same doping concentration as the semiconductor substrate 200. For example, the ohmic contact layer 203 may also have the same material as the semiconductor substrate 200. For example, by making the ohmic contact layer 203 and the semiconductor substrate 200 have the same material and doping concentration, the contact resistivity of the semiconductor substrate 200, that is, the contact resistivity of the semiconductor substrate on the side of the semiconductor substrate used for contacting the metal, can be obtained by measuring the contact resistivity of the ohmic contact layer 203.

[0091] In one example, such as Figure 2J As shown, the thickness of the ohmic contact layer 203 in the test area is less than 5 μm. Exemplarily, there are no specific requirements for the thickness of the ohmic contact layer 203 in the device area, as long as it meets the actual needs. Exemplarily, the thickness of the ohmic contact layer 203 in the test area is less than the thickness of the ohmic contact layer 203 in the device area. In other embodiments, the thickness of the ohmic contact layer 203 in the test area can also be equal to the thickness of the ohmic contact layer 203 in the device area. Exemplarily, when the thickness of the ohmic contact layer 203 in the test area is less than 5 μm, the error of the measured contact resistivity can be controlled within a certain range. If the error requirement is further relaxed, the thickness of the ohmic contact layer 203 in the test area can also be greater than 5 μm according to actual needs.

[0092] In one example, such as Figure 2J As shown, a conductive test pattern 209 is formed on the ohmic contact layer 203 within the test area. This pattern is used to measure the contact resistivity of the ohmic contact layer 305, characterizing the contact resistivity of the semiconductor substrate on the side in contact with the metal. In other words, the measured contact resistivity of the ohmic contact layer 305 is the contact resistivity of the semiconductor substrate on the side in contact with the metal. In this embodiment, the conductive test pattern 209 can be a TLM pattern or a CTLM pattern. The calculation method for TLM has been mentioned above, and the calculation method for CTLM is similar to that for TLM, and will not be repeated here. Exemplarily, the conductive test pattern 209 can acquire relevant characteristic data related to the ohmic contact layer 203 within the test area. The contact resistivity is calculated using this relevant characteristic data, and the thickness of the ohmic contact layer 203 is controlled to be less than 5 μm, making the measurement error acceptable or even negligible, thereby improving the measurement accuracy.

[0093] In one example, such as Figure 2JAs shown, an epitaxial structure layer 204 is formed above the ohmic contact layer 203. Exemplarily, the epitaxial structure layer 204 can be formed using an epitaxial growth process or a suitable technique. In this embodiment, the epitaxial structure layer 204 can be formed using any of several methods in the epitaxial growth process, non-limiting examples including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). The specific structure of the epitaxial structure layer 204 is determined according to the type of semiconductor device. For example, when the semiconductor device is a vertical-cavity surface-emitting laser, the epitaxial structure layer 204 may include stacked N-type Balagare mirror layers and multiple quantum well (MQW) layers, etc.

[0094] In one example, such as Figure 2J As shown, an opening 205 is formed in the epitaxial structure layer 204, and the opening 205 exposes at least the conductive test pattern 209. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, plasma etching, etc., can be used to etch the epitaxial structure layer 204 to form the opening 205.

[0095] In one example, such as Figure 2J As shown, a groove 206 is also formed within the test area, corresponding to the opening 205. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, and plasma etching, can be used to etch a portion of the thickness of the ohmic contact layer 203 within the test area to form the groove 206. Exemplarily, the conductive test pattern 209 is located on the ohmic contact layer 203 at the bottom of the groove 206. In other embodiments, the groove 206 may not be formed, as long as the thickness of the ohmic contact layer 203 within the test area meets the requirements.

[0096] In one example, the insulating layer 208 and the semiconductor material layer 202 are located in the same layer, and the insulating layer 208 is obtained by processing the semiconductor material layer 202 previously located in the test area. Exemplarily, processing the semiconductor material layer 202 previously located in the test area includes performing an oxidation process or a doping process.

[0097] For example, the insulating layer 208 is obtained by oxidizing the semiconductor material layer 202 previously located below the ohmic contact layer 203 in the test area. During the semiconductor device formation process, a semiconductor material layer 202 is first formed in the test area, and then an oxidizing process is performed on the semiconductor material layer 202 to obtain the insulating layer 208. The resistance of this insulating layer 208 is significantly increased compared to the semiconductor material layer 202, and it can also be referred to as a high-resistance layer. For example, the oxidation process may include furnace tube oxidation, rapid thermal annealing (RTO), in-situ steam oxidation (ISSG), etc. For example, when the semiconductor material layer 202 is made of Al... x Ga 1-x When x is greater than or equal to 0.97, the material of the insulating layer 208 may include Al2O3. In other embodiments, the semiconductor material layer 202 may also be any other suitable material, such as Si, Ge, SiGe, SiC, SiGeC, etc., or the semiconductor material layer 202 may also be other materials with semiconductor or conductor properties, such as graphene.

[0098] In one example, such as Figure 2J As shown, when the semiconductor material layer 202 previously located in the test area is oxidized to obtain the insulating layer 208, a trench 207 is also formed in the edge region of the test area. The trench 207 penetrates at least the ohmic contact layer 203 and the insulating layer 208. At this time, the semiconductor material layer 202 previously located in the test area is oxidized through the trench 207. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, plasma etching, etc., can be used to form the trench 207. Exemplarily, the edge region of the test area can be the four edges, two sides, one side, or at least a portion of the edge region of the test area. Preferably, the trench 207 is formed at the four edges of the test area, and its projection on the substrate surface is generally annular, such as a square annular, circular annular, or other suitable annular shape. Exemplarily, as... Figure 2K As shown, the groove 207 is annular, and the groove 207 exposes the buffer layer 201.

[0099] In one example, the semiconductor material layer 202 previously located in the test area can also be doped to obtain an insulating layer 208. Exemplarily, the doping process includes a high-energy ion implantation process, wherein the implanted ions may include at least one of hydrogen ions and boron ions, wherein, preferably, the implanted ions include hydrogen ions.

[0100] In other examples, the process can also be other processes that can transform the semiconductor material layer 202 into an insulating layer, such as nitriding or carbonization.

[0101] In summary, the semiconductor device of the present invention has an insulating layer 208 formed below the ohmic contact layer 203 in the test area, and a conductive test pattern 209 formed on the ohmic contact layer 203 in the test area. The contact resistivity of the ohmic contact layer is measured through the conductive test pattern to characterize the contact resistivity of the semiconductor substrate on the side for contact with the metal. This allows for direct measurement of the substrate-side contact resistivity on the semiconductor device, and effectively controls the thickness of the ohmic contact layer 203 in the test area. For example, the thickness of the ohmic contact layer 203 in the test area is controlled to be less than 5 μm, which greatly reduces the measurement error, improves the measurement accuracy of the contact resistivity, and makes the measurement results valuable for reference, which can truly reflect the actual process level. Furthermore, because the insulating layer 208 is formed only in the test area, it does not affect the current flow in the device area.

[0102] Figure 3F A cross-sectional schematic diagram of a semiconductor device according to another specific embodiment of the present invention is shown. Without conflict, the technical features of the various embodiments of this application can be combined with each other.

[0103] In one example, such as Figure 3F As shown, the semiconductor device of the present invention includes a substrate, which includes a test region and a device region. It should be noted that the division between the test region and the device region can be made according to actual conditions and is not limited in the embodiments of the present invention; it is merely illustrated by example.

[0104] In one example, such as Figure 3F As shown, the substrate includes a semiconductor substrate 300. Exemplarily, the semiconductor substrate 300 is a bulk silicon substrate, which can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form the semiconductor substrate 300 have been described herein, any material that can be used as the semiconductor substrate 300 falls within the spirit and scope of the invention. In this embodiment, the semiconductor substrate 300 can be a GaAs substrate. In other embodiments, the semiconductor substrate 300 can also be any other suitable substrate. Exemplarily, the semiconductor substrate 300 can have a P-type conductivity type or an N-type conductivity type; in this embodiment, an N-type conductivity type semiconductor substrate 300 is used as an example. For example, a metal electrode for the device region may also be formed on the surface of the semiconductor substrate 300 away from the epitaxial structure layer 301.

[0105] In one example, such as Figure 3F As shown, an insulating layer 304 is formed in the semiconductor substrate 300 within the test area. Exemplarily, the insulating layer 304 can be formed using an ion implantation process, and the implanted ions can include at least one of oxygen ions, nitrogen ions, and carbon ions, wherein, preferably, the implanted ions include oxygen ions.

[0106] In one example, such as Figure 3F As shown, the semiconductor substrate 300 above the insulating layer 304 serves as the ohmic contact layer 305. Exemplarily, the thickness of the ohmic contact layer 305 is less than 5 μm. Exemplarily, when the thickness of the ohmic contact layer 305 is less than 5 μm, the error in the measured contact resistivity can be controlled within a certain range. If the error requirement is further relaxed, the thickness of the ohmic contact layer 305 can also be greater than 5 μm according to actual needs.

[0107] In one example, such as Figure 3F As shown, a conductive test pattern 306 is formed on the ohmic contact layer 305 to measure the contact resistivity of the ohmic contact layer 305, thereby characterizing the contact resistivity of the semiconductor substrate on the side used for contact with the metal. In other words, the measured contact resistivity of the ohmic contact layer 305 is the contact resistivity of the semiconductor substrate on the side used for contact with the metal. In this embodiment, the conductive test pattern 306 can be a TLM pattern or a CTLM pattern. The calculation method for TLM has been mentioned above, and the calculation method for CTLM is similar to that for TLM, and will not be repeated here. Exemplarily, the conductive test pattern 306 can obtain relevant characteristic data for ohmic contact with the ohmic contact layer 305. The contact resistivity is calculated from this relevant characteristic data, and the thickness of the ohmic contact layer 305 is controlled within a range of less than 5 μm, making the measurement error acceptable or even negligible, thereby improving the measurement accuracy.

[0108] In one example, such as Figure 3FAs shown, an epitaxial structure layer 301 is also formed on the semiconductor substrate 300. Exemplarily, the epitaxial structure layer 301 can be formed using an epitaxial growth process or a suitable technique. In this embodiment, the epitaxial structure layer 301 can be formed using any of several methods in the epitaxial growth process, non-limiting examples including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). The specific structure of the epitaxial structure layer 301 is determined according to the type of semiconductor device. For example, when the semiconductor device is a vertical-cavity surface-emitting laser, the epitaxial structure layer 301 may include stacked N-type Balagare mirror layers and multiple quantum well (MQW) layers, etc.

[0109] In one example, such as Figure 3F As shown, an opening 302 is formed in the epitaxial structure layer 301, and the opening 302 exposes at least the conductive test pattern 306. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, plasma etching, etc., can be used to etch the epitaxial structure layer 301 to form the opening 302.

[0110] In one example, such as Figure 3F As shown, a groove 303 is also formed in the ohmic contact layer within the test area, corresponding to the opening 302. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, and plasma etching, can be used to etch a portion of the semiconductor substrate 300 to form the groove 303. Exemplarily, the conductive test pattern 306 is located at the bottom of the groove 303. In other embodiments, the groove 303 may not be formed, provided the thickness of the ohmic contact layer 305 meets the requirements.

[0111] This concludes the introduction to the structure of the semiconductor device of the present invention. The complete device may also include other components, which will not be described in detail here.

[0112] In summary, the semiconductor device of the present invention has an insulating layer 304 formed in the semiconductor substrate 300 of the test area, and uses the semiconductor substrate above the insulating layer 304 as an ohmic contact layer 305. A conductive test pattern 306 is formed on the ohmic contact layer 305. The contact resistivity of the ohmic contact layer is measured through the conductive test pattern to characterize the contact resistivity of the semiconductor substrate on the side that is in contact with the metal. This allows for direct measurement of the substrate-side contact resistivity on the semiconductor device, and effectively controls the thickness of the ohmic contact layer 305. For example, the thickness of the ohmic contact layer 305 is controlled to be less than 5 μm, which greatly reduces the measurement error, improves the measurement accuracy of the contact resistivity, and makes the measurement results valuable for reference, which can truly reflect the actual process level. Furthermore, since the insulating layer 304 is formed only within the test area, it does not affect the current flow in the device area.

[0113] Example 2

[0114] Below, for reference Figures 2A-2K and Figure 4 And reference Figures 3A-3F and Figure 5 The method for fabricating the semiconductor device of the present invention is described in detail, wherein, Figures 2A-2J The diagram shows a cross-sectional view of the semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of the present invention. Figure 2K A top view of a semiconductor device according to a specific embodiment of the present invention is shown. Figures 3A-3F The diagram shows a cross-sectional view of the semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to another specific embodiment of the present invention. Figure 4 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of the present invention is shown. Figure 5 A flowchart illustrating a method for fabricating a semiconductor device according to another specific embodiment of the present invention is shown.

[0115] First, refer to Figures 2A-2K and Figure 4 A detailed description is provided of a method for fabricating a semiconductor device according to a specific embodiment of the present invention. For example, as shown... Figure 4 As shown, a method for fabricating a semiconductor device according to a specific embodiment of the present invention includes the following steps:

[0116] First, step S410 is performed to provide a semiconductor substrate, which includes a test area and a device area.

[0117] Specifically, such as Figure 2AAs shown, the semiconductor substrate 200 is a bulk silicon substrate, which can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form the semiconductor substrate 200 have been described herein, any material that can be used as the semiconductor substrate 200 falls within the spirit and scope of the invention. In this embodiment, the semiconductor substrate 200 can be a GaAs substrate. In other embodiments, the semiconductor substrate 200 can also be any other suitable substrate. Exemplarily, the semiconductor substrate 200 can have a P-type conductivity type or an N-type conductivity type; in this embodiment, an N-type conductivity type semiconductor substrate 200 is used as an example. It should be noted that the division between the test area and the device area can be made according to the actual situation, and is not limited in the embodiments of the present invention. It is only illustrated in the form of an example.

[0118] For example, such as Figure 2B As shown, after performing step S410 and before performing step S420, the method further includes: forming a buffer layer 201 on the semiconductor substrate 200 to reduce defects in the epitaxial layers grown above the buffer layer. The buffer layer 201 may have the same material as the semiconductor substrate 200, and it may be lattice-matched with the semiconductor substrate 200, thereby reducing the migration of defects in the semiconductor substrate 200 to the buffer layer, and further, it also helps to reduce the migration of defects in the semiconductor substrate 200 to other epitaxial layers on the buffer layer. Exemplarily, the buffer layer 201 may be formed using an epitaxial growth process or a suitable technique. In this embodiment, the buffer layer 201 may be formed using any of several methods in the epitaxial growth process, non-limiting examples including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).

[0119] Next, step S420 is performed to sequentially form a semiconductor material layer and an ohmic contact layer on the semiconductor substrate.

[0120] In one example, such as Figure 2CAs shown, a semiconductor material layer 202 is formed on the buffer layer 201. Exemplarily, the semiconductor material layer 202 can be formed using epitaxial growth processes or suitable techniques. In this embodiment, the semiconductor material layer 202 can be formed using any of several methods in epitaxial growth processes, non-limiting examples including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). Exemplarily, the semiconductor material layer 202 is made of Al. x Ga 1-x As (where x is greater than or equal to 0.97). For example, the thickness of the semiconductor material layer 202 ranges from 20nm to 100nm. It should be noted that the material and thickness range of the semiconductor material layer 202 can be selected according to actual conditions. In other embodiments, the semiconductor material layer 202 can also be any other suitable material, such as Si, Ge, SiGe, SiC, SiGeC, etc.

[0121] In one example, such as Figure 2D As shown, an ohmic contact layer 203 is formed on a semiconductor material layer 202. Exemplarily, the ohmic contact layer 203 can be formed using an epitaxial growth process or a suitable technique. In this embodiment, the ohmic contact layer 203 can be formed using any of several methods in epitaxial growth processes, non-limiting examples including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). Exemplarily, the ohmic contact layer 203 is used to form an ohmic contact with a metal electrode or the like.

[0122] For example, the ohmic contact layer 203 has the same doping concentration as the semiconductor substrate 200. For example, the ohmic contact layer 203 may also have the same material as the semiconductor substrate 200. For example, by making the ohmic contact layer 203 and the semiconductor substrate 200 have the same material and doping concentration, the contact resistivity of the semiconductor substrate 200 can be obtained by measuring the contact resistivity of the ohmic contact layer 203.

[0123] Next, step S430 is performed to form an epitaxial structure layer on the ohmic contact layer.

[0124] In one example, such as Figure 2EAs shown, an epitaxial structure layer 204 is formed on the ohmic contact layer 203. Exemplarily, the epitaxial structure layer 204 can be formed using an epitaxial growth process or a suitable technique. In this embodiment, the epitaxial structure layer 204 can be formed using any of several methods in the epitaxial growth process, non-limiting examples including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). The specific structure of the epitaxial structure layer 204 is determined according to the type of semiconductor device. For example, when the semiconductor device is a vertical-cavity surface-emitting laser, the epitaxial structure layer 204 may include stacked N-type Balagare mirror layers and multiple quantum well (MQW) layers, etc.

[0125] Next, step S440 is performed to etch away the epitaxial structure layer in the test area to form an opening that exposes the ohmic contact layer.

[0126] In one example, such as Figure 2F As shown, the epitaxial structure layer 204 within the test area is etched away to form an opening 205. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, and plasma etching, can be used to etch the epitaxial structure layer 204 to form the opening 205. Exemplarily, the opening 205 exposes the ohmic contact layer 203 within the test area.

[0127] For example, such as Figure 2G As shown, after performing step S440 and before performing step S450, the method further includes: etching away a portion of the exposed thickness of the ohmic contact layer 203 in the opening 205 to form a groove 206. Exemplarily, the groove 206 corresponds to the opening 205. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, plasma etching, etc., can be used to etch the ohmic contact layer 203 in the test area to form the groove 206. In other embodiments, the groove 206 may not be formed, as long as the thickness of the ohmic contact layer 203 in the test area meets the requirements.

[0128] In one example, the thickness of the ohmic contact layer 203 in the test area is less than 5 μm. Exemplarily, there are no specific requirements for the thickness of the ohmic contact layer 203 in the device area, as long as it meets the actual needs. Exemplarily, the thickness of the ohmic contact layer 203 in the test area is less than the thickness of the ohmic contact layer 203 in the device area. In other embodiments, the thickness of the ohmic contact layer 203 in the test area can also be equal to the thickness of the ohmic contact layer 203 in the device area. Exemplarily, when the thickness of the ohmic contact layer 203 in the test area is less than 5 μm, the error in the measured contact resistivity can be controlled within a certain range. If the error requirement is further relaxed, the thickness of the ohmic contact layer 203 in the test area can also be greater than 5 μm according to actual needs.

[0129] Next, step S450 is performed to process the semiconductor material layer in the test area to obtain an insulating layer.

[0130] In one example, processing the semiconductor material layer within the test region to obtain an insulating layer includes: forming a trench in the edge region of the test region, the trench penetrating at least the ohmic contact layer and the semiconductor material layer, and oxidizing the semiconductor material layer within the test region through the trench to obtain the insulating layer; or, doping the semiconductor material layer within the test region to obtain the insulating layer. In one example, such as... Figure 2H As shown, a trench 207 is formed in the edge region of the test area. The trench 207 penetrates at least the ohmic contact layer 203 and the semiconductor material layer 202, for example, the trench 207 is formed in the edge region at the bottom of the recess 206. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, plasma etching, etc., can be used to form the trench 207. Exemplarily, the edge region of the test area can be the four edges, two sides, one side, or at least a portion of the edge region of the test area. Preferably, the trench 207 is formed at the four edges of the test area, and its projection on the substrate surface is generally annular, such as a square annular, circular annular, or other suitable annular shape. Exemplarily, the trench 207 is located in the edge region of the recess 206. Exemplarily, as... Figure 2K As shown, the groove 207 is annular, and the groove 207 exposes the buffer layer 201.

[0131] In one example, such as Figure 2IAs shown, the semiconductor material layer 202 in the test area is oxidized through trench 207 to obtain an insulating layer 208. The resistance of this insulating layer 208 is significantly increased compared to the semiconductor material layer 202, and it can also be referred to as a high-resistivity layer. Exemplarily, the oxidation process may include furnace tube oxidation, rapid thermal annealing (RTO), in-situ steam oxidation (ISSG), etc. Exemplarily, when the semiconductor material layer 202 is made of Al... x Ga 1-x When As (where x is greater than or equal to 0.97), the material of the insulating layer 208 may include Al2O3.

[0132] In one example, the semiconductor material layer 202 within the test region can also be doped to obtain an insulating layer 208. Exemplarily, the doping process can be achieved through an ion implantation process, such as high-energy ion implantation, wherein the implanted ions can include at least one of carbon ions, nitrogen ions, oxygen ions, hydrogen ions, and boron ions, wherein, preferably, the implanted ions include hydrogen ions.

[0133] In other examples, the process can also be other processes that can transform the semiconductor material layer 202 into an insulating layer, such as nitriding or carbonization.

[0134] Finally, step S460 is performed to form a conductive test pattern on the ohmic contact layer within the test area. The conductive test pattern is used to measure the contact resistivity of the ohmic contact layer to characterize the contact resistivity of the semiconductor substrate on the side that is in contact with the metal.

[0135] In one example, such as Figure 2J As shown, a conductive test pattern 209 is formed on the ohmic contact layer 203 within the test area. In this embodiment, the conductive test pattern 209 can be a TLM pattern or a CTLM pattern. The calculation method for TLM has been mentioned above, and the calculation method for CTLM is similar to that for TLM, and will not be repeated here. Exemplarily, the conductive test pattern 209 can be used to obtain relevant characteristic data of ohmic contact with the ohmic contact layer 203 within the test area. The contact resistivity is calculated using this relevant characteristic data, and the thickness of the ohmic contact layer 203 is controlled within a range of less than 5 μm, making the measurement error acceptable or even negligible, thereby improving the measurement accuracy.

[0136] In summary, the semiconductor device fabrication method of the present invention forms an insulating layer 208 below the ohmic contact layer 203 in the test area and a conductive test pattern 209 on the ohmic contact layer 203 in the test area. The contact resistivity of the ohmic contact layer is measured through the conductive test pattern to characterize the contact resistivity of the semiconductor substrate on the side that contacts the metal. This allows for direct measurement of the substrate-side contact resistivity on the semiconductor device and effectively controls the thickness of the ohmic contact layer 203 in the test area. For example, the thickness of the ohmic contact layer 203 in the test area is controlled to be less than 5 μm, which greatly reduces measurement error, improves the measurement accuracy of contact resistivity, and makes the measurement results valuable and able to truly reflect the actual process level. Furthermore, because the insulating layer 208 is formed only within the test area, it does not affect the current flow in the device area.

[0137] The following is for reference. Figures 3A-3F and Figure 5 A method for fabricating a semiconductor device according to another specific embodiment of the present invention will be described in detail. For example, as shown... Figure 5 As shown, another specific embodiment of the present invention describes a method for fabricating a semiconductor device that includes the following steps:

[0138] First, step S510 is performed to provide a semiconductor substrate, which includes a test area and a device area.

[0139] Specifically, such as Figure 3A As shown, the semiconductor substrate 300 is a bulk silicon substrate, which can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. Although several examples of materials that can form the semiconductor substrate 300 have been described herein, any material that can be used as the semiconductor substrate 300 falls within the spirit and scope of the invention. In this embodiment, the semiconductor substrate 300 can be a GaAs substrate. In other embodiments, the semiconductor substrate 300 can also be any other suitable substrate. Exemplarily, the semiconductor substrate 300 can have a P-type conductivity type or an N-type conductivity type; in this embodiment, an N-type conductivity type semiconductor substrate 300 is used as an example. It should be noted that the division between the test area and the device area can be made according to the actual situation, and is not limited in the embodiments of the present invention. It is only illustrated in the form of an example.

[0140] Next, step S520 is performed to form an epitaxial structure layer on the semiconductor substrate.

[0141] In one example, such as Figure 3B As shown, an epitaxial structure layer 301 is formed on a semiconductor substrate 300. Exemplarily, the epitaxial structure layer 301 can be formed using an epitaxial growth process or a suitable technique. In this embodiment, the epitaxial structure layer 301 can be formed using any of several methods in the epitaxial growth process, non-limiting examples including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE). The specific structure of the epitaxial structure layer 301 is determined according to the type of semiconductor device. For example, when the semiconductor device is a vertical-cavity surface-emitting laser, the epitaxial structure layer 301 may include stacked N-type Balagas mirror layers and multiple quantum well (MQW) layers, etc.

[0142] Next, step S530 is performed to etch away the epitaxial structure layer in the test area to form an opening that exposes the semiconductor substrate.

[0143] In one example, such as Figure 3C As shown, the epitaxial structure layer 301 within the test area is etched away to form an opening 302. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, and plasma etching, can be used to etch the epitaxial structure layer 301 to form the opening 302. Exemplarily, the opening 205 exposes the semiconductor substrate 300 within the test area.

[0144] For example, such as Figure 3D As shown, after performing step S530 and before performing step S540, the method further includes: etching away a portion of the semiconductor substrate 300 exposed in the opening 302 to form a groove 303. Exemplarily, the groove 206 corresponds to the opening 205. Exemplarily, etching processes known to those skilled in the art, such as reactive ion etching (RIE), ion beam etching, plasma etching, etc., can be used to etch the semiconductor substrate 300 to form the groove 303.

[0145] Next, step S540 is performed to process the portion of the semiconductor substrate exposed in the opening below the surface of the semiconductor substrate to form an insulating layer, wherein the portion of the semiconductor substrate located within the test area and above the insulating layer serves as an ohmic contact layer.

[0146] In one example, such as Figure 3EAs shown, the portion of the semiconductor substrate 300 below the surface of the semiconductor substrate 300 exposed by the opening 302 is processed to form an insulating layer 304, wherein the portion of the semiconductor substrate above the insulating layer 304 serves as an ohmic contact layer 305. Exemplarily, the portion of the semiconductor substrate 300 below the surface of the semiconductor substrate 300 exposed by the opening 302 can be doped to form the insulating layer 304. Exemplarily, the doping process can be achieved by an ion implantation process (e.g., a high-energy ion implantation process), whereby the energy of the ion implantation can be controlled to implant the portion of the semiconductor substrate 300 below the surface without affecting the portion of the semiconductor substrate above it. Exemplarily, the implanted ions can include at least one of carbon ions, nitrogen ions, oxygen ions, hydrogen ions, and boron ions, wherein preferably, hydrogen ions are implanted.

[0147] The implanted ions may include at least one of oxygen ions, nitrogen ions, carbon ions, hydrogen ions, and boron ions, wherein, preferably, the implanted ions include hydrogen ions.

[0148] In one example, such as Figure 3E As shown, the portion of the semiconductor substrate 300 located within the test area and above the insulating layer 304 serves as the ohmic contact layer 305. Exemplarily, the thickness of the ohmic contact layer 305 is less than 5 μm. Exemplarily, when the thickness of the ohmic contact layer 305 is less than 5 μm, the error in the measured contact resistivity can be controlled within a certain range. If the error requirement is further relaxed, the thickness of the ohmic contact layer 305 can also be greater than 5 μm according to actual needs.

[0149] Finally, step S550 is performed to form a conductive test pattern on the ohmic contact layer within the test area. The conductive test pattern is used to measure the contact resistivity of the ohmic contact layer to characterize the contact resistivity of the semiconductor substrate on the side that is in contact with the metal.

[0150] In one example, such as Figure 3F As shown, a conductive test pattern 306 is formed on the ohmic contact layer 305 within the test area. In this embodiment, the conductive test pattern 306 can be a TLM pattern or a CTLM pattern. The calculation method for TLM has been mentioned above, and the calculation method for CTLM is similar to that for TLM, and will not be repeated here. Exemplarily, the conductive test pattern 306 can be used to obtain relevant characteristic data of the ohmic contact with the ohmic contact layer 305. The contact resistivity is calculated using this relevant characteristic data, and the thickness of the ohmic contact layer 305 is controlled within a range of less than 5 μm, making the measurement error acceptable or even negligible, thereby improving the measurement accuracy.

[0151] This concludes the description of the key steps in the method for fabricating the semiconductor device of the present invention. Other steps may also be included in the fabrication of a complete semiconductor device, which will not be elaborated here.

[0152] In summary, the semiconductor device fabrication method of the present invention forms an insulating layer 304 in the semiconductor substrate 300 of the test area, uses the semiconductor substrate above the insulating layer 304 as an ohmic contact layer 305, and forms a conductive test pattern 306 on the ohmic contact layer 305. The conductive test pattern is used to measure the contact resistivity of the ohmic contact layer to characterize the contact resistivity of the semiconductor substrate on the side that contacts the metal. This allows for direct measurement of the substrate-side contact resistivity on the semiconductor device, and effectively controls the thickness of the ohmic contact layer 305. For example, the thickness of the ohmic contact layer 305 is controlled to be less than 5 μm, which greatly reduces measurement error, improves the measurement accuracy of contact resistivity, and makes the measurement results valuable and able to truly reflect the actual process level. Furthermore, because the insulating layer 304 is formed only within the test area, it does not affect the current flow in the device area.

[0153] Example 3

[0154] In another embodiment of the present invention, an electronic device is provided, including the aforementioned semiconductor device, or the semiconductor device is prepared according to the aforementioned method.

[0155] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned semiconductor devices, has better performance.

[0156] in, Figure 6 An example of a mobile phone is shown. The mobile phone 600 is provided with a display 602, operation buttons 603, an external connection port 604, a speaker 605, a microphone 606, etc., included in a housing 601.

[0157] The mobile phone includes a semiconductor device, which includes:

[0158] A substrate, the substrate including a test region and a device region, wherein the substrate includes a semiconductor substrate, an ohmic contact layer formed on the semiconductor substrate, and an insulating layer formed in the test region between the ohmic contact layer and the semiconductor substrate, or the substrate includes a semiconductor substrate, an insulating layer formed in the semiconductor substrate in the test region, wherein the portion of the semiconductor substrate located in the test region and above the insulating layer serves as the ohmic contact layer;

[0159] A conductivity test pattern is formed on the ohmic contact layer within the test area to measure the contact resistivity of the ohmic contact layer, thereby characterizing the contact resistivity of the semiconductor substrate on the side that contacts the metal.

[0160] An epitaxial structure layer is formed on the substrate, and an opening is formed in the epitaxial structure layer to expose the conductive test pattern.

[0161] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A semiconductor device, characterized in that, include: A substrate, the substrate including a test region and a device region, wherein the substrate includes a semiconductor substrate, an ohmic contact layer formed on the semiconductor substrate, and an insulating layer formed in the test region between the ohmic contact layer and the semiconductor substrate, or the substrate includes a semiconductor substrate, an insulating layer formed in the semiconductor substrate in the test region, wherein the portion of the semiconductor substrate located in the test region and above the insulating layer serves as the ohmic contact layer; A conductivity test pattern is formed on the ohmic contact layer within the test area to measure the contact resistivity of the ohmic contact layer, thereby characterizing the contact resistivity of the semiconductor substrate on the side that contacts the metal. An epitaxial structure layer is formed on the substrate, and an opening is formed in the epitaxial structure layer to expose the conductive test pattern.

2. The semiconductor device according to claim 1, characterized in that, A semiconductor material layer is formed between the ohmic contact layer and the semiconductor substrate, and the insulating layer is obtained by processing the semiconductor material layer located in the test area.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor material layer is made of at least one of the following: Al x Ga 1-x As, Si, Ge, SiGe, SiC, SiGeC, and graphene, wherein x is greater than or equal to 0.97; the processing of the semiconductor material layer located in the test area includes oxidation or doping.

4. The semiconductor device according to claim 2 or 3, characterized in that, The edge region of the test area in the substrate is further formed with a trench that penetrates at least the ohmic contact layer and the insulating layer.

5. The semiconductor device according to claim 1, characterized in that, The ohmic contact layer is made of the same material as the semiconductor substrate and has the same doping concentration.

6. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a test region and a device region; A semiconductor material layer and an ohmic contact layer are sequentially formed on the semiconductor substrate; An epitaxial structure layer is formed on the ohmic contact layer; The epitaxial structure layer within the test area is etched away to form an opening that exposes the ohmic contact layer; An insulating layer is obtained by processing the semiconductor material layer within the test area; A conductive test pattern is formed on the ohmic contact layer within the test area. The conductive test pattern is used to measure the contact resistivity of the ohmic contact layer to characterize the contact resistivity of the semiconductor substrate on the side that is in contact with the metal.

7. The preparation method according to claim 6, characterized in that, The process of processing the semiconductor material layer in the test area to obtain an insulating layer includes: A trench is formed at the edge region of the test area, the trench penetrating at least the ohmic contact layer and the semiconductor material layer. The insulating layer is obtained by oxidizing the semiconductor material layer within the test area through the trench; or... The insulating layer is obtained by doping the semiconductor material layer in the test area.

8. The preparation method according to claim 6, characterized in that, The method further includes forming a buffer layer on the semiconductor substrate before forming the semiconductor material layer.

9. The preparation method according to claim 6, characterized in that, The ohmic contact layer is made of the same material as the semiconductor substrate and has the same doping concentration.

10. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate including a test region and a device region; An epitaxial structure layer is formed on the semiconductor substrate; The epitaxial structure layer within the test area is etched away to form an opening exposing the semiconductor substrate; The portion of the semiconductor substrate exposed in the opening below the surface of the semiconductor substrate is processed to form an insulating layer, wherein the portion of the semiconductor substrate located within the test area and above the insulating layer serves as an ohmic contact layer; A conductive test pattern is formed on the ohmic contact layer within the test area. The conductive test pattern is used to measure the contact resistivity of the ohmic contact layer to characterize the contact resistivity of the semiconductor substrate on the side that is in contact with the metal.

11. The preparation method according to claim 10, characterized in that, The process of treating the portion of the semiconductor substrate below the surface exposed in the opening to form an insulating layer includes: The portion of the semiconductor substrate below the surface exposed in the opening is doped to form the insulating layer.

12. An electronic device, characterized in that, The electronic device includes the semiconductor device according to any one of claims 1-5, or includes the semiconductor device prepared by the preparation method according to any one of claims 6-11.

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