Solid-state imaging device and electronic apparatus

Abstract

The present invention relates to a solid-state imaging device and an electronic apparatus. The solid-state imaging device can include one or more photoelectric conversion elements disposed on and above a first surface of a semiconductor substrate, a through electrode connected to the one or more photoelectric conversion elements and disposed between the first surface and a second surface of the semiconductor substrate, and a dielectric layer disposed between the through electrode and the semiconductor substrate, the dielectric layer being disposed above the through electrode and extending along a surface of the one or more photoelectric conversion elements, and the dielectric layer being disposed between the surface of the one or more photoelectric conversion elements and the first surface of the semiconductor substrate, wherein the through electrode is made of an electrically conductive material, and wherein the dielectric layer is further disposed along a vertical side portion of the through electrode and includes an outer dielectric layer and an inner dielectric layer with a gap therebetween.

Description

[0001] This application is a divisional application of Patent Application No. 201910141497.1 with a filing date of August 7, 2014, entitled "Solid-state Imaging Device and Electronic Device" (hereinafter referred to as "Subcase").

[0002] This application is filed in the case where the State Intellectual Property Office considers that the above-mentioned Subcase does not meet the requirement of unity, specifically the first Notice of First Examination of the Subcase, which was issued on September 7, 2022, and the issue serial number is 2022090202386250.

[0003] In addition, the above-mentioned Subcase is a divisional application of Patent Application No. 201480042659.1 (hereinafter referred to as "Parent Case") with a filing date of August 7, 2014, entitled "Solid-state Imaging Device and Electronic Device". TECHNICAL FIELD

[0004] The present disclosure relates to a solid-state imaging device suitable for a so-called longitudinal light-splitting type and an electronic device including the solid-state imaging device. BACKGROUND

[0005] A CMOS (Complementary Metal Oxide Semiconductor) image sensor can exemplify a solid-state imaging device mounted in a digital video camera, a digital still camera, a smart phone, a mobile phone, and the like. In the CMOS image sensor, photoelectric charges are accumulated in a pn junction capacitor of a photodiode serving as a photoelectric conversion element; the photoelectric charges thus accumulated are read out through a MOS transistor.

[0006] A conventional solid-state imaging unit generally uses a pixel array in which red, green, and blue pixels are arranged on a plane, which causes pseudo colors associated with generation of color signals by performing interpolation processing between pixels. Therefore, a longitudinal light-splitting type solid-state imaging device in which red, green, and blue photoelectric conversion regions are stacked along a longitudinal direction of the same pixel has been studied. For example, in Patent Literature 1, a solid-state imaging device is disclosed in which a blue photodiode and a red photodiode are stacked within a semiconductor substrate, and a green photoelectric conversion element using an organic photoelectric conversion film is provided on the light-receiving surface side (back surface side or first surface side) of the semiconductor substrate.

[0007] [LIST OF CITATIONS]

[0008] [PATENT LITERATURE]

[0009] Patent Literature 1: Japanese Unexamined Patent Application Publication No. 2011-29337 SUMMARY

[0010] Patent Literature 1 describes that the electric charge generated in a green photoelectric conversion element is accumulated in an n-type semiconductor region on the wiring layer side (front side or second surface side) of a semiconductor substrate via a conductive plug that penetrates the semiconductor substrate. The conductive plug is essential to smoothly transfer the electric charge from the photoelectric conversion element on the first surface side of the semiconductor substrate to the second surface side of the semiconductor substrate, thereby enhancing characteristics such as conversion efficiency, and there is still room for study on the configuration of the conductive plug.

[0011] Therefore, it is desirable to provide a solid-state imaging element that allows enhancement of characteristics and an electronic apparatus including the solid-state imaging element.

[0012] A first solid-state imaging element according to an embodiment of the present disclosure includes: at least one photoelectric conversion element provided on a first surface side of a semiconductor substrate; a through electrode connected to the at least one photoelectric conversion element and provided between a first surface and a second surface of the semiconductor substrate; and an amplification transistor and a floating diffusion portion provided on the second surface of the semiconductor substrate, wherein the at least one photoelectric conversion element is connected to a gate of the amplification transistor and the floating diffusion portion via the through electrode.

[0013] In the first solid-state imaging element according to the embodiment of the present disclosure, the electric charge generated in the photoelectric conversion element on the first surface side of the semiconductor substrate is transferred to the second surface side of the semiconductor substrate via the through electrode to be accumulated in the floating diffusion portion. The amplification transistor modulates the amount of the electric charge generated in the photoelectric conversion element into a voltage.

[0014] A second solid-state imaging element according to an embodiment of the present disclosure includes: a photoelectric conversion element provided on a first surface side of a semiconductor substrate; a through electrode connected to the photoelectric conversion element and provided between a first surface and a second surface of the semiconductor substrate; a separation groove provided between the through electrode and the semiconductor substrate; and a dielectric layer filling the separation groove and having an insulating property.

[0015] In the second solid-state imaging element according to the embodiment of the present disclosure, the through electrode and the semiconductor substrate are separated from each other by the separation groove and the dielectric layer. Therefore, the capacitance generated between the through electrode and the semiconductor substrate is reduced, thereby improving characteristics such as conversion efficiency.

[0016] A third solid-state imaging element according to an embodiment of the present disclosure includes: a photoelectric conversion element provided on a first surface side of a semiconductor substrate; a through electrode connected to the photoelectric conversion element and provided between a first surface and a second surface of the semiconductor substrate; a separation groove provided between the through electrode and the semiconductor substrate; an outer side dielectric layer covering an outer side surface of the separation groove; an inner side dielectric layer covering an inner side surface of the separation groove; and a gap provided between the outer side dielectric layer and the inner side dielectric layer.

[0017] In the third solid-state imaging element according to the embodiment of the present disclosure, the through electrode and the semiconductor substrate are separated from each other by the separation groove, the outer side dielectric layer, the inner side dielectric layer, and the gap. Therefore, the capacitance generated between the through electrode and the semiconductor substrate is reduced, and thus the characteristics such as conversion efficiency are improved.

[0018] The first electronic device according to the embodiment of the present disclosure is provided with a solid-state imaging element, and the solid-state imaging element includes: at least one photoelectric conversion element provided on a first surface side of a semiconductor substrate; a through electrode connected to the at least one photoelectric conversion element and provided between a first surface and a second surface of the semiconductor substrate; and an amplification transistor and a floating diffusion portion provided on the second surface of the semiconductor substrate, in which the at least one photoelectric conversion element is connected to a gate of the amplification transistor and the floating diffusion portion via the through electrode.

[0019] The second electronic device according to the embodiment of the present disclosure is provided with a solid-state imaging element, and the solid-state imaging element includes: a photoelectric conversion element provided on a first surface side of a semiconductor substrate; a through electrode connected to the photoelectric conversion element and provided between a first surface and a second surface of the semiconductor substrate; a separation groove provided between the through electrode and the semiconductor substrate; and a dielectric layer filling the separation groove and having an insulating property.

[0020] The third electronic device according to the embodiment of the present disclosure is provided with a solid-state imaging element, and the solid-state imaging element includes: a photoelectric conversion element provided on a first surface side of a semiconductor substrate; a through electrode connected to the photoelectric conversion element and provided between a first surface and a second surface of the semiconductor substrate; a separation groove provided between the through electrode and the semiconductor substrate; an outer side dielectric layer covering an outer side surface of the separation groove; an inner side dielectric layer covering an inner side surface of the separation groove; and a gap provided between the outer side dielectric layer and the inner side dielectric layer.

[0021] In the first to third electronic devices according to the respective embodiments of the present disclosure, imaging is performed by the first to third solid-state imaging elements according to the respective embodiments of the present disclosure.

[0022] According to the first solid-state imaging element according to the embodiment of the present disclosure or the first electronic device according to the embodiment of the present disclosure, the photoelectric conversion element is connected to the gate of the amplification transistor and the floating diffusion portion via the through electrode. This makes it possible to smoothly transfer the electric charge generated in the photoelectric conversion element on the first surface side of the semiconductor substrate to the second surface side of the semiconductor substrate via the through electrode, and thus the characteristics are enhanced.

[0023] In the second solid-state imaging element or the second electronic device according to an embodiment of the present disclosure, the through electrode and the semiconductor substrate are separated from each other by a separation trench and a dielectric layer. This allows for a reduction in the capacitance generated between the through electrode and the semiconductor substrate, thereby enhancing characteristics such as conversion efficiency.

[0024] According to the third solid-state imaging element or the third electronic device according to the present disclosure, the through electrode and the semiconductor substrate are separated from each other by a separation trench, an outer dielectric layer, an inner dielectric layer, and a gap. This allows for a reduction in the capacitance generated between the through electrode and the semiconductor substrate, thereby enhancing characteristics such as conversion efficiency. Attached Figure Description

[0025] Figure 1 This is a cross-sectional view of the solid-state imaging element according to the first embodiment of this disclosure.

[0026] Figure 2 It has four configurations. Figure 1 The diagram shows a planar representation of the solid-state imaging element.

[0027] Figure 3 yes Figure 1 The cross-sectional view of the manufacturing method of the solid-state imaging element shown is arranged in the order of steps.

[0028] Figure 4 It continues Figure 3 A cross-sectional view of the process.

[0029] Figure 5 It continues Figure 4 A cross-sectional view of the process.

[0030] Figure 6 It continues Figure 5 A cross-sectional view of the process.

[0031] Figure 7 It continues Figure 6 A cross-sectional view of the process.

[0032] Figure 8 It continues Figure 7 A cross-sectional view of the process.

[0033] Figure 9 This is a cross-sectional view of the configuration of a solid-state imaging element according to the second embodiment of this disclosure.

[0034] Figure 10 yes Figure 9 The cross-sectional view of the manufacturing method of the solid-state imaging element shown is arranged in the order of steps.

[0035] Figure 11 It continues Figure 10is a cross-sectional view of the process.

[0036] Figure 12 is then Figure 11 is a cross-sectional view of the process.

[0037] Figure 13 is then Figure 12 is a cross-sectional view of the process.

[0038] Figure 14 is then Figure 13 is a cross-sectional view of the process.

[0039] Figure 15 is then Figure 14 is a cross-sectional view of the process.

[0040] Figure 16 is then Figure 15 is a cross-sectional view of the process.

[0041] Figure 17 is then Figure 16 is a cross-sectional view of the process.

[0042] Figure 18 is then Figure 17 is a cross-sectional view of the process.

[0043] Figure 19 is a cross-sectional view of the configuration of the solid-state imaging device according to Modification 1.

[0044] Figure 20 is a cross-sectional view of the configuration of the solid-state imaging device according to the third embodiment of the present disclosure.

[0045] Figure 21 is a cross-sectional view of the process of the manufacturing method of the solid-state imaging device shown in Figure 20

[0046] is then Figure 22 is a cross-sectional view of the process. Figure 21

[0047] is a cross-sectional view of the configuration of the solid-state imaging device according to the fourth embodiment of the present disclosure. Figure 23

[0048] is a cross-sectional view of the process of the manufacturing method of the solid-state imaging device shown in Figure 24 Figure 20 is a cross-sectional view of the configuration of the solid-state imaging device according to Modification 2.

[0049] Figure 25 is a functional block diagram of the solid-state imaging unit.

[0050] Figure 26

[0051] ​​Figure 27 is a functional block diagram of an electronic device according to an application example. DETAILED DESCRIPTION

[0052] Hereinafter, some embodiments of the present disclosure will be explained in detail with reference to the drawings. Note that the explanation will be made in the following order.

[0053] 1. First Embodiment (Solid-state Imaging Element; Example in which Through Electrode is Composed of Semiconductor and Separation Groove at Periphery of Through Electrode has Gap)

[0054] 2. Second Embodiment (Solid-state Imaging Element; Example in which Through Electrode is Composed of Metal and Separation Groove at Periphery of Through Electrode has Gap)

[0055] 3. Modified Example 1 (Example in which Thermal Oxidation Film is Provided on Outer Side Surface of Separation Groove)

[0056] 4. Third Embodiment (Solid-state Imaging Element; Example in which Through Electrode is Composed of Semiconductor and Separation Groove at Periphery of Through Electrode is Filled with Dielectric Layer)

[0057] 5. Fourth Embodiment (Solid-state Imaging Element; Example in which Through Electrode is Composed of Metal and Separation Groove at Periphery of Through Electrode is Filled with Dielectric Layer)

[0058] 6. Modified Example 2 (Example in which Thermal Oxidation Film is Provided on Outer Side Surface of Separation Groove)

[0059] 7. Overall Configuration Example of Solid-state Imaging Unit

[0060] 8. Application Example (Example of Electronic Device)

[0061] (First Embodiment)

[0062] Figure 1 A cross-sectional configuration of a solid-state imaging element 10 according to the first embodiment of the present disclosure is shown. The solid-state imaging element 10 can constitute, for example, a pixel portion as an imaging pixel region in a solid-state imaging unit (to be described later) such as a CMOS image sensor and the like in an electronic device such as a digital camera and a video camera and the like.

[0063] The solid-state imaging element 10 can be, for example, a so-called longitudinal split type in which one photoelectric conversion element 20 and two photodiodes PD1 and PD2 are stacked along a thickness direction of a semiconductor substrate 30. The photoelectric conversion element 20 is provided on the first face (back face) 30A side of the semiconductor substrate 30. The photodiodes PD1 and PD2 are provided within the semiconductor substrate 30 to be stacked along the thickness direction of the semiconductor substrate 30.

[0064] The photoelectric conversion element 20 and the photodiodes PD1 and PD2 selectively detect light of mutually different wavelength ranges to photoelectrically convert the light thus detected. More specifically, the photoelectric conversion element 20 obtains a color signal of green (G). The photodiodes PD1 and PD2 obtain color signals of blue (B) and red (R), respectively, by virtue of differences in absorption coefficients. This allows the solid-state imaging device 10 to obtain a plurality of color signals in one pixel without using color filters.

[0065] Note that, in the present embodiment, a case in which an electron of an electron-hole pair generated by photoelectric conversion is read out as signal charge (a case in which an N-type semiconductor region serves as a photoelectric conversion layer) is described. Further, in the drawings, "+" after "P" and "N" indicates that the P-type or N-type impurity concentration is high, and "++" indicates that the P-type or N-type impurity concentration is higher than that in "+".

[0066] For example, the floating diffusion portions (floating diffusion portion layers) FD1, FD2, and FD3, the vertical transistor (transfer transistor) Tr1, the transfer transistor Tr2, the amplification transistor (modulator) AMP, the reset transistor RST, and the multilayer wiring 40 can be provided on the second face (front face) 30B of the semiconductor substrate 30. For example, the multilayer wiring 40 can have a configuration in which the wiring layers 41, 42, and 43 are laminated in the insulating film 44.

[0067] Note that, in the drawings, the first face 30A side and the second face 30B side of the semiconductor substrate 30 are referred to as the light incident side S1 and the wiring layer side S2, respectively.

[0068] For example, the photoelectric conversion element 20 can have a configuration in which the lower transparent electrode 21, the photoelectric conversion film 22, and the upper transparent electrode 23 are laminated in this order from the first face 30A side of the semiconductor substrate 30. The transparent electrodes 21 are separated for each photoelectric conversion element 20. The photoelectric conversion film 22 and the transparent electrode 23 are provided as a continuous layer shared by a plurality of photoelectric conversion elements 20. For example, the film 24 having a fixed charge, the dielectric layer 25 having insulating properties, and the interlayer insulating film 26 can be provided between the first face 30A of the semiconductor substrate 30 and the transparent electrode 21. The protective film 27 is provided on the transparent electrode 23. An optical member such as a planarization film and an on-chip lens (both not shown) are provided on the protective film 27.

[0069] A through electrode 50 is disposed between the first surface 30A and the second surface 30B of the semiconductor substrate 30. The photoelectric conversion element 20 is connected to the gate Gamp and the floating diffuser FD3 of the amplifying transistor AMP via the through electrode 50. This allows the solid-state imaging element 10 to smoothly transfer the charge generated in the photoelectric conversion element 20 on the first surface 30A side of the semiconductor substrate 30 to the second surface 30B side of the semiconductor substrate 30 via the through electrode 50, thereby enhancing its performance.

[0070] The through-electrode 50 functions as a connector between the photoelectric conversion element 20 and the gate Gamp of the amplifying transistor AMP, and between the photoelectric conversion element 20 and the floating diffuser FD3, and also acts as a transport path for the charge (here, electrons) generated in the photoelectric conversion element 20. For example, the lower end of the through-electrode 50 can be connected to the connection portion 41A in the wiring layer 41 of the multilayer wiring 40 via the lower first contact 51. The connection portion 41A and the gate Gamp of the amplifying transistor AMP are connected to each other via the lower second contact 52. The connection portion 41A and the floating diffuser FD3 are connected to each other via the lower third contact 53. For example, the upper end of the through-electrode 50 can be connected to the lower transparent electrode 21 via the upper contact 54.

[0071] Figure 2 Several of these are shown as seen from the second surface 30B side of the semiconductor substrate 30 (e.g., Figure 2 The example shown is a planar configuration of a solid-state imaging element 10 arranged in two rows and two columns, with four photoelectric conversion elements 20 in the middle. It is preferable to provide a through electrode 50 for each of the multiple photoelectric conversion elements 20. In other words, while the lower transparent electrode 21 of the photoelectric conversion elements 20 is separated for each of the multiple photoelectric conversion elements 20, a through electrode 50 is also provided for each of the multiple photoelectric conversion elements 20.

[0072] like Figure 1 and Figure 2 As shown, the reset gate Grst of the reset transistor RST can preferably be located adjacent to the floating diffuser FD3. This allows the charge accumulated in the floating diffuser FD3 to be reset via the reset transistor RST.

[0073] It should be pointed out that, Figure 2 Only the amplifying transistor AMP and the reset transistor RST, which handle the charge from the photoelectric conversion element 20, are shown. The transfer transistors Tr1 and Tr2, associated with photodiodes PD1 and PD2, are not shown. Figure 2 As shown, but appropriately placed in unoccupied areas.

[0074] Figure 1The through electrode 50 shown in FIG. 1 penetrates the semiconductor substrate 30, and is also separated from the semiconductor substrate 30 by the separation groove 60. For example, the through electrode 50 can be composed of the same semiconductor as the semiconductor of the semiconductor substrate 30, such as silicon (Si), and can preferably have a resistance value reduced by doping N-type or P-type impurities (for example, P+). Figure 1 Furthermore, a high-concentration impurity region (for example, P+) can be preferably provided in the upper end and the lower end of the through electrode 50, so as to further reduce the connection resistance with the upper contact 54 and the connection resistance with the lower first contact 51. Figure 1

[0075] As shown in FIG. 1, the outer side surface 61, the inner side surface 62, and the bottom surface 63 of the separation groove 60 can be covered with a dielectric layer 25 having insulating properties. For example, the dielectric layer 25 can include an outer side dielectric layer 25A covering the outer side surface 61 of the separation groove 60, and an inner side dielectric layer 25B covering the inner side surface 62 of the separation groove 60. The outer side dielectric layer 25A and the inner side dielectric layer 25B can be preferably separated by a gap 70. In other words, the separation groove 60 can have a ring shape or a circular shape, and the gap 70 can have a ring shape or a circular shape concentric with the separation groove 60. This makes it possible to reduce the capacitance generated between the through electrode 50 and the semiconductor substrate 30, thereby improving the conversion efficiency and suppressing the delay (afterimage). Figure 1 The following describes this. As described above, the through electrode 50 is composed of a conductive material such as P+ silicon, and the dielectric layer 25 is provided between the through electrode 50 and the semiconductor substrate 30. Since the through electrode 50 penetrates the semiconductor substrate 30 and is connected to the amplification transistor AMP and the floating diffusion FD3, it can be desirable to reduce the capacitance generated between the through electrode 50 and the semiconductor substrate 30. The following three measures are considered to reduce the capacitance. The first measure is to reduce the area of the side wall of the through electrode 50. The second measure is to increase the distance d between the through electrode 50 and the semiconductor substrate 30. The third measure is to reduce the dielectric constant of the insulator between the through electrode 50 and the semiconductor substrate 30.

[0076] The first measure of reducing the area of the side wall of the through electrode 50 allows the thickness of the semiconductor substrate 30 to be reduced or the diameter of the through electrode 50 to be reduced. However, this can cause the area of the photodiodes PD1 and PD2 to be reduced, or the difficulty of the formation process of the semiconductor substrate 30 to be increased. The second measure of increasing the distance d between the through electrode 50 and the semiconductor substrate 30 is an easier measure, but causes the increase in the element area.

[0077]

[0078] ​​In the present embodiment, a gap 70 is provided in the separation groove 60 to take the above-described third measure, i.e., to reduce the dielectric constant of the insulator between the through electrode 50 and the semiconductor substrate 30. For example, although there are gases such as hydrogen and nitrogen in the gap 70, the dielectric constant of the gases can be lower than that of a solid medium such as a TEOS (tetraethyl orthosilicate) film, and can be close to that of a vacuum. This makes it possible to significantly reduce the capacitance between the through electrode 50 and the semiconductor substrate 30.

[0079] Note that the size variation of the gap 70 in the solid-state imaging device 10 or in the wafer can preferably be as small as possible, and can for example preferably be within plus or minus 10%. The reason for this is that the capacitance between the through electrode 50 and the semiconductor substrate 30 is sensitive to the size of the gap 70.

[0080] Further, in the solid-state imaging device 10, as shown in Figure 1 , it can be preferable to provide an impurity region (P+ in the present embodiment) of the same conductivity type (N-type or P-type) as that of the through electrode 50 on the outer side surface 61 of the separation groove 60 in the semiconductor substrate 30. Figure 1 In addition, it can be preferable to provide the film 24 having a fixed charge on the outer side surface 61, the inner side surface 62, and the bottom surface 63 of the separation groove 60 and the first surface 30A of the semiconductor substrate 30. More specifically, for example, it can be preferable to provide a P-type impurity region (P+ in the present embodiment) on the outer side surface 61 of the separation groove 60 in the semiconductor substrate 30 and a film having a negative fixed charge as the film 24 having a fixed charge. This allows the dark current to be reduced. Figure 1

[0081] The following is described. In the longitudinal split-type solid-state imaging device 10, the through electrode 50 and the separation groove 60 are provided simultaneously in the vicinity of the photodiodes PD1 and PD2 in the semiconductor substrate 30 for each photoelectric conversion element 20. The surfaces of the through electrode 50 and the separation groove 60 are different from the surface of the semiconductor substrate 30, and are processed by dry etching or other processing, which generally has a large defect level. This can increase the dark current and the white spot of the photodiodes PD1 and PD2 adjacent to the through electrode 50 and the separation groove 60.

[0082] Here, in order to reduce the dark current or the white spot, a P-type impurity region (P+ in the present embodiment) is provided on the outer side surface 61 of the separation groove 60 in the semiconductor substrate 30. Figure 1 ​The film 24 having a fixed charge is a film having a positive fixed charge (P+), and is further provided with a film having a negative fixed charge as a film 24 having a fixed charge. A hole accumulation layer is formed on the outer side surface 61 of the separation groove 60 by an electric field induced by the film 24 having a negative fixed charge. The hole accumulation layer suppresses the generation of electrons from the outer side surface 61 of the separation groove 60. Furthermore, even if a charge (electron) is generated from the outer side surface 61 of the separation groove 60, the electron thus generated disappears in the hole accumulation layer during electron diffusion, and thus the dark current is reduced.

[0083] Hereinafter, the configuration and materials of each component will be described.

[0084] The photoelectric conversion element 20 can be configured to photoelectrically convert green light corresponding to a part or all of the wavelength range of 495 nm to 570 nm. For example, the transparent electrodes 21 and 23 can include a conductive film having light transmittance, and can be configured of ITO (indium tin oxide), for example. The photoelectric conversion film 22 is an organic film configured of an organic photoelectric conversion material that photoelectrically converts light of a selective wavelength range while allowing light of other wavelength ranges to pass therethrough. For example, the photoelectric conversion film 22 can be configured of an organic photoelectric conversion material containing rhodamine-based dye, merocyanine-based dye, quinacridone, or any other dye. Note that the photoelectric conversion element 20 can be provided with other layers not shown such as a base layer, an electron-blocking layer, and a buffer layer, in addition to the transparent electrodes 21 and 23 and the photoelectric conversion film 22.

[0085] The film 24 having a fixed charge can be a film having a positive fixed charge or a film having a negative fixed charge. Non-limiting examples of the material of the film having a negative fixed charge can include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide. Furthermore, non-limiting examples of the material other than the above-described materials can include lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, aluminum nitride film, hafnium oxynitride film, and aluminum oxynitride film.

[0086] The film 24 having a fixed charge can have a configuration in which two or more film layers are stacked. For example, in the case of a film having a negative fixed charge, such a configuration makes it possible to further enhance the function as a hole accumulation layer.

[0087] Examples of the material of the dielectric layer 25 can include, but are not particularly limited to, a silicon oxide film, TEOS, a silicon nitride film, and a silicon oxynitride film.

[0088] For example, the interlayer insulating film 26 can be configured of a silicon oxide film. For example, the protective film 27 can be configured of a silicon nitride film.

[0089] For example, the semiconductor substrate 30 can be composed of an n-type silicon (Si) substrate, and can have a p-well 31 in a predetermined region. The above-described vertical transistor Trl, transfer transistor Tr2, amplification transistor AMP, reset transistor RST, and other components are provided on the second surface 30B of the p-well 31. Further, for example, a peripheral circuit (not shown) including, but not limited to, a logic circuit is provided on the periphery of the semiconductor substrate 30.

[0090] The photodiodes PDl and PD2 each have a PN junction in a predetermined region of the semiconductor substrate 30. The photodiodes PDl and PD2 allow light to be dispersed toward the longitudinal direction using a difference in wavelength of light that is absorbed by a light incidence depth of the silicon substrate. The photodiode PDl selectively detects blue light to accumulate signal charges corresponding to blue, and is provided at a depth that allows the blue light to be efficiently photoelectrically converted. The photodiode PD2 selectively detects red light to accumulate signal charges corresponding to red, and is provided at a depth that allows the red light to be efficiently photoelectrically converted. Note that blue (B) is a color corresponding to a wavelength range of, for example, 450 nm to 495 nm, and red (R) is a color corresponding to a wavelength range of, for example, 620 nm to 750 nm. Each of the photodiodes PDl and PD2 need only be able to detect light in a part or all of the respective wavelength ranges.

[0091] For example, the photodiode PDl can include a P+ region that functions as a hole accumulation layer and an N region that functions as an electron accumulation layer. For example, the photodiode PD2 can include a P+ region that functions as a hole accumulation layer and an N region that functions as an electron accumulation layer (i.e., can have a P-N-P layer stack). The N region of the photodiode PDl is connected to the vertical transistor Trl. The P+ region of the photodiode PDl is curved along the vertical transistor Trl to be connected to the P+ region of the photodiode PD2.

[0092] The vertical transistor Trl is a transfer transistor that transfers signal charges corresponding to blue (electrons in the present embodiment) generated and accumulated in the photodiode PDl to the floating diffusion FDl. Since the photodiode PDl is formed at a position deeper from the second surface 30B of the semiconductor substrate 30, the transfer transistor of the photodiode PDl can preferably be composed of the vertical transistor Trl.

[0093] The transfer transistor Tr2 transfers signal charges corresponding to red (electrons in the present embodiment) generated and accumulated in the photodiode PD2 to the floating diffusion FD2, and can be composed of, for example, a MOS transistor.

[0094] The amplification transistor AMP is a modulator that modulates the amount of charge generated in the photoelectric conversion element into a voltage, and can be composed of, for example, a MOS transistor.

[0095] The reset transistor RST is configured to reset the charge transferred from the photoelectric conversion element 20 to the floating diffusion section FD3, and can be, for example, a MOS transistor.

[0096] For example, the lower first to third contacts 51 to 53 and the upper contact 54 can be made of doped silicon materials such as PDAS (phosphorus-doped amorphous silicon) or metal materials such as aluminum, tungsten, titanium, cobalt, hafnium and tantalum.

[0097] For example, the solid-state imaging element 10 can be manufactured as follows.

[0098] Figures 3 to 8 The manufacturing method of the solid-state imaging element 10 is shown in the step sequence. First, as... Figure 3 As shown, for example, a p-well 31 of a first conductivity type can be formed within the semiconductor substrate 30, and photodiodes PD1 and PD2 of a second conductivity type (e.g., N-type) can be formed within the p-well 31. A P+ region can be formed near the first surface 30A of the semiconductor substrate 30.

[0099] Similarly, Figure 3 As shown, impurity regions (P+ regions) can be formed in the region where the through electrode 50 and the separation trench 60 will be formed, extending from the first surface 30A through the second surface 30B of the semiconductor substrate 30. Furthermore, high-concentration impurity regions (P++ regions) can be formed in the regions at the upper and lower ends where the through electrode 50 will be formed.

[0100] Similarly, Figure 3 As shown, N+ regions that will serve as floating diffusion portions FD1 to FD3 can be formed along the second surface 30B of the semiconductor substrate 30. Subsequently, a gate insulating film 32 and a gate wiring 33 including the gates of a vertical transistor Tr1, a transmission transistor Tr2, an amplification transistor AMP, and a reset transistor RST can be formed on the second surface 30B of the semiconductor substrate 30. Therefore, the vertical transistor Tr1, the transmission transistor Tr2, the amplification transistor AMP, and the reset transistor RST can be formed. Furthermore, lower first to third contacts 51 to 53 and a multilayer wiring 40 including wiring layers 41 to 43 containing a connection portion 41A and an insulating film 44 can be formed on the second surface 30B of the semiconductor substrate 30.

[0101] An example of a substrate used as the semiconductor substrate 30 could be an SOI (silicon-on-insulator) substrate in which a semiconductor substrate 30, a buried oxide film (not shown), and a holding substrate (not shown) are stacked. Figure 3 The embedded oxide film and support substrate shown can be bonded to the first surface 30A of the semiconductor substrate 30. Annealing can be performed after ion implantation.

[0102] Subsequently, as Figure 4 As shown, a support substrate (not shown) or any other semiconductor substrate can be bonded to the second surface 30B (multilayer wiring 40) side of the semiconductor substrate 30, and the semiconductor substrate 30 can be flipped vertically. Next, the semiconductor substrate 30 can be separated from the buried oxide film and support substrate of the SOI substrate to expose the first surface 30A of the semiconductor substrate 30. The above process can be performed using techniques typically employed in CMOS processes, such as ion implantation and CVD (chemical vapor deposition).

[0103] After that, as Figure 5 As shown, for example, the semiconductor substrate 30 can be processed from the first surface 30A side by dry etching to form a ring-shaped or circular separation groove 60.

[0104] As by Figure 5 As indicated by arrow D60A, the depth of the separation trench 60 can preferably be deep enough to penetrate from the first surface 30A of the semiconductor substrate 30 to the second surface 30B and reach the gate insulating film 32. Furthermore, to further improve the insulation effect of the bottom surface 63 of the separation trench 60, as shown by... Figure 5 As indicated by arrow D60B, the separation groove 60 can preferably reach the insulating film 44 of the multilayer wiring 40 through the semiconductor substrate 30 and the gate insulating film 32. Figure 5 The separation trench 60 is shown to penetrate the semiconductor substrate 30 and the gate insulating film 32.

[0105] After the separation tank 60 is formed, as Figure 6 As shown, for example, a film 24 with a negative fixed charge can be formed on the outer surface 61, inner surface 62, and bottom surface 63 of the separation tank 60, as well as on the first surface 30A of the semiconductor substrate 30. Two or more films with a negative fixed charge can be stacked as the film 24. This allows for further enhancement of its function as a hole accumulation layer.

[0106] After forming a film 24 with a negative fixed charge, as Figure 7 As shown, a dielectric layer 25 comprising an outer dielectric layer 25A and an inner dielectric layer 25B can be formed. In this case, the film thickness and film formation conditions of the dielectric layer 25 can be suitably adjusted to form a gap 70 in the separation trench 60 between the outer dielectric layer 25A and the inner dielectric layer 25B.

[0107] After the dielectric layer 25 and the gap 70 are formed, as Figure 8 As shown, an interlayer insulating film 26 and an upper contact 54 can be formed, and the upper contact 54 can be connected to the upper end of the through electrode 50. Thereafter, as... Figure 1As shown, the lower transparent electrode 21, the photoelectric conversion film 22, the upper transparent electrode 23, and the protective film 27 can be formed. Finally, optical components such as a planarization film and an on-chip lens (not shown) can be provided. In this way, the solid-state imaging device 10 shown in FIG. 1 is completed. Figure 1 The solid-state imaging device 10 shown in FIG. 1 is completed.

[0108] In the solid-state imaging device 10, when light is incident into the photoelectric conversion element 20 via the on-chip lens (not shown), the light passes through the photoelectric conversion element 20 and the photodiodes PD1 and PD2 in this order to be photoelectrically converted into green, blue, and red light, respectively, in this passing process. Hereinafter, the obtaining action of signals of various colors will be described.

[0109] (Green signal obtained by the photoelectric conversion element 20)

[0110] Among the light that has passed through the photoelectric conversion element 20, the green light is first selectively detected (absorbed) and photoelectrically converted by the photoelectric conversion element 20.

[0111] The photoelectric conversion element 20 is connected to the gate Gamp of the amplification transistor AMP and the floating diffusion FD3 via the through electrode 50. Therefore, the electron of the electron-hole pair generated in the photoelectric conversion element 20 is extracted from the transparent electrode 21 side to be transmitted to the second surface 30B side of the semiconductor substrate 30 via the through electrode 50, and then accumulated in the floating diffusion FD3. At the same time, the amount of charge generated in the photoelectric conversion element 20 is modulated into a voltage by the amplification transistor AMP.

[0112] Further, the reset gate Grst of the reset transistor RST is provided adjacent to the diffusion FD3. Therefore, the charge accumulated in the floating diffusion FD3 is reset by the reset transistor RST.

[0113] Here, the photoelectric conversion element 20 is connected to not only the amplification transistor AMP but also the floating diffusion FD3 via the through electrode 50, which makes it easy to reset the charge accumulated in the floating diffusion FD3 by the reset transistor RST.

[0114] In the case where the through electrode 50 and the floating diffusion FD3 are not connected to each other, it is difficult to reset the charge accumulated in the floating diffusion FD3, and thus a large voltage is applied to attract the charge to the transparent electrode 23 side. This can cause damage to the photoelectric conversion film 22. Further, since the configuration that allows resetting in a short time can cause an increase in dark noise, resulting in a trade-off effect, such a configuration is difficult.

[0115] (Blue signal and red signal obtained by the photodiodes PD1 and PD2)

[0116] Next, among the light that has passed through the photoelectric conversion element 20, the blue light and the red light are sequentially absorbed by the photodiodes PD1 and PD2 and photoelectrically converted. In the photodiode PD1, electrons corresponding to the incident blue light are accumulated in the N region of the photodiode PD1, and the thus-accumulated electrons are transferred to the floating diffusion FD1 through the vertical transistor Tr1. Similarly, in the photodiode PD2, electrons corresponding to the incident red light are accumulated in the N region of the photodiode PD2, and the thus-accumulated electrons are transferred to the floating diffusion FD2 through the vertical transistor Tr2.

[0117] Therefore, in the present embodiment, since the photoelectric conversion element 20 is connected to the gate Gamp of the amplification transistor AMP and the floating diffusion layer FD3 via the through electrode 50, the charges generated in the photoelectric conversion element 20 on the first surface 30A side of the semiconductor substrate 30 can be smoothly transferred to the second surface 30B side of the semiconductor substrate 30 via the through electrode 50, thereby enhancing the characteristics.

[0118] Further, since the through electrode 50 and the semiconductor substrate 30 are separated from each other by the separation groove 60, the outer dielectric layer 25A, the inner dielectric layer 25B, and the gap 70, the capacitance generated between the through electrode 50 and the semiconductor substrate 30 can be reduced, thereby further improving the characteristics such as the conversion efficiency.

[0119] In addition, since the reset gate Grst of the reset transistor RST is disposed adjacent to the floating diffusion FD3, the charges accumulated in the floating diffusion FD3 can be easily reset by the reset transistor RST. This makes it possible to reduce the damage to the photoelectric conversion film 22, thereby improving the reliability. Further, this makes it possible to reset the charges in a short time without increasing the dark-time noise.

[0120] (Second Embodiment)

[0121] Figure 9 A cross-sectional configuration of a solid-state imaging element 10A according to a second embodiment of the present disclosure is shown. The solid-state imaging element 10A can include a through electrode 50 composed of a metal or a conductive material, and can have similar configurations, functions, and effects to those of the above-described first embodiment except for this. Therefore, the description is made in a manner that similar components are denoted by similar reference numerals.

[0122] As with the first embodiment, the solid-state imaging device 10A can be, for example, a so-called longitudinal light-splitting type in which one photoelectric conversion element 20 and two photodiodes PD1 and PD2 are stacked along the thickness direction of the semiconductor substrate 30. The photoelectric conversion element 20 is provided on the first face (back face) 30A side of the semiconductor substrate 30. The photodiodes PD1 and PD2 are provided within the semiconductor substrate 30 so as to be stacked along the thickness direction of the semiconductor substrate 30.

[0123] The photoelectric conversion element 20, the photodiodes PD1 and PD2, and the semiconductor substrate 30 can have similar configurations as the first embodiment. The floating diffusion portions FD1 to FD3, the vertical transistor Tr1, the transfer transistor Tr2, the amplification transistor AMP, the reset transistor RST, and the multilayer wiring 40 can have similar configurations as the first embodiment.

[0124] As with the first embodiment, the through electrode 50 is provided between the first face 30A and the second face 30B of the semiconductor substrate 30. The photoelectric conversion element 20 is connected to the gate Gamp of the amplification transistor AMP and the floating diffusion portion FD3 via the through electrode 50. As with the first embodiment, this allows the solid-state imaging device 10A to smoothly transfer the charge generated in the photoelectric conversion element 20 on the first face 30A side of the semiconductor substrate 30 to the second face 30B side of the semiconductor substrate 30 via the through electrode 50, thereby enhancing the characteristics.

[0125] As with the first embodiment, the floating diffusion portion FD3 is provided in the vicinity of the through electrode 50. It can be preferable to provide the reset gate Grst of the reset transistor RST adjacent to the floating diffusion portion FD3. This makes it possible to reset the charge accumulated in the floating diffusion portion FD3 by the reset transistor RST.

[0126] In the present embodiment, as described above, the through electrode 50 can be composed of a metal or a conductive material. This makes it possible to further reduce the resistance value of the through electrode 50 and further reduce the connection resistance between the through electrode 50 and the lower first to third contacts 51 to 53 and between the through electrode 50 and the upper contact 54. This makes it possible to more smoothly transfer the charge generated in the photoelectric conversion element 20 on the first face 30A side of the semiconductor substrate 30 to the second face 30B side of the semiconductor substrate 30 via the through electrode 50, thereby further enhancing the characteristics. Non-limiting examples of the metal or the conductive material that forms the through electrode 50 can include aluminum, tungsten, titanium, cobalt, hafnium, and tantalum.

[0127] As with the first embodiment, it can be preferable to provide the separation groove 60 between the through electrode 50 and the semiconductor substrate 30. The outer side surface 61, the inner side surface 62, and the bottom surface 63 of the separation groove 60 can be preferably covered with the dielectric layer 25 having insulating properties. The outer side dielectric layer 25A covering the outer side surface 61 of the separation groove 60 and the inner side dielectric layer 25B covering the inner side surface 62 of the separation groove 60 can be preferably spaced apart by the gap 70. This makes it possible to reduce the capacitance generated between the through electrode 50 and the semiconductor substrate 30, thereby improving the conversion efficiency and suppressing the delay (afterimage).

[0128] Further, in the solid-state imaging device 10A, as with the first embodiment, it can be preferable to provide an impurity region (P+ in the present case) on the outer side surface 61 of the separation groove 60 in the semiconductor substrate 30. In addition, it can be preferable to provide the film 24 having a fixed charge on the outer side surface 61, the inner side surface 62, and the bottom surface 63 of the separation groove 60 and the first surface 30A of the semiconductor substrate 30. More specifically, for example, it can be preferable to provide a P-type impurity region (P+ in the present case) on the outer side surface 61 of the separation groove 60 in the semiconductor substrate 30 and the film having a negative fixed charge as the film 24 having a fixed charge. This allows the dark current to be reduced. Figure 9 Figure 9

[0129] As with the first embodiment, the film 24 having a fixed charge can be a film having a positive fixed charge or a film having a negative fixed charge. Non-limiting examples of the material of the film having a negative fixed charge include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, and titanium oxide. Further, non-limiting examples of the material other than the above-described materials can include lanthanum oxide, praseodymium oxide, cerium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, thulium oxide, ytterbium oxide, lutetium oxide, yttrium oxide, aluminum nitride film, hafnium oxynitride film, and aluminum oxynitride film.

[0130] As with the first embodiment, the film 24 having a fixed charge can have a configuration in which two or more film layers are stacked. For example, in the case of the film having a negative fixed charge, such a configuration makes it possible to further enhance the function as a hole accumulation layer.

[0131] As with the first embodiment, examples of the material of the dielectric layer 25 can include, but are not particularly limited to, a silicon oxide film, TEOS, a silicon nitride film, and a silicon oxynitride film.

[0132] As with the first embodiment, for example, the lower first to third contacts 51 to 53 and the upper contact 54 can be configured of a doped silicon material such as PDAS (phosphorus-doped amorphous silicon) or a metal material such as aluminum, tungsten, titanium, cobalt, hafnium, and tantalum.

[0133] ​​For example, the solid-state imaging element 10A can be manufactured as follows.

[0134] Figures 10 to 18 The manufacturing method of the solid-state imaging element 10A is shown in the step sequence. First, as in the first embodiment, by... Figure 3 The process shown, for example, involves forming a p-well 31 of a first conductivity type within the semiconductor substrate 30, and forming photodiodes PD1 and PD2 of a second conductivity type (e.g., N-type) within the p-well 31. A P+ region can be formed near the first surface 30A of the semiconductor substrate 30.

[0135] Furthermore, similar to the first implementation scheme, it is also through... Figure 3 The process shown allows for the formation of impurity regions (P+ regions) in the area where the through electrode 50 and the separation trench 60 will be formed, extending from the first surface 30A through the second surface 30B of the semiconductor substrate 30. It should be noted that, in this embodiment, since the through electrode 50 is made of metal or a conductive material, high-concentration impurity regions (P++ regions) at the upper and lower ends of the through electrode 50 are unnecessary.

[0136] Similar to the first implementation scheme, it is also through Figure 3 The process shown involves forming N+ regions, which will serve as floating diffusion portions FD1 to FD3, along the second surface 30B of the semiconductor substrate 30. Subsequently, a gate insulating film 32 and gate wiring 33, including the gates of a vertical transistor Tr1, a transmission transistor Tr2, an amplification transistor AMP, and a reset transistor RST, can be formed on the second surface 30B of the semiconductor substrate 30. Therefore, the vertical transistor Tr1, the transmission transistor Tr2, the amplification transistor AMP, and the reset transistor RST can be formed. Furthermore, lower first to third contacts 51 to 53 and a multilayer wiring 40, including wiring layers 41 to 43 containing connection portions 41A and an insulating film 44, can be formed on the second surface 30B of the semiconductor substrate 30.

[0137] Similar to the first embodiment, an example of a substrate used as the semiconductor substrate 30 can be an SOI substrate. Annealing can be performed after ion implantation.

[0138] Subsequently, as Figure 10 As shown, a support substrate (not shown) or any other semiconductor substrate can be bonded to the second surface 30B (multilayer wiring 40) of the semiconductor substrate 30, and the semiconductor substrate 30 can be flipped vertically. Next, the semiconductor substrate 30 can be separated from the buried oxide film of the SOI substrate and the support substrate to expose the first surface 30A of the semiconductor substrate 30. The above process can be performed using techniques commonly used in CMOS processes, such as ion implantation and CVD (chemical vapor deposition).

[0139] Thereafter, as shown in Figure 11 for example, a separation groove 60 of a ring shape or a circular shape that penetrates the semiconductor substrate 30 can be formed by dry etching from the first surface 30A side of the semiconductor substrate 30.

[0140] After the separation groove 60 is formed, as shown in Figure 12 , an insulating film 80 can be formed on the outer side surface 61 and the bottom surface 63 of the separation groove 60 and the first surface 30A of the semiconductor substrate 30. As the material of the insulating film 80, TEOS or a SiO film, a SiN film, or any other film formed by an ALD method can be used.

[0141] Subsequently, as shown in Figure 13 , the insulating film 80 can be recessed by dry etching or any other method.

[0142] Thereafter, as shown in Figure 14 , a metal material film 50A can be embedded in the separation groove 60.

[0143] After the metal material film 50A is embedded, as shown in Figure 15 , the metal material film 50A can be recessed or planarized by dry etching or CMP (chemical mechanical polishing) to form a through electrode 50. At this time, the thickness of the insulating film 80 near the entrance of the separation groove 60 can be reduced by etch-back; therefore, the metal material film 50A can preferably be recessed to a depth that ensures the thickness of the insulating film 80. This makes it possible to prevent short-circuiting between the through electrode 50 and the semiconductor substrate 30.

[0144] After the through electrode 50 is formed, as shown in Figure 16 , the insulating film 80 can be removed.

[0145] After the insulating film 80 is removed, as shown in Figure 17 , for example, a film 24 having a negative fixed charge can be formed on the outer side surface 61, the inner side surface 62, and the bottom surface 63 of the separation groove 60 and the first surface 30A of the semiconductor substrate 30. As the film 24 having a negative fixed charge, two or more films can be laminated. This makes it possible to further enhance the function as a hole accumulation layer.

[0146] After the film 24 having a negative fixed charge is formed, as also shown in Figure 17 , a dielectric layer 25 can be formed. In this case, the film thickness and film formation conditions of the dielectric layer 25 can be appropriately adjusted to form a gap 70 in the separation groove 60. Note that the surface of the dielectric layer 25 can be planarized by CMP or any other method.

[0147] After the dielectric layer 25 and the gap 70 are formed, as shown inFigure 18 As shown, the interlayer insulating film 26 and the upper contact 54 can be formed, and the upper contact 54 can be connected with the upper end of the through electrode 50. Thereafter, as shown Figure 9 As shown, the lower transparent electrode 21, the photoelectric conversion film 22, the upper transparent electrode 23, and the protective film 27 can be formed. Finally, optical elements such as a planarization film and an on-chip lens (not shown) can be provided. In this way, the solid-state imaging device 10A shown in the first embodiment is completed. Figure 9 As shown, the interlayer insulating film 26 and the upper contact 54 can be formed, and the upper contact 54 can be connected with the upper end of the through electrode 50. Thereafter, as shown

[0148] In the solid-state imaging device 10A, when light is incident into the photoelectric conversion element 20 via the on-chip lens (not shown), the light passes through the photoelectric conversion element 20 and the photodiodes PD1 and PD2 in this order to be photoelectrically converted into green, blue, and red light, respectively, in this passing process, and thus signals of various colors are obtained in a similar manner to the first embodiment.

[0149] Since the through electrode 50 here is composed of a metal or a conductive material, the resistance value of the through electrode 50 can be reduced, and thus the characteristics can be further improved.

[0150] Therefore, in the present embodiment, the through electrode 50 is composed of a metal or a conductive material, which makes it possible to reduce the resistance value of the through electrode 50, and thus the characteristics can be further enhanced.

[0151] (Modified Example 1)

[0152] Figure 19 A cross-sectional configuration of a solid-state imaging device 10B according to Modified Example 1 is shown. The solid-state imaging device 10B can include a thermal oxidation film 34 between the dielectric layer 25 and the through electrode 50 and between the dielectric layer 25 and the semiconductor substrate 30. For example, the thermal oxidation film 34 can be composed of, but not limited to, a silicon oxide film, a silicon nitride oxide film, or a high dielectric insulating film in which silicon in the semiconductor substrate 30 is thermally oxidized. In addition to this, the solid-state imaging device 10B can have similar configurations, actions, and effects to the above-described first embodiment. Furthermore, the solid-state imaging device 10B can be manufactured in a similar manner to the first embodiment, except that the thermal oxidation film 34 is provided on the outer side surface 61 and the inner side surface 62 of the separation groove 60.

[0153] (Third Embodiment)

[0154] Figure 20 A cross-sectional configuration of a solid-state imaging device 10C according to the third embodiment of the present disclosure is shown. The solid-state imaging device 10C is configured to reduce the capacitance generated between the through electrode 50 and the semiconductor substrate 30 by filling the separation groove 60 with the dielectric layer 25 having insulating properties, and thus to further improve characteristics such as conversion efficiency. In addition to this, the solid-state imaging device 10C can have similar configurations, actions, and effects to the above-described first embodiment.

[0155] For example, the solid-state imaging element 10C can be manufactured as follows.

[0156] Figures 21 to 22 The manufacturing method of the solid-state imaging element 10C is shown in the step sequence. It should be noted that, referring to... Figures 3 to 6 The process is the same as the first implementation scheme described above.

[0157] First, as with the first implementation scheme, through Figure 3 The process shown, for example, involves forming a p-well 31 of a first conductivity type within the semiconductor substrate 30, and forming photodiodes PD1 and PD2 of a second conductivity type (e.g., N-type) within the p-well 31. A P+ region can be formed near the first surface 30A of the semiconductor substrate 30.

[0158] Furthermore, similar to the first implementation scheme, it is also through... Figure 3 The process shown allows for the formation of impurity regions (P+ regions) in the areas where the through electrode 50 and the separation trench 60 will be formed, extending from the first surface 30A through the second surface 30B of the semiconductor substrate 30. Furthermore, high-concentration impurity regions (P++ regions) can be formed in the areas above and below where the through electrode 50 will be formed.

[0159] Similar to the first implementation scheme, it is also through Figure 3 The process shown involves forming N+ regions, which will serve as floating diffusion portions FD1 to FD3, along the second surface 30B of the semiconductor substrate 30. Subsequently, a gate insulating film 32 and gate wiring 33, including the gates of a vertical transistor Tr1, a transmission transistor Tr2, an amplification transistor AMP, and a reset transistor RST, can be formed on the second surface 30B of the semiconductor substrate 30. Therefore, the vertical transistor Tr1, the transmission transistor Tr2, the amplification transistor AMP, and the reset transistor RST can be formed. Furthermore, lower first to third contacts 51 to 53 and a multilayer wiring 40, including wiring layers 41 to 43 containing connection portions 41A and an insulating film 44, can be formed on the second surface 30B of the semiconductor substrate 30.

[0160] Similar to the first embodiment, an example of a substrate used as the semiconductor substrate 30 can be an SOI substrate. Annealing can be performed after ion implantation.

[0161] Subsequently, as in the first implementation plan, through Figure 4The process shown, a support substrate (not shown) or any other semiconductor base can be bonded with the second face 30B (multilayer wiring 40) side of the semiconductor substrate 30, and the semiconductor substrate 30 can be upside down. Next, the semiconductor substrate 30 can be separated from the buried oxide film of the SOI substrate and the support substrate to expose the first face 30A of the semiconductor substrate 30. The above process can be performed by techniques used in a usual CMOS process such as ion implantation and CVD (Chemical Vapor Deposition).

[0162] Thereafter, as with the first embodiment, by Figure 5 The process shown, for example, the semiconductor substrate 30 can be processed from the first face 30A side by dry etching to form a ring-shaped or circular-shaped separation groove 60.

[0163] After forming the separation groove 60, as with the first embodiment, by Figure 6 The process shown, for example, a film 24 having a negative fixed charge can be formed on the outer side face 61, inner side face 62, and bottom face 63 of the separation groove 60 and the first face 30A of the semiconductor substrate 30. As the film 24 having a negative fixed charge, two or more films can be laminated. This makes it possible to further enhance the function as a hole accumulation layer.

[0164] After forming the film 24 having a negative fixed charge, as Figure 21 shown, the separation groove 60 can be filled with a dielectric layer 25.

[0165] After forming the dielectric layer 25, as Figure 22 shown, an interlayer insulating film 26 and an upper contact 54 can be formed, and the upper contact 54 can be connected with the upper end of the through electrode 50. Thereafter, as Figure 20 shown, a lower transparent electrode 21, a photoelectric conversion film 22, an upper transparent electrode 23, and a protective film 27 can be formed. Finally, optical elements such as a planarization film and an on-chip lens (not shown) can be provided. Thus, the solid-state imaging element 10C shown in Figure 20 is completed.

[0166] (Fourth Embodiment)

[0167] Figure 23 A cross-sectional configuration of a solid-state imaging element 10D according to a fourth embodiment of the present disclosure is shown. The solid-state imaging element 10D is configured to further improve characteristics such as conversion efficiency by reducing the capacitance generated between the through electrode 50 and the semiconductor substrate 30 by filling the separation groove 60 with a dielectric layer 25 having insulating properties. In addition to this, the solid-state imaging element 10D can have a similar configuration, action, and effect to the above-described first embodiment.

[0168] As Figure 24As shown, the solid-state imaging device 10D can be manufactured in a similar manner to the second embodiment, except that the separation groove 60 is filled with the dielectric layer 25.

[0169] (Modified Example 2)

[0170] Figure 25 A cross-sectional configuration of a solid-state imaging device 10E according to a modified example 2 is shown. The solid-state imaging device 10E can include a thermal oxide film 34 similar to that in the modified example 1 between the dielectric layer 25 and the through electrode 50 and between the dielectric layer 25 and the semiconductor substrate 30. As with the modified example 1, for example, the thermal oxide film 34 can be, but is not limited to, composed of a silicon oxide film, a silicon nitride oxide film, or a high dielectric insulating film in which silicon in the semiconductor substrate 30 is thermally oxidized. In addition to this, the solid-state imaging device 10E can have similar configurations, actions, and effects to those of the above-described third embodiment. Further, the solid-state imaging device 10E can be manufactured in a similar manner to the third embodiment, except that the thermal oxide film 34 is provided on the outer side surface 61 and the inner side surface 62 of the separation groove 60.

[0171] (Overall Configuration of Solid-state Imaging Unit)

[0172] Figure 26 An overall configuration of a solid-state imaging unit including one of the solid-state imaging devices 10 and 10A to 10E described in the above-described embodiments as a pixel section 110 is shown. For example, the solid-state imaging unit 1 can be a CMOS image sensor, and can include, for example, the pixel section 110 as an imaging pixel region and a circuit section 130. For example, the circuit section 130 can include a row scanning section 131, a horizontal selection section 133, a column scanning section 134, and a system control section 132. The circuit section 130 can be provided in a peripheral region around the pixel section 110. Alternatively, the circuit section 130 can be stacked above or below (i.e., in a region facing the pixel section 110) the pixel section 110.

[0173] For example, the pixel section 110 can include a plurality of pixels PXL arranged in a two-dimensional array. The pixels PXL can be wiredly connected to a pixel drive line Lread (specifically, a row selection line and a reset control line) of each pixel row, and can be wiredly connected to a vertical signal line Lsig of each pixel column. The pixel drive line Lread is adapted to transfer a drive signal to read a signal from the pixels. One end of the pixel drive line Lread can be connected to an output terminal corresponding to each row of the row scanning section 131.

[0174] For example, the row scanning section 131 can include a shift register and an address decoder, and can function as a pixel driving section that drives the pixels PXL of the pixel section 110 in units of rows, for example. A signal can be output from the pixels PXL of the pixel row selected and scanned by the row scanning section 131; and the signal thus output can be supplied to the horizontal selection section 133 through the respective vertical signal lines Lsig. The horizontal selection section 133 can include an amplifier and a horizontal selection switch provided for each vertical signal line Lsig, for example.

[0175] For example, the column scanning section 134 can include a shift register and an address decoder, and is adapted to scan and sequentially drive the horizontal selection switches of the horizontal selection section 133. This selective scanning by the column scanning section 134 allows the signals transferred from the pixels PXL through the respective vertical signal lines Lsig to be sequentially transferred to the horizontal signal line 135 and output through the horizontal signal line 135.

[0176] The system control section 132 is adapted to receive a clock supplied from the outside, data of an instruction regarding the operation mode, and to output data such as internal information of the solid-state imaging unit 1, for example. In addition, the system control section 132 can include a timing generator that generates various timing signals, and is adapted to perform driving control of the row scanning section 131, the horizontal selection section 133, the column scanning section 134, and other sections based on the various timing signals generated by the timing generator.

[0177] (Application Examples)

[0178] The solid-state imaging unit according to the above-described description including the above-described exemplary embodiments can be applied to various electronic devices having an imaging function. Some examples can include a camera system such as a digital camera and a video camera, and a mobile phone having an imaging function. As examples, Figure 27 The overall configuration of an electronic device 2 (e.g., a camera) is shown. The electronic device 2 can be a video camera configured to capture still images and moving images, and can include the solid-state imaging unit 1, an optical system (imaging lens) 310, a shutter device 311, a driving section 313 (including the above-described circuit section 130), a signal processing section 312, a user interface 314, and a monitor 315. The driving section 313 is adapted to drive the solid-state imaging unit 1 and the shutter device 311.

[0179] The optical system 310 is adapted to guide image light (incident light) from an object toward the pixel section 110 of the solid-state imaging unit 1. The optical system 310 can include a plurality of optical lenses. The shutter device 311 is adapted to control a light irradiation period and a light blocking period of the solid-state imaging unit 1. The drive section 313 is adapted to control a transfer operation of the solid-state imaging unit 1 and a shutter operation of the shutter device 311. The signal processing section 312 is adapted to perform various signal processes on a signal output from the solid-state imaging unit 1. The picture signal Dout after the signal processing can be output to the monitor 315. Alternatively, the picture signal Dout can be stored in a storage medium such as a memory. The user interface 314 allows a shooting scene to be specified (for example, a dynamic range is specified and a wavelength (such as terahertz, visible light, infrared, ultraviolet, and X-ray) is specified). Such a specification (that is, an input signal from the user interface 314) can be sent to the drive section 313; based on the specification, desired imaging can be performed in the solid-state imaging unit 1.

[0180] Although described by giving the above-described exemplary embodiments, the present disclosure is not limited to the above-described exemplary embodiments and the like, and can be modified in various ways. For example, the pixel circuit of the solid-state imaging element 10 can have a three-transistor configuration including a transfer transistor, an amplification transistor, and a reset transistor, or a four-transistor configuration including a selection transistor in addition to the three transistors.

[0181] Further, for example, in the foregoing exemplary embodiments, a case in which the solid-state imaging unit is applied to a camera is described as an example; however, the solid-state imaging unit can also be applied to general electronic devices that image light (electromagnetic waves) such as an endoscope, a vision chip (artificial retina), and a biological sensor.

[0182] Further, in the foregoing exemplary embodiments, the configuration of the back-illuminated solid-state imaging element 10 is described; however, the present disclosure is also applicable to a front-illuminated solid-state imaging element.

[0183] For example, in the solid-state imaging element 10 and the solid-state imaging unit 1 according to the foregoing exemplary embodiments, it is not necessary to include all of the components, and another component or other components can also be provided.

[0184] Note that the content of the present technology can have the following configuration:

[0185] (1) A solid-state imaging element including:

[0186] at least one photoelectric conversion element provided on a first surface side of a semiconductor substrate;

[0187] a through electrode connected to the at least one photoelectric conversion element and disposed between the first face and the second face of the semiconductor substrate; and

[0188] an amplification transistor and a floating diffusion disposed on the second face of the semiconductor substrate,

[0189] wherein the at least one photoelectric conversion element is connected to the gate of the amplification transistor and the floating diffusion via the through electrode.

[0190] (2) The solid-state imaging element according to (1), further comprising a reset transistor disposed on the second face of the semiconductor substrate, the reset transistor including a reset gate,

[0191] wherein the reset gate is disposed adjacent to the floating diffusion.

[0192] (3) The solid-state imaging element according to (1) or (2), wherein

[0193] the at least one photoelectric conversion element includes a plurality of photoelectric conversion elements, and

[0194] the through electrode is provided for each of the plurality of photoelectric conversion elements.

[0195] (4) The solid-state imaging element according to any one of (1) to (3), wherein the through electrode penetrates the semiconductor substrate and is separated from the semiconductor substrate by a separation groove.

[0196] (5) The solid-state imaging element according to (4), wherein

[0197] the through electrode is composed of a semiconductor doped with an N-type or P-type impurity, and

[0198] an impurity region of the same conductivity type as that of the through electrode is disposed on an outer side of the separation groove in the semiconductor substrate.

[0199] (6) The solid-state imaging element according to (4), wherein the through electrode is composed of a metal or a conductive material.

[0200] (7) The solid-state imaging element according to any one of (4) to (6), wherein the separation groove is filled with a dielectric layer having insulating properties.

[0201] (8) The solid-state imaging element according to any one of (4) to (6), wherein

[0202] an outer side of the separation groove is covered with an outer side dielectric layer,

[0203] an inner side of the separation groove is covered with an inner side dielectric layer, and

[0204] a gap is provided between the outer dielectric layer and the inner dielectric layer.

[0205] (9) The solid-state imaging device according to any one of (4) to (8), wherein a film having a fixed charge is provided on an outer side surface, an inner side surface, and a bottom surface of the separation groove and the first surface of the semiconductor substrate.

[0206] (10) The solid-state imaging device according to any one of (1) to (9), further comprising one or more photodiodes provided inside the semiconductor substrate.

[0207] (11) A solid-state imaging device comprising:

[0208] a photoelectric conversion element provided on a first surface side of a semiconductor substrate;

[0209] a through electrode connected to the photoelectric conversion element and provided between the first surface and a second surface of the semiconductor substrate;

[0210] a separation groove provided between the through electrode and the semiconductor substrate; and

[0211] a dielectric layer filling the separation groove and having an insulating property.

[0212] (12) A solid-state imaging device comprising:

[0213] a photoelectric conversion element provided on a first surface side of a semiconductor substrate;

[0214] a through electrode connected to the photoelectric conversion element and provided between the first surface and a second surface of the semiconductor substrate;

[0215] a separation groove provided between the through electrode and the semiconductor substrate;

[0216] an outer dielectric layer covering an outer side surface of the separation groove;

[0217] an inner dielectric layer covering an inner side surface of the separation groove; and

[0218] a gap provided between the outer dielectric layer and the inner dielectric layer.

[0219] (13) An electronic device provided with a solid-state imaging device, the solid-state imaging device comprising:

[0220] at least one photoelectric conversion element provided on a first surface side of a semiconductor substrate;

[0221] a through electrode connected to the at least one photoelectric conversion element and provided between the first surface and a second surface of the semiconductor substrate; and

[0222] an amplification transistor and a floating diffusion provided on the second face of the semiconductor substrate,

[0223] wherein the at least one photoelectric conversion element is connected with the gate of the amplification transistor and the floating diffusion via the through electrode.

[0224] (14) An electronic device provided with a solid-state imaging element, the solid-state imaging element comprising:

[0225] a photoelectric conversion element provided on a first face side of a semiconductor substrate;

[0226] a through electrode connected with the photoelectric conversion element and provided between the first face and a second face of the semiconductor substrate;

[0227] a separation groove provided between the through electrode and the semiconductor substrate; and

[0228] a dielectric layer filling the separation groove and having an insulating property.

[0229] (15) An electronic device provided with a solid-state imaging element, the solid-state imaging element comprising:

[0230] a photoelectric conversion element provided on a first face side of a semiconductor substrate;

[0231] a through electrode connected with the photoelectric conversion element and provided between the first face and a second face of the semiconductor substrate;

[0232] a separation groove provided between the through electrode and the semiconductor substrate;

[0233] an outer side dielectric layer covering an outer side face of the separation groove;

[0234] an inner side dielectric layer covering an inner side face of the separation groove; and

[0235] a gap provided between the outer side dielectric layer and the inner side dielectric layer.

[0236] This application claims the benefit of Japanese Priority Patent Application JP 2013-169553 filed August 19, 2013, the entire contents of which are incorporated herein by reference.

[0237] Those skilled in the art will appreciate that various modifications, combinations, sub-combinations and changes can be made to the embodiments of the present application disclosed herein without departing from the scope of the present application as recited in the following claims or the scope of equivalents thereof.

Claims

1. A solid-state imaging device comprising: one or more photoelectric conversion elements disposed on and above a first surface of a semiconductor substrate; a through electrode connected to the one or more photoelectric conversion elements and disposed between the first surface and a second surface of the semiconductor substrate; and a dielectric layer disposed between the through electrode and the semiconductor substrate, the dielectric layer being disposed above the through electrode and extending along a surface of the one or more photoelectric conversion elements, and the dielectric layer being disposed between the surface of the one or more photoelectric conversion elements and the first surface of the semiconductor substrate, wherein the through electrode is made of a conductive material, wherein the dielectric layer is further disposed along a vertical side portion of the through electrode and includes an outer dielectric layer and an inner dielectric layer, there is a gap between the outer dielectric layer and the inner dielectric layer, and wherein a film configured to have a fixed charge is disposed at least between the outer dielectric layer and the semiconductor substrate, or at least between the inner dielectric layer and the semiconductor substrate.

2. The solid-state imaging device according to claim 1, further comprising an amplification transistor and a floating diffusion portion disposed on the second surface of the semiconductor substrate. The one or more photoelectric conversion elements are connected to the floating diffusion portion and a gate of the amplification transistor via the through electrode, and wherein the through electrode penetrates the semiconductor substrate and is separated from the semiconductor substrate by a separation groove.

3. The solid-state imaging device according to claim 2, wherein The dielectric layer is made of silicon oxide.

4. The solid-state imaging device according to claim 1, wherein The one or more photoelectric conversion elements are connected to the floating diffusion portion and the gate of the amplification transistor via the through electrode.

5. The solid-state imaging device according to claim 1, wherein The one or more photoelectric conversion elements include a plurality of photoelectric conversion elements, and the through electrode is provided for each of the plurality of photoelectric conversion elements.

6. The solid-state imaging device according to claim 1, wherein 7. The solid-state imaging device according to claim 1, further comprising one or more photodiodes disposed in the semiconductor substrate. The through electrode penetrates the semiconductor substrate and is separated from the semiconductor substrate by a separation groove.

8. The solid-state imaging device according to claim 1, wherein The outer dielectric layer, the inner dielectric layer, and the gap are disposed within the separation groove, and wherein the dielectric layer has an insulating property.

9. The solid-state imaging device according to claim 8, wherein 10. An electronic device provided with a solid-state imaging device, the solid-state imaging device comprising: one or more photoelectric conversion elements disposed on and above a first surface of a semiconductor substrate; a through electrode connected to the one or more photoelectric conversion elements and disposed between the first surface and a second surface of the semiconductor substrate; and a dielectric layer disposed between the through electrode and the semiconductor substrate, the dielectric layer being disposed above the through electrode and extending along a surface of the one or more photoelectric conversion elements, and the dielectric layer being disposed between the surface of the one or more photoelectric conversion elements and the first surface of the semiconductor substrate, wherein the through electrode is made of a conductive material, wherein the dielectric layer is further disposed along a vertical side portion of the through electrode and includes an outer dielectric layer and an inner dielectric layer, there is a gap between the outer dielectric layer and the inner dielectric layer, and wherein a film configured to have a fixed charge is disposed at least between the outer dielectric layer and the semiconductor substrate, or at least between the inner dielectric layer and the semiconductor substrate. a dielectric layer provided between the through electrode and the semiconductor substrate, the dielectric layer being provided over the through electrode and extending along a surface of the one or more photoelectric conversion elements, and the dielectric layer being provided between the surface of the one or more photoelectric conversion elements and the first surface of the semiconductor substrate, wherein the through electrode is made of an electrically conductive material, wherein the dielectric layer is further provided along a vertical side portion of the through electrode and includes an outer dielectric layer and an inner dielectric layer, there is a gap between the outer dielectric layer and the inner dielectric layer, and wherein a film configured to have a fixed charge is provided at least between the outer dielectric layer and the semiconductor substrate, or at least between the inner dielectric layer and the semiconductor substrate.

11. The electronic device according to claim 10, further comprising an amplification transistor and a floating diffusion provided on the second surface of the semiconductor substrate.

12. The electronic device of claim 11, wherein, The one or more photoelectric conversion elements are connected to the floating diffusion and a gate of the amplification transistor via the through electrode, and wherein the through electrode penetrates the semiconductor substrate and is separated from the semiconductor substrate by a separation groove.

13. The electronic device of claim 10, wherein, The dielectric layer is made of silicon oxide.

14. The electronic device of claim 10, wherein, The one or more photoelectric conversion elements are connected to a floating diffusion and a gate of an amplification transistor via the through electrode.

15. The electronic device of claim 10, wherein, The one or more photoelectric conversion elements include a plurality of photoelectric conversion elements, and the through electrode is provided for each of the plurality of photoelectric conversion elements.

16. The electronic device according to claim 10, further comprising one or more photodiodes provided in the semiconductor substrate.

17. The electronic device of claim 10, wherein, The through electrode penetrates the semiconductor substrate and is separated from the semiconductor substrate by a separation groove.

18. The electronic device of claim 17, wherein, The outer dielectric layer, the inner dielectric layer, and the gap are provided within the separation groove, and wherein the dielectric layer has an insulating property.

19. A solid-state imaging device, comprising: one or more photoelectric conversion elements provided on and over a first surface of a semiconductor substrate; a through electrode connected to the one or more photoelectric conversion elements and provided between the first surface and a second surface of the semiconductor substrate; and a dielectric layer provided between the through electrode and the semiconductor substrate, the dielectric layer being provided over the through electrode and extending along a surface of the one or more photoelectric conversion elements, and the dielectric layer being provided between the surface of the one or more photoelectric conversion elements and the first surface of the semiconductor substrate, wherein the through electrode is made of an electrically conductive material, wherein the through electrode penetrates the semiconductor substrate and is separated from the semiconductor substrate by a separation groove, and wherein the dielectric layer is further provided along a vertical side portion of the through electrode and includes an outer dielectric layer and an inner dielectric layer, there is a gap between the outer dielectric layer and the inner dielectric layer, and wherein a film configured to have a fixed charge is provided at least between the outer dielectric layer and the semiconductor substrate, or at least between the inner dielectric layer and the semiconductor substrate. The film configured to have a fixed charge is disposed at least between the outer dielectric layer and the semiconductor substrate, or at least between the inner dielectric layer and the semiconductor substrate.

20. The solid-state imaging device according to claim 19, wherein The outer dielectric layer, the inner dielectric layer and the gap are disposed in the separation groove, and wherein the dielectric layer has insulating properties.

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