A three-loop digital LDO circuit with fast response and no output capacitor

Abstract

The present invention discloses a three - loop digital LDO circuit with fast response and no output capacitor, which is composed of 1 dynamic comparator, 2 control modules, 2 multiplexer modules, 1 delay module, 1 20 - bit bidirectional shift register, 1 carry - skip module, 2 OR gates, 1 16 - bit bidirectional shift register and 3 groups of MOS transistor arrays. The present invention adopts a three - loop structure of two synchronous loops and one asynchronous loop, controls the three groups of MOS transistor arrays through three loops to adjust the output OUT of the digital LDO, removes the output capacitor, reduces the ripple and overall power consumption, improves the transient response of the circuit and saves the chip area.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a three-loop digital LDO circuit with fast response and no output capacitor. Background Art

[0002] With the development of the field of integrated circuits, LDO (low dropout linear regulator) is also applied to various systematic chips, such as biomedical chips and RF chips, etc., to provide a stable voltage for each module in the system that is not affected by process, temperature, and power supply voltage. Compared with traditional analog LDOs, digital LDOs can operate at lower input voltages and can be better updated with the upgrade of the process, but their disadvantage is that the transient response is slower. In recent years, the research on digital LDOs mainly focuses on improving performance parameters, such as transient response, power consumption, ripple, and recovery time, etc. In the existing digital LDO technology, there are mainly two methods to improve the transient response: one is to increase the size of the power transistor, which can make the step size of each adjustment larger, reduce the number of adjustments, and thus improve the transient response, but at the same time, the ripple of the output waveform will also increase; the other is to increase the clock frequency, which can make the adjustment speed faster, but at the same time, the overall power consumption of the circuit will also increase. Summary of the Invention

[0003] The problems to be solved by the present invention are the large ripple, slow transient response, and the need for an output capacitor in digital LDOs, and a three-loop digital LDO circuit with fast response and no output capacitor is provided.

[0004] To solve the above problems, the present invention is realized through the following technical solutions:

[0005] A three-loop digital LDO circuit with fast response and no output capacitor, characterized in that it is composed of 1 dynamic comparator, 2 control modules, 2 multiplexer modules, 1 delay module, 1 20-bit bidirectional shift register, 1 carry / borrow module, 2 OR gates, 1 16-bit bidirectional shift register, and 3 groups of MOS transistor arrays; the two input terminals of the dynamic comparator are respectively connected to the reference voltage V ref and the output terminal of the digital LDO circuit, and its enable control terminal is connected to the total clock signal CLK; the three input terminals of the first control module are respectively connected to the first reference voltage V ref1 , the second reference voltage V ref2 , and the output terminal of the digital LDO, and its enable control terminal is connected to the total clock signal CLK; the seven input terminals of the second control module are respectively connected to the third reference voltage V ref3 , the fourth reference voltage V ref4 , the fifth reference voltage V ref5 , the sixth reference voltage V ref6 , the seventh reference voltage Vref7, the eighth reference voltage V ref8 and the output terminal of the digital LDO; the input terminal of the delay module is connected to the total clock signal CLK, and the output terminal of the delay module is connected to the second input terminal of the first multiplexer and the first input terminal of the second multiplexer; the first input terminal of the first multiplexer and the second input terminal of the second multiplexer are grounded; the enable control terminals of the first multiplexer and the second multiplexer are connected to the output terminal of the first control module; the 4 input terminals of the 20-bit bidirectional shift register are respectively connected to the output terminal of the dynamic comparator, the output terminal of the second controller, the output terminal of the first multiplexer, and the output terminal of the second OR gate; the 2 input terminals of the carry / borrow module are respectively connected to the output terminal of the first multiplexer and the output terminal of the 20-bit bidirectional shift register; the 2 output terminals of the carry / borrow module are respectively connected to the 2 input terminals of the first OR gate; the output terminal of the first OR gate and the output terminal of the second multiplexer are respectively connected to the 2 input terminals of the second OR gate; the 3 input terminals of the 16-bit bidirectional shift register are respectively connected to the output terminal of the second multiplexer, the output terminal of the dynamic comparator, and the output terminal of the first OR gate; the 3 groups of MOS transistor arrays are the L group MOS transistor array, the M group MOS transistor array, and the S group MOS transistor array; the L group MOS transistor array includes 6 MOS transistors of the same size, the M group MOS transistor array includes 16 MOS transistors of the same size, and the S group MOS transistor array includes 20 MOS transistors of the same size; the size of the MOS transistors in the L group MOS transistor array is larger than the size of the MOS transistors in the M group MOS transistor array, and the size of the MOS transistors in the M group MOS transistor array is larger than the size of the MOS transistors in the S group MOS transistor array; the gates of all the MOS transistors in the L group MOS transistor array are simultaneously connected to the output terminal of the second control module, the gates of all the MOS transistors in the M group MOS transistor array are simultaneously connected to the output terminal of the 16-bit bidirectional shift register, and the gates of all the MOS transistors in the S group MOS transistor array are simultaneously connected to the output terminal of the 20-bit bidirectional shift register; the sources of all the MOS transistors in the L group MOS transistor array, the sources of all the MOS transistors in the M group MOS transistor array, and the sources of all the MOS transistors in the S group MOS transistor array are connected to the power supply voltage; the drains of all the MOS transistors in the L group MOS transistor array, the drains of all the MOS transistors in the M group MOS transistor array, and the drains of all the MOS transistors in the S group MOS transistor array form the output terminal of the digital LDO circuit.

[0006] In the above solution, the first reference voltage V ref1 is greater than the second reference voltage V ref2 .

[0007] In the above solution, the ratio of the MOS transistor sizes of the L group MOS transistor array, the M group MOS transistor array, and the S group MOS transistor array is L:M:S = 16:8:1.

[0008] Compared with the prior art, the present invention has the following characteristics:

[0009] 1. The triple-loop regulation technology is adopted to reduce the ripple and overall power consumption.

[0010] 2. An asynchronous loop is adopted to greatly improve the transient response of the circuit.

[0011] 3. The output capacitor is not used, greatly reducing the layout area. Brief Description of the Drawings

[0012] Figure 1 It is a system block diagram of a triple-loop digital LDO circuit with fast response and no output capacitor.

[0013] Figure 2 It is a characteristic curve of a triple-loop digital LDO circuit with fast response and no output capacitor. (a) Output voltage characteristic curve, (b) Asynchronous loop compensation current I DYN Variation characteristic curve when the load current changes suddenly, (c) Output current I OUT Variation characteristic curve when the load current changes suddenly, (d) Load current I LOAD Variation characteristic curve. Detailed Embodiment

[0014] To make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific examples.

[0015] A triple-loop digital LDO circuit with fast response and no output capacitor, as Figure 1 shown, mainly consists of 1 dynamic comparator, 2 control modules, 2 multiplexer modules, 1 delay module, 1 20-bit bidirectional shift register, 1 carry / borrow module, 2 OR gates, 1 16-bit bidirectional shift register and 3 groups of MOS transistor arrays.

[0016] The dynamic comparator has its first input terminal connected to the total reference voltage V ref , its second input terminal connected to the output voltage OUT of the digital LDO, and its enable control terminal connected to the total clock signal CLK. The dynamic comparator operates at the rising edge of the total clock signal CLK, compares the values of the total reference voltage V ref and the output voltage OUT, and outputs the comparison result CMP.

[0017] The first control module has its first input terminal connected to the first reference voltage V ref1 , its second input terminal connected to the second reference voltage V ref2 , its third input terminal connected to the output voltage OUT of the digital LDO, and its enable control terminal connected to the total clock signal CLK. V ref1 > V ref2 . The first control module is a horizontal voltage tracker, which tracks at the rising edge of the total clock signal CLK and outputs the tracking result S.

[0018] The second control module, with its first input terminal connected to the third reference voltage V ref3 , its second input terminal connected to the fourth reference voltage V ref4 , its third input terminal connected to the fifth reference voltage V ref5 , its fourth input terminal connected to the sixth reference voltage V ref6 , its fifth input terminal connected to the seventh reference voltage V ref7 , its sixth input terminal connected to the eighth reference voltage V ref8 ; its seventh input terminal connected to the output voltage OUT of the digital LDO. The second control module directly outputs the parallel signal A<1:6> without clock control.

[0019] The delay module, with its input terminal connected to the total clock signal CLK, and after passing through the internal circuit, its output terminal outputs the first clock signal CLK1.

[0020] The first multiplexer, with its first input terminal grounded, its second input terminal connected to the first clock signal CLK1 output by the delay module, and its enable control terminal connected to the tracking result S output by the first control module. The first multiplexer makes a selection based on the signal received at the enable terminal and outputs the result.

[0021] The second multiplexer, with its first input terminal connected to the first clock signal CLK1 output by the delay module, its second input terminal grounded, and its enable control terminal connected to the tracking result S output by the first control module. The second multiplexer makes a selection based on the signal received at the enable terminal and outputs the result.

[0022] The 20-bit bidirectional shift register, with its first input terminal connected to the comparison result CMP output by the dynamic comparator, its second input terminal connected to the parallel signal A<1:6> output by the second controller, its third input terminal connected to the output signal of the first multiplexer, and its fourth input terminal connected to the reset signal RESET output by the second OR gate. When the 20-bit bidirectional shift register receives the reset signal RESET, it resets the output signal to F<0:19>=0000_0000_0000_0000_0000 and outputs the parallel signal F<0:19>.

[0023] The carry / borrow module, with its first input terminal connected to the output signal of the first multiplexer and its second input terminal connected to the parallel signal F<0:19> output by the 20-bit bidirectional shift register.

[0024] The first OR gate, with its first input terminal connected to the first output terminal of the carry / borrow module, its second input terminal connected to the second output terminal of the carry / borrow module, and its output terminal outputting the signal B.

[0025] The second OR gate, with its first input terminal connected to the signal B output by the first OR gate and its second input terminal connected to the output of the second multiplexer, and its output terminal outputting the reset signal RESET.

[0026] A 16-bit bidirectional shift register, with its first input terminal connected to the output signal of a second 2-to-1 selector, its second input terminal connected to the comparison result CMP output by a dynamic comparator, its third input terminal connected to the signal B output by a first OR gate, and its output terminal outputting a parallel signal Q<0:15>.

[0027] All MOS transistors are divided into three groups according to their different sizes. The array composed of the MOS transistors with the largest size is the L-group MOS transistor array (including 6 MOS transistors with the same size), the array composed of the MOS transistors with the medium size is the M-group MOS transistor array (including 16 MOS transistors with the same size), and the array composed of the MOS transistors with the smallest size is the S-group MOS transistor array (including 20 MOS transistors with the same size). And the ratio of the MOS transistor sizes of these three groups of MOS transistor arrays is L:M:S = 16:8:1. The gates of all MOS transistors in the L-group MOS transistor array are connected to the output of the second controller module, receiving the parallel signal A<1:6> output by the second controller module. The gates of all MOS transistors in the M-group MOS transistor array are connected to the output of the 16-bit bidirectional shift register, receiving the parallel signal Q<0:15> output by the 16-bit bidirectional shift register. The gates of all MOS transistors in the S-group MOS transistor array are connected to the output of the 20-bit bidirectional shift register, receiving the parallel signal F<0:19> output by the 20-bit bidirectional shift register. When the parallel signal output is "1", the MOS transistor becomes in the on state, and when the parallel signal output is "0", the MOS transistor becomes in the off state. The sources of all MOS transistors in the three groups of MOS transistor arrays are connected to the power supply voltage. The drains of all MOS transistors in the three groups of MOS transistor arrays output the output voltage OUT of the digital LDO.

[0028] The present invention adopts a three-loop structure of two synchronous loops and one asynchronous loop, controls three groups of MOS transistor arrays through three loops to adjust the output OUT of the digital LDO, and removes the output capacitor, greatly saving the chip area. The dynamic comparator, the first control module, the carry / borrow module, and 2 bidirectional shift comparators all work only in the rising edge stage of the clock. At the rising edge of the clock, the dynamic comparator outputs the comparison result, the first control module detects whether the output voltage is within the corresponding range and outputs the result, and 2 2-to-1 data selector modules select to adjust the S-group MOS transistors or the M-group MOS transistors according to the result output by the first control module to stabilize the output voltage, and the carry / borrow module will detect whether the 20-bit bidirectional shift register module is all 0 or all 1 and perform corresponding carry / borrow operations; The second control module does not require clock control. When it detects that the voltage is between V ref3 ~V ref8Output the corresponding value during the interval, then adjust the MOS transistors in group L, and finally obtain a stable output voltage, which is then fed back to the dynamic comparator to form a complete control loop. The control loop formed by the second control module is an asynchronous cycle, which can effectively avoid cycle delay and control demonstration. Without passing through a bidirectional shift register, the output voltage is adjusted at the fastest speed, greatly improving the transient response of the circuit and reducing the undershoot voltage of the circuit. When the load current changes suddenly, the second control module will provide additional current to reduce the sudden change at the output point, which is equivalent to an output capacitor.

[0029] The dynamic comparator works when the clock signal rises. When "V ref >OUT", the output CMP = "1". When "V ref <OUT", the output CMP = "0". Since the output changes every time the up signal comes, the situation of V ref = OUT does not exist.

[0030] The first controller module works when the clock signal rises. When "V ref1 >OUT>V ref2 ", the output S = "1". When "V ref1 <OUT, OUT<V ref2 ", the output S = "0".

[0031] After receiving the tracking result S output by the first control module, the two multiplexers select the corresponding working mode. When S = 0, the second multiplexer selects the clock signal CLK1 for output. The 16-bit bidirectional shift register will output according to the comparison result CMP output by the dynamic comparator, and finally control the on / off of the MOS transistors, thereby adjusting the output voltage OUT, and finally feeding it back to the dynamic comparator to form a loop. This loop is called the coarse loop. When S = 1, the first multiplexer selects the clock signal CLK1 for output. The 20-bit bidirectional shift register will output according to the comparison result CMP output by the dynamic comparator, and finally control the on / off of the MOS transistors, thereby adjusting the output voltage OUT, and finally feeding it back to the dynamic comparator to form a loop. This loop is called the fine loop. The sum of the currents output by the above two loops is I OUT .

[0032] The second control module can always detect whether the voltage range where the output voltage OUT is located is within [V ref3 , V ref8 without being driven by a clock signal, so as to judge whether the circuit needs to start the asynchronous loop. When V ref3 <OUT<V ref4 , A<1:6> outputs "011111". When V ref4<OUT < V ref5 When A<1:6> outputs "001111", when V ref5 <OUT < V ref6 When A<1:6> outputs "000111", when V ref6 <OUT < V ref7 When A<1:6> outputs "000011", when V ref7 <OUT < V ref8 When A<1:6> outputs "000001". When the load current I LOAD When there is a mutation, due to the control delay and cycle delay in the coarse loop and the fine loop, the S-group MOS transistors and the M-group MOS switches cannot immediately control the current shortage, and there will be a large undershoot voltage. Since the asynchronous loop does not require clock control, when the load current I LOAD When there is a mutation, it will turn on the MOS controlled by the corresponding voltage to supplement the lacking current. When OUT < V ref3 At this time, the MOS transistors in the L group do not work and are regulated by the thick and thin loops.

[0033] When the output voltage V ref1 <OUT < V ref2 At this time, the circuit is in the fine loop mode and the ripple of the circuit is also the smallest. When OUT > V ref At this time, the output of the dynamic comparator CMP = "1", then the 20-bit bidirectional shift register as a whole shifts one bit to the highest bit and enters "1" at the lowest bit. At this time, one MOS transistor is turned off. When OUT < V ref At this time, the output of the dynamic comparator CMP = "0", then the 20-bit bidirectional shift register as a whole shifts one bit to the highest bit and enters "0" at the lowest bit. At this time, one MOS transistor is turned on. When the outputs of the 20-bit bidirectional shift register are all "0" or "1", and the written value is "0" or "1", the carry / borrow module will be triggered. The coarse adjustment loop will perform carry / borrow according to the signal output by the carry / borrow module, and the fine adjustment loop will be reset to reset all the values of the 20-bit bidirectional shift register to "0" or "1".

[0034] When the output voltage V ref1 > OUT or V ref2 < OUT, at this time the circuit starts the coarse loop regulation, controls the M-group MOS transistors to turn on or off according to the output CMP of the received dynamic comparator. After several cycles, it enters the fine loop regulation to adjust the output voltage to the [V ref1 , V ref2 interval, and the ripple is the smallest when the system enters the steady state.

[0035] Figure 2For the characteristic curves of a three-loop digital LDO circuit with fast response and no output capacitor, (a) output voltage characteristic curve, (b) compensation current I DYN Variation characteristic curve when the load current changes suddenly, (c) output current I OUT Variation characteristic curve when the load current changes suddenly, (d) load current I LOAD Variation characteristic curve. As can be seen from the figure, when the load current I LOAD jumps from 0.5 mA to 25 mA within 1 ns, the undershoot voltage of the output voltage OUT is 105 mV, and the compensation current I DYN provided by the asynchronous loop increases rapidly from 0 to 15 mA and then slowly decreases to 0. The output current I OUT provided by the coarse loop and the fine loop increases slowly from 0 to 25 mA and finally stabilizes, and the ripple at steady state is 0.001 V.

[0036] It should be noted that although the embodiments described above of the present invention are illustrative, this is not a limitation of the present invention. Therefore, the present invention is not limited to the above specific embodiments. Without departing from the principle of the present invention, any other embodiments obtained by those skilled in the art under the inspiration of the present invention are considered to be within the protection scope of the present invention.

Claims

1. A three - loop digital LDO circuit with fast response and no output capacitor, characterized in that, it is composed of 1 dynamic comparator, 2 control modules, 2 multiplexer modules, 1 delay module, 1 20 - bit bidirectional shift register, 1 carry - skip module, 2 OR gates, 1 16 - bit bidirectional shift register and 3 groups of MOS transistor arrays; The two input terminals of the dynamic comparator are respectively connected to the reference voltage V ref and the output terminal of the digital LDO circuit, and its enable control terminal is connected to the total clock signal CLK; The three input terminals of the first control module are respectively connected to the first reference voltage V ref1 , the second reference voltage V ref2 and the output terminal of the digital LDO, and its enable control terminal is connected to the total clock signal CLK; The seven input terminals of the second control module are respectively connected to the third reference voltage V ref3 , the fourth reference voltage V ref4 , the fifth reference voltage V ref5 , the sixth reference voltage V ref6 , the seventh reference voltage Vref7 , the eighth reference voltage V ref8 and the output terminal of the digital LDO; The input end of the delay module is connected to the total clock signal CLK, and the output end of the delay module is connected to the second input end of the first multiplexer and the first input end of the second multiplexer; the first input end of the first multiplexer and the second input end of the second multiplexer are grounded; the enable control ends of the first multiplexer and the second multiplexer are connected to the output end of the first control module; The 4 input ends of the 20 - bit bidirectional shift register are respectively connected to the output end of the dynamic comparator, the output end of the second controller, the output end of the first multiplexer and the output end of the second OR gate; The 2 input ends of the carry - skip module are respectively connected to the output end of the first multiplexer and the output end of the 20 - bit bidirectional shift register; the 2 output ends of the carry - skip module are respectively connected to the 2 input ends of the first OR gate; the output end of the first OR gate and the output end of the second multiplexer are respectively connected to the 2 input ends of the second OR gate; The 3 input ends of the 16 - bit bidirectional shift register are respectively connected to the output end of the second multiplexer, the output end of the dynamic comparator and the output end of the first OR gate; The 3 groups of MOS transistor arrays are the L - group MOS transistor array, the M - group MOS transistor array and the S - group MOS transistor array respectively; the L - group MOS transistor array includes 6 MOS transistors of the same size, the M - group MOS transistor array includes 16 MOS transistors of the same size, and the S - group MOS transistor array includes 20 MOS transistors of the same size; the size of the MOS transistors in the L - group MOS transistor array is larger than that of the MOS transistors in the M - group MOS transistor array, and the size of the MOS transistors in the M - group MOS transistor array is larger than that of the MOS transistors in the S - group MOS transistor array; the gates of all the MOS transistors in the L - group MOS transistor array are simultaneously connected to the output end of the second control module, the gates of all the MOS transistors in the M - group MOS transistor array are simultaneously connected to the output end of the 16 - bit bidirectional shift register, and the gates of all the MOS transistors in the S - group MOS transistor array are simultaneously connected to the output end of the 20 - bit bidirectional shift register; the sources of all the MOS transistors in the L - group MOS transistor array, the sources of all the MOS transistors in the M - group MOS transistor array and the sources of all the MOS transistors in the S - group MOS transistor array are connected to the power supply voltage; the drains of all the MOS transistors in the L - group MOS transistor array, the drains of all the MOS transistors in the M - group MOS transistor array and the drains of all the MOS transistors in the S - group MOS transistor array form the output end of the digital LDO circuit.

2. The three - loop digital LDO circuit with fast response and no output capacitor according to claim 1, characterized in that, The first reference voltage V ref1 is greater than the second reference voltage V ref2 .

3. The three - loop digital LDO circuit with fast response and no output capacitor according to claim 1, characterized in that, The ratio of the MOS transistor sizes of the L - group MOS transistor array, the M - group MOS transistor array and the S - group MOS transistor array is L:M:S = 16:8:1.

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