Display panel, short circuit test method of display panel and display device

Abstract

This application discloses a display panel, a short-circuit testing method for the display panel, and a display device, relating to the field of display technology. The display panel includes: multiple first data lines located in a first display area and electrically connected to first pixel units in the first display area; multiple second data lines located in a second display area and electrically connected to second pixel units in the second display area; multiple first pads and multiple second pads located in a non-display area, with the multiple second pads distributed among the multiple first pads in a first direction; a first fan-out line electrically connected between the first data lines and the first pads; a second fan-out line electrically connected between the second data lines and the second pads; a first type of test terminal electrically connected to the first data lines via a first test control module; and a second type of test terminal electrically connected to the second data lines via a second test control module. According to the embodiments of this application, short circuits in the fan-out lines of the conventional display area in a reverse-order FIAA display panel can be detected.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel, a short-circuit test method for the display panel, and a display device. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for display panels. Related technologies use a CT2 circuit added to the screen to detect short circuits between fan-out traces, so as to detect defective products in a timely manner and reduce material waste. However, because the fan-out line sequence of products with reverse-order fanout (fanout in AA, FIAA) is disordered, the CT2 circuit in related technologies cannot detect short circuits in the fan-out lines of the regular display area. Summary of the Invention

[0003] This application provides a display panel, a short-circuit test method for the display panel, and a display device, which can detect short circuits in the fan-out lines of the conventional display area in a reverse-order FIAA display panel.

[0004] This application embodiment provides a display panel having a display area and a non-display area. The display area includes a first display area and a second display area arranged in a first direction, with the second display area near the edge of the display panel. The display panel includes:

[0005] Multiple first data lines are located in the first display area and are electrically connected to the first pixel unit of the first display area;

[0006] Multiple second data lines are located in the second display area and are electrically connected to the second pixel unit of the second display area;

[0007] Multiple first pads and multiple second pads are located in a non-display area, with the multiple second pads distributed among the multiple first pads in a first direction;

[0008] The first outgoing line is electrically connected between the first data line and the first pad;

[0009] The second outgoing line is electrically connected between the second data line and the second pad;

[0010] The first type of test terminal is electrically connected to the first data line through the first test control module;

[0011] The second type of test terminal is electrically connected to the second data line through the second test control module.

[0012] In some alternative implementations, the display panel includes a plurality of first data line groups, each first data line group including at least one first data line, and each first data line group being electrically connected to a first pixel unit;

[0013] The first type of test terminal includes a first test terminal and a second test terminal, and the first test control module includes a first switch and a second switch;

[0014] The first data line in the odd-numbered first data line group is electrically connected to the first test terminal through the first switch, and the first data line in the even-numbered first data line group is electrically connected to the second test terminal through the second switch.

[0015] In some optional implementations, at the same time during the first test sub-cycle, the signal at the first test terminal is at a first level, and the signal at the second test terminal is at a second level. The first level enables the first pixel unit to emit light, and the second level enables the first pixel unit to be in a black state.

[0016] In some alternative implementations, the first switch and the second switch are electrically connected to the same control signal line.

[0017] In some alternative implementations, the display panel includes a plurality of first data line groups, each first data line group including at least one first data line, and each first data line group being electrically connected to a first pixel unit;

[0018] The first type of test terminal includes a first test terminal and a second test terminal, and the first test control module includes a first switch and a second switch;

[0019] The first data line in the odd-numbered first data line group is electrically connected to the first test terminal through the first switch, and the first data line in the even-numbered first data line group is electrically connected to the second test terminal through the second switch.

[0020] In some optional implementations, at the same time during the first test sub-cycle, the signal at the first test terminal is at a first level, and the signal at the second test terminal is at a second level. The first level enables the first pixel unit to emit light, and the second level enables the first pixel unit to be in a black state.

[0021] In some alternative implementations, the first switch and the second switch are electrically connected to the same control signal line.

[0022] In some optional implementations, the first pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel with different emission colors, and the first data line group includes two first data lines, one of which is electrically connected to the first sub-pixel and the second sub-pixel, and the other is electrically connected to the third sub-pixel.

[0023] In some alternative implementations, the odd-numbered first data line group includes two first data lines, each of which is electrically connected to a first test terminal via at least one first switch;

[0024] In some alternative implementations, the two first data lines of the even-numbered first data line group are each electrically connected to the second test terminal via at least one second switch.

[0025] In some optional implementations, the second type of test terminal includes a third test terminal, and the second test control module includes a third switch;

[0026] Multiple second data lines are all connected to the third test terminal via a third switch.

[0027] In some alternative implementations, multiple second data lines are each electrically connected to a third test terminal via at least one third switch.

[0028] In some alternative implementations, the third test terminal may be multiplexed with either a high-level signal terminal or a low-level signal terminal.

[0029] In some alternative implementations, the display panel includes a plurality of second data line groups, each second data line group including at least one second data line.

[0030] Each second data line group is electrically connected to the second pixel unit;

[0031] The second type of test terminal includes the fourth test terminal and the fifth test terminal, and the second test control module includes the fourth switch and the fifth switch;

[0032] The second data line in the odd-numbered second data line group is electrically connected to the fourth test terminal through the fourth switch, and the second data line in the even-numbered second data line group is electrically connected to the fifth test terminal through the fifth switch.

[0033] In some alternative implementations, at the same time during the first test sub-cycle, the signal at the fourth test terminal is at a first level, and the signal at the fifth test terminal is at a second level. The first level enables the second pixel unit to emit light, and the second level enables the second pixel unit to be in a black state.

[0034] In some alternative implementations, the fourth and fifth switches are electrically connected to the same control signal line.

[0035] In some optional implementations, the second pixel unit includes a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel with different emission colors, and the second data line group includes two second data lines, one of which is electrically connected to the fourth sub-pixel and the fifth sub-pixel, and the other is electrically connected to the sixth sub-pixel.

[0036] In some alternative implementations, the two second data lines of the odd-numbered second data line group are each electrically connected to the fourth test terminal via at least one fourth switch.

[0037] In some alternative implementations, the two second data lines of the even-numbered second data line group are each electrically connected to the fifth test terminal via at least one fifth switch.

[0038] In some alternative implementations, the first test control module and the second test control module are electrically connected to the same control signal line.

[0039] In some optional implementations, N first pads are distributed between two adjacent second pads, where N is an integer greater than or equal to 1;

[0040] In some alternative implementations, N=1;

[0041] In some alternative implementations, N=2.

[0042] Based on the same inventive concept, in a second aspect, embodiments of this application also provide a short-circuit test method for a display panel, wherein a test cycle of the display panel includes a first test sub-cycle, and the method includes:

[0043] During the first test sub-cycle, the first test control module is turned on, and different level signals are provided to the first pixel units of two adjacent columns through the first type of test terminal;

[0044] The short circuit status of the display panel is determined based on the light emission status of the first pixel unit.

[0045] In some optional embodiments, the display panel includes a plurality of first data line groups, each first data line group including at least one first data line, and each first data line group being electrically connected to a first pixel unit; the first type of test terminal includes a first test terminal and a second test terminal, and the first test control module includes a first switch and a second switch; the first data line in the odd-numbered first data line group is electrically connected to the first test terminal through the first switch, and the first data line in the even-numbered first data line group is electrically connected to the second test terminal through the second switch;

[0046] During the first test sub-cycle, the first test control module is turned on, providing different level signals to the first pixel units of two adjacent columns through the first test terminal, including:

[0047] At the same moment within the first test sub-cycle, the first switch is turned on, and a first level is provided to the first pixel unit corresponding to the odd-numbered first data line group in the two adjacent columns through the first test terminal. The second switch is turned on, and a second level is provided to the first pixel unit corresponding to the even-numbered first data line group in the two adjacent columns through the second test terminal. The first level enables the first pixel unit to emit light, and the second level enables the first pixel unit to be in a black state.

[0048] Based on the light emission status of the first pixel unit, determine the short circuit status of the display panel, including:

[0049] If the first pixel units in two adjacent columns are both emitting light or both are black, it is determined that the first fan-out line is short-circuited.

[0050] In some alternative implementations, a test cycle of the display panel further includes a second test sub-cycle, and the method further includes:

[0051] At the same moment within the second test sub-cycle, the first switch is turned on, and a second level is provided to the first pixel unit corresponding to the odd-numbered first data line group in the two adjacent columns through the first test terminal; the second switch is turned on, and a first level is provided to the first pixel unit corresponding to the even-numbered first data line group in the two adjacent columns through the second test terminal.

[0052] During the first and second test sub-cycles, the second test control module is turned on to provide the same level signal to the second pixel units of the two adjacent columns through the second type of test terminal;

[0053] The short circuit status of the display panel is determined based on the light emission status of the second pixel unit.

[0054] In some optional implementations, the second type of test terminal includes a third test terminal, and the second test control module includes a third switch; multiple second data lines are all electrically connected to the third test terminal through the third switch;

[0055] During the first and second test sub-cycles, the second test control module is activated to provide the same level signal to the second pixel units of two adjacent columns through the second type of test terminal, including:

[0056] During the first and second test sub-cycles, the third switch is turned on, and a first level is provided to the second pixel units in the two adjacent columns through the third test terminal, wherein the first level enables the second pixel units to emit light.

[0057] Based on the emission status of the second pixel unit, determine the short circuit status of the display panel, including:

[0058] During the first test sub-cycle, if the second pixel units in at least one of the two adjacent columns are both in a black state, it is determined that the second fan-out line is short-circuited.

[0059] In some optional implementations, the second type of test terminal includes a third test terminal, and the second test control module includes a third switch; multiple second data lines are all electrically connected to the third test terminal through the third switch;

[0060] During the first and second test sub-cycles, the second test control module is activated to provide the same level signal to the second pixel units of two adjacent columns through the second type of test terminal, including:

[0061] During the first and second test sub-cycles, the third switch is turned on, and a second level is provided to the second pixel units of the two adjacent columns through the third test terminal, wherein the second level enables the second pixel units to be in a black state;

[0062] Based on the emission status of the second pixel unit, determine the short circuit status of the display panel, including:

[0063] During the first test sub-cycle, if the second pixel unit in at least one of the two adjacent columns is in a black state, it is determined that the second fan-out line is short-circuited.

[0064] According to the display panel, short-circuit test method and display device provided in the embodiments of this application, by setting a first type of test terminal and a second type of test terminal, that is, separating the test terminals of the first display area and the second display area (i.e., the FIAA area), even if the overall order of the first fan-out line and the second fan-out line is disordered, it will not affect the short-circuit detection of the first display area. Furthermore, by controlling the test signal of the first type of test terminal, the short-circuit condition of the fan-out line of the conventional display area (i.e., the first display area) in the reverse FIAA display panel can be detected. Attached Figure Description

[0065] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0066] Figure 1 A schematic diagram of a CT2 circuit in the related art is shown;

[0067] Figure 2 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application;

[0068] Figure 3 This illustration shows another structural diagram of the display panel provided in an embodiment of this application;

[0069] Figure 4 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application;

[0070] Figure 5 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application;

[0071] Figure 6 This diagram illustrates a timing diagram of a display panel provided in an embodiment of this application.

[0072] Figure 7 This illustration shows yet another structural diagram of the display panel provided in an embodiment of this application;

[0073] Figure 8 This is a schematic flowchart illustrating a short-circuit detection method for a display panel provided in an embodiment of this application;

[0074] Figure 9 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0075] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0076] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0077] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0078] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0079] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0080] like Figure 1 As shown, the CT2 circuit in the related technology includes a first pixel column 1, a second pixel column 2, a third pixel column 3, and a fourth pixel column 4. The first pixel column 1 and the third pixel column 3 each include a red sub-pixel R and a blue sub-pixel B, while the second pixel column 2 and the third pixel column 3 each include a green sub-pixel G. The first pixel column 1 and the second pixel column 2 are electrically connected to the first test signal line D1 via different data lines and different transistors M1, respectively. The third pixel column 3 and the fourth pixel column 4 are electrically connected to the second test signal line D2 via different data lines and different transistors M2, respectively. The gates of each transistor are electrically connected to the same switching signal line SW1. For example, during the fan-out line short-circuit test, the first test signal line D1 provides a low-level signal, and the second test signal line D2 provides a high-level signal. When there is no fan-out line short circuit, both the first pixel column 1 and the second pixel column 2 are illuminated, while the third pixel column 3 and the fourth pixel column 4 are both black, resulting in a black and white alternating test screen. When the fan-out line corresponding to the first pixel column 1 is short-circuited with the fan-out line corresponding to the third pixel column 3, the low level on the data line corresponding to the third pixel column 3 is pulled high, causing both the blue sub-pixel B and the red sub-pixel R on the third pixel column 3 to illuminate, resulting in a purple test screen corresponding to the third pixel column 3. That is, a purple line appears on the entire test screen of the display panel. In this way, it is possible to determine whether the fan-out line corresponding to the regular display area is short-circuited through the test screen.

[0081] The inventors discovered that for reverse-order FIAA display panels, because the overall order of the fan-out lines corresponding to the regular display area and the FIAA display area is disordered, testing using the aforementioned CT2 circuit and fan-out line short-circuit test method will result in abnormal image quality under normal circumstances. Alternatively, if the fan-out line connections are adjusted according to a normal black-and-white alternating image, it cannot be guaranteed that all short circuits in the fan-out lines will be detected. Therefore, the CT2 circuit in the related technology cannot detect short circuits in the fan-out lines of the regular display area.

[0082] To address the aforementioned issues, this application provides a display panel, a short-circuit testing method for the display panel, and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel, the short-circuit testing method for the display panel, and the display device.

[0083] Figure 2 This diagram illustrates a structural schematic of a display panel provided in an embodiment of this application. Figure 2As shown, the display panel 100 provided in this embodiment may include a display area AA and a non-display area NA. The display area AA can be used to display images, and the non-display area NA can be used to set up wiring, etc.

[0084] The display area AA may include a first display area AA1 and a second display area AA2 arranged in the first direction X, with the second display area AA2 located near the edge of the display panel. Figure 2 The following example illustrates the concept of display area AA, which includes one first display area AA1 and two second display areas AA2, with the first direction X being the row direction. However, this is not a limitation. The number of first display areas AA1 and the number of second display areas AA2 can be set according to the actual situation, and the first direction X can also be the column direction.

[0085] like Figures 3 to 5 As shown, the display panel 100 may include multiple first data lines 11, multiple second data lines 21, multiple first pads M1, multiple second pads M2, a first fan-out line 30, a second fan-out line 40, a first type of test terminal 50, and a second type of test terminal 60.

[0086] The first data line 11 can be located in the first display area AA1 and electrically connected to the first pixel unit 70 of the first display area AA1. The number of the first data lines 11 can be set according to the actual situation and is not limited here. For example, the number of the first data lines 11 can be 2, 3, 4, etc.

[0087] The second data line 21 can be located in the second display area AA2 and electrically connected to the second pixel unit 80 of the second display area AA2. The number of the second data lines 21 can be set according to the actual situation and is not limited here. For example, the number of the second data lines 21 can be 2, 3, 4, etc.

[0088] The number of first data lines 11 can be greater than or equal to the number of second data lines 21, and the number of first data lines 11 can also be less than the number of second data lines 21.

[0089] Both the first pad M1 and the second pad M2 can be located in the non-display area NA. In the first direction X, multiple second pads M2 can be distributed among multiple first pads M1. That is, the first pads M1 and the second pads M2 can be interspersed in the non-display area NA.

[0090] The number of first pads M1 can be greater than or equal to the number of second pads M2, or it can be less than the number of second pads M2; no limitation is made here.

[0091] It is worth noting that, Figure 2 The thickness of the lines is only to better distinguish between various data lines and fan-out lines, and is not used to limit the actual width of various data lines and fan-out lines.

[0092] Optionally, N first pads M1 can be distributed between two adjacent second pads M2, where N is an integer greater than or equal to 1.

[0093] As an example, N=1. That is, the first pad M1 and the second pad M2 are distributed alternately.

[0094] As another example, N=2.

[0095] The first fan-out line 30 can be electrically connected between the first data line 11 and the first pad M1. In this way, the driver IC can transmit data signals to the first data line 11 sequentially through the first pad M1 and the first fan-out line 30, so that the first pixel unit 70 electrically connected to the first data line 11 can drive the sub-pixels in the first pixel unit 70 to emit light according to the received data signals.

[0096] The number of first fan-outlines 30, the number of first data lines 11, and the number of first pads M1 can all be equal.

[0097] The second fan-out line 40 can be electrically connected between the second data line 21 and the second pad M2. In this way, the driver chip can transmit data signals to the second data line 21 sequentially through the second pad M2 and the second fan-out line 40, so that the second pixel unit 80 electrically connected to the second data line 21 can be driven to emit light in the sub-pixels of the second pixel unit 80 according to the received data signals.

[0098] The number of second fan-outlines 40, the number of second data lines 21, and the number of second pads M2 can all be equal.

[0099] The first type of test terminal 50 can be electrically connected to the first data line 11 through the first test control module 91. Under the control of the first test control module 91, the first type of test terminal 50 can provide signals from the first type of test terminal 50 to the first data line 11.

[0100] The second type of test terminal 60 can be electrically connected to the second data line 21 through the second test control module 92. Under the control of the second test control module 92, the second type of test terminal 60 can provide signals from the second type of test terminal 60 to the second data line 21.

[0101] Optionally, the first test control module 91 and the second test control module 92 can be electrically connected to the same control signal line SW2. This reduces the number of control signal lines SW2, lowers the cost of the display panel, and facilitates a narrow bezel design.

[0102] According to the display panel provided in the embodiments of this application, by setting a first type of test terminal and a second type of test terminal, that is, separating the test terminals of the first display area and the second display area (i.e., the FIAA area), even if the overall order of the first fan-out line and the second fan-out line is disordered, it will not affect the short circuit detection of the first display area. In this way, by controlling the test signal of the first type of test terminal, the short circuit of the fan-out line of the conventional display area (i.e., the first display area) in the reverse FIAA display panel can be detected.

[0103] In some alternative implementations, such as Figure 5 As shown, the display panel 100 may include multiple first data line groups 10, each first data line group 10 may include at least one first data line 11, and each first data line group 10 may be electrically connected to a first pixel unit 70. The first type of test terminal 50 may include a first test terminal 51 and a second test terminal 52, and the first test control module 91 may include a first switch K1 and a second switch K2; the first data line 11 in the odd-numbered first data line groups 10 is electrically connected to the first test terminal 51 through the first switch K1, and the first data line 11 in the even-numbered first data line groups 10 is electrically connected to the second test terminal 52 through the second switch K2.

[0104] For example, such as Figure 5 As shown, the first switch K1 can be the first transistor T1, and the second switch K2 can be the second transistor T2. The first data line 11 in the 2P+1th first data line group 10 can be electrically connected to the first test terminal 51 through the first transistor T1. That is, the first terminal of the first transistor T1 can be electrically connected to the first test terminal 51, and the second terminal of the first transistor T1 can be electrically connected to the first data line 11 in the 2P+1th first data line group 10. The first data line 11 in the 2P+2th first data line group 10 can be electrically connected to the second test terminal 52 through the second transistor T2. That is, the first terminal of the second transistor T2 can be electrically connected to the second test terminal 52, and the second terminal of the second transistor T2 can be electrically connected to the first data line 11 in the 2P+1th first data line group 10. Where P is a positive integer.

[0105] It is worth noting that in this application, the first terminal of the transistor can be either the source or the drain, and the second terminal of the transistor can be either the source or the drain. The transistors in this application can all be either N-type transistors or P-type transistors. The on-state level of an N-type transistor is high, and the off-state level is low; the on-state level of a P-type transistor is low, and the off-state level is high.

[0106] Thus, when the first transistor T1 is turned on, the signal of the first test terminal 51 can be transmitted through the first transistor T1 to the first data line 11 in the 2P+1 first data line group 10 to drive the sub-pixel in the first pixel unit 70 corresponding to the 2P+1 first data line group 10 to emit light or be in a black state; the signal of the second test terminal 52 can be transmitted through the first transistor T1 to the first data line 11 in the 2P+2 first data line group 10 to drive the sub-pixel in the first pixel unit 70 corresponding to the 2P+2 first data line group 10 to emit light or be in a black state.

[0107] In some alternative implementations, such as Figure 6 As shown, the test period t of the display panel may include a first test sub-period t1. At the same moment within the first test sub-period t1, the signal of the first test terminal 51 is at a first level, and the signal of the second test terminal 52 is at a second level. The first level enables the first pixel unit 70 to emit light, and the second level enables the first pixel unit 70 to be in a black state.

[0108] For example, in the embodiments of this application, the first level can be a low level and the second level can be a high level.

[0109] Understandably, when the first fan-out line 30 is not short-circuited, at the same moment within the first test sub-cycle t1, the first pixel unit 70 corresponding to the 2P+1th first data line group 10 emits light, while the first pixel unit 70 corresponding to the 2P+2th first data line group 10 remains black, resulting in a black and white alternating image on the test screen. When the first fan-out line 30 is short-circuited, an abnormal bright line appears in the first pixel unit 70 corresponding to the 2P+2th first data line group 10, thus enabling short-circuit detection of the first fan-out line 30. Furthermore, based on the location of the abnormal bright line, the location of the short-circuited first fan-out line 30 can be determined. This avoids the problem in related technologies where defective products with the first fan-out line 30 are carried over to the later manufacturing process, affecting the yield of the display device. This achieves short-circuit detection of the first fan-out line 30 in the reverse-order FIAA display panel, which is beneficial for improving the yield of the display device.

[0110] In other alternative implementations, such as Figure 6 As shown, the test period t of the display panel may also include a second test sub-period t2. At the same time as the second test sub-period t2, the signal of the first test terminal 51 is at the second level, and the signal of the second test terminal 52 is at the first level.

[0111] Understandably, when the first fan-out line 30 is not short-circuited, at the same moment within the second test sub-cycle t2, the first pixel unit 70 corresponding to the 2P+1th first data line group 10 is black, while the first pixel unit 70 corresponding to the 2P+2th first data line group 10 is lit, resulting in a black and white alternating image on the test screen. When the first fan-out line 30 is short-circuited, an abnormal dark line appears in the first pixel unit 70 corresponding to the 2P+2th first data line group 10, thus enabling short-circuit detection of the first fan-out line 30. Furthermore, based on the location of the abnormal dark line, the location of the short-circuited first fan-out line 30 can be determined. This avoids the problem in related technologies where defective products with the first fan-out line 30 are left in the later manufacturing process, affecting the yield of the display device. This achieves short-circuit detection of the first fan-out line 30 in the reverse-order FIAA display panel, which is beneficial for improving the yield of the display device.

[0112] In some alternative implementations, the first switch K1 and the second switch K2 can be electrically connected to the same control signal line SW2. By multiplexing the control signal line SW2 with the first switch K1 and the second switch K2, the number of control signal lines can be reduced, the cost of the display panel can be lowered, and it is beneficial to achieve a narrow bezel design.

[0113] like Figure 5 As shown, the gate of the first transistor T1 and the gate of the second transistor T3 can both be electrically connected to the same control signal line SW2.

[0114] In some optional implementations, the first pixel unit 70 may include a first sub-pixel R1, a second sub-pixel B1 and a third sub-pixel G1 with different emission colors, and the first data line group 10 may include two first data lines 11, one of which is electrically connected to the first sub-pixel R1 and the second sub-pixel B1, and the other is electrically connected to the third sub-pixel G1.

[0115] For example, such as Figure 5 As shown, both the 2P+1th and 2P+2th first data line groups 10 can include two first data lines 11. One of the first data lines 11 in the first data line group 10 can be electrically connected to a first sub-pixel R1 and a second sub-pixel B1, and the first sub-pixel R1 and the second sub-pixel B1 are alternately arranged in the second direction Y. The other first data line 11 in the first data line group 10 can be electrically connected to a third sub-pixel G1. In this embodiment, the second direction Y can be a column direction; in other embodiments, the second direction Y can also be a row direction.

[0116] The first sub-pixel R1 can be a red sub-pixel, the second sub-pixel B1 can be a blue sub-pixel, and the third sub-pixel G1 can be a green sub-pixel.

[0117] Optionally, the two first data lines 11 included in the odd-numbered first data line group 10 are each electrically connected to the first test terminal 51 via at least one first switch K1.

[0118] As an example, such as Figure 5 As shown, the two first data lines 11 of the 2P+1th first data line group 10 can each be electrically connected to the first test terminal 51 through a first transistor T1. That is, each of the two first data lines 11 in the 2P+1th first data line group 10 can be connected in series with a first transistor T1 to the first test terminal 51.

[0119] As another example, the two first data lines 11 of the 2P+1th first data line group 10 can each be electrically connected to the first test terminal 51 through two first transistors T1. That is, each of the two first data lines 11 in the 2P+1th first data line group 10 can be connected in series with two first transistors T1 to the first test terminal 51.

[0120] The number of first switches K1 connected in series between each of the two first data lines 11 in the odd-numbered first data line group 10 and the first test terminal 51 can be set according to the actual situation and is not limited here.

[0121] Optionally, the even-numbered first data line group 10 includes two first data lines 11, each electrically connected to the second test terminal 52 via at least one second switch K2.

[0122] As an example, such as Figure 5 As shown, the two first data lines 11 of the 2P+2nd first data line group 10 can each be electrically connected to the second test terminal 52 through a second transistor T2. That is, a second transistor T2 can be connected in series between each of the two first data lines 11 of the 2P+2nd first data line group 10 and the second test terminal 52.

[0123] As another example, the two first data lines 11 of the 2P+2th first data line group 10 can each be electrically connected to the second test terminal 52 via two second transistors T2. That is, each of the two first data lines 11 in the 2P+2th first data line group 10 can be connected in series with two second transistors T2 to the second test terminal 52.

[0124] The number of second switches K2 connected in series between each of the two first data lines 11 in the even-numbered first data line group 10 and the second test terminal 52 can be set according to the actual situation and is not limited here.

[0125] In some alternative implementations, the second type of test terminal 60 may include a third test terminal 61, the second test control module 92 may include a third switch K3, and multiple second data lines 20 may be electrically connected to the third test terminal 61 through the third switch K3.

[0126] For example, such as Figure 5 As shown, the third switch K3 may include a third transistor T3. The first terminal of the third transistor T3 may be electrically connected to the second data line 20, and the second terminal of the third transistor T3 may be electrically connected to the third test terminal 61. Thus, when the third transistor T3 is turned on, the signal from the third test terminal 61 can be transmitted to the second data line 20 through the third transistor T3, thereby driving the sub-pixels in the second pixel unit 80 to emit light or appear black.

[0127] In some alternative implementations, multiple second data lines 21 are each electrically connected to a third test terminal 61 via at least one third switch K3.

[0128] As an example, such as Figure 5 As shown, each of the multiple second data lines 21 can be electrically connected to the third test terminal 61 through a third transistor T3. That is, each of the multiple second data lines 21 can be connected in series with the third test terminal 61 via a third transistor T3.

[0129] As another example, multiple second data lines 21 can each be electrically connected to a third test terminal 61 via two third transistors T3. That is, each of the multiple second data lines 21 can be connected in series with two third transistors T3 to the third test terminal 61.

[0130] The number of third switches K3 connected in series between each of the multiple second data lines 21 and the third test terminal 61 can be set according to the actual situation and is not limited here.

[0131] Optionally, the first switch K1, the second switch K2, and the third switch K3 can share the same control signal line SW2. This reduces the number of control signal lines SW2, lowers the cost of the display panel, and facilitates a narrow bezel design.

[0132] Optionally, the third test terminal 61 can be multiplexed with either a high-level signal terminal or a low-level signal terminal, thus eliminating the need to increase the number of fan-out package pins.

[0133] In some optional embodiments, the display panel 100 may include a plurality of second data line groups 20, each second data line group 20 may include at least one second data line 21, and each second data line group 21 may be electrically connected to a second pixel unit 80; the second type of test terminal 60 may include a fourth test terminal 62 and a fifth test terminal 63, and the second test control module 92 may include a fourth switch K4 and a fifth switch K5; the second data line 21 in the odd-numbered second data line groups 20 may be electrically connected to the fourth test terminal 62 through the fourth switch K4, and the second data line 21 in the even-numbered second data line groups 20 may be electrically connected to the fifth test terminal 63 through the fifth switch K5.

[0134] For example, such as Figure 7 As shown, the fourth switch K4 can be the fourth transistor T4, and the fifth switch K5 can be the fifth transistor T5. The second data line 21 in the 2Q+1th second data line group 20 can be electrically connected to the fourth test terminal 62 through the fourth transistor T4. That is, the first terminal of the fourth transistor T4 can be electrically connected to the fourth test terminal 62, and the second terminal of the fourth transistor T4 can be electrically connected to the second data line 21 in the 2Q+1th second data line group 20. The second data line 21 in the 2Q+2th second data line group 20 can be electrically connected to the fifth test terminal 63 through the fifth transistor T5. That is, the first terminal of the fifth transistor T5 can be electrically connected to the fifth test terminal 63, and the second terminal of the fifth transistor T5 can be electrically connected to the second data line 21 in the 2Q+1th second data line group 20. Here, Q is a positive integer, and Q can be equal to or different from P.

[0135] Thus, when the fourth transistor T4 is turned on, the signal from the fourth test terminal 62 can be transmitted through the fourth transistor T4 to the second data line 21 within the second data line group 20 of the 2Q+1th second data line group 20, so as to drive the sub-pixel within the second pixel unit 80 corresponding to the second data line group 20 to emit light or appear black; the signal from the fifth test terminal 63 can be transmitted through the fifth transistor T5 to the second data line 21 within the second data line group 20 of the 2Q+2th second data line group 20, so as to drive the sub-pixel within the second pixel unit 80 corresponding to the second data line group 20 to emit light or appear black.

[0136] In some alternative implementations, such as Figure 7 As shown, at the same moment within the first test sub-cycle t1, the signal of the fourth test terminal 62 is at the first level, and the signal of the fifth test terminal 63 is at the second level. The first level enables the second pixel unit 80 to emit light, and the second level enables the second pixel unit 80 to be in a black state.

[0137] Understandably, when the second fan-out line 40 is not short-circuited, at the same moment within the first test sub-cycle t1, the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 emits light, while the second pixel unit 80 corresponding to the 2Q+2th second data line group 20 remains black, resulting in a black and white alternating image on the test screen. When the second fan-out line 40 is short-circuited, an abnormal bright line appears in the second pixel unit 80 corresponding to the 2Q+2th second data line group 20, thus enabling short-circuit detection of the second fan-out line 40. Furthermore, based on the location of the abnormal bright line, the location of the short-circuited second fan-out line 40 can be determined. This avoids the problem in related technologies where defective products with the second fan-out line 40 are carried over to the later manufacturing process, affecting the yield of the display device. This achieves short-circuit detection of the second fan-out line 40 in the reverse-order FIAA display panel, which is beneficial for improving the yield of the display device.

[0138] In other alternative implementations, such as Figure 6 As shown, at the same moment within the second test sub-cycle t2, the signal at the fourth test terminal 62 is at the second level, and the signal at the fifth test terminal 63 is at the first level.

[0139] Understandably, when the second fan-out line 40 is not short-circuited, at the same moment within the first test sub-cycle t1, the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 is black, while the second pixel unit 80 corresponding to the 2Q+2th second data line group 20 is lit, resulting in a black and white alternating image on the test screen. When the second fan-out line 40 is short-circuited, an abnormal dark line appears in the second pixel unit 80 corresponding to the 2Q+2th second data line group 20, thus enabling short-circuit detection of the second fan-out line 40. Furthermore, based on the location of the abnormal dark line, the location of the short-circuited second fan-out line 40 can be determined. This avoids the problem in related technologies where defective products with the second fan-out line 40 are carried over to the later manufacturing process, affecting the yield of the display device. This achieves short-circuit detection of the second fan-out line 40 in the reverse-order FIAA display panel, which is beneficial for improving the yield of the display device.

[0140] Optionally, the fourth switch K4 and the fifth switch K5 can be electrically connected to the same control signal line SW2. By multiplexing the control signal line SW2 between the fourth switch K4 and the fifth switch K5, the number of control signal lines can be reduced, the cost of the display panel can be lowered, and a narrow bezel design can be achieved.

[0141] like Figure 7 As shown, the gates of the fourth transistor T4 and the fifth transistor T5 can both be electrically connected to the same control signal line SW2.

[0142] Optionally, the second pixel unit may include a fourth sub-pixel R2, a fifth sub-pixel B2, and a sixth sub-pixel G2 with different emission colors. The second data line group 20 may include two second data lines 21. One of the second data lines 21 in the second data line group 20 may be electrically connected to the fourth sub-pixel R2 and the fifth sub-pixel B2, and the other second data line may be electrically connected to the sixth sub-pixel G2.

[0143] For example, such as Figure 7 As shown, both the 2Q+1th and 2Q+2nd second data line groups 20 can include two second data lines 21. One of the second data lines 21 in the second data line group 20 can be electrically connected to the fourth sub-pixel R2 and the fifth sub-pixel B2, and the fourth sub-pixel R2 and the fifth sub-pixel B2 are alternately arranged in the second direction Y. The other second data line 21 in the second data line group 20 can be electrically connected to the sixth sub-pixel G2.

[0144] The fourth sub-pixel R2 can be a red sub-pixel, the fifth sub-pixel B2 can be a blue sub-pixel, and the sixth sub-pixel G2 can be a green sub-pixel.

[0145] Optionally, the odd-numbered second data line group 20 may include two second data lines 21, each electrically connected to a fourth test terminal 62 via at least one fourth switch K4.

[0146] As an example, such as Figure 7 As shown, the two second data lines 21 of the 2Q+1th second data line group 20 can each be electrically connected to the fourth test terminal 62 through a fourth transistor T4. That is, each of the two second data lines 21 in the 2Q+1th second data line group 20 can be connected in series with the fourth test terminal 62 through a fourth transistor T4.

[0147] As another example, the two second data lines 21 of the 2Q+1th second data line group 20 can each be electrically connected to the fourth test terminal 62 via two fourth transistors T4. That is, each of the two second data lines 21 in the 2Q+1th second data line group 20 can be connected in series with two fourth transistors T4 to the fourth test terminal 62.

[0148] The number of fourth switches K4 connected in series between each of the two second data lines 21 in the odd-numbered second data line group 20 and the fourth test terminal 62 can be set according to the actual situation and is not limited here.

[0149] Optionally, the two second data lines 21 included in the even-numbered second data line group 20 can each be electrically connected to the fifth test terminal 63 via at least one fifth switch K5.

[0150] As an example, such as Figure 7 As shown, the two second data lines 21 of the 2Q+2nd second data line group 20 can each be electrically connected to the fifth test terminal 63 through a fifth transistor T5. That is, each of the two second data lines 21 in the 2Q+1th second data line group 20 can be connected in series with the fifth test terminal 63 through a fifth transistor T5.

[0151] As another example, the two second data lines 21 of the 2Q+2nd second data line group 20 can each be electrically connected to the fifth test terminal 63 via two fifth transistors T5. That is, each of the two second data lines 21 in the 2Q+2nd second data line group 20 can be connected in series with two fifth transistors T5 to the fifth test terminal 63.

[0152] The number of fifth switches K5 connected in series between each of the two second data lines 21 in the even-numbered second data line group 20 and the fifth test terminal 63 can be set according to the actual situation and is not limited here.

[0153] It should be noted that in the embodiments of this application, all first fan-out lines 30 and all second fan-out lines 40 can be located in the same film layer, or adjacent fan-out lines can be located in different film layers, which is not limited here. For example, as Figure 5 As shown, in the 2P+1th first data line group 10, one first fan-out line 30 adjacent to the 2Q+1th second data line group 20 can be located in the first metal layer; another first fan-out line 30 in the 2P+1th first data line group 10 can be located in the second metal layer; a second fan-out line 40 in the 2Q+1th second data line group 20 adjacent to the 2P+1th first data line group 10 can be located in the first metal layer; a first fan-out line 30 in the 2P+2th first data line group 10 adjacent to the 2P+1th first data line group 10 can be located in the second metal layer; another first fan-out line 30 in the 2P+2th first data line group 10 can be located in the first metal layer; and another second fan-out line 40 in the 2Q+1th second data line group 20 can be located in the second metal layer.

[0154] Based on the same inventive concept, this application also provides a short-circuit test method for a display panel, which is described below.

[0155] Figure 8 This diagram illustrates a flow chart of a short-circuit testing method for a display panel provided in an embodiment of this application.

[0156] The short-circuit test method for the display panel provided in this application embodiment can be applied to the display panel in the above embodiments. One test cycle of the display panel may include a first test sub-cycle, such as... Figure 8 As shown, the short-circuit test method for the display panel may include S810 to S820.

[0157] S810: During the first test sub-cycle, control the first test control module to turn on, and provide different level signals to the first pixel units of two adjacent columns through the first type of test terminal.

[0158] S820: Determine the short circuit status of the display panel based on the light emission status of the first pixel unit.

[0159] According to the short-circuit testing method for display panels provided in the embodiments of this application, during the first test sub-cycle, the first test control module is controlled to provide different level signals to the first pixel units of two adjacent columns through the first type of test terminal. Based on the light emission status of the first pixel units, the short-circuit status of the display panel can be determined. This avoids the problem in related technologies where defective products with the first fan-outline are left in the later manufacturing process, thus affecting the yield of the display device. This method realizes short-circuit detection of the first fan-outline in the reverse FIAA display panel, which is beneficial to improving the yield of the display device.

[0160] The following describes S810 to S820 in conjunction with specific implementation methods.

[0161] First, let's introduce the S810.

[0162] In some alternative implementations, S810 may include S811.

[0163] S811. At the same time within the first test sub-cycle, control the first switch to turn on, and provide a first level to the first pixel unit corresponding to the odd-numbered first data line group in the two adjacent columns through the first test terminal; control the second switch to turn on, and provide a second level to the first pixel unit corresponding to the even-numbered first data line group in the two adjacent columns through the second test terminal; wherein, the first level enables the first pixel unit to emit light, and the second level enables the first pixel unit to be in a black state.

[0164] As an example, such as Figure 5 and Figure 6 As shown, at the same moment within the first test sub-cycle t1, the first transistor T1 is turned on, and a low level is provided to the first pixel unit 70 corresponding to the 2P+1th first data line group 10 through the first test terminal 51. The second transistor T2 is turned on, and a high level is provided to the first pixel unit 70 corresponding to the 2P+2th first data line group 10 through the second test terminal 52.

[0165] Next, let's introduce the S820.

[0166] In some alternative implementations, S820 may include S821.

[0167] S821. If the first pixel units of two adjacent columns are both emitting light or both are in a black state, determine that the first fan-out line is short-circuited.

[0168] In the short-circuit test of the display panel, when there is no short circuit in the first fan-out line 30, at the same moment within the first test sub-cycle t1, the first pixel unit 70 corresponding to the 2P+1 first data line group 10 is in a black state, and the first pixel unit 70 corresponding to the 2P+2 first data line group 10 is illuminated. The test screen includes at least one dark line corresponding to the 2P+1 first data line group 10 and one bright line corresponding to the 2P+2 first data line group 10. If there is a short circuit in two adjacent columns of first fan-out lines 30, the first pixel unit 70 corresponding to the 2P+2 first data line group 10 receives a high level due to the short circuit, causing the first pixel unit 70 corresponding to the 2P+2 first data line group 10 to illuminate; or, the first pixel unit 70 corresponding to the 2P+1 first data line group 10 receives a high level due to the short circuit, causing the first pixel unit 70 corresponding to the 2P+1 first data line group 10 to illuminate. Thus, the test screen includes at least one bright line corresponding to the 2P+1th first data line group 10 and one bright line corresponding to the 2P+2th first data line group 10. That is, if there are two adjacent bright lines on the display panel, the first fan-out line 30 is determined to be short-circuited. Based on the positions of at least two consecutive columns of bright lines, the location of the first fan-out line where the short circuit occurs can be determined, realizing short-circuit detection of the first fan-out line in the reverse FIAA display panel, which is beneficial to improving the yield of the display device.

[0169] For example, such as Figure 2 , Figure 5 and Figure 6As shown, taking the short circuit of the first fan-out line 30 corresponding to the two adjacent columns of first data lines 10 electrically connected to the third sub-pixel G1 as an example, at the same moment within the first test sub-cycle t1, the first transistor T1 is controlled to be turned on, and a high level is provided to the first pixel unit 70 corresponding to the 2P+1th first data line group 10 through the first test terminal 51. The second transistor T2 is controlled to be turned on, and a low level is provided to the first pixel unit 70 corresponding to the 2P+2th first data line group 10 through the second test terminal 52. Because the first fan-out line 30 in the first pixel unit 70 corresponding to the 2P+1 first data line group 10, which is electrically connected to the third sub-pixel G1, is short-circuited with the first fan-out line 30 in the first pixel unit 70 corresponding to the 2P+2 first data line group 10, the third sub-pixel G1 in the first pixel unit 70 corresponding to the 2P+2 first data line group 10 emits light, and an abnormal green bright line appears in the third sub-pixel G1 in the first pixel unit 70 corresponding to the 2P+2 first data line group 10 in the test screen. Therefore, by observing whether an abnormal green image appears in the test screen and the location of the abnormal green bright line, it can be determined whether the first fan-out line 30 is short-circuited and the location of the short-circuited first fan-out line 30.

[0170] In some alternative implementations, the short-circuit test method for the display panel may also include S830 to S850.

[0171] S830, at the same moment within the second test sub-cycle, control the first switch to turn on, and provide a second level to the first pixel unit corresponding to the odd-numbered first data line group in the two adjacent columns through the first test terminal; control the second switch to turn on, and provide a first level to the first pixel unit corresponding to the even-numbered first data line group in the two adjacent columns through the second test terminal.

[0172] S840: During the first test sub-cycle and the second test sub-cycle, the second test control module is turned on, and the same level signal is provided to the second pixel units of the two adjacent columns through the second type of test terminal.

[0173] S850: Determine the short circuit status of the display panel based on the light emission status of the second pixel unit.

[0174] In the embodiments of this application, by providing the same level signal to the second pixel units in two adjacent columns during the first and second test sub-cycles, providing a first level to the first pixel units corresponding to the odd-numbered first data line groups in the two adjacent columns during the first test sub-cycle, providing a second level to the first pixel units corresponding to the even-numbered first data line groups in the two adjacent columns, and providing a second level to the first pixel units corresponding to the odd-numbered first data line groups in the two adjacent columns during the first test sub-cycle, and providing a first level to the first pixel units corresponding to the even-numbered first data line groups in the two adjacent columns, the short-circuit condition of the display panel can be determined based on the light emission status of the second pixel units. This achieves short-circuit detection of the second fan-out line in the reverse-order FIAA display panel, which is beneficial to improving the yield of the display device.

[0175] In S830, for example, as follows Figure 2 , Figure 5 and Figure 6 As shown, at the same moment within the second test sub-cycle t2, the first transistor T1 is turned on, and a high level is provided to the first pixel unit 70 corresponding to the 2P+1th first data line group 10 through the first test terminal 51. The second transistor T2 is turned on, and a low level is provided to the first pixel unit 70 corresponding to the 2P+2th first data line group 10 through the second test terminal 52.

[0176] In some alternative implementations, S840 may include S841, and S850 may include S851.

[0177] S841. During the first test sub-cycle and the second test sub-cycle, the third switch is turned on, and a first level is provided to the second pixel units of the two adjacent columns through the third test terminal, wherein the first level enables the second pixel units to emit light.

[0178] S851. During the first test sub-cycle, if the second pixel units of at least one of the two adjacent columns are both in a black state, it is determined that the second fan-out line is short-circuited.

[0179] In S841, for example, as follows Figure 6 and Figure 7 As shown, during the first test sub-cycle t1 and the second test sub-cycle t2, the third transistor T3 is turned on, and a low level is provided to the second pixel unit 80 corresponding to the second data line group 20 and the second pixel unit 80 corresponding to the second data line group 20 through the third test terminal 61.

[0180] When the second fan-out line 40 and the first fan-out line 30 are not short-circuited, the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 and the second pixel unit 80 corresponding to the 2Q+2th second data line group 20 both emit light during the first test sub-cycle t1 and the second test sub-cycle t2. When the second fan-out line 40 of the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 is short-circuited with the first fan-out line 30 of the first pixel unit 70 corresponding to the 2P+2th first data line group 10, the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 receives a high level during the first test sub-cycle t1, causing the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 to be in a black state, and the position corresponding to the second pixel unit 80 of the 2Q+1th second data line group 20 appears black on the test screen. When the second fan-out line 40 of the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 is short-circuited with the first fan-out line 30 of the first pixel unit 70 corresponding to the 2P+2th first data line group 10, the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 receives a high-level signal during the second test sub-cycle t2. This causes the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 to appear in a black state, resulting in a dark line appearing at the position corresponding to the second pixel unit 80 of the 2Q+1th second data line group 20 on the test screen. Therefore, the presence of an abnormal dark line on the test screen can determine whether the second fan-out line 40 is short-circuited, and the location of the short-circuited second fan-out line can be determined based on the location of the abnormal dark line.

[0181] In some alternative implementations, S840 may include S842, and S850 may include S852.

[0182] S842, during the first test sub-cycle and the second test sub-cycle, control the third switch to be turned on, and provide a second level to the second pixel units of the two adjacent columns through the third test terminal, wherein the second level can make the second pixel unit black.

[0183] S852. During the first test sub-cycle, if the second pixel unit of at least one of the two adjacent columns emits light, it is determined that the second fan-out line is short-circuited.

[0184] In S842, for example, as follows Figure 5 and Figure 6 As shown, during the first test sub-cycle t1 and the second test sub-cycle t2, the third transistor T3 is turned on, and a high level is provided to the second pixel unit 80 corresponding to the second data line group 20 and the second pixel unit 80 corresponding to the second data line group 20 through the third test terminal 61.

[0185] In some optional implementations, when the second fan-out line 40 and the first fan-out line 30 are not short-circuited, the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 and the second pixel unit 80 corresponding to the 2Q+2th second data line group 20 are both in a black state during the first test sub-cycle t1 and the second test sub-cycle t2. When the second fan-out line 40 of the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 is short-circuited with the first fan-out line 30 of the first pixel unit 70 corresponding to the 2P+2th first data line group 10, the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 receives a low level during the first test sub-cycle t1, causing the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 to emit light, and a bright line appears at the position corresponding to the second pixel unit 80 of the 2Q+1th second data line group 20 on the test screen. When the second fan-out line 40 of the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 is short-circuited with the first fan-out line 30 of the first pixel unit 70 corresponding to the 2P+2th first data line group 10, during the second test sub-cycle t2, the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 receives a low-level signal, causing the second pixel unit 80 corresponding to the 2Q+1th second data line group 20 to emit light, resulting in a bright line appearing at the position corresponding to the second pixel unit 80 of the 2Q+1th second data line group 20 on the test screen. Therefore, whether the second fan-out line 40 is short-circuited can be determined by whether an abnormal bright line appears on the test screen, and the position of the short-circuited second fan-out line 40 can be determined by the position of the abnormal bright line.

[0186] It is worth noting that, in this embodiment of the application, the first sub-test period t1 is taken after the second sub-test period t2. In some other embodiments, the first sub-test period t1 may be before the second sub-test period t2.

[0187] In some optional implementations, the short-circuit test method for the display panel provided in this application embodiment may further include: S860 and S870.

[0188] S860: During the first test sub-cycle, control the second test module to turn on, provide the second type of test terminal, and provide different level signals to the second pixel units of the two adjacent columns.

[0189] S870: Determine the short circuit status of the display panel based on the light emission status of the second pixel unit.

[0190] In some alternative implementations, S860 may include S861, and S870 may include S871.

[0191] S861. At the same moment in the first test sub-cycle, control the fourth switch to turn on, provide the fourth test terminal, and provide the first level to the second pixel unit corresponding to the odd-numbered first data line group in the two adjacent columns. Control the fifth switch to turn on, and provide the second level to the second pixel unit corresponding to the even-numbered second data line group in the two adjacent columns through the fifth test terminal. The first level enables the second pixel unit to emit light, and the second level enables the second pixel unit to be in a black state.

[0192] The implementation and principle of S861 are similar to those of S811, and will not be repeated here.

[0193] S871. If the second pixel units in two adjacent columns are both emitting light or both are in a black state, determine that the second fan-out line is short-circuited.

[0194] The implementation method and principle of S871 are similar to those of S821, and will not be repeated here.

[0195] Based on the same inventive concept, this application also provides a display device, which will be described below with reference to the accompanying drawings.

[0196] Figure 9 This is a schematic diagram of a display device provided in an embodiment of this application.

[0197] like Figure 9 As shown, the display device 1000 provided in this application embodiment may include the display panel 100 in the above embodiment.

[0198] According to the display device provided in the embodiments of this application, by setting a first type of test terminal and a second type of test terminal, that is, separating the test terminals of the first display area and the second display area (i.e., the FIAA area), even if the overall order of the first fan-out line and the second fan-out line is disordered, it will not affect the short circuit detection of the first display area. Furthermore, by controlling the test signal of the first type of test terminal, the short circuit of the fan-out line of the conventional display area (i.e., the first display area) in the reverse FIAA display panel can be detected.

[0199] The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific description of the display panel in the above embodiments. This embodiment will not repeat the description here.

[0200] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized by, The display panel has a display area and a non-display area. The display area includes a first display area and a second display area arranged in a first direction, the second display area being near the edge of the display panel. The display panel includes: Multiple first data lines are located in the first display area and are electrically connected to the first pixel unit of the first display area; Multiple second data lines are located in the second display area and are electrically connected to the second pixel units of the second display area; Multiple first pads and multiple second pads are located in the non-display area, and in the first direction, multiple second pads are distributed among the multiple first pads; The first outgoing line is electrically connected between the first data line and the first pad; The second outgoing line is electrically connected between the second data line and the second pad. The first type of test terminal is electrically connected to the first data line through the first test control module; The second type of test terminal is electrically connected to the second data line via the second test control module; A test cycle of the display panel includes a first test sub-cycle and a second test sub-cycle. During the first test sub-cycle, the first test control module is turned on and provides different level signals to the first pixel units in two adjacent columns through the first type of test terminal. During the first and second test sub-cycles, the second test control module is turned on and provides the same level signal to the second pixel units in two adjacent columns through the second type of test terminal, so as to determine the short circuit status of the display panel based on the light emission status of the second pixel units; The second type of test terminal includes a third test terminal, and the second test control module includes a third switch; all of the multiple second data lines are electrically connected to the third test terminal through the third switch; During the first and second test sub-cycles, the second test control module is activated, providing the same level signal to the second pixel units in two adjacent columns through the second type of test terminal, including: During the first test sub-cycle and the second test sub-cycle, the third switch is turned on, and a first level is provided to the second pixel units in two adjacent columns through the third test terminal, wherein the first level enables the second pixel units to emit light; Determining the short-circuit status of the display panel based on the light emission status of the second pixel unit includes: During the first test sub-cycle, if at least one of the second pixel units in two adjacent columns is in a black state, it is determined that the second fan-out line is short-circuited. And / or, the second type of test terminal includes a third test terminal, and the second test control module includes a third switch; all of the multiple second data lines are electrically connected to the third test terminal through the third switch; During the first and second test sub-cycles, the second test control module is activated, providing the same level signal to the second pixel units in two adjacent columns through the second type of test terminal, including: During the first test sub-cycle and the second test sub-cycle, the third switch is turned on, and a second level is provided to the second pixel units in two adjacent columns through the third test terminal, wherein the second level enables the second pixel units to be in a black state; Determining the short-circuit status of the display panel based on the light emission status of the second pixel unit includes: During the first test sub-cycle, if at least one of the second pixel units in two adjacent columns emits light, it is determined that the second fan-out line is short-circuited.

2. The display panel of claim 1, wherein, The display panel includes a plurality of first data line groups, each first data line group including at least one first data line, and each first data line group is electrically connected to the first pixel unit. The first type of test terminal includes a first test terminal and a second test terminal, and the first test control module includes a first switch and a second switch; The first data line in the odd-numbered first data line group is electrically connected to the first test terminal through the first switch, and the first data line in the even-numbered first data line group is electrically connected to the second test terminal through the second switch.

3. The display panel according to claim 2, characterized in that, At the same moment within the first test sub-cycle, the signal at the first test terminal is at a first level, and the signal at the second test terminal is at a second level. The first level enables the first pixel unit to emit light, and the second level enables the first pixel unit to be in a black state.

4. The display panel according to claim 2, characterized in that, The first switch and the second switch are electrically connected to the same control signal line.

5. The display panel according to claim 2, characterized in that, The first pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel with different emission colors. The first data line group includes two first data lines. One of the first data lines in the first data line group is electrically connected to the first sub-pixel and the second sub-pixel, and the other first data line is electrically connected to the third sub-pixel.

6. The display panel according to claim 2, characterized in that, The odd-numbered first data line groups each include two first data lines that are electrically connected to the first test terminal via at least one first switch.

7. The display panel according to claim 2, characterized in that, The even-numbered first data line groups each include two first data lines that are electrically connected to the second test terminal via at least one second switch.

8. The display panel according to claim 1, characterized in that, Each of the plurality of second data lines is electrically connected to the third test terminal via at least one of the third switches.

9. The display panel according to claim 1, characterized in that, The third test terminal can be a high-level signal terminal or a low-level signal terminal.

10. The display panel according to any one of claims 1 to 7, characterized in that, The display panel includes multiple second data line groups, and each second data line group includes at least one second data line. Each of the second data line groups is electrically connected to the second pixel unit; The second type of test terminal includes a fourth test terminal and a fifth test terminal, and the second test control module includes a fourth switch and a fifth switch; The second data line in the odd-numbered second data line group is electrically connected to the fourth test terminal through the fourth switch, and the second data line in the even-numbered second data line group is electrically connected to the fifth test terminal through the fifth switch.

11. The display panel according to claim 10, characterized in that, At the same moment within the first test sub-cycle, the signal at the fourth test terminal is at a first level, and the signal at the fifth test terminal is at a second level. The first level enables the second pixel unit to emit light, and the second level enables the second pixel unit to be in a black state.

12. The display panel according to claim 10, characterized in that, The fourth switch and the fifth switch are electrically connected to the same control signal line.

13. The display panel according to claim 10, characterized in that, The second pixel unit includes a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel with different emission colors. The second data line group includes two second data lines. One of the second data lines in the second data line group is electrically connected to the fourth sub-pixel and the fifth sub-pixel, and the other second data line is electrically connected to the sixth sub-pixel.

14. The display panel according to claim 10, characterized in that, The odd-numbered second data line groups each include two second data lines that are each electrically connected to the fourth test terminal via at least one of the fourth switches.

15. The display panel according to claim 10, characterized in that, The even-numbered second data line group includes two second data lines, each of which is electrically connected to the fifth test terminal via at least one of the fifth switches.

16. The display panel according to claim 1, characterized in that, The first test control module and the second test control module are electrically connected to the same control signal line.

17. The display panel according to claim 1, characterized in that, There are N first pads distributed between two adjacent second pads, where N is an integer greater than or equal to 1.

18. The display panel according to claim 17, characterized in that, N=1。 19. The display panel according to claim 17, characterized in that, N=2。 20. A short-circuit test method for a display panel, characterized in that, Applied to a display panel according to any one of claims 1 to 19, wherein a test cycle of the display panel includes a first test sub-cycle and a second test sub-cycle, the method includes: During the first test sub-cycle, the first test control module is turned on, and different level signals are provided to the first pixel units in two adjacent columns through the first type of test terminal; The short circuit status of the display panel is determined based on the light emission status of the first pixel unit; During the first test sub-cycle and the second test sub-cycle, the second test control module is turned on, and the same level signal is provided to the second pixel units in two adjacent columns through the second type of test terminal; The short circuit status of the display panel is determined based on the light emission status of the second pixel unit; The second type of test terminal includes a third test terminal, and the second test control module includes a third switch; all of the multiple second data lines are electrically connected to the third test terminal through the third switch; The step of controlling the second test control module to be turned on during the first test sub-cycle and the second test sub-cycle, and providing the same level signal to the second pixel units in two adjacent columns through the second type of test terminal, includes: During the first test sub-cycle and the second test sub-cycle, the third switch is turned on, and the first level is provided to the second pixel units in two adjacent columns through the third test terminal, wherein the first level enables the second pixel units to emit light; Determining the short-circuit status of the display panel based on the light emission status of the second pixel unit includes: During the first test sub-cycle, if at least one of the second pixel units in two adjacent columns is in a black state, it is determined that the second fan-out line is short-circuited. And / or, the second type of test terminal includes a third test terminal, and the second test control module includes a third switch; all of the multiple second data lines are electrically connected to the third test terminal through the third switch; The step of controlling the second test control module to be turned on during the first test sub-cycle and the second test sub-cycle, and providing the same level signal to the second pixel units in two adjacent columns through the second type of test terminal, includes: During the first test sub-cycle and the second test sub-cycle, the third switch is turned on, and the second level is provided to the second pixel units in two adjacent columns through the third test terminal, wherein the second level enables the second pixel units to be in a black state; Determining the short-circuit status of the display panel based on the light emission status of the second pixel unit includes: During the first test sub-cycle, if at least one of the second pixel units in two adjacent columns emits light, it is determined that the second fan-out line is short-circuited.

21. The short-circuit test method for a display panel according to claim 20, characterized in that, The display panel includes multiple first data line groups, each first data line group including at least one first data line, and each first data line group is electrically connected to the first pixel unit; the first type of test terminal includes a first test terminal and a second test terminal, and the first test control module includes a first switch and a second switch; the first data line in the odd-numbered first data line group is electrically connected to the first test terminal through the first switch, and the first data line in the even-numbered first data line group is electrically connected to the second test terminal through the second switch. During the first test sub-cycle, controlling the first test control module to be turned on, and providing different level signals to the first pixel units in two adjacent columns through the first test terminal, including: At the same moment within the first test sub-cycle, the first switch is turned on, and a first level is provided to the first pixel unit corresponding to the odd-numbered first data line group in the two adjacent columns through the first test terminal; the second switch is turned on, and a second level is provided to the first pixel unit corresponding to the even-numbered first data line group in the two adjacent columns through the second test terminal; wherein, the first level enables the first pixel unit to emit light, and the second level enables the first pixel unit to be in a black state. Determining the short-circuit status of the display panel based on the light emission status of the first pixel unit includes: If the first pixel units in two adjacent columns are both emitting light or both are black, it is determined that the first fan-out line is short-circuited.

22. The short-circuit test method for a display panel according to claim 21, characterized in that, One test cycle of the display panel further includes a second test sub-cycle, and the method further includes: At the same moment within the second test sub-cycle, the first switch is controlled to be turned on, and the second level is provided to the first pixel unit corresponding to the odd-numbered first data line group in the two adjacent columns through the first test terminal. The second switch is controlled to be turned on, and the first level is provided to the first pixel unit corresponding to the even-numbered first data line group in the two adjacent columns through the second test terminal.

23. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 19.

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