A fully differential low-offset high-gain operational amplifier

Abstract

The present invention belongs to the technical field of operational amplifiers, and particularly relates to a fully differential low-offset high-gain operational amplifier. The present invention includes an operational amplifier core and a feedforward common-mode feedback. The operational amplifier core amplifies the differential signal, and the feedforward common-mode feedback circuit stabilizes the common-mode voltage of the input and output. The present invention uses a floating-biased common-gate circuit and a high-gain NPN transistor series resistor as a current mirror, which significantly improves the gain, reduces the input offset voltage, and at the same time has a high output swing and good stability, and is suitable for use in an analog front-end programmable gain circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of operational amplifiers, and particularly relates to a fully differential low-offset high-gain operational amplifier. Background Art

[0002] As a basic module in analog and mixed-signal circuits, the most common application of a fully differential operational amplifier is used in the analog front-end circuit as a variable gain amplifier for analog front-end sampling. In some high-performance mixed circuits, the accuracy and noise performance of front-end sampling directly determine the performance of the entire chip. For the operational amplifier used in front-end sampling, high gain and low offset determine the accuracy of front-end sampling. Moreover, various portable devices have strong requirements for low power consumption. Therefore, extensive research has been carried out on fully differential operational amplifiers with low offset, low noise, low power consumption, and high gain in the academic and industrial fields. Summary of the Invention

[0003] The purpose of the present invention is to provide a fully differential operational amplifier circuit with low power consumption, low noise, high gain, and low offset.

[0004] The technical solution adopted by the present invention is as follows:

[0005] A fully differential low-offset high-gain operational amplifier includes a gain stage circuit, an output stage circuit, a Miller compensation circuit, and a feedforward common-mode feedback circuit;

[0006] The gain stage circuit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a first triode Q1, a second triode Q2, a first resistor R1, and a second resistor R2; wherein the source of the third MOS transistor M3 is connected to the power supply, its gate is connected to the common-mode feedback output of the feedforward common-mode feedback circuit, and its drain is connected to the sources of the first MOS transistor M1 and the second MOS transistor M2; the gate of the first MOS transistor M1 is connected to the negative input terminal of the amplifier, and its drain is connected to the source of the fourth MOS transistor M4; the gate of the second MOS transistor M2 is connected to the positive input terminal of the amplifier, and its drain is connected to the source of the fifth MOS transistor M5; the gates of the fourth MOS transistor M4 and the fifth MOS transistor M5 are connected to a floating bias voltage, the drain of the fourth MOS transistor M4 is connected to the collector of the first triode Q1, and the drain of the fifth MOS transistor M5 is connected to the collector of the second triode Q2; the bases of the first triode Q1 and the second triode Q2 are connected to a bias voltage, the emitter of the first triode Q1 is grounded through the first resistor R1, and the emitter of the second triode Q2 is grounded through the second resistor R2;

[0007] The Miller compensation circuit includes a first capacitor C1, a second capacitor C2, a third resistor R3, and a fourth resistor R4. The output stage circuit includes a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, and a ninth MOS transistor M9. The source of the sixth MOS transistor M6 is connected to the power supply, and its drain is connected to the drain of the fourth MOS transistor M4 and the gate of the ninth MOS transistor M9 through the first capacitor C1 and the third resistor R3. The drain of the sixth MOS transistor M6 is also connected to the drain of the ninth MOS transistor M9, and the gate of the sixth MOS transistor M6 is connected to the feedforward output of the feedforward common-mode feedback circuit. The source of the seventh MOS transistor M7 is connected to the power supply, and its drain is connected to the drain of the fifth MOS transistor M5 and the gate of the eighth MOS transistor M8 through the second capacitor C2 and the fourth resistor R4. The gate of the seventh MOS transistor M7 is connected to the feedforward output of the feedforward common-mode feedback circuit. The sources of the eighth MOS transistor M8 and the ninth MOS transistor M9 are grounded.

[0008] The feedforward common-mode feedback circuit includes a third capacitor C3, a fourth capacitor C4, a fifth resistor R5, a sixth resistor R6, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a fourteenth MOS transistor M14. The third capacitor C3 and the fifth resistor R5 form a first parallel circuit. One end of the first parallel circuit is connected to the gate of the twelfth MOS transistor M12, and the other end is connected to the drain of the seventh MOS transistor M7. The fourth capacitor C4 and the sixth resistor R6 form a second parallel circuit. One end of the second parallel circuit is connected to the gate of the twelfth MOS transistor M12, and the other end is connected to the drain of the sixth MOS transistor M6. The source of the tenth MOS transistor M10 is connected to the power supply, its gate and drain are interconnected, and its drain is connected to the drain of the twelfth MOS transistor M12. The drain of the tenth MOS transistor M10 is the common-mode feedback output of the feedforward common-mode feedback circuit. The source of the eleventh MOS transistor M11 is connected to the power supply, its gate and drain are interconnected, and its drain is connected to the drain of the thirteenth MOS transistor M13. The drain of the eleventh MOS transistor M11 is the feedforward output of the feedforward common-mode feedback circuit. The gate of the thirteenth MOS transistor M13 is connected to the common-mode power supply. The source of the thirteenth MOS transistor M13 is connected to the source of the twelfth MOS transistor M12 and the drain of the fourteenth MOS transistor M14. The gate of the fourteenth MOS transistor M14 is connected to the bias voltage, and its source is grounded.

[0009] The drain of the sixth MOS transistor M6 is connected to the negative output terminal of the amplifier, and the drain of the seventh MOS transistor M7 is connected to the positive output terminal of the amplifier.

[0010] The beneficial effects of the present invention are as follows: The present invention improves the gain by using a common-gate stage and an NPN transistor. The common-gate stage uses a floating bias to increase the input voltage range. The NPN transistor plus a resistor as a current mirror also reduces the offset voltage and noise. The second stage uses a simple common-source stage with a feedforward common-mode feedback to improve the common-mode stability and the output voltage range. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is the schematic diagram of the fully differential low-offset high-gain operational amplifier provided by the present invention;

[0012] Figure 2 is the frequency response diagram of the fully differential low-offset high-gain operational amplifier provided by the present invention;

[0013] Figure 3 is the schematic diagram of the simulation result of the input offset voltage after 300 times of Monte Carlo simulation in the embodiment of the present invention;

[0014] Figure 4 is the noise frequency curve of the high fully differential low-offset high-gain operational amplifier provided by the present invention;

[0015] Figure 5 is the schematic diagram of the sine output simulation waveform when the embodiment of the present invention is connected in a closed-loop with a gain of 2 times. DETAILED DESCRIPTION OF THE INVENTION

[0016] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0017] Figure 1 is the schematic diagram of a fully differential low-offset high-gain operational amplifier provided by the present invention, including a first-stage gain stage, a second-stage output stage, a Miller compensation circuit, and a feedforward common-mode feedback. The first-stage gain stage uses a current mirror load composed of a common-gate stage, a PNP transistor, and a resistor to increase the output resistance of the first stage, thereby increasing the gain of the first stage. The common-gate transistor uses a floating bias, and the bias voltage VBP2 is 1.5V lower than the fixed drain voltage of M3. The current mirror is composed of Q1, Q2, R1, and R2, and the PNP transistor as the current mirror further reduces the mismatch voltage. The gate voltage of the bias current transistor in the first-stage gain stage is the common-mode feedback output VP1, which improves the common-mode stability. The second-stage output stage is a simple common-source circuit, and the current bias uses the feedforward common-mode feedback voltage output VP2 to form a common-mode feedforward feedback, which greatly improves the common-mode stability. The Miller compensation circuit uses a resistor-capacitor series connection to improve the differential-mode stability of the circuit. The feedforward common-mode feedback uses two pairs of resistor-capacitor voltage dividers to take the output common-mode voltage, uses a PMOS transistor connected in diode configuration as the load, and NMOS transistor pairs as the input to form a common-mode feedback with feedforward, where the voltage VCM is the reference common-mode level.

[0018] As Figure 1As shown, in the fully differential low-offset high-gain operational amplifier according to the embodiment of the present invention, MOS transistors M1 and M2 are input pair transistors with a relatively large transistor area, thereby reducing offset and noise. M4 and M5 are common-gate transistors, and the gate voltage VBP2 is fixed 1.5V lower than the source voltage of the input pair transistors to achieve floating biasing. The operational amplifier current mirror is composed of Q1, R1, Q2, and R2, and the presence of the resistors further improves the gain. The second stage is a simple common-source circuit, and MOS transistors M8 and M9 are the input transistors of the second stage, with a relatively small l. In order to reduce its overdrive voltage to achieve a relatively large output swing. The Miller compensation circuit composed of capacitors C1, C2 and resistors R3, R4 compensates the frequency response of the operational amplifier, and introduces an in-band zero point through resistors R3, R4, so that the operational amplifier has a phase margin of more than 60 degrees, stabilizing the working state.

[0019] Figure 1 The right is the feedforward common-mode feedback part of the present invention. The common-mode level of the output voltage is taken through C3, C4, R5, and R6, amplified by the common-mode input pair transistors M12 and M11, and the output common-mode feedback signal is fed back to the first-stage bias and the second-stage bias in the form of generating the mirror current of M10 and M11. The common-mode feedback voltage generated by M11 is directly transmitted to the output signals VOUTP and VOUTN through the second-stage bias transistors M6 and M7, so it becomes feedforward common-mode feedback. This feedback enables the common-mode level to be maintained stable while achieving high differential gain and low common-mode feedback power consumption. The common-mode feedback module only consumes a current of 6.03 μA, and the total power consumption of the present invention is only 58.35 μA.

[0020] Figure 2 It is the simulation result of the frequency characteristics of a fully differential low-offset high-gain operational amplifier. It can be seen that when the input resistance is 1 MΩ and the gain is set to 3.2 times, the gain is 118.51 dB and the phase margin is 81°. It can be seen that the technical effect of gain improvement is obvious.

[0021] Figure 3 It is the simulation result of the input offset voltage of 200 Monte Carlo simulations of a fully differential low-offset high-gain operational amplifier. The maximum offset voltage is only 183.4 μV, and the technical effect is obvious.

[0022] Figure 4 It is the noise frequency curve of the high fully differential low-offset high-gain operational amplifier provided by the present invention, and the integrated noise is only 276 μV in the range of 0.1 Hz - 10 KHz.

[0023] Figure 5 It is a schematic diagram of the sine output simulation waveform when the embodiment of the present invention is connected in a closed loop with a gain of 3.2 times; it can be seen that the output can reach an output swing of ±4V when the power supply voltage is 4.5V.

Claims

1. A fully differential low-offset high-gain operational amplifier, characterized in that, it includes a gain stage circuit, an output stage circuit, a Miller compensation circuit and a feed-forward common-mode feedback circuit; The gain stage circuit includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a first triode Q1, a second triode Q2, a first resistor R1 and a second resistor R2; wherein the source of the third MOS transistor M3 is connected to the power supply, its gate is connected to the common-mode feedback output of the feed-forward common-mode feedback circuit, and its drain is connected to the sources of the first MOS transistor M1 and the second MOS transistor M2; the gate of the first MOS transistor M1 is connected to the negative input terminal of the amplifier, and its drain is connected to the source of the fourth MOS transistor M4; the gate of the second MOS transistor M2 is connected to the positive input terminal of the amplifier, and its drain is connected to the source of the fifth MOS transistor M5; the gates of the fourth MOS transistor M4 and the fifth MOS transistor M5 are connected to a floating bias voltage, the drain of the fourth MOS transistor M4 is connected to the collector of the first triode Q1, and the drain of the fifth MOS transistor M5 is connected to the collector of the second triode Q2; the bases of the first triode Q1 and the second triode Q2 are connected to a bias voltage, the emitter of the first triode Q1 is grounded after passing through the first resistor R1, and the emitter of the second triode Q2 is grounded after passing through the second resistor R2; The Miller compensation circuit includes a first capacitor C1, a second capacitor C2, a third resistor R3 and a fourth resistor R4, and the output stage circuit includes a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8 and a ninth MOS transistor M9; Wherein the source of the sixth MOS transistor M6 is connected to the power supply, its drain is connected to the drain of the fourth MOS transistor M4 and the gate of the ninth MOS transistor M9 after passing through the first capacitor C1 and the third resistor R3, the drain of the sixth MOS transistor M6 is also connected to the drain of the ninth MOS transistor M9, and the gate of the sixth MOS transistor M6 is connected to the feed-forward output of the feed-forward common-mode feedback circuit; the source of the seventh MOS transistor M7 is connected to the power supply, its drain is connected to the drain of the fifth MOS transistor M5 and the gate of the eighth MOS transistor M8 after passing through the second capacitor C2 and the fourth resistor R4, and the gate of the seventh MOS transistor M7 is connected to the feed-forward output of the feed-forward common-mode feedback circuit; the sources of the eighth MOS transistor M8 and the ninth MOS transistor M9 are grounded; The feedforward common-mode feedback circuit includes a third capacitor C3, a fourth capacitor C4, a fifth resistor R5, a sixth resistor R6, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a fourteenth MOS transistor M14. Among them, the third capacitor C3 and the fifth resistor R5 form a first parallel circuit. One end of the first parallel circuit is connected to the gate of the twelfth MOS transistor M12, and the other end is connected to the drain of the seventh MOS transistor M7. The fourth capacitor C4 and the sixth resistor R6 form a second parallel circuit. One end of the second parallel circuit is connected to the gate of the twelfth MOS transistor M12, and the other end is connected to the drain of the sixth MOS transistor M6. The source of the tenth MOS transistor M10 is connected to the power supply, its gate and drain are interconnected, its drain is connected to the drain of the twelfth MOS transistor M12, and the drain of the tenth MOS transistor M10 is the common-mode feedback output of the feedforward common-mode feedback circuit. The source of the eleventh MOS transistor M11 is connected to the power supply, its gate and drain are interconnected, its drain is connected to the drain of the thirteenth MOS transistor M13, and the drain of the eleventh MOS transistor M11 is the feedforward output of the feedforward common-mode feedback circuit. The gate of the thirteenth MOS transistor M13 is connected to the common-mode power supply, and the source of the thirteenth MOS transistor M13 is connected to the source of the twelfth MOS transistor M12 and the drain of the fourteenth MOS transistor M14. The gate of the fourteenth MOS transistor M14 is connected to the bias voltage, and its source is grounded. The drain of the sixth MOS transistor M6 is connected to the negative output terminal of the amplifier, and the drain of the seventh MOS transistor M7 is connected to the positive output terminal of the amplifier.

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