A method and apparatus for data transmission

Abstract

This application provides a data transmission method and apparatus, relating to the field of communication technology, which can improve the flexibility of security control for mutual access between nodes on a PCIe bus. The method is applied to the root node or parent / child node in the PCIe topology tree corresponding to the PCIe bus. It receives transmission messages sent by a transmitting device, which includes any one of the root node, the parent / child node, or an endpoint device. The endpoint device is connected to the root node or the parent / child node, and the root node is connected to the system memory manager. When the transmission message is determined to be valid based on pre-acquired security configuration information, the transmission message is transmitted to the next device. The transmission message is a TLP message.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method and apparatus for data transmission. Background Technology

[0002] Typically, in computing devices, integrated circuits (ICs) capable of performing different computing functions are integrated into the device to meet various computing requirements. In the industry, these ICs integrated into a single computing device (such as graphics processing units (GPUs), network interface cards (NICs), and graphics cards) are usually interconnected via the high-speed peripheral component interconnect express (PCIe) bus. In the era of big data, there is an urgent need for privacy protection technologies that support computation and data-intensive (CDI) computing. From machine learning model training and inference to computing tasks supporting autonomous driving, these tasks are typically implemented in a massive computing system centered on a central processing unit (CPU), interconnected with various endpoint devices such as accelerators or dedicated devices via the PCIe bus. Communication between the CPU and endpoint devices, and between endpoint devices themselves, will become increasingly frequent, making the security of point-to-point communication on the PCIe bus increasingly important.

[0003] Currently, the security of inter-node access on the PCIe bus is mainly achieved through the following method: the sending device uses a transport layer packet (TLP) message as specified in the PCIe protocol to carry the integrity check value of the data access corresponding to the current TLP message, and then the receiving end verifies the result of this integrity check value to determine whether the data access corresponding to the current TLP message is legitimate.

[0004] However, adding an integrity check value to the TLP message inevitably increases the message overhead of the PCIe bus, thereby reducing the effective bandwidth utilization of the PCIe bus; furthermore, it places higher demands on the design of PCIe devices that support the calculation and verification mechanism of the integrity check value. In summary, in the existing scheme, the security control of mutual access between nodes on the PCIe bus relies entirely on the integrity check value, resulting in low flexibility. Summary of the Invention

[0005] This application provides a data transmission method and apparatus that can improve the flexibility of security control for mutual access between nodes on the PCIe bus.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] Firstly, a data transmission method is provided. This method is applied to the root node or parent / child node in the PCIe topology tree corresponding to the PCIe bus. Specifically, it includes the following steps: receiving a transmission message sent by a transmitting device, which includes any one of the root node, parent / child node, or endpoint device, wherein the endpoint device is connected to the root node or parent / child node, and the root node is connected to the system memory manager; and, if the transmission message is determined to be valid based on pre-acquired security configuration information, transmitting the transmission message to the next device, wherein the transmission message is a TLP message. In the data transmission method provided in the embodiments of this application, the PCIe security control device mainly verifies the validity of the transmitted TLP message through pre-set security configuration information. This security configuration information is flexibly configurable, therefore it is not necessary to change the content of the TLP message. Compared with existing technologies, it is not necessary to add a prefix and integrity check value to the TLP message, thus reducing the dependence on the prefix and integrity check value, reducing the requirement for PCIe devices to support the calculation and verification mechanism of integrity check values, and not increasing the message overhead of the PCIe bus, thus providing greater flexibility. Furthermore, since the security configuration information can be flexibly configured, it can reduce the risk of the prefix and integrity check value scheme being counterfeited due to design flaws compared to setting fixed prefixes and integrity check values.

[0008] In one possible implementation, before determining the legitimacy of the transmission message based on the pre-acquired security configuration information, the method further includes: acquiring a configuration access request; when it is determined that the configuration access request originates from the operating system under the Trusted Operating Environment (TEE), acquiring the security configuration information carried by the configuration access request, wherein the configuration access request is a TLP message. Furthermore, to ensure the security of the acquired security configuration information, embodiments of this application can provide a secure configuration interface for the trusted system software, allowing for more flexible configuration of security mechanisms on each node of the entire PCIe topology tree. The security configuration information can be configured and controlled by secure and trusted system software (trusted system software under the TEE) on the processor CPU. Thus, when the security configuration information is a TLP message targeting one or more specific leaf nodes on the PCIe topology tree, enclave protection for one or more specific leaf nodes on the PCIe topology tree can be provided.

[0009] In one possible implementation, before determining the legitimacy of a transmission message based on pre-acquired security configuration information, the process further includes: obtaining a configuration message containing security verification information from the configuration space of the root node or parent / child nodes; and, when the security verification information is determined to be legitimate, obtaining the security configuration information carried in the configuration message, which is a TLP message. The security configuration information of the PCIe security control device is implemented in the configuration space of the root node or parent / child nodes. Specifically, it is implemented in the Type 1 configuration space of the PCIe root port of the PCIe root federation (which acts as the root node) or in the configuration space of the uplink or downlink port of the PCIe switch (which acts as the parent / child nodes). Alternatively, the security configuration information is configured through an indirect access programming interface provided by a register group implemented in the configuration space of the parent node or parent / child nodes. In this case, the security configuration information is configured through a configuration message. The corresponding configuration message needs to contain security verification information. Only when the security verification information is determined to be legitimate will the security configuration information carried in the configuration message be allowed to take effect; otherwise, the configuration will not take effect. Trusted system software (such as software running on a TEE) needs to determine whether to include security verification information in the configuration message based on whether the access is secure.

[0010] In one possible implementation, before determining the legitimacy of the transmitted message based on pre-acquired security configuration information, the method further includes: acquiring a memory message generated by the processor CPU, wherein the memory message contains a memory message carrying security verification information; when the security verification information is determined to be legitimate, acquiring the security configuration information carried in the memory message, wherein the memory message is a TLP message. In this case, the security configuration information of the PCIe security control device is implemented in the base address space (BAR space) of the root node or the parent / child nodes. Specifically, it is implemented in the base address space (BAR space) of the PCIe root port of the PCIe root federation acting as the root node, or the uplink or downlink port of the PCIe switch acting as the parent / child nodes. At this time, the security configuration information of the PCIe security control device needs to be configured through PCIe memory messages (Memory TLP, specifically PCIe memory write TLP, PCIe MemWr TLP). The MemWr TLP message prefix needs to include security verification information. When the security verification information is determined to be valid, the security configuration information carried by the MemWr TLP message is obtained.

[0011] In one possible implementation, the destination address of the transmitted message is the root node; the security configuration information includes one or more requester identifiers to be matched; determining the legitimacy of the transmitted message based on the pre-acquired security configuration information includes: determining that the transmitted message is legitimate if the first requester identifier in the transmitted message is one of one or more requester identifiers to be matched. In this scheme, if the destination address of the transmitted message is the root node (e.g., a PCIe root union), then the transmitted message is an uplink data stream. The PCIe security control device determines the legitimacy of the transmitted message based on whether the first requester identifier in the transmitted message is one of one or more requester identifiers to be matched. Simultaneously, the PCIe security control device can also decide whether to perform other security checks based on the security configuration information, including but not limited to deciding whether to index the security table based on the requester identifier of the transmitted message, obtain information from the security table to check whether the requester with the corresponding requester identifier has permission to access the corresponding space, and what those permissions are, etc.

[0012] In one possible implementation, the destination address of the transmitted message is the root node; the security configuration information includes one or more requester IDs to be matched, and security entries corresponding one-to-one with the one or more requester IDs to be matched; determining the legitimacy of the transmitted message based on the pre-acquired security configuration information includes: indexing a first security entry based on the security configuration information and the first requester ID in the transmitted message, verifying the transmitted message based on the content of the first security entry, and determining the transmitted message to be legitimate after the verification passes. In this scheme, if the destination address of the transmitted message is the root node (e.g., a PCIe root union), then the transmitted message is an uplink data stream. An uplink security table is formed by one or more requester IDs to be matched (reqesterID) and security entries corresponding one-to-one with the one or more requester IDs to be matched; in this security table, the requester ID is used as the index for each security entry. Specifically, the PCIe security control device indexes the first security entry based on the security configuration information and the first requester ID in the transmitted message, verifies the transmitted message based on the content of the first security entry, and determines the transmitted message to be legitimate after the verification passes. For a security entry in the uplink security table, its content may include security information, whether a security page table is used, and other information. Security information includes whether the transport message corresponding to this requester ID is allowed to access the secure memory space, and whether the security attributes of the accessed memory space (e.g., secure world or normal world memory space) are determined by the page table or directly controlled by the configuration of this security entry. This security entry may also store control information such as whether the transport message corresponding to the requester ID requires a specific security page table and whether a page table lookup is required.

[0013] In one possible implementation, the destination address of the transmitted message is an endpoint device; the security configuration information includes one or more root port numbers to be matched; determining the legitimacy of the transmitted message based on the pre-acquired security configuration information includes: determining that the transmitted message is legitimate when the first root port number in the transmitted message is one of the one or more root port numbers to be matched. In this scheme, since the destination address of the transmitted message is an endpoint device, the transmitted message is a downlink data stream, and the PCIe security control device determines the legitimacy of the transmitted message based on whether the first root port number in the transmitted message is one of the one or more root port numbers to be matched.

[0014] In one possible implementation, the destination address of the transmitted message is an endpoint device; the security configuration information includes one or more root port numbers to be matched and security entries corresponding one-to-one with the one or more root port numbers to be matched; determining the validity of the transmitted message based on the pre-acquired security configuration information includes: indexing a second security entry based on the security configuration information and the first root port number in the transmitted message, verifying the transmitted message based on the content of the second security entry, and determining the transmitted message to be valid after the verification passes. In this scheme, since the destination address of the transmitted message is an endpoint device, the transmitted message is a downlink data stream. A downlink security table is formed by one or more root port numbers to be matched and security entries corresponding one-to-one with the one or more root port numbers to be matched; wherein, in this security entry table, the root port number is used as the index of each security entry. Specifically, the PCIe security control device indexes the second security entry based on the security configuration information and the first root port number in the transmitted message, verifies the transmitted message based on the content of the second security entry, and determines the transmitted message to be valid after the verification passes. In this case, the PCIe security control device on the last-level parent and child nodes can determine the legitimacy of the transmitted message solely by the root port number, without using the downlink security table; or it can use any of the bus number, device number, or function number of the leaf node (endpoint device) to index the security entry in the downlink security table.

[0015] In one possible implementation, the transmitted message includes a security signature configured by the root node according to security configuration information; the transmitted message is verified according to the content of a second security entry, including verifying the security signature of the transmitted message according to the content of the second security entry. In this scheme, the content of a security entry in the downlink security table includes a security signature corresponding to the root port number, and may also include security level and other information. For data streams output from the root node (e.g., a PCIe root union), the corresponding security entry in the downlink security table is indexed according to the outgoing root port number, and the content of the corresponding security entry is used to determine whether to mark the transmitted message with a security signature. The security signature of the transmitted message can be placed in a vendor-defined Type 1 prefix. The PCIe security control devices corresponding to all parent and child nodes under this topology tree need to recognize this Type 1 prefix of the transmitted message issued by the PCIe root union and perform parsing processing on the Type 1 prefix according to the provisions of the present invention.

[0016] Secondly, a PCIe security control device is provided, applied to the root node or parent / child node in the corresponding PCIe topology tree of the PCIe bus. The device includes: a receiving unit for receiving a transmission message sent by a sending device, wherein the sending device includes any one of the root node, the parent / child node, or an endpoint device, wherein the endpoint device is connected to the root node or the parent / child node, and the root node is connected to the system memory manager; and a processing unit for transmitting the transmission message to a next device through the sending unit when the transmission message is determined to be valid based on pre-acquired security configuration information, wherein the transmission message is a TLP message.

[0017] In one possible implementation, the processing unit is further configured to acquire a configuration access request, and when it is determined that the configuration access request comes from an operating system under a Trusted Operating Environment (TEE), acquire the security configuration information carried by the configuration access request, wherein the configuration access request is a TLP message.

[0018] In one possible implementation, the processing unit is further configured to obtain a configuration message in the configuration space of the root node or the parent / child node, the configuration message containing security verification information, and when the security verification information is determined to be valid, obtain the security configuration information carried by the configuration message, wherein the configuration message is a TLP message.

[0019] In one possible implementation, the processing unit is further configured to acquire a memory packet generated by the CPU, wherein the memory packet contains a memory packet carrying security verification information, and when the security verification information is determined to be valid, acquire the security configuration information carried in the memory packet, wherein the memory packet is a TLP packet.

[0020] In one possible implementation, the destination address of the transmission message is the root node; the security configuration information includes one or more requester identifiers to be matched; the processing unit is specifically used to determine that the transmission message is valid when the first requester identifier in the transmission message is one of the one or more requester identifiers to be matched.

[0021] In one possible implementation, the destination address of the transmission message is the root node; the security configuration information includes one or more requester identifiers to be matched, and security entries corresponding one-to-one with the one or more requester identifiers to be matched; the processing unit is specifically used to index out the first security entry based on the security configuration information and the first requester identifier in the transmission message, verify the transmission message based on the content of the first security entry, and determine that the transmission message is valid after the verification is passed.

[0022] In one possible implementation, the destination address of the transmission message is an endpoint device; the security configuration information includes one or more root port numbers to be matched; the processing unit is specifically used to determine that the transmission message is valid when the first root port number in the transmission message is one of the one or more root port numbers to be matched.

[0023] In one possible implementation, the destination address of the transmission message is an endpoint device; the security configuration information includes one or more root port numbers to be matched and security entries corresponding one-to-one with the one or more root port numbers to be matched; the processing unit is specifically used to index out a second security entry based on the security configuration information and the first root port number in the transmission message, verify the transmission message based on the content of the second security entry, and determine that the transmission message is valid after the verification is passed.

[0024] In one possible implementation, the transmission message includes a security signature configured by the root node according to the security configuration information; the processing unit is specifically used to verify the security signature of the transmission message according to the content of the second security entry.

[0025] Thirdly, a PCIe bus is provided, wherein the PCIe security control device provided in the second aspect above is applied to the root node or child / parent node in the PCIe topology tree corresponding to the PCIe bus.

[0026] Fourthly, an electronic device is provided, characterized in that it includes a PCIe bus as described in the third aspect, wherein an endpoint device is connected to the memory of the electronic device via the PCIe bus.

[0027] The technical effects of any of the possible implementations of the second, third, and fourth aspects can be found in the technical effects of the different implementations of the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0028] Figure 1 A schematic diagram of a TLP message provided for an embodiment of this application;

[0029] Figure 2 A schematic diagram of the structure of an electronic device provided for an embodiment of this application;

[0030] Figure 3 A flowchart illustrating a data transmission method provided for an embodiment of this application;

[0031] Figure 4 A schematic diagram illustrating a register group configuration method provided for an embodiment of this application;

[0032] Figure 5 A schematic diagram illustrating a method for obtaining security configuration information provided in an embodiment of this application;

[0033] Figure 6 A schematic diagram of a TLP message provided for another embodiment of this application;

[0034] Figure 7 A schematic diagram of a TLP message provided for yet another embodiment of this application;

[0035] Figure 8 A schematic diagram of a PCIe topology provided for an embodiment of this application;

[0036] Figure 9 A schematic diagram illustrating a data transmission method according to another embodiment of this application;

[0037] Figure 10 A schematic diagram of a PCIe topology provided for another embodiment of this application;

[0038] Figure 11 A schematic diagram of a TLP message provided for yet another embodiment of this application;

[0039] Figure 12 A schematic diagram of a data transmission method provided in another embodiment of this application;

[0040] Figure 13 A schematic diagram of a computing system provided for an embodiment of this application;

[0041] Figure 14 A schematic diagram illustrating a method for an endpoint device (EP) to switch from REE to TEE, provided as an embodiment of this application;

[0042] Figure 15 A schematic diagram illustrating a method for an endpoint device (EP) to exit a TEE, provided as an embodiment of this application;

[0043] Figure 16 This is a schematic diagram of the structure of a PCIe security control device provided for an embodiment of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0046] Typically, in computing devices, integrated circuits (ICs) capable of performing different computing functions are integrated into the device to meet various computing requirements. In the industry, these ICs integrated into a single computing device (such as graphics processing units (GPUs), network interface cards (NICs), and graphics cards) are usually interconnected via the high-speed peripheral component interconnect express (PCIe) bus. In the era of big data, there is an urgent need for privacy protection technologies that support computation and data-intensive (CDI) computing. From machine learning model training and inference to computing tasks supporting autonomous driving, these tasks are typically implemented in a massive computing system centered on a central processing unit (CPU), interconnected with various endpoint devices such as accelerators or dedicated devices via the PCIe bus. Communication between the CPU and endpoint devices, and between endpoint devices themselves, will become increasingly frequent, making the security of point-to-point communication on the PCIe bus increasingly important.

[0047] Currently, the security of inter-node access on the PCIe bus is mainly achieved through the following method: the sending device uses a transport layer packet (TLP) message as specified in the PCIe protocol to carry the integrity check value of the data access corresponding to the current TLP message, and then the receiving end verifies the result of this integrity check value to determine whether the data access corresponding to the current TLP message is legitimate.

[0048] Combination Figure 1As shown, a TLP message structure is provided, specifically including: a prefix field, where 100 is the prefix identifier. The prefix field carries the packet number and, following the packet payload, an integrity check value. The receiving end specifically verifies whether the data access corresponding to the current TLP message is legitimate based on the packet's sequence number and integrity check value. In addition, TLP messages typically contain other fields, such as the format (fmt) field and the type field. The format (fmt) field is usually used to determine whether the current TLP message is a 3-double word (DW) or 4-DW, and whether the current TLP message contains data. The type field is used to determine the type of request in the current TLP message. The format (fmt) field and the type (type) field together determine the transaction type of the current TLP message (e.g., the current TLP message is a memory read request (MRd), a memory read lock request (MRd), a memory write request (MWr), a type0 configuration read request (CfgRd0), a type1 configuration read request (CfgRd1), a type0 configuration write request (CfgWr0), and a type1 configuration write request (CfgWr1). (And of course, its transaction types, only a few are listed here as examples). The T9 field indicates the 9th symbol. The Tc field indicates the transmission type of the current TLP message. The PCIe bus specifies 8 transmission types, and the specific classification of each transmission type is related to the QoS of the PCIe bus. The Attr field includes 3 symbol bits, where the 2nd bit indicates whether the current TLP supports PCIe bus ID-based ordering; the 1st bit indicates whether it supports relaxed ordering; and the 0th bit indicates whether the current TLP needs to perform cache sharing consistency processing when it reaches memory through the PCIe root complex (RC). The AT field is a reserved field, mainly used for address translation related to the input / output memory management unit (IOMMU) system.The length field describes the size of the current TLP payload in bytes (DW). The requester ID field contains the bus number, device number, and function number of the PCIe device that generated the current TLP message; the device number is optional. The tag field is used to return a completion message for the current TLP message, providing a correspondence between the current TLP message and the completion message. The first and last DW enable (EN) fields are used because the PCIe bus transmits data in bytes, but the length field uses DW as the smallest unit. Therefore, the fast DW EN and last DW EN fields are used in the TLP message to enable bytes, ensuring that valid data in a TLP message is in bytes. Each of the two DW EN fields consists of 4 bits. Each bit of the last DW EN field corresponds to the enable bit of the last double-word byte of the data payload; while each bit of the first DW EN field corresponds to the enable bit of the first double-word byte of the data payload. The address [63:32] and address [31:2] fields indicate that the current TLP message uses a 64-bit wide memory, i.e., 4DW. When the current TLP message uses a 32-bit wide memory (3DW), the current TLP message only contains the address [31:2] fields. The above mainly addresses... Figure 1 The table illustrates the various fields of a typical TLP message. Of course, when processing different transactions, the TLP message may have other fields or omit some of the fields mentioned above.

[0049] However, adding the aforementioned prefix and integrity check value to the TLP message will inevitably increase the message overhead of the PCIe bus, thereby reducing the effective bandwidth utilization of the PCIe bus; and it places higher demands on the design of PCIe devices that support the calculation and verification mechanism of the integrity check value. In short, as Figure 1 The TLP message scheme shown makes the security control of inter-node access on the PCIe bus rely entirely on the prefix and integrity check value, resulting in low flexibility.

[0050] To address the aforementioned issues, the data transmission method provided in the embodiments of this application utilizes a PCIe security control device that primarily verifies the legitimacy of transmitted TLP messages through pre-set security configuration information. This security configuration information is flexibly configurable, thus eliminating the need to alter the content of the TLP messages. Compared to existing technologies, it avoids the need to add prefixes and integrity check values ​​to the TLP messages of the main transmitted data, thereby reducing reliance on prefixes and integrity check values ​​and lowering the requirements for PCIe devices to support integrity check value calculation and verification mechanisms. Furthermore, it does not increase the message overhead of the main transmitted data on the PCIe bus, resulting in greater flexibility. Moreover, because the security configuration information is flexibly configurable, it reduces the risk of counterfeiting due to design flaws in the prefix and integrity check value scheme compared to setting fixed prefixes and integrity check values. Additionally, the security configuration information can originate from the operating system within a trusted execution environment (TEE), or a security check can be performed on the security configuration information first, followed by verification of the TLP message's legitimacy after the security check passes, ensuring the security of TLP message-based mutual access between nodes on the PCIe bus. This avoids the security risks caused by other devices using insecure software to access the base address register (BAR) space of devices that do not belong to them via the CPU.

[0051] The application scenarios of the embodiments of this application are first introduced as follows:

[0052] Reference Figure 2 As shown, embodiments of this application provide an electronic device 100, which can be a mobile phone, tablet computer, personal computer (PC), personal digital assistant (PDA), smartwatch, netbook, wearable electronic device, augmented reality (AR) device, virtual reality (VR) device, in-vehicle device, smart car, smart speaker, robot, smart glasses, and other different types of electronic devices.

[0053] Figure 2 This is a schematic diagram of the structure of an electronic device 100 provided in an embodiment of this application. Figure 2As shown, electronic device 100 may include: processor 101, memory 102, memory management unit (MMU) 103, system memory management unit (SMMU) 104 (or input / output memory management unit, IOMMU), PCIe bus 105, and endpoint device 106. It is understood that the structure illustrated in this embodiment does not constitute a specific limitation on electronic device 100. In other embodiments, electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. For example, electronic device may also include: external memory interface, universal serial bus (USB) interface, charging management module, power management module, battery, antenna, mobile communication module, wireless communication module, audio module, speaker, receiver, microphone, headphone jack, sensor module, buttons, vibration motor, camera, display screen, subscriber identification module (SIM) card interface, indicator, etc.

[0054] Processor 101 may include one or more processing units, such as application processors (APs), modem processors, controllers, memory, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors. The processor can serve as the central nervous system and command center of electronic device 100. The processor can generate operation control signals based on instruction opcodes and timing signals to control instruction fetching and execution.

[0055] The processor 101 may also include memory for storing instructions and data. In some embodiments, the memory in the processor 101 is a cache memory (e.g., a cache). This memory can store instructions or data that the processor 101 has just used or that are used repeatedly. If the processor 101 needs to use the instruction or data again, it can retrieve it directly from the memory. This avoids repeated accesses, reduces the waiting time of the processor 101, and thus improves the efficiency of the system.

[0056] In some embodiments, the processor 101 may include one or more interfaces. Interfaces may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0057] The memory 102 can be used to store computer executable program code, which includes instructions. The processor 101 executes various functional applications and data processing of the electronic device 101 by running the instructions stored in the memory 102. For example, in this embodiment, the processor 101 can execute instructions stored in the memory 102, which may include a program storage area and a data storage area.

[0058] The program storage area can store the operating system, at least one application required for a function (such as a client application (CA), a trusted application (TA), a rich operating system (Rich OS), a trusted operating system (Trusted OS), etc.). The data storage area can store data created during the use of the electronic device 100 (such as security configuration information, TLP messages, etc.). Furthermore, the memory 102 can include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc. The processor 101 is connected to the memory 102 through the memory manager 103, and reads or writes data to the memory 102 through the memory manager 103.

[0059] Furthermore, the PCIe bus 105 of the electronic device 100 is used to connect the endpoint device 106 to the memory 102. Specifically, the endpoint device 106 reads or writes data to the memory 102 through the system memory manager 104. The system memory manager 104 functions similarly to the memory manager 103, the only difference being that the memory manager 103 supports the processor 101 in reading or writing data to the memory 102, while the system memory manager 104 supports the endpoint device 106 in reading or writing data to the memory 102. For example... Figure 2 Two PCIe bus topologies 105 are shown. In one PCIe bus topology, a PCIe root complex 1051-2 (RC) serves as the root node, with endpoint equipment (EP) directly connected as leaf nodes to the PCIe root complex. In the other PCIe bus topology, a PCIe root complex 1051-1 serves as the root node, and several PCIe switches 1052 serve as parent and child nodes, such as... Figure 2 As shown, the system includes two PCIe switches, 1052-1 and 1052-2. PCIe root union 1051-1 is connected to PCIe switch 1052-1 as its parent node. PCIe switch 1052-1 is connected to PCIe switch 1052-2 as its parent node. PCIe root union 1051-1, acting as a parent-child node, also connects to one endpoint device (a leaf node). PCIe root union 1051-2, acting as a parent-child node, also connects to two endpoint devices (leaf nodes). These endpoint devices can read or write data to memory 102 via the PCIe bus. This enables data access between the nodes connected via the PCIe bus. The above is just one example. It should be noted that in other forms of PCIe topology trees, the root node and child / parent nodes may also be devices of various types. For example, the root node may be the root port on a PCIe root union, and the child / parent nodes may be uplink or downlink ports on a PCIe switch. Of course, in the following examples, the PCIe root union is mainly used as the root node and the PCIe switch is used as the child / parent node for illustration, but this does not constitute a limitation that the child / parent nodes or root node in some embodiments of this application can be replaced with other types of devices or apparatuses.

[0060] The endpoint device 106 includes, but is not limited to, a graphics processing unit (GPU), an image signal processor (ISP), a network interface card (NIC), etc.

[0061] Based on the aforementioned electronic device, embodiments of this application provide a data transmission method, applied to the root node or parent / child node in the PCIe topology tree corresponding to the PCIe bus, referring to... Figure 3 As shown, it includes the following steps:

[0062] S101, the PCIe security control device receives transmission messages sent by the transmitting device.

[0063] The sending device includes any one of the root node, child / parent nodes, or endpoint devices. The transmitted message is a TLP message. In embodiments of this application, the transmission direction of the transmitted message may be one of two types: either the destination address of the transmitted message is an endpoint device (i.e., the transmitted message may be a downstream data flow TLP message), or the destination address of the transmitted message is a PCIe root union (i.e., the transmitted message may be an upstream data flow TLP message).

[0064] S102, when the PCIe security control device determines that the transmission message is valid based on the pre-acquired security configuration information, it transmits the transmission message to the next device. The transmission message is a TLP message.

[0065] The security configuration information includes configuration information in the PCIPC capability control registers and the security table (implementation and use of this table are optional) of the PCIe protection control (PCIPC) device implemented on the PCIe root union (RC) and PCIe switch. The PCIe security control device can then implement step S102 using this configuration information. The configuration information in the capability control registers includes whether the PCIe security control device's control functions are enabled, whether the PCIe security control device supports the security table (which can include uplink and downlink security tables depending on the transmission direction of the transmitted message), the size of the supported security table, and whether control of transmitted messages is required based on the contents of security entries in the security table (if the security table is used). The security entries in the security table include more granular configuration information, such as the granularity of security control, the security level of the corresponding security control address space domain, and whether read / write verification is performed.

[0066] Specifically, the PCIe security control device can be located at the root node (e.g., a PCIe root federation) or under a parent / child node (e.g., a PCIe switch). For the TLP messages of uplink data streams from all its connected subtrees or leaf nodes, it determines whether the TLP messages conform to expectations (consistent with the security configuration information (including the functional control requirements of the PCIe security control device)). For example, if the requester ID conforms to expectations, it can directly block the uplink transmission of these data streams. Alternatively, the PCIe security control device determines whether the TLP messages of downlink data streams transmitted from the root node or a parent / child node to all subtrees or leaf nodes are as expected (based on the security configuration information of the PCIe security control device). If not, it ensures that access to these subtrees and leaf nodes by the TLP messages of these downlink data streams is blocked.

[0067] In the data transmission method provided in the embodiments of this application, the PCIe security control device mainly verifies the legality of the transmitted TLP message through pre-set security configuration information. This security configuration information is flexibly configurable, thus eliminating the need to change the content of the TLP message. Compared to existing technologies, it eliminates the need to add prefixes and integrity check values ​​to the TLP message, thereby reducing reliance on prefixes and integrity check values ​​and lowering the requirements for PCIe devices to support integrity check value calculation and verification mechanisms. Furthermore, it does not increase the message overhead of the PCIe bus, thus offering greater flexibility. Moreover, because the security configuration information is flexibly configurable, compared to setting fixed prefixes and integrity check values, it reduces the risk of design flaws in the prefix and integrity check value scheme being counterfeited.

[0068] Furthermore, to ensure the security of the acquired security configuration information, embodiments of this application can provide a secure configuration interface for trusted system software, allowing for more flexible configuration of security mechanisms on each node of the entire PCIe topology tree. Before step S101, the security of the security configuration information can also be guaranteed in the following ways: For example, the security configuration information can be configured and controlled by secure and trusted system software (trusted system software) on the processor CPU. Thus, when the security configuration information is a TLP message targeting one or more specific leaf nodes on the PCIe topology tree, enclave protection for one or more specific leaf nodes on the PCIe topology tree can be provided. Additionally, security configuration information on parent and child nodes far from the PCIe root union can only have its related register groups configured by configuration access requests coming down from a trusted configuration channel, or it needs to identify which security configuration information is secure and trustworthy, and only these secure and trustworthy security configuration information can configure its related register groups. Specific explanations are as follows:

[0069] Method 1: The PCIe security control device obtains the configuration access request. When it is determined that the configuration access request comes from the operating system under the Trusted Operating Environment (TEE), the security configuration information carried in the configuration access request is obtained.

[0070] First, trusted system software (e.g., software in an operating system running under TEE) performs security authentication on each parent and child node (e.g., a PCIe switch device) in the PCIe topology tree. Once authentication is successful, the trusted system software on the CPU (e.g., an operating system (OS) kernel or system software running under TEE) can recognize that the corresponding parent and child nodes are trusted and support the PCIe security control device provided in the embodiments of this application. Then, the trusted system software on the CPU configures the register sets (also called the PCIe security control (PCIPC) device capability control registers) and security tables (the implementation and use of the security table are optional) in the parent and parent and child nodes throughout the PCIe topology tree via the secure channel of the host CPU. Furthermore, when a node in the aforementioned PCIe topology receives a data stream, steps S101 and S102 are executed on the data stream. This includes determining whether the data stream emitted by each leaf node of the PCIe topology conforms to expectations, controlling whether the data stream flowing into each node of the PCIe topology conforms to expectations, and controlling (e.g., blocking) the outflow and retention of data streams that do not conform to expectations, as well as handling the corresponding processing of data stream access that does not conform to expectations. The trusted system software can control whether the data stream to one or more leaf nodes is subject to PCIe security protection by configuring register sets and security tables (if security tables are implemented), thereby providing enclave protection for a specific leaf node.

[0071] Reference Figure 4As shown, a PCIe security control device can include a set of registers that provide a secure configuration control interface for trusted system software. The PCIe security control device determines the security control of the corresponding data flow based on the security configuration information stored in these registers. Specifically, for the root node or parent / child nodes in the PCIe topology tree, the PCIe security control device on them must implement secure identification of configuration access requests for the register set according to the CPU's system security architecture. Only configuration access requests from the secure world (e.g., an operating system under a Trusted Execution Environment, TEE) can configure the register set. This register set can only be configured by configuration access requests from the secure world; configuration access requests from the normal world are ignored. How to determine whether a configuration access request comes from the secure world mainly depends on the system security architecture implementation of the PCIe topology tree. For example, a PCIe security control device on a PCIe RC can determine this based on the security identifier field of the internal bus. Meanwhile, PCIe security control devices located on parent and child nodes of the PCIe topology tree, far from the PCIe RC, can carry over the security label fields from the host CPU via the vendor-defined local prefix type 1 (TLP) in the PCIe TLP message. These security label fields are hardware-implemented and cannot be counterfeited or modified.

[0072] Furthermore, the PCIe security control device on the root node or parent / child nodes can be configured to determine whether some or all of the data streams from all leaf nodes or parent / child nodes below it can access the system memory space (e.g., ...). Figure 2 The secure space (e.g., the memory space of the TEE) is used for memory 102. This allows configuration control of the root node or parent / child nodes to place one or more leaf nodes or parent / child nodes under them into the secure space, thus providing enclave security protection for the data flow of these nodes, ensuring the security of their training data, communication data, etc. The trusted system software can see all the PCIe security control devices on all parent and parent / child nodes in the entire PCIe topology, and can control and maintain the security configuration information of these PCIe security control devices.

[0073] Method 1 describes how secure configuration information on parent and child nodes far from the RC can be configured with their associated function control register sets and security tables (if implemented) via configuration access requests from trusted configuration channels. Methods 2 and 3 below provide that PCIe security controllers can proactively identify which security configuration information is secure and trusted, and only these secure and trusted security configuration information can be used to configure their associated function control register sets and security tables. Trusted system software configures the PCIe security controllers of parent and leaf nodes throughout the PCIe topology tree using messages carrying specific security verification information. Only secure and trusted security configuration information carried in TLP messages verified by the PCIe security controller can configure its associated register sets. See details... Figure 5 As shown, when a PCIe security control device receives a TLP message, it can determine whether it carries a prefix. It then verifies the security verification information in the prefix. If the verification result is valid, it obtains the security configuration information carried in the TLP message; otherwise, it discards the TLP message.

[0074] Method 2: The security configuration information of the PCIe security control device is implemented in the configuration space of the root node or parent / child nodes. Specifically, it is implemented in the Type 1 configuration space of the PCIe root port of the PCIe root federation, or in the configuration space of the uplink or downlink port of the PCIe switch. Alternatively, the security configuration information is configured through the indirect access programming interface provided by the register group implemented in the configuration space of the parent or parent / child nodes. In this case, the security configuration information is configured through configuration messages. The corresponding configuration message needs to include security verification information. Only when the security verification information is determined to be valid will the security configuration information carried in the configuration message be allowed to take effect; otherwise, the configuration will not take effect. Trusted system software (e.g., software running on TEE) needs to determine whether to include security verification information in the configuration message based on whether the access is secure. Specifically, the transaction type of this configuration message can be the CfgWr TLP message mentioned above, and the security verification information can be carried in the Type 1 prefix (vendor defined local TLP type 1 prefix, abbreviated as VendPrefixL1), such as... Figure 6 As shown, the message format of this configuration message is provided. A type 1 prefix field of 4 bytes or more can be added to the message header to carry this security verification information.

[0075] Method 3: The security configuration information of the PCIe security control device is implemented in the base address space (BAR space) of the root node or parent / child nodes. Specifically, it is implemented in the base address space (BAR space) of the PCIe root port of the PCIe root federation or the uplink or downlink port of the PCIe switch. In this case, the security configuration information of the PCIe security control device needs to be configured through PCIe memory TLPs (specifically, PCIe memory write TLPs, PCIe MemWr TLPs). The MemWr TLP packet prefix needs to include security verification information. When the security verification information is determined to be valid, the security configuration information carried in the MemWr TLP packet is obtained.

[0076] If the security configuration information is in the base address register (BAR) space, the CPU configures this security configuration information through the PCIe MemWr TLP of the type 1 prefix (VendPrefixL1) of the vendor-defined local TLP message. At this point, the trusted system software (e.g., software running on the TEE) needs to determine whether to include security verification information in the memory message based on whether the access is secure. The specific security verification information can be carried in the type 1 prefix of the memory message, such as... Figure 7 As shown, the message format of this memory message is provided. A 4-byte or more Type 1 prefix field can be added to the message header to carry the security verification information.

[0077] Methods two and three can also be implemented in combination. For example, the function control register group can be implemented using method two, while the safety table can be implemented in the BAR space, and the specific BAR and its corresponding offset can be indicated in the relevant registers in the function control register group.

[0078] Furthermore, the specific implementation method of the above step S102 is explained as follows: The PCIe security control device can identify whether the transmission packets in the incoming data stream are valid based on the physical root port on the PCIe root federation, or identify whether the transmission packets in the data stream are valid based on the requester ID of the transmission packets in the incoming data stream from the root.

[0079] Specific combination Figure 8As shown, for uplink data flow, taking the PCIe switch acting as a parent node receiving a transmission packet sent by endpoint device 1 as an example, if the destination address of the transmission packet is the PCIe root union, then after the PCIe switch receives the transmission packet, the PCIe security control device on the PCIe switch determines the legitimacy of the transmission packet based on pre-acquired security configuration information. This security configuration information includes one or more requester IDs to be matched. Specifically, the PCIe security control device determines that the first requester ID in the transmission packet is one of one or more requester IDs to be matched, thus determining the transmission packet to be legitimate. Simultaneously, the PCIe security control device can also decide whether to perform other security checks based on the security configuration information, including but not limited to deciding whether to index the security table based on the requester ID of the transmission packet, obtaining information from the security table to check whether the requester of the corresponding requester ID has permission to access the corresponding space, and what those permissions are. Of course, this is only an example using a PCIe switch; the legitimacy of transmission packets can also be determined in the same way on the PCIe root union / root port.

[0080] In another example, the same combination Figure 8As shown, for uplink data flow, taking the PCIe Root Consortium (PCIe RC) as the root node receiving a transmission packet sent by endpoint device 3 as an example, if the source address of the transmission packet is endpoint device 3, then after the PCIe RC receives the transmission packet, the PCIe security control device on the PCIe RC determines the legitimacy of the transmission packet based on pre-acquired security configuration information. This security configuration information includes one or more requester IDs to be matched, and an uplink security table consisting of security entries corresponding one-to-one with each of the one or more requester IDs to be matched; in this security entry table, the requester ID is used as the index for each security entry. Specifically, the PCIe security control device indexes the first security entry based on the security configuration information and the first requester ID in the transmission packet, verifies the transmission packet based on the content of the first security entry, and determines the legitimacy of the transmission packet after successful verification. Of course, this is only an example using the PCIe RC; the legitimacy of transmission packets can also be determined in the same way on a PCIe switch. The difference lies in the potential differences in security configuration information between the PCIe switch and the PCIe root federation. This is done to distribute different authentication controls evenly across different nodes in the PCIe topology tree, ensuring a more balanced workload for verifying transmitted packets across each node. Of course, both authentication controls can be implemented simultaneously on a single node. For security entries in the uplink security table, the content can include security information, whether a security page table is used, etc. Security information includes whether the transmitted packet corresponding to this requester ID is allowed to access the secure memory space, and whether the security attributes of the accessed memory space (e.g., secure world or normal world memory space) are determined by the page table or directly controlled by the configuration of this security entry. This security entry can also store control information such as whether the transmitted packet corresponding to the requester ID requires a specific security page table and whether a page table lookup is required.

[0081] Thus, combined Figure 9As shown, the PCIe security controller indexes the corresponding security entry in the uplink security table based on the requester ID. It then uses the content of the security entry to determine whether the corresponding transport packet requires secure access, whether a page table lookup is needed, and whether a secure page table is required. If the corresponding security entry is not found in the uplink security table, the transport packet can only access the general memory space, with access permissions determined by the page table of the IOMMU or SMMU. For data streams with this requester ID, the PCIe security controller disables verification. Furthermore, for data streams from leaf nodes (upstream data streams), the PCIe security controller determines whether verification is required based on the security configuration information. Verification may include, for example, whether the requester ID is valid and whether secure access is required. If verification is required, it is performed based on the security configuration information (e.g., the requester ID to be matched and the security entry mentioned above). Only after successful verification can the upstream data stream continue accessing; otherwise, it is directly blocked. After the parent node and child parent node verify the upstream data stream, they also need to determine whether to judge the security attributes of the memory space it accesses based on the configuration. The root node can combine the security technology of this CPU to implement a security mark on the upstream data stream to enable safe access to the system memory space.

[0082] Specific combination Figure 10 As shown, for downlink data flow, taking the PCIe switch (as a parent node) receiving a transmission packet sent to endpoint device 1 from the PCIe Root Union (PCIe RC) as an example, where the destination address of the transmission packet is endpoint device 1, after receiving the transmission packet, the PCIe security control device on the PCIe switch determines the legitimacy of the transmission packet based on pre-acquired security configuration information. This security configuration information includes one or more root port numbers to be matched; specifically, the PCIe security control device determines the transmission packet is legitimate when it determines that the first root port number in the transmission packet is one of one or more root port numbers to be matched. Of course, this is only an example using a PCIe switch; the legitimacy of transmission packets can also be determined in the same way on a PCIe Root Union.

[0083] In another example, the same combination Figure 10As shown, for downlink data flow, taking the PCIe RC (as the root node) receiving a transmission packet sent to endpoint device 3 by the local CPU or other engines of the system, with the destination address of the transmission packet being endpoint device 3, after receiving the transmission packet, the PCIe security control device on the PCIe RC determines whether to perform a security check on the downlink packet based on pre-acquired security configuration information. If a check is required, how is the legitimacy of the transmission packet determined? The security configuration information includes a downlink security table consisting of one or more root port numbers to be matched and security entries corresponding one-to-one with each of the one or more root port numbers to be matched; in this security entry table, the root port number serves as the index for each security entry. Specifically, the PCIe security control device indexes the second security entry based on the security configuration information and the first root port number in the transmission packet, verifies the transmission packet based on the content of the second security entry, and determines the transmission packet to be legitimate after successful verification. In this scenario, the PCIe security control devices on the last-level parent and child nodes can determine the legitimacy of transmitted packets solely through the root port number, without using a downlink security table; alternatively, they can use any of the bus number, device number, or function number of the leaf node (endpoint device) to index the security entry in the downlink security table. This explanation uses the PCIe root federation as an example; the same method can be used on PCIe switches to determine the legitimacy of transmitted packets. The difference lies in the security configuration information configured in the PCIe switch and the PCIe root federation. This is done to distribute different authentication controls evenly across different nodes in the PCIe topology tree, ensuring a more balanced workload for packet authentication across all nodes. Of course, both authentication controls can be implemented simultaneously on a single node.

[0084] For a security entry in the downlink security table, its content includes a security signature for the corresponding root port number, and may also include security level information. For data streams output from the PCIe root union, the corresponding security entry in the downlink security table is indexed based on the outgoing root port number, and the content of the corresponding security entry determines whether to mark the transmitted message with a security signature. The security signature of the transmitted message can be placed in a vendor-defined Type 1 prefix. The PCIe security control devices corresponding to all parent and child nodes under this topology tree need to recognize this Type 1 prefix of the transmitted messages sent by the PCIe root union and perform parsing processing on the Type 1 prefix according to the provisions of this invention.

[0085] Specifically, the security configuration information of the PCIe security controller on the PCIe root federation determines whether the endpoint device for the corresponding downlink access needs secure access. If not, the transmission message is sent normally. If secure access is required, the PCIe security controller on the PCIe root federation needs to add a Type 1 prefix to this transmission message, and the Type 1 prefix needs to include: the smallest PCIe bus number occupied by the endpoint device of this transmission message and a security signature.

[0086] All root nodes (PCIe root federations) and parent / child nodes (PCIe switches) containing PCIe security control devices must recognize the content of the Type 1 prefix in the transmitted packets. They only need to process Type 1 prefixes whose bus number (the smallest PCIe bus number) is equal to their secondary bus number. Type 1 prefixes whose bus number is not equal to their secondary bus number are forwarded directly without further processing. For example... Figure 11 As shown, the message format of this transmission message is provided. A 4-byte or more Type 1 prefix field can be added to the message header to carry the minimum PCIe bus number and security signature.

[0087] Combination Figure 12 As shown, when processing transport packets whose bus number in the Type 1 prefix equals its second-level bus number, the PCIe security control devices at the root node (PCIe root federation) and parent / child nodes (PCIe switches) need to verify the security signature of the transport packet based on the security entry in the downlink security table indexed by the root port number of the transport packet (if such a security entry exists). The PCIe security control device determines whether the transport packet is secure and trustworthy based on the verification result. Only if it is deemed secure and trustworthy can it be forwarded to the corresponding leaf node; otherwise, for write access transport packets, they are discarded directly; for read access transport packets, they are discarded, and a completion message with an unsupported status or a normal status (all 0s / all 1s) is returned. If no security entry is found, the transport packet is forwarded directly to the corresponding leaf node.

[0088] Furthermore, it should be noted that in the PCIe topology tree, when the PCIe security control device of any parent or child node resolves the bus number in the Type 1 prefix to be equal to the second-level bus number, it can either remove this Type 1 prefix from the transmitted message and no longer forward it, or it can retain the prefix and continue forwarding it. Because it is a Type 1 prefix, leaf nodes can directly ignore it. Moreover, in the entire PCIe topology tree, it is sufficient to resolve the bus number in the Type 1 prefix to be equal to the second-level bus number on only one node; it is not necessary to perform this resolution on all nodes, thus reducing resource waste.

[0089] Furthermore, it should be noted that the aforementioned data transmission method can be implemented based on a CPU security technology architecture and can provide software programming interfaces for trusted system software. This allows for more flexible choices and expansion of the security scheme for the entire computing system, and also provides personalized and user-friendly options for the security scheme of large-scale commercial computing systems. This enables the provision of secure computing environments for individual or group users, allowing specific users to complete their computing tasks in a secure environment, while providing general computing environments for users with lower security requirements or lower priority, achieving low-cost computing. Figure 13The diagram illustrates the architecture of a computing system. The computing device is built upon a Rich Execution Environment (REE) and a Trusted Execution Environment (TEE). The REE, also known as the general runtime environment, primarily consists of a rich operating system (Rich OS) running on a general-purpose processor, or the operating system under the REE, and client applications (CAs) running on the operating system under the REE. However, this open environment provides channels for information leakage and malware propagation, exposing terminal devices to a growing number of diverse attacks, leading to increasingly prominent security issues for terminal devices. The TEE is an independent runtime environment running outside the REE, primarily consisting of a trusted operating system (Trusted OS), or the operating system under the TEE, and one or more trusted applications (TAs) running on the operating system under the TEE. The TEE is isolated from the REE. In one possible implementation, a monitoring system can handle the switching between the processor's REE operating system and the TEE operating system. When a process running on the processor is running on the REE, the process running on the TEE is suspended; conversely, when a process running on the processor is running on the TEE, the process running on the REE is suspended. Each TA running on the TEE's operating system is independent, and a TA cannot access the security resources of another TA without authorization. The REE cannot directly access the hardware and software resources of the TEE; the two can only interact through authorized application programming interfaces (APIs). For simplicity, the interaction between processes in the TEE (such as TA processes or TEE operating system processes) and processes in the REE (such as CA processes or REE operating system processes) described in this application no longer emphasizes that it is implemented through APIs. Therefore, the TEE can resist software attacks occurring on the REE side. For example, a portion of the device's storage medium (referred to as TEE storage medium, or trusted memory space) is configured with security attributes, allowing access only by the TEE. The TEE storage medium includes TEE memory, which includes memory allocated to TAs (TA memory) and the memory of the operating system running on the TEE. It should be noted that the TEE storage medium and the REE storage medium may be physically separate or integrated. To ensure the security of the aforementioned data transmission methods, such as... Figure 14As shown, the agent (which can be the CA and / or Rich OS under the REE) of the endpoint device EP directly requests access to the agent (which can be the TA and / or Trusted OS under the TEE) running under the TEE to perform its computing tasks. The agent under the TEE decides whether to allow access based on current system resources. If allowed, the agent under the TEE, based on the PCIe topology tree where the requester is located and the layout of PCIe security control devices in the entire PCIe topology tree, opens the configurations related to all PCIe security control devices along the entire path from the root to the leaf node where the endpoint device EP is located, and configures the relevant security configuration information (configuration information of PCIPC CapabilityControl Registers and security table configuration information). Specifically, the agent under the TEE and the agent under the REE see the same PCIe topology tree where the EP device is located, and then the agent under the TEE can configure the security configuration information of all critical nodes on the path according to this tree. Afterwards, the result is returned to the agent of this endpoint device EP under the REE, informing it that it can now switch to the TEE for operation. The corresponding EP driver is loaded under the TEE, and the EP driver under the TEE completes all initialization of the corresponding endpoint device. At this point, a secure computing environment can be requested under the TEE through the user programming interface of the agent under the TEE, and specific security configuration information can be adjusted according to the interface parameters of the user programming interface. Thus, the agent under the TEE may adjust the relevant configurations of PCIe security control devices along the entire path from the PCIe root union to the corresponding EP. Then, the EP driver under the TEE notifies the agent under the REE that device initialization is complete, and the agent under the REE reports the returned result to its agent under the REE. Furthermore, as... Figure 15As shown, an endpoint device (EP) can actively exit the TEE through a proxy under the TEE and resume execution under the REE. After receiving a request to exit the TEE (either sent by a proxy under the REE or initiated by the EP's proxy under the TEE), the proxy under the TEE actively requests the TEE topology tree to close the EP. The TEE topology tree releases all related resources on parent and child nodes along all paths from the root to the endpoint device EP, and notifies the EP driver under the TEE to release related resources. The EP driver under the TEE reports the resource release completion to the TEE topology tree, which then returns a successful closure message to the proxy under the TEE. Next, the proxy under the TEE requests the TEE topology tree to close the security configuration corresponding to the EP. The PCIe security controllers on parent and child nodes along all paths from the root to the endpoint device EP in the TEE topology tree close the relevant security configuration for the endpoint device EP. Finally, the TEE topology tree returns a successful exit message to the proxy under the TEE.

[0090] It is understandable that the above Figure 14 or Figure 15 The security solutions related to the accompanying software shown can be more flexible and diverse, and the embodiments of this application are not limited to the above. Figure 14 or Figure 15 The security software system solution shown is implemented. Because the embodiments of this application provide a flexible and trusted programming interface, the upper-layer trusted software solution can be flexible and diverse.

[0091] It is understood that in the above embodiments of data transmission methods, the methods and / or steps implemented by the PCIe security control device can also be implemented by components (such as chips or circuits) that can be used in the PCIe security control device.

[0092] It is understood that, in order to achieve the above-mentioned functions, the PCIe security control device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0093] This application embodiment can divide the PCIe security control device into functional modules according to the above method embodiment. For example, each function can be divided into a separate functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. It should be noted that the module division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0094] Figure 16 A schematic diagram of a PCIe security control device is shown. This PCIe security control device is applied to the root node or parent / child node in the PCIe topology tree corresponding to the PCIe bus, and includes a receiving unit 3101, a processing unit 3102, and a transmitting unit 3103.

[0095] In the above method embodiments, all relevant content of each step can be referenced from the functional description of the corresponding functional module.

[0096] In this embodiment, the PCIe security control device is presented in an integrated manner, divided into various functional modules or units. Here, "module" or "unit" can refer to a specific ASIC, circuit, processor and memory executing one or more software or firmware programs, integrated logic circuits, and / or other devices that can provide the above-mentioned functions.

[0097] Specifically: the receiving unit 3101 is used to receive transmission messages sent by the sending device, wherein the sending device includes any one of the root node, the parent / child node, or the endpoint device, wherein the endpoint device is connected to the root node or the parent / child node, and the memory manager is connected to the root node;

[0098] The processing unit 3102 is used to transmit the transmission message to the next device through the sending unit 3103 when the transmission message is determined to be legitimate based on the pre-acquired security configuration information. The transmission message is a TLP message.

[0099] Optionally, the processing unit 3102 is further configured to acquire a configuration access request, and when it is determined that the configuration access request comes from an operating system under a Trusted Operating Environment (TEE), acquire the security configuration information carried by the configuration access request.

[0100] Optionally, the processing unit 3102 is further configured to obtain a configuration message in the configuration space of the root node or the parent / child node, the configuration message containing security verification information, and when the security verification information is determined to be valid, obtain the security configuration information carried by the configuration message, the configuration message being a TLP message.

[0101] Optionally, the processing unit 3102 is further configured to acquire a memory message generated by the CPU, wherein the memory message includes a memory message carrying security verification information, and when the security verification information is determined to be valid, acquire the security configuration information carried in the memory message, wherein the memory message is a TLP message.

[0102] Optionally, the destination address of the transmission message is the root node; the security configuration information includes one or more requester identifiers to be matched; the processing unit 3102 is specifically used to determine that the transmission message is valid when the first requester identifier in the transmission message is one of the one or more requester identifiers to be matched.

[0103] Optionally, the destination address of the transmission message is the root node; the security configuration information includes one or more requester identifiers to be matched, and security entries corresponding one-to-one with the one or more requester identifiers to be matched; the processing unit 3102 is specifically used to index out the first security entry according to the security configuration information and the first requester identifier in the transmission message, verify the transmission message according to the content of the first security entry, and determine that the transmission message is valid after the verification is passed.

[0104] Optionally, the destination address of the transmission message is an endpoint device; the security configuration information includes one or more root port numbers to be matched; the processing unit 3102 is specifically used to determine that the transmission message is valid when the first root port number in the transmission message is one of the one or more root port numbers to be matched.

[0105] Optionally, the destination address of the transmission message is an endpoint device; the security configuration information includes one or more root port numbers to be matched and security entries corresponding one-to-one with the one or more root port numbers to be matched; the processing unit 3102 is specifically used to index out the second security entry based on the security configuration information and the first root port number in the transmission message, verify the transmission message based on the content of the second security entry, and determine that the transmission message is valid after the verification is passed.

[0106] Optionally, the transmission message includes a security signature configured by the root node according to the security configuration information; the processing unit 3102 is specifically used to verify the security signature of the transmission message according to the content of the second security entry.

[0107] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0108] Optionally, embodiments of this application also provide a PCIe security control device (e.g., the PCIe security control device may be a chip or a chip system), which includes a processor for implementing the methods in any of the above method embodiments. In one possible design, the PCIe security control device further includes a memory. The memory is used to store necessary program instructions and data, and the processor can call the program code stored in the memory to instruct the PCIe security control device to execute the methods in any of the above method embodiments. Of course, the memory may not be included in the PCIe security control device. When the PCIe security control device is a chip system, it may be composed of chips or may include chips and other discrete devices; embodiments of this application do not specifically limit this.

[0109] This application also provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the methods corresponding to the above-described method embodiments.

[0110] This application also provides a computer program product containing instructions that run on a computer to cause the computer to perform the method corresponding to the above method embodiments.

[0111] The technical effects of the electronic devices, computer-readable storage media, and computer program products involved in the embodiments of this application are the same as those described above regarding the technical effects of the phase synchronization method, and will not be repeated here.

[0112] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0113] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0116] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0117] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0118] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0119] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data transmission method, applied to the root node or parent / child node in a PCIe topology tree corresponding to a PCIe bus, characterized in that, The system receives transmission messages sent by a sending device, wherein the sending device includes any one of the root node, the parent / child node, or the endpoint device, wherein the endpoint device is connected to the root node or the parent / child node, and the root node is connected to the system memory manager. When the transmission message is determined to be valid based on the pre-acquired security configuration information, the transmission message is transmitted to the next device. The transmission message is a TLP message and the TLP message does not contain an integrity check value. Before determining the legitimacy of the transmission message based on pre-acquired security configuration information, the process also includes: Obtain a configuration access request. When it is determined that the configuration access request originates from an operating system under a Trusted Execution Environment (TEE), obtain the security configuration information carried in the configuration access request. The configuration access request is a TLP message; or... A configuration message containing security verification information is obtained from the configuration space of the root node or its parent / child nodes. When the security verification information is deemed valid, the security configuration information carried in the configuration message is obtained. The configuration message is a TLP message; or... The processor CPU generates a memory packet, wherein the memory packet contains a memory packet carrying security verification information. When the security verification information is determined to be valid, the security configuration information carried in the memory packet is obtained. The memory packet is a TLP packet.

2. The method of claim 1, wherein, The destination address of the transmitted message is the root node; the security configuration information includes one or more requester identifiers to be matched; Determining the legitimacy of the transmission message based on pre-acquired security configuration information includes: determining that the transmission message is legitimate when the first requester identifier in the transmission message is one of the one or more requester identifiers to be matched.

3. The method of claim 1, wherein, The destination address of the transmitted message is the root node; the security configuration information includes one or more requester identifiers to be matched, and a security entry corresponding to each of the one or more requester identifiers to be matched. The step of determining the legitimacy of the transmission message based on pre-acquired security configuration information includes: The first security entry is indexed based on the security configuration information and the first requester identifier in the transmission message. The transmission message is then verified based on the content of the first security entry. If the verification passes, the transmission message is determined to be legitimate.

4. The method of claim 1, wherein, The destination address of the transmitted message is the endpoint device; the security configuration information includes one or more root port numbers to be matched; Determining the legitimacy of the transmission message based on pre-acquired security configuration information includes: determining that the transmission message is legitimate when the first root port number in the transmission message is one of the one or more root port numbers to be matched.

5. The method according to claim 1, characterized in that, The destination address of the transmitted message is the endpoint device; the security configuration information includes one or more root port numbers to be matched and security entries corresponding one-to-one with the one or more root port numbers to be matched. The step of determining the legitimacy of the transmission message based on pre-acquired security configuration information includes: The second security entry is indexed based on the security configuration information and the first root port number in the transmitted message. The transmitted message is then verified based on the content of the second security entry. If the verification passes, the transmitted message is determined to be legitimate.

6. The method according to claim 5, characterized in that, The transmitted message includes a security signature configured by the root node based on the security configuration information; Verification of the transmitted message based on the content of the second security entry includes: The security signature of the transmitted message is verified based on the content of the second security entry.

7. A PCIe security control device, applied to the root node or parent / child node in the PCIe topology tree corresponding to the PCIe bus, characterized in that, A receiving unit is used to receive transmission messages sent by a sending device, wherein the sending device includes any one of the root node, the parent / child node, or the endpoint device, wherein the endpoint device is connected to the root node or the parent / child node, and the root node is connected to the system memory manager. The processing unit is used to transmit the transmission message to the next device through the sending unit when it is determined that the transmission message is legal based on the pre-acquired security configuration information. The transmission message is a TLP message and the TLP message does not contain an integrity check value. The processing unit is further configured to acquire a configuration access request, and when it is determined that the configuration access request originates from an operating system under a Trusted Execution Environment (TEE), acquire the security configuration information carried in the configuration access request, wherein the configuration access request is a TLP message; or, The processing unit is further configured to obtain a configuration message from the configuration space of the root node or child / parent node, the configuration message containing security verification information; when the security verification information is determined to be valid, the unit obtains the security configuration information carried in the configuration message, wherein the configuration message is a TLP message; or, The processing unit is further configured to acquire a memory message generated by the CPU, wherein the memory message includes a memory message carrying security verification information, and when the security verification information is determined to be valid, acquire the security configuration information carried in the memory message, wherein the memory message is a TLP message.

8. The PCIe security control device according to claim 7, characterized in that, The destination address of the transmitted message is the root node; the security configuration information includes one or more requester identifiers to be matched; The processing unit is specifically used to determine that the transmission message is valid when the first requester identifier in the transmission message is one of the one or more requester identifiers to be matched.

9. The PCIe security control device according to claim 7, characterized in that, The destination address of the transmitted message is the root node; the security configuration information includes one or more requester identifiers to be matched, and a security entry corresponding to each of the one or more requester identifiers to be matched. The processing unit is specifically configured to index a first security entry based on the security configuration information and the first requester identifier in the transmission message, verify the transmission message based on the content of the first security entry, and determine the transmission message to be valid after the verification is passed.

10. The PCIe security control device according to claim 7, characterized in that, The destination address of the transmitted message is the endpoint device; the security configuration information includes one or more root port numbers to be matched; The processing unit is specifically used to determine that the transmission message is valid when it determines that the first root port number in the transmission message is one of the one or more root port numbers to be matched.

11. The PCIe security control device according to claim 7, characterized in that, The destination address of the transmitted message is the endpoint device; the security configuration information includes one or more root port numbers to be matched and security entries corresponding one-to-one with the one or more root port numbers to be matched. The processing unit is specifically used to index the second security entry based on the security configuration information and the first root port number in the transmitted message, verify the transmitted message based on the content of the second security entry, and determine the transmitted message to be valid after the verification is successful.

12. The PCIe security control device according to claim 11, characterized in that, The transmitted message includes a security signature configured by the root node based on the security configuration information; The processing unit is specifically used to verify the security signature of the transmitted message according to the content of the second security entry.

13. A PCIe bus, characterized in that, The PCIe security control device as described in any one of claims 7-12 is applied to the root node or child / parent node in the PCIe topology tree corresponding to the PCIe bus.

14. An electronic device, characterized in that, Includes the PCIe bus as described in claim 13, wherein the endpoint device is connected to the memory of the electronic device via the PCIe bus.

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