Synchronous metronome, data acquisition synchronization device and dual-computer hot standby system

Abstract

The application discloses a synchronous metronome, a data acquisition synchronization device and a dual-computer hot backup system, relates to the technical field of dual-computer hot backup, and comprises a frame signal clock generation module, a signal detection module and a frame synchronization signal generation module.The frame signal clock generation module is used for mixing the first clock signal and the second clock signal to obtain a mixed signal, and processing the mixed signal into a first frame signal clock with a preset frequency.The signal detection module is used for outputting a synchronization start signal when the second clock signal and the first clock signal are detected.The frame synchronization signal generation module is used for generating a frame synchronization pulse signal according to the first frame signal clock when the synchronization start signal is detected.The application solves the problem that in the dual-computer high-availability scheme, the real-time accuracy of software implementation depends on the operating system, and it is difficult to ensure the consistency of the working rhythm of the dual computer.

Description

Technical Field

[0001] This application relates to the field of dual-machine hot standby technology, specifically to a synchronous metronome, a data acquisition synchronization device, and a dual-machine hot standby system. Background Technology

[0002] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. It should not be construed as an admission that the description herein is prior art.

[0003] In the industrial sector, a dual-machine hot standby solution is needed for edge computing, edge data acquisition, and other scenarios. This solution aims to achieve high availability of data collection, distribution, and storage while maintaining cost-effectiveness. In dual-machine high-availability solutions for edge computing in the industrial field, service synchronization is sometimes implemented in software, such as distributed locks. A distributed lock in software can synchronize the service states of multiple machines. However, the real-time accuracy of this software implementation depends on the operating system. For example, Linux operating systems cannot guarantee the real-time performance of signal synchronization under increased I / O load, leading to decreased synchronization accuracy and making it difficult to ensure the consistency of the dual-machine operating cycle. Summary of the Invention

[0004] This application provides a synchronized metronome, a data acquisition synchronization device, and a dual-machine hot standby system to at least solve the problem in existing dual-machine high availability solutions where the real-time accuracy implemented by the software depends on the operating system, making it difficult to ensure the consistency of the working rhythm of the two machines.

[0005] According to one aspect of this application, a synchronized metronome is also provided, comprising:

[0006] A frame signal clock generation module is used to perform frequency mixing processing on a first clock signal and a second clock signal to obtain a mixed signal, and process the mixed signal into a first frame signal clock at a preset frequency. The first clock signal is a clock signal generated by the synchronizer itself, and the second clock signal is a clock signal generated by another synchronizer.

[0007] The signal detection module is used to output a synchronization start signal when the second clock signal and the first clock signal are detected;

[0008] The frame synchronization signal generation module is used to generate a frame synchronization pulse signal according to the clock of the first frame signal when the synchronization start signal is detected.

[0009] In some embodiments, the synchronizer further includes:

[0010] A signal gating circuit is provided, which is used to input the first frame signal clock into the frame synchronization signal generation module when the signal detection module detects the second clock signal.

[0011] In some embodiments, when the signal detection module does not detect the second clock signal but detects the first clock signal, the frame signal clock generation module is further configured to process the first clock signal into a second frame signal clock of a preset frequency, and the signal gating circuit is further configured to input the second frame signal clock into the frame synchronization signal generation module, so that the frame synchronization signal generation module generates the frame synchronization pulse signal according to the second frame signal clock.

[0012] In some embodiments, the frame signal clock generation module includes:

[0013] A mixer is used to receive a first clock signal and a second clock signal, and to perform a mixing process on the first clock signal and the second clock signal to obtain a mixed signal, wherein the mixed signal includes a high-frequency signal and a low-frequency signal;

[0014] The signal processing unit has its input terminal connected to the output terminal of the mixer and its output terminal connected to the input terminal of the frame synchronization signal generation module. The signal processing unit is used to filter out the low-frequency signal, process the high-frequency signal into a first frame signal clock of a preset frequency, and input the first frame signal clock into the frame synchronization signal generation module.

[0015] In some embodiments, the signal processing unit includes:

[0016] A high-pass filter, the input of which is connected to the output of the mixer, is used to filter out the low-frequency signal and output the high-frequency signal;

[0017] The frequency divider circuit has its input terminal connected to the output terminal of the high-pass filter and its output terminal connected to the input terminal of the frame synchronization signal generation module. The frequency divider circuit is used to process the high-frequency signal into a first frame signal clock of a preset frequency and input the first frame signal clock into the frame synchronization signal generation module.

[0018] In some embodiments, the frequency divider circuit includes:

[0019] A first frequency divider, the input of which is connected to the output of the high-pass filter, is used to process the frequency of the high-frequency signal to be the same as the frequency of the first clock signal.

[0020] The second frequency divider has its input terminal connected to the output terminal of the first frequency divider, and its output terminal connected to the input terminal of the frame synchronization signal generation module. The second frequency divider is used to process the high-frequency signal divided by the first frequency divider into a first frame signal clock of a preset frequency, and input the first frame signal clock into the frame synchronization signal generation module.

[0021] In some embodiments, the synchronizer further includes:

[0022] A synchronization signal output module is provided, which is used to input the first clock signal into another synchronizer as a second clock signal for the other synchronizer.

[0023] In some embodiments, the signal detection module includes:

[0024] An internal signal detector, which outputs a first detection signal when detecting the first clock signal;

[0025] An external signal detector, wherein the external signal detector is configured to output a second detection signal when the second clock signal is detected;

[0026] The AND gate circuit is configured such that the outputs of the external signal detector and the internal signal detector are respectively connected to the input of the AND gate circuit, and the output of the AND gate circuit is connected to the input of the frame synchronization signal generation module. When the AND gate circuit receives the first detection signal and the second detection signal, it inputs the synchronization start signal to the frame synchronization signal generation module.

[0027] According to another aspect of this application, a data acquisition and synchronization device is also provided, comprising:

[0028] First synchronized metronome;

[0029] Second synchronizer;

[0030] The first and second synchronized metronomes are structured as described above.

[0031] The first metronome and the second metronome are connected. The first clock signal of the first metronome is sent to the second metronome as the second clock signal of the second metronome. The first metronome receives the first clock signal from the second metronome as the second clock signal of the first metronome.

[0032] According to another aspect of this application, a dual-machine hot standby system is also provided, comprising:

[0033] First server;

[0034] Second server;

[0035] Data acquisition and synchronization device;

[0036] The data acquisition and synchronization device includes a first metronome connected to the first server and a second metronome connected to the second server. The first server and the second server ensure the synchronous operation of their services through the frame synchronization pulse signal generated by the data acquisition and synchronization device.

[0037] The synchronous metronome provided in this application uses a hardware computing module to generate a frame synchronization pulse signal by fusing the synchronous clock signals of the two machines. The real-time accuracy does not depend on the operating system, ensuring the consistency of the working rhythm of the two machines. Furthermore, when used as a peripheral device of the dual-machine edge device, no third-party carrier is required, reducing cost and system complexity. Attached Figure Description

[0038] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 This is a schematic diagram of the structure of a synchronized metronome provided in an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the frame synchronization signal generation module provided in an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of the structure of a data acquisition and synchronization device provided in an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram illustrating the specific implementation principle of an external signal detector and an internal signal detector according to an embodiment of the present invention.

[0043] Figure 5 This is a schematic diagram of a dual-machine hot standby system provided in an embodiment of the present invention.

[0044] In the picture:

[0045] 10. Frame signal clock generation module; 11. Mixer; 12. High-pass filter; 13. First frequency divider; 14. Selector switch; 15. Second frequency divider; 16. Local oscillator clock; 17. Third frequency divider; 20. Signal detection module; 21. Internal signal detector; 22. External signal detector; 23. AND gate circuit; 30. Frame synchronization signal generation module; 31. Register; 32. Counter; 33. Comparator; 34. Flip-flop; 35. OR gate circuit; 40. Synchronization signal output module; 101. First synchronous metronome; 102. Second synchronous metronome; 103. First server; 104. Second server. Detailed Implementation

[0046] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0047] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0048] The first embodiment of the present invention provides a time synchronization device, such as... Figure 1 As shown, the synchronized metronome includes a frame signal clock generation module 10, a signal detection module 20, and a frame synchronization signal generation module 30. The frame signal clock generation module 10 is used to perform frequency mixing processing on a first clock signal and a second clock signal to obtain a mixed signal, and then processes the mixed signal into a first frame signal clock of a preset frequency. Figure 1 As shown, the first clock signal is the clock signal generated by the synchronizer itself (i.e., as shown in the image). Figure 1 The internal clock signal shown), the second clock signal is the clock signal generated by another synchronizer (such as...). Figure 1 (External clock signal shown). The signal detection module 20 is used to output a synchronization start signal when the second clock signal and the first clock signal are detected. The frame synchronization signal generation module 30 is used to generate a frame synchronization pulse signal according to the first frame signal clock when the synchronization start signal is detected.

[0049] In this embodiment of the invention, when both the second clock signal and the first clock signal are present, the signal detection module 20 outputs a synchronization start signal. Upon detecting the synchronization start signal, the frame synchronization signal generation module 30 generates a frame synchronization pulse signal based on the first frame signal clock calculated by the frame signal clock generation module 10. Because the frame synchronization pulse signal (i.e....) Figure 1The signal shown is generated by calculating the frame signal clock from the internal and external clock signals of the two synchronizers. At this time, the frame signal clocks of the two synchronizers are completely consistent, and there will be no large cumulative error even if they run for a long time.

[0050] Therefore, the synchronous metronome provided in this embodiment of the invention uses hardware computing modules (i.e., frame signal clock generation module 10, signal detection module 20, and frame synchronization signal generation module 30, etc.) to generate frame synchronization pulse signals by fusing and calculating the synchronous clock signals of the two machines. Real-time accuracy does not depend on the operating system, ensuring the consistency of the working rhythm of the two machines. Furthermore, when used as a peripheral device for dual-machine edge devices, no third-party carrier is required, reducing cost and system complexity.

[0051] Because existing software implementations such as distributed locks cannot handle the split-brain anomaly when the dual-machine link fails, manual intervention is required for recovery; otherwise, the frame synchronization signal will lose synchronization. To address this, the synchronization metronome provided in this embodiment of the invention, when used as a peripheral device for dual-machine edge devices, further includes a signal gating circuit. This circuit inputs the first frame signal clock to the frame synchronization signal generation module 30 when the signal detection module 20 detects the second clock signal. If the signal detection module 20 does not detect the second clock signal but detects the first clock signal, indicating a dual-machine link failure, the frame signal clock generation module 10 further processes the first clock signal into a second frame signal clock with a preset frequency. The signal gating circuit then inputs the second frame signal clock to the frame synchronization signal generation module 30, enabling the frame synchronization signal generation module 30 to generate a frame synchronization pulse signal based on the second frame signal clock.

[0052] Therefore, the signal gating circuit provided in this embodiment of the invention can provide the frame synchronization signal generation module 30 with the first frame signal clock calculated by the frame signal clock generation module 10 when the dual-machine link is normal, so that the frame synchronization signal generation module 30 generates a frame synchronization pulse signal that ensures the consistent working rhythm of the two machines. When the dual-machine link is abnormal (i.e., a split-brain problem occurs), it can ensure that each synchronizer provides a second frame signal clock based on the first clock signal. The second frame signal clock is used to enable the frame synchronization signal generation module 30 to generate a frame synchronization pulse signal with an error within the controllable range, thus avoiding the dual-machine split-brain problem. That is, it can still continue to operate under the condition of dual-machine link failure, and the error is controllable.

[0053] The frame signal clock generation module 10 provided in this embodiment of the invention includes a mixer 11 and a signal processing unit. The mixer 11 receives a first clock signal and a second clock signal, and performs frequency mixing on the first clock signal and the second clock signal to obtain a mixed signal, wherein the mixed signal includes a high-frequency signal and a low-frequency signal. Specifically, the frame signal clock generation module 10 also includes a local oscillator clock 16 and a third frequency divider 17. The local oscillator clock 16 generates an original clock signal, which is then divided by the third frequency divider 17 to obtain the first clock signal and the second clock signal (i.e.,...) Figure 1 The external clock signal shown is generated by the local oscillator clock 16 of another synchronizer and the third frequency divider 17. The calculation steps for the mixer 11 to mix the first clock signal and the second clock signal are as follows:

[0054] The first clock signal (represented by s1) is: s1=cos(ω1t+θ1), where ω1 represents the frequency of the first clock signal s1 and θ1 represents the initial phase of the first clock signal s1.

[0055] The second clock signal (represented by s2) is:

[0056] s2=cos(ω2t+θ2), where ω2 represents the frequency of the second clock signal s2 and θ2 represents the initial phase of the second clock signal s2.

[0057] The mixing formula is as follows:

[0058] s1×s2=f1+f2, where f1 is a high-frequency signal and f2 is a low-frequency signal. That is, the signal after mixing the first and second clock signals is equivalent to the sum of the two signals f1 and f2.

[0059] f1=1 / 2cos((ω1+ω2)t+θ1+θ2).

[0060] f2=1 / 2cos((ω1-ω2)t+θ1-θ2).

[0061] After mixing, two signals are obtained: a high-frequency signal f1 and a low-frequency signal f2. Since the parameters of the local oscillator clocks 16 of the two synchronized metronomes are generally identical, the first clock signal is obtained by dividing the local oscillator clock 16 by the third frequency divider 17, and the second clock signal is obtained by dividing the local oscillator clock 16 of the opposite synchronized metronome by its third frequency divider 17. The frequencies of the two signals have only a small device error; therefore, the frequencies of the first and second clock signals are ω1≈ω2. Since ω1 is approximately equal to ω2, for ease of calculation, this embodiment uses ω to represent the values ​​of ω1 and ω2. Therefore, the frequency of the high-frequency signal f1 is approximately 2ω, and the frequency of the low-frequency signal f2 is approximately 0. If the signal detection module 20 does not detect the second clock signal, the frequency of the high-frequency signal f1 is approximately ω, and the frequency of the low-frequency signal f2 is 0.

[0062] As can be seen, the calculated result of f2 also verifies that f2 is a low-frequency signal, providing a basis for the subsequent calculation of the first frame signal clock or the second frame signal clock. When processing to obtain the first frame signal clock or the second frame signal clock, the low-frequency signal f2 is filtered out. To this end, the input terminal of the signal processing unit is connected to the output terminal of the mixer 11, and the output terminal is connected to the input terminal of the frame synchronization signal generation module 30. The signal processing unit is used to filter out low-frequency signals, process the high-frequency signal into a first frame signal clock of a preset frequency, and input the first frame signal clock into the frame synchronization signal generation module 30. Upon detecting the synchronization start signal, the frame synchronization signal generation module 30 can generate a frame synchronization pulse signal based on the first frame signal clock, ensuring the consistency of dual-machine synchronization.

[0063] The signal processing unit includes a high-pass filter 12 and a frequency divider circuit. The input of the high-pass filter 12 is connected to the output of the mixer 11, used to filter out low-frequency signals and output high-frequency signals. The input of the frequency divider circuit is connected to the output of the high-pass filter 12, and its output is connected to the input of the frame synchronization signal generation module 30. The frequency divider circuit processes the high-frequency signal into a first frame signal clock of a preset frequency and inputs the first frame signal clock into the frame synchronization signal generation module 30. By filtering out the low-frequency signal f2 through the high-pass filter 12, only the high-frequency signal f1 is retained. This ensures a high degree of consistency of the high-frequency signals f1 of the two synchronizers, thereby ensuring the consistency of the dual-machine synchronization.

[0064] Specifically, the frequency division circuit provided in this embodiment of the invention includes a first frequency divider 13 and a second frequency divider 15. The input terminal of the first frequency divider 13 is connected to the output terminal of the high-pass filter 12. The first frequency divider 13 is used to process the frequency of the high-frequency signal to be the same as the frequency of the first clock signal. Specifically, the first frequency divider 13 is a 2-divider, mainly because the frequency of the high-frequency signal f1 is basically twice that of the internal and external clock signals (i.e., the frequency of the high-frequency signal f1 is about 2ω). By using a 2-divider, the frequency of the high-frequency signal can be processed to be the same as the frequency of the first clock signal (i.e., ω). The input terminal of the second frequency divider 15 is connected to the output terminal of the first frequency divider 13, and the output terminal is connected to the input terminal of the frame synchronization signal generation module 30. The second frequency divider 15 is used to process the high-frequency signal divided by the first frequency divider 13 into a first frame signal clock with a preset frequency, and input the first frame signal clock into the frame synchronization signal generation module 30. That is, the required first frame signal clock is divided by the second frequency divider 15. The frequency range of the first frame signal clock can be set between the kilohertz (kHz) and megahertz (MHz) levels. The first frame signal clock of the two synchronizers (such as...) Figure 1 The Signal shown is consistent.

[0065] In this embodiment of the invention, the signal gating circuit is a selector switch 14 connected between the first frequency divider 13 and the second frequency divider 15. Figure 1 The selector switch 14 (shown in the Mux) is used to enable each of the two metronomes to independently generate frame synchronization pulse signals using only the local oscillator clock 16 when the synchronization lines of the two metronomes are disconnected.

[0066] Specifically, such as Figure 1As shown, the selection signal of selector switch 14 is generated by monitoring the second clock signal. When the signal detection module 20 detects that the second clock signal is valid, selector switch 14 selects path 0 to be turned on, that is, selects the high-frequency signal that has been mixed by mixer 11 and then passed through the first frequency divider 13. Then, the second frequency divider 15 is used to process the high-frequency signal divided by the second frequency divider 15 into the first frame signal clock of the preset frequency. At this time, since the frame synchronization pulse signal is generated by the first frame signal clock calculated from the internal and external clock signals of the two synchronizers, the frame signal clocks of the two synchronizers are completely consistent, eliminating the device error of the local oscillator clock 16 of the two synchronizers. Even if it runs for a long time, there will be no large cumulative error. If the signal detection module 20 does not detect the second clock signal, the selector switch 14 selects one path to be on, that is, directly inputs the high-frequency signal of the first clock signal obtained by the synchronizer through the local oscillator clock 16 and the third frequency divider 17 into the second frequency divider 15. The second frequency divider 15 processes the high-frequency signal into a second frame signal clock of a preset frequency and inputs it into the frame synchronization signal generation module 30. Thus, the frame synchronization signal generation module 30 generates a frame synchronization pulse signal according to the second frame signal clock. That is, when the dual-machine link is lost, the synchronizer can also independently generate a frame synchronization pulse signal, so that even after the dual-machine link is lost, no human intervention is required for a long time and the synchronizer can still output a stable synchronizer signal (i.e., a frame synchronization pulse signal).

[0067] In this embodiment of the invention, the metronome further includes a synchronization signal output module 40, which is used to input a first clock signal into another metronome as a second clock signal for the other metronome. This ensures that the frame synchronization pulse signal is generated by calculating the first frame signal clock from the internal and external clock signals of the two metronomes, and that the frame signal clocks of the two metronomes are completely synchronized, preventing large cumulative errors even after long-term operation.

[0068] In this embodiment of the invention, the signal detection module 20 includes an internal signal detector 21, an external signal detector 22, and an AND gate circuit 23. Figure 1 (As shown in the AND diagram). The internal signal detector 21 outputs a first detection signal when detecting the first clock signal. The external signal detector 22 outputs a second detection signal when detecting the second clock signal. The outputs of the external signal detector 22 and the internal signal detector 21 are respectively connected to the input of the AND gate circuit 23. The output of the AND gate circuit 23 is connected to the input of the frame synchronization signal generation module 30. When the AND gate circuit 23 receives the first detection signal and the second detection signal, it inputs a synchronization start signal to the frame synchronization signal generation module 30, which triggers the frame synchronization signal generation module 30 to generate a frame synchronization pulse signal.

[0069] like Figure 2 As shown, the frame synchronization signal generation module 30 in this embodiment of the invention includes a register 31, a counter 32, a comparator 33, and a flip-flop 34. The register 31 stores a user-set synchronization period parameter. The input of the counter 32 is connected to the output of the frame signal clock generation module and is used to count the number of clock cycles of the received first or second frame signal clock. The input of the comparator 33 is connected to the outputs of the register 31 and the counter 32, and is used to determine whether the number of clock cycles calculated by the counter 32 is equal to the synchronization period parameter. If so, it outputs a high level; otherwise, it outputs a low level. The input of the flip-flop 34 is connected to the output of the comparator 33 and is used to output a frame synchronization pulse signal when a high level is received; otherwise, it does not output a frame synchronization pulse signal. This allows the frame synchronization signal generation module 30 to periodically output a frame synchronization pulse signal, and simultaneously output the sequence number (data) of this frame synchronization pulse signal. When two frame synchronization metronomes are synchronized, their frame synchronization pulse signals maintain timing consistency, and the sequence number (data) of the frame synchronization pulse signals also remains consistent.

[0070] In addition, the frame synchronization signal generation module 30 also includes an OR gate circuit 35. One input of the OR gate circuit 35 is connected to the output of the signal detection module to receive the synchronization start signal. The output of the OR gate circuit 35 is connected to the RST terminal (reset terminal) of the counter 32 and the comparator 33. When the RST terminal receives a high level from the OR gate circuit 35, it can trigger the counter 32 and the comparator 33 to restart counting and comparing. When the OR gate circuit 35 receives the synchronization start signal, it outputs a high level to start the counter 32 and the comparator 33. The synchronization start signal is a rising edge trigger signal. When both the first clock signal and the second clock signal are valid, the signal detection module 20 outputs a synchronization start signal, and the frame synchronization signal generation module 30 begins to output the frame synchronization pulse signal. Another input terminal of the OR gate circuit 35 is also used to receive an external signal (which is a trigger signal input by a person). When the OR gate circuit 35 receives the external signal, it outputs a high level to trigger the counter 32 and comparator 33 to start counting and comparing again. That is, by manually inputting a signal, the counter 32 and comparator 33 are simultaneously notified to clear the count, so as to achieve the trigger synchronization of the trigger 34 in the frame synchronization signal generation module.

[0071] In conclusion, the synchronous metronome provided in this embodiment of the invention can calculate the first frame signal clock, or the second frame signal clock in the case of a dual-machine disconnection, by using the frame signal clock generation module 10 to generate the first clock signal and the second clock signal. When the signal detection module 20 detects the first clock signal and the second clock signal, it outputs a synchronization start signal to trigger the frame synchronization signal generation module 30 to periodically output a frame synchronization pulse signal according to the first frame signal clock or the second frame signal clock. Since this synchronous metronome is a hardware device, its use as a peripheral for dual-machine edge devices avoids the increased cost and system complexity caused by introducing a third-party carrier. Compared with existing signal generators that can only be used by a single machine, it solves the problem of synchronous output between dual machines. The first clock signal generated by the frame signal clock generation module 10 is a high-speed signal obtained by processing the local oscillator clock 16 and the third frequency divider 17. The frequency range of the local oscillator clock 16 signal can be from gigahertz (GHz) to hundreds of megahertz (MHZ), ensuring the real-time performance and high accuracy of the frame synchronization pulse signal. The hardware computing module is used to generate frame synchronization pulse signals by performing fusion calculations on the dual-machine synchronous clock signals, thus ensuring the synchronization of the beat signals.

[0072] Furthermore, in this embodiment of the invention, the signal detection module 20 determines the validity of the dual-machine link. Because of the high precision of the high-frequency clock, the link breakage situation is detected in real time. Then, the frame signal clock is quickly switched through the signal gating circuit. Thus, the frame synchronization signal generation module 30 based on the high-speed signal can ensure that each synchronizing metronome can provide a frame signal clock based on the local oscillator clock 16 even when the dual-machine link is broken, so as to generate a frame synchronization pulse signal with an error within the control range.

[0073] The second embodiment of the present invention also provides a data acquisition and synchronization device, such as... Figure 3 As shown, the data acquisition synchronization device includes a first metronome 101 and a second metronome 102. The structure of the first metronome 101 and the second metronome 102 is the same as that provided in the first embodiment of the present invention. The first metronome 101 and the second metronome 102 are connected. The first clock signal of the first metronome 101 is sent to the second metronome 102 as a second clock signal of the second metronome 102. The first metronome 101 receives the first clock signal from the second metronome 102 as a second clock signal of the first metronome 101. Specifically, the first metronome 101 and the second metronome 102 are connected through a synchronization signal output module 40 to receive each other's first clock signals.

[0074] Based on the structural composition of the synchronizer provided in the first embodiment of the present invention, the data acquisition synchronization device provided in this embodiment is a hardware device that can be used for dual-machine interconnection. It maintains signal synchronization between the first synchronizer 101 and the second synchronizer 102 through interconnection synchronization signals. The clock signals of the two synchronizers have the same frequency. The frame signal clock calculated by adding the first clock signal of each synchronizer to the first clock signal of the other synchronizer (e.g., for the first synchronizer 101, the first clock signal of the second synchronizer 102 is the second clock signal of the first synchronizer 101) can achieve signal synchronization. Simultaneously, the user sets the frame synchronization signal period (i.e., the synchronization period parameter) in the frame synchronization signal generation module 30, causing the frame synchronization signal generation module 30 to periodically output frame synchronization pulse signals (signals) based on the frame signal clock. In the field of industrial data sampling, the set synchronization period parameter can be as short as milliseconds (ms) or as long as seconds. Each metronome is designed based on a signal gating circuit. Even if the first metronome 101 and the second metronome 102 are disconnected, each metronome will continue to output frame synchronization pulse signals according to its own first clock signal. Even if it runs for a long time, there will be no large cumulative error.

[0075] In this embodiment of the invention, the generation of the synchronization clock (i.e., the frame signal clock) is mainly achieved by mixing the first clock signal and the second clock signal. The local oscillator 16 and the third frequency divider 17 of the two synchronizers are set to the same parameters to ensure that the second clock signal and the first clock signal are essentially consistent. The calculation steps for mixing the first clock signal and the second clock signal by the mixer 11 are as follows:

[0076] The first clock signal (represented by s1) is: s1=cos(ω1t+θ1), where ω1 represents the frequency of the first clock signal s1 and θ1 represents the initial phase of the first clock signal s1.

[0077] The second clock signal (represented by s2) is:

[0078] s2=cos(ω2t+θ2), where ω2 represents the frequency of the second clock signal s2 and θ2 represents the initial phase of the second clock signal s2.

[0079] The mixing formula is as follows:

[0080] s1×s2=f1+f2, where f1 is a high-frequency signal and f2 is a low-frequency signal. That is, the signal after mixing the first and second clock signals is equivalent to the sum of the two signals f1 and f2.

[0081] f1=1 / 2cos((ω1+ω2)t+θ1+θ2).

[0082] f2=1 / 2cos((ω1-ω2)t+θ1-θ2).

[0083] After mixing, two signals are obtained: a high-frequency signal f1 and a low-frequency signal f2. Since the parameters of the local oscillator clocks 16 of the two synchronized metronomes are generally identical, the first clock signal is obtained by dividing the local oscillator clock 16 by the third frequency divider 17, and the second clock signal is obtained by dividing the local oscillator clock 16 of the opposite synchronized metronome by its third frequency divider 17. The frequencies of the two signals have only a small device error; therefore, the frequencies of the first and second clock signals are ω1≈ω2. Since ω1 is approximately equal to ω2, for ease of calculation, this embodiment uses ω to represent the values ​​of ω1 and ω2. Therefore, the frequency of the high-frequency signal f1 is approximately 2ω, and the frequency of the low-frequency signal f2 is approximately 0. If the signal detection module 20 does not detect the second clock signal, the frequency of the high-frequency signal f1 is approximately ω, and the frequency of the low-frequency signal f2 is 0.

[0084] As can be seen, the calculated result of f2 also verifies that f2 is a low-frequency signal, providing a basis for the subsequent calculation of the first frame signal clock or the second frame signal clock. When processing to obtain the first frame signal clock or the second frame signal clock, the low-frequency signal f2 is filtered out. To this end, each metronome filters out the low-frequency signal f2 through a high-pass filter 12, retaining only the high-frequency signal f1, which ensures a high degree of consistency of the high-frequency signal f1 between the two metronomes. Specifically, the input terminal of the first frequency divider 13 of each metronome is connected to the output terminal of the high-pass filter 12. The first frequency divider 13 processes the frequency of the high-frequency signal to be the same as the frequency of the first clock signal. The first frequency divider 13 is a divide-by-two divider, mainly because the frequency of the high-frequency signal f1 is approximately twice that of the internal and external clock signals (i.e., the frequency of the high-frequency signal f1 is approximately 2ω). Through the divide-by-two divider, the frequency of the high-frequency signal can be processed to be the same as the frequency of the first clock signal (i.e., ω). The input of the second frequency divider 15 is connected to the output of the signal gating circuit, the input of the signal gating circuit is connected to the output of the first frequency divider 13, and the output of the second frequency divider 15 is connected to the input of the frame synchronization signal generation module 30. The second frequency divider 15 processes the high-frequency signal divided by the first frequency divider 13 into a first frame signal clock with a preset frequency, and inputs the first frame signal clock into the frame synchronization signal generation module 30. That is, the second frequency divider 15 divides the required first frame signal clock. The frequency of the first frame signal clock is generally between several hundred kHz and several MHz. The first frame signal clock of the two synchronized metronomes (such as...) Figure 1 The Signal shown is consistent.

[0085] In this embodiment of the invention, the signal gating circuit is a selector switch 14. The function of the selector switch 14 is to allow each of the two metronomes to independently generate a frame synchronization pulse signal using only its local oscillator clock 16 when the synchronization lines of the two metronomes are disconnected. Specifically, as shown in the example... Figure 1 As shown, the selection signal of selector switch 14 is generated by monitoring the second clock signal. When the signal detection module 20 detects that the second clock signal is valid, selector switch 14 selects path 0 to be turned on, that is, selects the high-frequency signal that has been mixed by mixer 11 and then passed through the first frequency divider 13. Then, the second frequency divider 15 is used to process the high-frequency signal divided by the second frequency divider 15 into the first frame signal clock of the preset frequency. At this time, since the frame synchronization pulse signal is generated by the first frame signal clock calculated from the internal and external clock signals of the two synchronizers, the frame signal clocks of the two synchronizers are completely consistent, eliminating the device error of the local oscillator clock 16 of the two synchronizers. Even if it runs for a long time, there will be no large cumulative error.

[0086] If the signal detection module 20 does not detect the second clock signal, the selector switch 14 selects one path to be on, that is, directly inputs the high-frequency signal of the first clock signal obtained by the synchronizer through the local oscillator clock 16 and the third frequency divider 17 into the second frequency divider 15. The second frequency divider 15 processes the high-frequency signal into a second frame signal clock of a preset frequency and inputs it into the frame synchronization signal generation module 30. Thus, the frame synchronization signal generation module 30 generates a frame synchronization pulse signal according to the second frame signal clock. That is, when the dual-machine link is lost, the synchronizer can also independently generate a frame synchronization pulse signal, so that even after the dual-machine link is lost, no human intervention is required for a long time and the synchronizer can still output a stable synchronizer signal (i.e., a frame synchronization pulse signal).

[0087] The signal detection module 20 determines the signal state by detecting the presence of the second clock signal and the first clock signal, that is, by detecting the rising edges and their number of internal and external clock signals. If the signal detection is normal, it outputs a high level; otherwise, it outputs a low level. If N consecutive rising edges of the same period are detected, the detection signal outputs a high level, indicating a normal state (i.e., state 1); otherwise, it outputs a low level, indicating a state 0. Here, N is a built-in fixed value, set based on debugging experience, and this parameter is the same in all synchronous metronomes.

[0088] The external signal detector 22 detects the second clock signal and outputs the second detection signal as the selection signal of the selector switch 14. That is, when the second clock signal is valid, Mux selects 0, otherwise it selects 1.

[0089] The second clock signal detection output (i.e., the second detection signal output by the external signal detector 22) and the first clock signal detection output (the first detection signal output by the internal signal detector 21) output a synchronization start signal through an AND gate circuit 23, which serves as the start marker of the frame synchronization signal generation module 30.

[0090] The signal detection of the internal signal detector 21 and the external signal detector 22 in this embodiment of the invention can be implemented using a repeatable monostable trigger 34, such as... Figure 4 As shown, signal detection can be achieved by selecting appropriate parameters so that the Tw time is greater than the input period T. When the input signal is present, i.e., a periodic clock signal is continuously input, the output is high. When the input signal is absent, i.e., the input is a single-level signal, the output is low.

[0091] like Figure 2 As shown, the frame synchronization signal generation modules 30 of the first and second synchronizer metronomes 101 and 102 in this embodiment of the invention both include a register 31, a counter 32, a comparator 33, and a flip-flop 34. The register 31 stores a user-set synchronization period parameter. The input of the counter 32 is connected to the output of the frame signal clock generation module and is used to count the number of clock cycles of the received first or second frame signal clock. The input of the comparator 33 is connected to the outputs of the register 31 and the counter 32 and is used to determine whether the number of clock cycles calculated by the counter 32 is equal to the synchronization period parameter. If so, a high level is output; otherwise, a low level is output. The input of the flip-flop 34 is connected to the output of the comparator 33 and is used to output a frame synchronization pulse signal when a high level is received; otherwise, no frame synchronization pulse signal is output. This allows the frame synchronization signal generation module 30 to periodically output a frame synchronization pulse signal. At the same time, it can also output the sequence number data of the frame synchronization pulse signal along with the frame synchronization pulse signal. When the two frame synchronization metronomes are synchronized, their frame synchronization pulse signals maintain the consistency of timing, and the sequence number data of the frame synchronization pulse signal also remains consistent.

[0092] In addition, the frame synchronization signal generation module 30 also includes an OR gate circuit 35. One input of the OR gate circuit 35 is connected to the output of the signal detection module to receive a synchronization start signal. The output of the OR gate circuit 35 is connected to the RST terminal of the counter 32 and the comparator 33. When the RST terminal receives a high level from the OR gate circuit 35, it can trigger the counter 32 and the comparator 33 to restart counting and comparing. When the OR gate circuit 35 receives the synchronization start signal, it outputs a high level to start the counter 32 and the comparator 33. The synchronization start signal is a rising edge trigger signal. When both the first clock signal and the second clock signal are valid, the signal detection module 20 outputs a synchronization start signal, and the frame synchronization signal generation module 30 begins to output a frame synchronization pulse signal. Another input terminal of the OR gate circuit 35 is also used to receive an external signal (which is a trigger signal input by a person). When the OR gate circuit 35 receives the external signal, it outputs a high level to trigger the counter 32 and comparator 33 to start counting and comparing again. That is, by manually inputting a signal, the counter 32 and comparator 33 are simultaneously notified to clear the count, so as to achieve the trigger synchronization of the trigger 34 in the frame synchronization signal generation module.

[0093] The data acquisition synchronization device provided in this embodiment of the invention can calculate the first frame signal clock, or the second frame signal clock in the case of a dual-machine disconnection, by using the frame signal clock generation module 10 of each synchronizer to generate the first clock signal and the second clock signal. When the signal detection module 20 detects the first clock signal and the second clock signal, it outputs a synchronization start signal to trigger the frame synchronization signal generation module 30 to periodically output a frame synchronization pulse signal according to the first frame signal clock or the second frame signal clock. Since this synchronizer is a hardware device, its use as a peripheral of the dual-machine edge device avoids the increased cost and system complexity caused by introducing a third-party carrier. Compared with existing signal generators that can only be used by a single machine, it solves the problem of synchronous output of dual-machine interconnection. The first clock signal generated by the frame signal clock generation module 10 is a high-speed signal obtained by processing the local oscillator clock 16 and the third frequency divider 17. The frequency range of the local oscillator clock 16 signal can be from gigahertz (GHz) to hundreds of megahertz (MHZ), ensuring the real-time performance and high accuracy of the frame synchronization pulse signal. The hardware computing module is used to generate frame synchronization pulse signals by performing fusion calculations on the dual-machine synchronous clock signals, thus ensuring the synchronization of the beat signals.

[0094] Furthermore, in this embodiment of the invention, each synchronizer determines the validity of the dual-machine link through the signal detection module 20. Because of the high precision of the high-frequency clock, it ensures real-time detection of link breakage. Then, the frame signal clock is quickly switched through the signal gating circuit. Thus, the frame synchronization signal generation module 30 based on the high-speed signal can ensure that each synchronizer can provide a frame signal clock based on the local oscillator clock 16 even when the dual-machine link is broken, so as to generate a frame synchronization pulse signal with an error within the control range.

[0095] Therefore, the data acquisition and synchronization device provided in this embodiment of the invention has precise dual-machine synchronization, can continue to operate even under dual-machine disconnection conditions, and the error is controllable, avoiding the dual-machine split-brain problem. It does not require the use of third-party devices or equipment, can be implemented with only two machines, and features strong real-time performance and high accuracy.

[0096] The third embodiment of the present invention also provides a dual-machine hot standby system, such as... Figure 5 As shown, the system includes a first server 103, a second server 104, and a data acquisition and synchronization device provided in the second embodiment of the present invention. For details on the structure of the data acquisition and synchronization device, please refer to the content provided in the second embodiment of the present invention; further details will not be repeated here. Specifically, the first metronome 101 in the data acquisition and synchronization device is connected to the first server 103, and the second metronome 102 is connected to the second server 104. The first server 103 and the second server 104 ensure the synchronous execution of service operations through the frame synchronization pulse signal generated by the data acquisition and synchronization device.

[0097] Because this dual-machine hot standby system uses the data acquisition and synchronization device as its peripheral, it avoids the increased costs and system complexity associated with introducing a third-party carrier. Furthermore, compared to using a signal generator that can only be used by a single machine, it solves the problem of synchronous output between the two machines. The first clock signal generated by the frame signal clock generation module 10 of each synchronizer under the data acquisition and synchronization device is a high-speed signal obtained by processing a local oscillator clock 16 and a third frequency divider 17. The frequency range of the local oscillator clock 16 signal can range from gigahertz (GHz) to hundreds of megahertz (MHZ), ensuring the real-time performance and high precision of the frame synchronization pulse signal. The frame synchronization pulse signal is generated by using a hardware computing module to perform fusion calculations on the dual-machine synchronization clock signals, ensuring the synchronization of the clock signals in the dual-machine hot standby system.

[0098] Furthermore, in this embodiment of the invention, the dual-machine hot standby system can determine the validity of the dual-machine link through the signal detection module 20 of each synchronizer under the data acquisition synchronization device. Because of the high precision of the high-frequency clock, it ensures real-time detection of link breakage. Then, the frame signal clock is quickly switched through the signal gating circuit. Thus, even if the dual-machine link is broken, it can ensure that each synchronizer can provide a frame signal clock based on the local oscillator clock 16 to generate a frame synchronization pulse signal with an error within the control range. Even if it runs for a long time, there will be no large cumulative synchronization error, ensuring the synchronous operation of the dual-machine hot standby system.

[0099] Therefore, in the dual-machine hot standby system of this invention, a synchronizer provided by a data acquisition and synchronization device is used to synchronize the service rhythm of the two machines, which is used to determine success or failure and to perform real-time hot standby switching. The synchronizer is mainly used to synchronize the working rhythm of the two edge computing machines. From data sampling and distribution to data storage at the edge of the digital factory, all actions are executed according to the rhythm. If one machine fails to complete its cycle, the other machine will seamlessly take over.

[0100] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0101] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A synchronized metronome, characterized in that, include: The frame signal clock generation module (10) is used to perform frequency mixing processing on the first clock signal and the second clock signal to obtain a mixed signal, and process the mixed signal into a first frame signal clock of a preset frequency. The first clock signal is a clock signal generated by the synchronizer itself, and the second clock signal is a clock signal generated by another synchronizer. The signal detection module (20) is used to output a synchronization start signal when the second clock signal and the first clock signal are detected; The frame synchronization signal generation module (30) is used to generate a frame synchronization pulse signal according to the first frame signal clock when the synchronization start signal is detected; The frame signal clock generation module (10) includes: A mixer (11) is used to receive the first clock signal and the second clock signal, and to perform a mixing process on the first clock signal and the second clock signal to obtain the mixed signal, wherein the mixed signal includes a high-frequency signal and a low-frequency signal; A high-pass filter (12) is connected to the output of the mixer (11) to filter out the low-frequency signal and output the high-frequency signal. The frequency divider circuit has its input terminal connected to the output terminal of the high-pass filter (12) and its output terminal connected to the input terminal of the frame synchronization signal generation module (30). The frequency divider circuit is used to process the high-frequency signal into a first frame signal clock of a preset frequency and input the first frame signal clock into the frame synchronization signal generation module (30).

2. The synchronized metronome according to claim 1, characterized in that, The synchronizer also includes: A signal gating circuit is used to input the first frame signal clock into the frame synchronization signal generation module (30) when the signal detection module (20) detects the second clock signal.

3. The synchronized metronome according to claim 2, characterized in that, When the signal detection module (20) does not detect the second clock signal but detects the first clock signal, the frame signal clock generation module (10) is further used to process the first clock signal into a second frame signal clock with a preset frequency. The signal gating circuit is further used to input the second frame signal clock into the frame synchronization signal generation module (30) so that the frame synchronization signal generation module (30) generates the frame synchronization pulse signal according to the second frame signal clock.

4. The synchronized metronome according to claim 1, characterized in that, The frequency divider circuit includes: The first frequency divider (13) has its input terminal connected to the output terminal of the high-pass filter (12). The first frequency divider (13) is used to process the frequency of the high-frequency signal to be the same as the frequency of the first clock signal. The second frequency divider (15) has its input terminal connected to the output terminal of the first frequency divider (13) and its output terminal connected to the input terminal of the frame synchronization signal generation module (30). The second frequency divider (15) is used to process the high-frequency signal divided by the first frequency divider (13) into the first frame signal clock of the preset frequency and input the first frame signal clock into the frame synchronization signal generation module (30).

5. The synchronized metronome according to claim 1, characterized in that, The synchronizer also includes: Synchronization signal output module (40) is used to input the first clock signal into another synchronizer as a second clock signal of the other synchronizer.

6. The synchronized metronome according to claim 1, characterized in that, The signal detection module (20) includes: An internal signal detector (21) is used to output a first detection signal when detecting the first clock signal; An external signal detector (22) is used to output a second detection signal when the second clock signal is detected; The output terminals of the external signal detector (22) and the internal signal detector (21) are respectively connected to the input terminal of the AND gate circuit (23). The output terminal of the AND gate circuit (23) is connected to the input terminal of the frame synchronization signal generation module (30). When the AND gate circuit (23) receives the first detection signal and the second detection signal, it inputs the synchronization start signal to the frame synchronization signal generation module (30).

7. A data acquisition and synchronization device, characterized in that, include: First synchronized metronome (101); Second synchronized metronome (102); The first synchronizer (101) and the second synchronizer (102) are structured as the synchronizer described in any one of claims 1 to 6; The first metronome (101) and the second metronome (102) are connected. The first clock signal of the first metronome (101) is sent to the second metronome (102) as the second clock signal of the second metronome (102). The first metronome (101) receives the first clock signal from the second metronome (102) as the second clock signal of the first metronome (101).

8. A dual-machine hot standby system, characterized in that, include: First server (103); Second server (104); The data acquisition and synchronization device according to claim 7; The first metronome (101) in the data acquisition synchronization device is connected to the first server (103), and the second metronome (102) is connected to the second server (104). The first server (103) and the second server (104) ensure the synchronous operation of the service through the frame synchronization pulse signal generated by the data acquisition synchronization device.

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