Systolic array structure supporting four single-bit computing modes and computing mode control method

Abstract

This invention discloses a systolic array structure supporting four single-bit computation modes and a computation mode control method, belonging to the technical field of systolic array structures. It improves upon the original systolic array by using combinations of different logic gates to process single-bit computations. By controlling the first and second computation mode selection signals, different computation modes can be controlled, enabling the systolic array to better support four different types of single-bit computation modes: XOR, XNOR, AND, and NAND, thereby improving the applicability of the systolic array to different computation modes.

Description

Technical Field

[0001] This invention relates to a pulsating array structure supporting four single-bit computing modes and a computing mode control method, belonging to the technical field of pulsating array structures. Background Technology

[0002] With the rise of artificial intelligence, deep learning is being applied more and more in various fields. Among deep learning operations, matrix multiplication is used extensively. Currently, a convenient and efficient method for matrix operations is using systolic arrays. One implementation of systolic arrays involves moving A and B through systolic array cells and storing the result Y within those cells. This invention improves upon this approach; in matrix operations, the two matrices to be multiplied are input from different directions within the systolic array, and the final calculation result is stored within the systolic array cells.

[0003] In neural networks, single-bit matrix multiplication is frequently performed. However, single-bit matrix multiplication is often not limited to conventional multiplication and accumulation calculations. In many cases, multiplication calculations are replaced with other calculations such as XOR, XOR, AND, and NAND, and then accumulated. However, there is no systolic array structure in the current technology that can support the above four calculation modes simultaneously. Summary of the Invention

[0004] The purpose of this invention is to provide a pulsating array structure and a computing mode control method that support four single-bit computing modes, thereby solving the problem that the prior art cannot support four single-bit computing modes simultaneously.

[0005] To achieve the above objectives, the present invention employs the following technical solution:

[0006] In a first aspect, the present invention provides a systolic array structure that supports four single-bit computation modes, including multiple interconnected systolic array units. Each systolic array unit includes an input register, a weight register, three NOT gates, four three-input AND gates, a four-input OR gate, an accumulator, and a computation result register. The three-input AND gates include a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate.

[0007] The output of the input register is directly connected to the input of the second and third AND gates, and connected to the input of the first and fourth AND gates through a NOT gate.

[0008] The output of the weight register is directly connected to the inputs of the second and fourth AND gates, and connected to the inputs of the first and third AND gates through a NOT gate.

[0009] It also includes a first transmitter for sending a first calculation mode selection signal, and the output of the first transmitter is connected to the input of a first AND gate;

[0010] It also includes a second transmitter for sending a second calculation mode selection signal. The output of the second transmitter is directly connected to the inputs of the third AND gate and the fourth AND gate, and is connected to the input of the second AND gate through a NOT gate.

[0011] The outputs of the four three-input AND gates are all connected to the inputs of the four-input OR gate. The output of the four-input OR gate is connected to the input of the accumulator. The accumulator calculates the received data and then transmits the calculation result to the calculation result register.

[0012] By sending different first calculation mode selection signals through the first transmitter and different second calculation mode selection signals through the second transmitter, the calculation mode of the input data sent by the input register and the weight data sent by the weight register can be controlled. The first calculation mode selection signal, the second calculation mode selection signal, the input data and the weight data are all single-bit signals.

[0013] In conjunction with the first aspect, it further includes a two-input AND gate, the input of which is connected to the first transmitter and the second transmitter, and the output of which is connected to the reset input of the input register. Each time the first transmitter and the second transmitter receive a reset signal, they send a first calculation mode selection signal and a second calculation mode selection signal, which are transmitted to the input register through the two-input AND gate to achieve the reset of the input register.

[0014] In conjunction with the first aspect, furthermore, the output terminal of the first transmitter is connected to the reset input terminal of the weight register. Each time the first transmitter receives a reset signal, it sends a first calculation mode selection signal to the weight register to achieve the reset of the weight register.

[0015] In conjunction with the first aspect, furthermore, the output terminal of the input register is connected to the input terminal of the input register in the next pulsating array unit, thereby realizing the transmission of input data in the pulsating array unit.

[0016] In conjunction with the first aspect, furthermore, the output terminal of the weight register is connected to the input terminal of the weight register in the next pulsating array unit, thereby realizing the transmission of weight data in the pulsating array unit.

[0017] In conjunction with the first aspect, furthermore, the output terminal of the first transmitter is connected to the input terminal of the first transmitter in the next pulse array unit, thereby realizing the transmission of the first calculation mode selection signal in the pulse array unit.

[0018] In conjunction with the first aspect, furthermore, the output terminal of the second transmitter is connected to the input terminal of the second transmitter in the next pulse array unit, thereby realizing the transmission of the second calculation mode selection signal in the pulse array unit.

[0019] In conjunction with the first aspect, the pulse array unit further comprises nine units, arranged in a 3x3 grid.

[0020] In a second aspect, the present invention also provides a computational mode control method based on the pulsating array structure described in any one of the first aspects, comprising:

[0021] When C=0 and D=0, the input data and weight data are subjected to a single-bit AND operation.

[0022] When C=0 and D=1, the input data and weight data are XORed using a single bit.

[0023] When C=1 and D=1, the input data and weight data are subjected to a single-bit NAND operation.

[0024] When C=1 and D=0, the input data and weight data are subjected to a single-bit XOR operation.

[0025] Wherein, C is the first calculation mode selection signal, and D is the second calculation mode selection signal.

[0026] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0027] The present invention provides a systolic array structure and a calculation mode control method that support four single-bit calculation modes. It improves upon the original systolic array by using a combination of different logic gates to process single-bit calculations. By controlling the first calculation mode selection signal and the second calculation mode selection signal, different calculation modes can be controlled, enabling the systolic array to better support four different types of single-bit calculation modes: XOR, XNOR, AND, and NAND. This improves the applicability of the systolic array to different calculation modes. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a pulsating array unit supporting four single-bit computing modes provided in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a pulsating array structure supporting four single-bit computing modes provided in an embodiment of the present invention;

[0030] Figure 3 This is a computational schematic diagram of a pulsating array structure that supports four single-bit computation modes, provided in an embodiment of the present invention. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to illustrate the technical solution of the present invention more clearly, and should not be used to limit the scope of protection of the present invention.

[0032] Example 1

[0033] like Figure 2 As shown, this embodiment of the invention provides a systolic array structure supporting four single-bit computation modes, comprising nine interconnected systolic array units. Figure 2 To illustrate the connection method between pulsating array units, taking a 3×3 pulsating array structure as an example, numerous pulsating array units form a complete pulsating array structure.

[0034] Figure 2 In the diagram, the three lines between two vertically adjacent pulse array units are used to transmit weight data A, the first calculation mode selection signal C, and the second calculation mode selection signal D, respectively, while the lines between two horizontally adjacent pulse array units are used to transmit input data B.

[0035] like Figure 1 As shown, the systolic array unit includes an input register, a weight register, three NOT gates, four three-input AND gates, one two-input AND gate, one four-input OR gate, an accumulator, and a calculation result register. The three-input AND gates include a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate.

[0036] The output of the input register is directly connected to the input of the second and third AND gates, and connected to the input of the first and fourth AND gates through a NOT gate.

[0037] The output of the weight register is directly connected to the inputs of the second and fourth AND gates, and connected to the inputs of the first and third AND gates through a NOT gate.

[0038] It also includes a first transmitter for sending a first calculation mode selection signal, and the output of the first transmitter is connected to the input of a first AND gate;

[0039] It also includes a second transmitter for sending a second calculation mode selection signal. The output of the second transmitter is directly connected to the inputs of the third AND gate and the fourth AND gate, and is connected to the input of the second AND gate through a NOT gate.

[0040] The outputs of the four three-input AND gates are all connected to the inputs of the four-input OR gate. The output of the four-input OR gate is connected to the input of the accumulator. The accumulator calculates the received data and then transmits the calculation result to the calculation result register.

[0041] By sending different first calculation mode selection signals through the first transmitter and different second calculation mode selection signals through the second transmitter, the calculation mode of the input data sent by the input register and the weight data sent by the weight register can be controlled. The first calculation mode selection signal, the second calculation mode selection signal, the input data and the weight data are all single-bit signals.

[0042] Through the structure of the above-described pulsating array unit, the following can be achieved: the inputs of the first AND gate are ~A, ~B, and C; the inputs of the second AND gate are A, B, and ~D; the inputs of the third AND gate are ~A, B, and D; and the inputs of the fourth AND gate are A, ~B, and D. The inputs of the four three-input AND gates are connected to a four-input OR gate. Then the output of the four-input OR gate is (~A)&(~B)&C+A&B&(~D)+(~A)&B&D+A&(~B)&D. This Boolean logic expression can realize different logical operations between the weighted data A and the input data B when C and D take different values.

[0043] Specific logical operations include:

[0044] When C=0 and D=0, the input data and weight data are subjected to a single-bit AND operation.

[0045] When C=0 and D=1, the input data and weight data are XORed using a single bit.

[0046] When C=1 and D=1, the input data and weight data are subjected to a single-bit NAND operation.

[0047] When C=1 and D=0, the input data and weight data are subjected to a single-bit XOR operation.

[0048] In addition to serving as selection signals, C and D also determine the reset data for the weight register and input register. The reset data for the weight register is signal C, and the reset data for the input register is C and D. This is achieved through the following settings:

[0049] The input of the two-input AND gate is connected to the first transmitter and the second transmitter, and the output of the two-input AND gate is connected to the reset input of the input register. Each time the first transmitter and the second transmitter receive a reset signal, they send a first calculation mode selection signal and a second calculation mode selection signal, which are transmitted to the input register through the two-input AND gate to realize the reset of the input register.

[0050] The output of the first transmitter is connected to the reset input of the weight register. Each time the first transmitter receives a reset signal, it sends a first calculation mode selection signal to the weight register to reset the weight register.

[0051] like Figure 1As shown, the output of the input register is connected to the input of the input register in the next systolic array unit, realizing the transmission of input data in the systolic array unit; the output of the weight register is connected to the input of the weight register in the next systolic array unit, realizing the transmission of weight data in the systolic array unit; the output of the first transmitter is connected to the input of the first transmitter in the next systolic array unit, realizing the transmission of the first calculation mode selection signal in the systolic array unit; the output of the second transmitter is connected to the input of the second transmitter in the next systolic array unit, realizing the transmission of the second calculation mode selection signal in the systolic array unit.

[0052] For the input method of a systolic array, taking a 3×3 systolic array as an example, the matrix multiplication calculation is as follows:

[0053] ;

[0054] The weight data matrix and input data matrix are shown in the above formula. The first calculation mode selection signal C and the second calculation mode selection signal D also fill the weight data matrix and input data matrix to form a new input array. The weight data matrix is ​​filled with C, and the input data matrix is ​​filled with C&D, as shown above. Figure 3 As shown, C and D remain unchanged in one calculation.

[0055] Conventional matrix multiplication performs a multiplication-accumulation operation, but in practical single-bit neural network computations, it is often necessary to replace multiplication with operations such as XOR, XOR, AND, and NAND. This invention addresses this need by implementing different types of single-bit matrix computations, effectively improving the adaptability of systolic arrays to different types of matrix multiplication. In matrix operations, the two matrices to be multiplied are input from different directions of the systolic array, and the final calculation result is stored in the systolic array cells.

[0056] Example 2

[0057] This invention also provides a computational mode control method based on the pulsating array structure provided in Embodiment 1, including:

[0058] When C=0 and D=0, the input data and weight data are subjected to a single-bit AND operation.

[0059] When C=0 and D=1, the input data and weight data are XORed using a single bit.

[0060] When C=1 and D=1, the input data and weight data are subjected to a single-bit NAND operation.

[0061] When C=1 and D=0, the input data and weight data are subjected to a single-bit XOR operation.

[0062] Wherein, C is the first calculation mode selection signal, and D is the second calculation mode selection signal.

[0063] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A systolic array architecture supporting four single-bit computation modes, characterized in that, It includes multiple interconnected pulsation array units, each of which includes an input register, a weight register, three NOT gates, four three-input AND gates, a four-input OR gate, an accumulator, and a calculation result register. The three-input AND gates include a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate. The output of the input register is directly connected to the input of the second and third AND gates, and connected to the input of the first and fourth AND gates through a NOT gate. The output of the weight register is directly connected to the inputs of the second and fourth AND gates, and connected to the inputs of the first and third AND gates through a NOT gate. It also includes a first transmitter for sending a first calculation mode selection signal, and the output of the first transmitter is connected to the input of a first AND gate; It also includes a second transmitter for sending a second calculation mode selection signal. The output of the second transmitter is directly connected to the inputs of the third AND gate and the fourth AND gate, and is connected to the input of the second AND gate through a NOT gate. The outputs of the four three-input AND gates are all connected to the inputs of the four-input OR gate. The output of the four-input OR gate is connected to the input of the accumulator. The accumulator calculates the received data and then transmits the calculation result to the calculation result register. By sending different first calculation mode selection signals through the first transmitter and different second calculation mode selection signals through the second transmitter, the calculation mode of the input data sent by the input register and the weight data sent by the weight register can be controlled. The first calculation mode selection signal, the second calculation mode selection signal, the input data and the weight data are all single-bit signals. It also includes a two-input AND gate, the input of which is connected to the first transmitter and the second transmitter, and the output of which is connected to the reset input of the input register. Each time the first transmitter and the second transmitter receive a reset signal, they send a first calculation mode selection signal and a second calculation mode selection signal, which are transmitted to the input register through the two-input AND gate to achieve the reset of the input register.

2. The systolic array architecture supporting four single-bit computation modes according to claim 1, wherein, The output of the first transmitter is connected to the reset input of the weight register. Each time the first transmitter receives a reset signal, it sends a first calculation mode selection signal to the weight register to reset the weight register.

3. The systolic array architecture supporting four single-bit computation modes of claim 1, wherein, The output of the input register is connected to the input of the input register in the next pulsating array unit, thereby enabling the transmission of input data in the pulsating array unit.

4. The systolic array architecture supporting four single-bit computation modes of claim 1, wherein, The output of the weight register is connected to the input of the weight register in the next pulsating array unit, thereby enabling the transmission of weight data in the pulsating array unit.

5. The systolic array architecture supporting four single-bit computation modes according to claim 1, wherein, The output of the first transmitter is connected to the input of the first transmitter in the next pulse array unit, so as to realize the transmission of the first calculation mode selection signal in the pulse array unit.

6. The systolic array architecture supporting four single-bit computation modes according to claim 1, wherein, The output of the second transmitter is connected to the input of the second transmitter in the next pulse array unit, thereby enabling the transmission of the second calculation mode selection signal in the pulse array unit.

7. The systolic array architecture supporting four single-bit computation modes according to claim 1, wherein, The pulse array unit consists of nine units, arranged in a 3x3 grid.

8. A method of controlling the operation of a systolic array structure according to any one of claims 1 to 7, characterized in that include: When C=0 and D=0, the input data and weight data are subjected to a single-bit AND operation. When C=0 and D=1, the input data and the weight data are subjected to single-bit XOR operation; When C=1 and D=1, the input data and the weight data are subjected to single-bit NAND operation; When C=1 and D=0, the input data and the weight data are subjected to single-bit XNOR operation; wherein C is a first calculation mode selection signal, and D is a second calculation mode selection signal.

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