Semiconductor device manufacturing method and semiconductor device

Abstract

The present application discloses a method for preparing a semiconductor device and a semiconductor device, wherein the method comprises the following steps: homogeneously growing an epitaxial layer on a first silicon carbide substrate; making a doped well region in an epitaxial defect layer formed in the epitaxial layer and bonding it to a second silicon carbide substrate; the substrate quality of the first silicon carbide substrate is higher than that of the second silicon carbide substrate; peeling off a part of the device structure including the first silicon carbide substrate along the epitaxial defect layer and post-processing the peeled surface to expose the second surface in the peeled epitaxial layer; bonding the second surface after the conductive treatment to a silicon substrate; removing the second silicon carbide substrate, activating the bonding interface, and preparing a gate oxide layer and a metal layer to form a semiconductor device. Thus, the difficulty of growing silicon carbide epitaxially on a silicon substrate is solved, and the excellent performance of the silicon carbide material itself can be fully utilized to improve the performance of semiconductor devices, while reducing the dependence on high-quality silicon carbide materials and device costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] Silicon carbide (SiC), as a representative material of the third-generation semiconductors, combines many excellent properties such as wide band gap (2.4eV-3.2eV), high physical strength, high thermal conductivity, high corrosion resistance, high melting point, wide light transmission window (0.37-5.6μm) and wide-area defect luminescence window (visible light to mid-infrared). It is an ideal material for high-voltage power devices.

[0003] In addition, silicon carbide materials have more than 200 crystal forms, among which 3C-SiC, 4H-SiC and 6H-SiC are the most widely used. 3C-SiC thin films are mainly deposited on the surface of silicon substrates using atmospheric pressure chemical vapor deposition (APCVD) and reduced pressure chemical vapor deposition (RPCVD). However, the 3C-SiC thin films prepared by this method are mainly polycrystalline thin films, and the crystal quality cannot reach single crystal. Although relatively pure single crystal materials can be prepared by the PVT (Physical Vapor Transport) method, since the growth temperature of 4H-SiC prepared by the PVT method is greater than the melting point of silicon, single crystal silicon carbide thin films cannot be grown on silicon substrates by traditional thin film deposition heteroepitaxial methods. In addition, at the current 8-inch diameter expansion, problems such as defect control in the silicon carbide growth process and material loss caused by cutting, grinding and polishing have further highlighted the issues of silicon carbide yield and cost. This has increased the production cost of homoepitaxially generated single-crystalline silicon carbide films on large-size silicon carbide substrates, hindering the large-scale use of silicon carbide in the semiconductor field. Summary of the invention

[0004] In view of at least one technical problem in the prior art, the purpose of the present application is to provide a method for preparing a semiconductor device and a semiconductor device.

[0005] In order to solve the above technical problems, on the one hand, the present application provides a method for preparing a semiconductor device, comprising the following steps:

[0006] Providing a first silicon carbide substrate, and homoepitaxially growing an epitaxial layer on the first silicon carbide substrate;

[0007] Performing a first ion implantation on the exposed first surface of the epitaxial layer to form an epitaxial defect layer in the epitaxial layer;

[0008] Fabricating a doped well region between the first surface and the epitaxial defect layer to form a first intermediate device structure;

[0009] Providing a second silicon carbide substrate, and bonding the second silicon carbide substrate to the first intermediate device structure based on the first surface; the substrate quality of the first silicon carbide substrate is higher than the substrate quality of the second silicon carbide substrate;

[0010] Along the layer direction of the epitaxial defective layer, a portion of the device structure including the first silicon carbide substrate is peeled off and a peeled surface is post-processed to expose a second surface in the peeled epitaxial layer;

[0011] Performing a conductive treatment on the second surface to form a second intermediate device structure;

[0012] Providing a silicon substrate, and bonding the inverted second intermediate device structure based on the second surface;

[0013] removing the second silicon carbide substrate and activating the bonding interface to form a third intermediate device structure;

[0014] A gate oxide layer and a metal layer are prepared on the third intermediate device structure to form a semiconductor device.

[0015] In an optional embodiment, the implantation parameters of the first ions include at least one of the following:

[0016] The implanted element of the first ion includes one or more of hydrogen ions and helium ions;

[0017] The implantation dose of the first ion is in the range of 1E17 / cm 2 ~1E20 / cm 2 ;

[0018] The implantation energy of the first ions ranges from 2 MeV to 10 MeV.

[0019] In an optional embodiment, the doping element of the epitaxial layer includes one or more of nitrogen and phosphorus, and the doping concentration range is 1E12-1E15 / cm 3 ;

[0020] The measurement dimensions of the substrate quality include one or more of the substrate crystal type quantity, substrate crystal type, and substrate defect density.

[0021] In an optional embodiment, the post-processing of the peeled surface to expose the second surface of the peeled epitaxial layer comprises:

[0022] Based on a preset thinning thickness, the peeling surface is thinned;

[0023] Using the exposed peeled surface after the thinning process as the second surface in the peeled epitaxial layer;

[0024] The preset thinning thickness is any value between 1.5 and 3 μm.

[0025] In an optional implementation manner, performing conductive processing on the second surface to form a second intermediate device structure includes:

[0026] Performing a second ion implantation on the second surface to form a conductive layer in the stripped epitaxial layer; the type of the second ions is different from the type of the first ions; and the upper edge of the conductive layer is flush with the second surface;

[0027] The conductive layer and the doped well region are subjected to an annealing process to form the second intermediate device structure.

[0028] In an optional embodiment, the processing conditions of the primary annealing treatment include at least one of the following:

[0029] The annealing environment is vacuum, nitrogen atmosphere, or argon atmosphere;

[0030] The annealing temperature is 1500-1800°C, the annealing time is 0.5-5 hours, and the annealing time is inversely proportional to the annealing temperature;

[0031] A carbon film is applied for protection before annealing. The thickness of the carbon film is 100-1000 nanometers. The thickness of the carbon film is proportional to the annealing temperature and inversely proportional to the annealing pressure.

[0032] In an optional embodiment, activating the bonding interface to form a third intermediate device structure includes:

[0033] A secondary annealing process is performed on the device structure with the second silicon carbide substrate removed to activate the bonding interface between the silicon substrate and the inverted second intermediate device structure to form the third intermediate device structure.

[0034] In an optional embodiment, the processing conditions of the secondary annealing treatment include at least one of the following:

[0035] The annealing environment is vacuum or nitrogen atmosphere;

[0036] The annealing temperature is 1300-1370°C, and the annealing time is 3-5 hours. The annealing time is inversely proportional to the annealing temperature.

[0037] A carbon film is protected before annealing. The thickness of the carbon film is 100-500 nanometers. The thickness of the carbon film is proportional to the annealing temperature and inversely proportional to the annealing pressure.

[0038] In an optional embodiment, the first silicon carbide substrate is a single crystal silicon carbide substrate;

[0039] The second silicon carbide substrate includes at least one of a mixed crystal silicon carbide substrate and a polycrystalline silicon carbide substrate;

[0040] The resistance of the silicon substrate is lower than or equal to 10 ohms, and the conductivity type of the silicon substrate is the same as the conductivity type of the first silicon carbide substrate.

[0041] On the other hand, the present application also provides a semiconductor device, which is prepared by any method described in the embodiments of the present application.

[0042] The semiconductor device manufacturing method and the semiconductor device of the present application have at least the following beneficial effects:

[0043] In the embodiment of the present application, in the process of preparing the semiconductor device, only a high-quality first silicon carbide substrate is used for homogeneous epitaxial epitaxial layer, and the epitaxial layer is bonded to the low-quality second silicon carbide substrate, and the epitaxial defect layer formed in the epitaxial layer is used to peel off part of the device structure including the high-quality first silicon carbide substrate, and then the peeled device structure is transferred to the silicon substrate, and the doped well region is separated from the gate oxide layer and the metal layer to form a semiconductor device including a silicon substrate and a silicon carbide epitaxial layer. Therefore, the preparation process provided by the present application solves the problem of epitaxial silicon carbide on a silicon substrate. In addition, the prepared semiconductor device contains a part of the peeled silicon carbide epitaxial layer, which is conducive to exerting the excellent performance of the silicon carbide material itself and improving the performance of the semiconductor device. In addition, by first transferring the epitaxial silicon carbide film to a low-cost second silicon carbide substrate, and then transferring it to the silicon substrate through heterogeneous bonding, on the basis of overcoming the difficulties of preparing silicon carbide materials on a silicon basis, the cost of silicon carbide monolithic wafers is reduced, and the wafer size can be further expanded to 8 inches following the progress of the industry, while ensuring its compatibility with the existing silicon-based integrated circuit process. Furthermore, the prepared semiconductor device does not contain a high-quality first silicon carbide substrate, and only uses a high-quality first silicon carbide substrate to grow an epitaxial silicon carbide epitaxial layer, which reduces the dependence on high-quality silicon carbide materials, reduces device costs, and is conducive to increasing the widespread application of silicon carbide in the semiconductor field. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 is a flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0046] Figure 2 It is a schematic structural diagram of a device in step S102 in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0047] Figure 3 It is a schematic structural diagram of a device in step S103 of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0048] Figure 4 It is a schematic structural diagram of a device in step S105 in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0049] Figure 5 It is a schematic structural diagram of a device in step S106 in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0050] Figure 6 It is a schematic structural diagram of a device in step S107 in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0051] Figure 7 It is a schematic structural diagram of a device in step S108 in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0052] Figure 8 It is a schematic structural diagram of a device in step S109 in a method for preparing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0054] The "one embodiment" or "embodiment" referred to below refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. In the description of the present invention, unless otherwise clearly specified and limited, the orientation or position relationship indicated by the terms "upper", "lower", "left", "right", "top", "bottom", etc. is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0055] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being located "on" or "above" another layer or another region, it may mean that it is directly located on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be located "below" or "beneath" another layer or another region.

[0056] In the related art, although relatively pure single crystal materials can be prepared by the PVT (Physical Vapor Transport) method, since the growth temperature of 4H-SiC prepared by the PVT method is greater than the melting point of silicon, it is impossible to grow single crystal silicon carbide thin films on silicon substrates by the traditional thin film deposition heteroepitaxial method. In addition, at the current 8-inch diameter expansion, problems such as defect control in the silicon carbide growth process and material loss caused by cutting, grinding and polishing have further highlighted the silicon carbide yield and cost issues, thus increasing the production cost of homoepitaxially generating single crystal silicon carbide thin films on large-sized silicon carbide substrates, hindering the large-scale use of silicon carbide in the semiconductor field. To this end, the embodiment of the present application provides a method for preparing semiconductor devices containing silicon carbide at low cost.

[0057] Figure 1 It is a flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application. Figures 2 to 8It is a schematic diagram of the device in each step of the method for preparing a semiconductor device of some preferred embodiments of the present application. The accompanying drawings are only schematic diagrams of multiple embodiments including common and possibly non-common parts, and the parts with differences or distinctions are presented in a textual description. In order to reduce lengthy and unnecessary repeated descriptions of embodiments, based on the characteristics of the industry and the essence of the technology, technicians familiar with the field should be able to correctly and reasonably understand and judge whether the individual technical features described below or any combination of them can be characterized in the same embodiment, or whether multiple technical features that are mutually exclusive in essence can only be characterized in different variations.

[0058] An embodiment of the present application provides a method for preparing a semiconductor device, which includes the following steps.

[0059] Step S101 , providing a first silicon carbide substrate, and homoepitaxially growing an epitaxial layer on the first silicon carbide substrate.

[0060] The first silicon carbide substrate may refer to a high-quality silicon carbide substrate suitable for preparing semiconductor devices. Specifically, the first silicon carbide substrate may be a single crystal substrate with a low defect content, and the size of the silicon carbide substrate may be greater than or equal to a preset size threshold, and illustratively, the preset size threshold may be 8 inches. Of course, according to actual needs, the preset size threshold may be a value less than 8 inches or greater than 8 inches.

[0061] In some embodiments, Figure 2 As shown, an epitaxial layer 220 can be homoepitaxially grown on the first silicon carbide substrate 210 by an epitaxial process. The epitaxial process refers to the process of growing a completely ordered single crystal layer on a substrate. Generally speaking, the epitaxial process is to grow a crystal layer with the same lattice orientation as the original substrate on a single crystal substrate, which is equivalent to extending the crystal of the single crystal substrate outward for a section. Here, the epitaxial layer 220 is made of the same material as the first silicon carbide substrate 210 and has the same lattice orientation, that is, a single crystal silicon carbide epitaxial layer is obtained.

[0062] In some embodiments, the epitaxial layer 220 has a thickness of 11 μm to 21 μm. Specifically, the thickness may be 10 μm to 20 μm, such as 10.2 μm, 12 μm, 15 μm, 18.1 μm, and 20 μm.

[0063] In some embodiments, the epitaxial layer 220 has the same material properties as the first silicon carbide substrate 210. For example, if the first silicon carbide substrate 210 is an N-type silicon carbide substrate doped with a first dopant (e.g., nitrogen, phosphorus, or a combination thereof), the epitaxial layer 220 is the n-region of the device. The n-region can be obtained by doping the initial epitaxial layer obtained by epitaxy, and the doping elements of the epitaxial layer can include one or more of nitrogen and phosphorus, and the doping concentration range can be 1E12 to 1E15 / cm 3 For another example, if the first silicon carbide substrate 210 is a P-type silicon carbide substrate, the epitaxial layer 220 is a p-region of the device. The p-region can be obtained by doping the epitaxial layer obtained by epitaxy, and the doping element of the epitaxial layer includes boron, and the doping concentration range can be 1E12 to 1E15 / cm 3 .

[0064] Step S102 , performing a first ion implantation on the exposed first surface of the epitaxial layer to form an epitaxial defect layer in the epitaxial layer.

[0065] In some embodiments, continuing as Figure 2 As shown, the first surface a1 may be the exposed top surface of the epitaxial layer. The first ion implantation is performed on the exposed first surface a1 of the epitaxial layer 220 by an ion implantation process to form an epitaxial defect layer 222 in the epitaxial layer 220. The distance between the epitaxial defect layer and the exposed first surface of the epitaxial layer is much greater than the distance between the epitaxial defect layer and the lower edge of the epitaxial layer.

[0066] In some embodiments, the implantation energy of the first ion may be 5 to 15 times the conventional ion implantation energy. As an example only, the implantation energy of the first ion ranges from 2 MeV to 10 MeV, such as 3 MeV, 4 MeV, 4.5 MeV, 5.8 MeV, 7 MeV, 8 MeV, 9 MeV, 9.6 MeV, etc. The implantation energy of the first ion used here is much higher than the conventional ion implantation energy. Thus, through high ion implantation energy, the implantation depth of the obtained epitaxial defect layer 222 in the epitaxial layer 220 is deeper, which facilitates subsequent stripping to obtain a thicker stripped epitaxial film, that is, a stripped silicon carbide film, so that the preparation of a semiconductor device containing the stripped silicon carbide film fully utilizes the good performance of single-crystal silicon carbide.

[0067] In some embodiments, the implanted element of the first ions includes one or more of hydrogen ions and helium ions.

[0068] In some embodiments, the implantation dose of the first ion is in the range of 1E17 / cm 2 ~1E20 / cm 2 Any value in .

[0069] Step S103 , forming a doped well region between the first surface and the epitaxial defect layer to form a first intermediate device structure.

[0070] In some embodiments, Figure 3 As shown, a first well region 232a and a second well region 232b can be formed in the epitaxial layer by doping a second dopant between the first surface a1 and the epitaxial defect layer 222. The first well region 232a and the second well region 232b are arranged side by side and spaced apart, for example, the first well region 232a and the second well region 232b can be arranged at two corner regions of the epitaxial layer. Afterwards, the first dopant is doped in the first well region 232a and the second well region 232b respectively to form a first doping region 234a and a second doping region 234b, and the upper surface of the first doping region 234a and the upper surface of the second doping region 234b can be flush with the upper surface of the epitaxial layer 220, respectively. The doped well region 230 is formed by the first well region 232a and the corresponding first doping region 234a, and the second well region 232b and the corresponding second doping region 234b, to form a first intermediate device structure.

[0071] The preparation process for forming the well region and the corresponding doping region here may be: firstly depositing a mask on the epitaxial layer, and then respectively doping the exposed portions through the mask to realize the generation of the well region and the corresponding doping region.

[0072] The first dopant and the second dopant have different conductivity types. For example, if the conductivity type of the first dopant is N-type, the conductivity type of the second dopant is P-type, that is, a doped well region is formed including a P-type first well region 232a and a P-type second well region 232b, and an N-type first doping region 234a and an N-type second doping region 234b covering a portion of each well region.

[0073] In addition, after the doped well region is prepared on the surface of the implanted epitaxial structure, the subsequent bonding step can be directly performed without performing a doping activation process.

[0074] Step S104 , providing a second silicon carbide substrate, and bonding it to the first intermediate device structure based on the first surface; the substrate quality of the first silicon carbide substrate is higher than the substrate quality of the second silicon carbide substrate.

[0075] In some embodiments, the substrate quality of the first silicon carbide substrate 210 is higher than the substrate quality of the second silicon carbide substrate 240. That is, the second silicon carbide substrate 240 does not use high-quality single-crystal silicon carbide, but uses low-quality silicon carbide. The measurement dimensions of the substrate quality include one or more of the number of substrate crystal forms, the type of substrate crystal forms, and the substrate defect density.

[0076] As an example only, the first silicon carbide substrate 210 includes a high-quality single-crystal silicon carbide substrate, such as 4H-SiC, etc. The second silicon carbide substrate 240 may include one or more of a test-grade (Dummy-grade) single-crystal silicon carbide substrate, a mixed-crystal silicon carbide substrate, and a polycrystalline silicon carbide substrate. In addition, the defect density (e.g., micropipe density) content of the first silicon carbide substrate 210 is lower than the defect density of the second silicon carbide substrate 240.

[0077] In some embodiments, Figure 4 As shown, after providing the second silicon carbide substrate 240, the second silicon carbide substrate 240 can be bonded to the first surface a1 of the first intermediate device structure by a wafer bonding process to obtain a first bonding structure. The wafer bonding process includes but is not limited to one or more of direct bonding and hydrophilic bonding. Taking direct bonding as an example, the surface to be bonded is subjected to plasma activation treatment, and the two surfaces are directly bonded. The type of plasma activation includes but is not limited to nitrogen, oxygen or argon, and the bonding temperature can be 20-800°C.

[0078] Step S105 , stripping a portion of the device structure including the first silicon carbide substrate along the layer direction of the epitaxial defective layer and performing post-processing on the stripped surface to expose the second surface of the stripped epitaxial layer.

[0079] In some embodiments, continuing as Figure 4 As shown, the first bonding structure can be peeled off along the layer direction of the epitaxial defective layer 222 by a peeling process, and part of the device structure including the first silicon carbide substrate 210 can be peeled off, and the peeled surface can be post-processed to expose the second surface a2 in the peeled epitaxial layer 220a. The peeling process can include but is not limited to mechanical peeling or thermal peeling. Post-processing the peeled surface can improve the quality of the peeled surface and reduce the adverse effects of the defective layer.

[0080] Optionally, the thickness of the stripped epitaxial layer 220 a may be 10 μm to 20 μm, such as 10 μm, 11.8 μm, 14.9 μm, 18 μm, and 19.8 μm, etc. The difference in thickness between the epitaxial layer 220 and the stripped epitaxial layer 220 a may be greater than or approximately equal to zero.

[0081] In some embodiments, post-processing the peeling surface to expose the second surface of the peeled epitaxial layer includes: thinning the peeling surface based on a preset thinning thickness; using the exposed peeling surface after the thinning process as the second surface of the peeled epitaxial layer; wherein the preset thinning thickness is any value between 1.5 and 3 μm.

[0082] Specifically, the stripping surface can be thinned by an etching thinning process according to a preset thinning thickness, and then the stripping surface after the thinning process is exposed, and the exposed stripping surface after the thinning process is used as the second surface of the stripped epitaxial layer. The preset thinning thickness can be 1.5μm, 1.8μm, 2μm, 2.3μm, 2.5μm, 2.7μm, or 3μm.

[0083] Step S106, performing conductive processing on the second surface to form a second intermediate device structure.

[0084] The interface of the second intermediate device structure for bonding with the silicon substrate is conductive, and the conductive treatment can be achieved by ion implantation or other methods.

[0085] In some embodiments, performing conductive processing on the second surface to form a second intermediate device structure includes:

[0086] Performing a second ion implantation on the second surface to form a conductive layer in the stripped epitaxial layer; the type of the second ions is different from the type of the first ions; and the upper edge of the conductive layer is flush with the second surface;

[0087] The conductive layer and the doped well region are subjected to an annealing process to form a second intermediate device structure.

[0088] In the embodiments of the present application, Figure 5 As shown, by performing a second ion implantation on the second surface a2, a conductive layer 224 is formed in the stripped epitaxial layer 220a, and the upper edge of the conductive layer 224 can be flush with the second surface. The type of the second ion is different from the type of the first ion. Unlike the first ion used for film stripping, the second ion can be an ion used to form a conductive layer, such as one or more N-type implanted ions such as nitrogen and phosphorus, and the implantation dose is 5E13-1E16 / cm 2 , the injection energy is 5keV~30keV.

[0089] Furthermore, after the second ion implantation, the conductive layer 224 and the doped well region 230 are subjected to an annealing treatment to activate all implanted doped regions to form a second intermediate device structure. In this way, there is no need to perform activation treatment immediately after the doped well region is prepared, but the conductive layer and the doped well region are activated together, thereby reducing the activation treatment process and shortening the device preparation process. In addition, by reducing the number of activation times, the defects or adverse effects caused by activation can be reduced, which is beneficial to improving the recovery value of the first silicon carbide substrate and the overall device performance.

[0090] In some embodiments, the processing conditions of the primary annealing process may include at least one of the following:

[0091] The annealing environment is vacuum, nitrogen atmosphere, or argon atmosphere (pressure is 0.2 to 0.5 atmospheres);

[0092] The annealing temperature is 1500-1800°C, the annealing time is 0.5-5 hours, and the annealing time is inversely proportional to the annealing temperature;

[0093] A carbon film is applied for protection before annealing. The thickness of the carbon film is 100 to 1000 nanometers. The thickness of the carbon film is directly proportional to the annealing temperature and inversely proportional to the annealing pressure.

[0094] Step S107 , providing a silicon substrate, and bonding the second inverted intermediate device structure based on the second surface.

[0095] The conductivity type of the silicon substrate may be the same as that of the first silicon carbide substrate 210. For example, the silicon substrate may be an N-type low-resistance silicon wafer. Optionally, the resistance of the silicon substrate is less than or equal to 10 ohms, for example, the resistance of the silicon substrate is 0.01 to 10 ohms.

[0096] like Figure 6 As shown, after obtaining the N-type low-resistance silicon substrate 250, the silicon substrate 250 can be bonded to the inverted second intermediate device structure for a second time through a wafer bonding process, and the bonding surface is the second surface a2 after the conductive treatment in the second intermediate device structure and the top surface of the silicon substrate 250. The wafer bonding process includes but is not limited to one or more of direct bonding and hydrophilic bonding. Taking direct bonding as an example, the surface to be bonded is subjected to plasma activation treatment, and the two surfaces are directly bonded. The type of plasma activation includes but is not limited to nitrogen, oxygen or argon, and the bonding temperature can be 20-800°C.

[0097] Step S108, removing the second silicon carbide substrate and activating the bonding interface to form a third intermediate device structure.

[0098] like Figure 7 As shown, after bonding with the silicon substrate, the second silicon carbide substrate 240 can be removed by, for example, a thinning process (e.g., mechanical grinding, etc.), leaving the epitaxial layer 220a, the conductive layer 224, and the silicon substrate 250. Next, the bonding interface between the silicon substrate and the second intermediate device structure is activated by an activation process to form a third intermediate device structure.

[0099] In some embodiments, activating the bonding interface to form the third intermediate device structure includes: performing a secondary annealing process on the device structure with the second silicon carbide substrate 240 removed to activate the bonding interface between the silicon substrate 250 and the inverted second intermediate device structure to form the third intermediate device structure.

[0100] In some embodiments, the processing conditions of the secondary annealing process may include at least one of the following:

[0101] The annealing environment is vacuum, nitrogen atmosphere, or argon atmosphere (pressure is 0.2 to 0.5 atmospheres);

[0102] The annealing temperature is 1300-1370°C, and the annealing time is 3-5 hours. The annealing time is inversely proportional to the annealing temperature.

[0103] A carbon film is applied for protection before annealing. The thickness of the carbon film is 100 to 500 nanometers. The thickness of the carbon film is directly proportional to the annealing temperature and inversely proportional to the annealing pressure.

[0104] Step S109: preparing a gate oxide layer and a metal layer on the third intermediate device structure to form a semiconductor device.

[0105] After the third intermediate device structure is formed, a gate oxide layer and a metal layer may be prepared on the third intermediate device structure to form a semiconductor device.

[0106] In some embodiments, Figure 8 As shown, the gate oxide layer 260 may include a gate 264 and an interlayer dielectric layer 262 . The interlayer dielectric layer 262 is disposed on the top surface of the third intermediate device structure, and the gate 264 is disposed inside the interlayer dielectric layer 262 .

[0107] The metal layer 280 includes a first metal layer 282 disposed on the back of the third intermediate device structure and used to form a drain, and a second metal layer 284 disposed on the top surface of the third intermediate device structure and used to form a source. The first metal layer 282 is disposed on the back of the silicon substrate in the third intermediate device structure. The middle portion of the second metal layer 284 covers the gate oxide, and the two side portions of the second metal layer 284 cover the top surface of the third intermediate device structure and are flush with the side surfaces of the third intermediate device structure. Specifically, a second metal layer 284 is deposited on the upper surface of the third intermediate device structure and the upper surface of the gate oxide layer 260, and a source is formed by an annealing process. Among them, the material of the deposited metal includes but is not limited to Al, AlCu (aluminum-copper alloy), AlSiCu (aluminum-silicon-copper alloy), and the thickness of the second metal layer can be 1 to 10 μm.

[0108] The semiconductor device formed here may refer to a planar MOSFET (Metal-Oxide-SemiconductorField-Effect Transistor) device, or a trench MOSFET device. It should be noted that when forming a trench MOSFET device, a trench (not shown) may be first formed in the third intermediate device structure, and then a gate oxide and a metal layer may be prepared on the third intermediate device structure after the trench is formed to obtain the trench MOSFET device.

[0109] In the above embodiment, during the preparation process of the semiconductor device, only a high-quality first silicon carbide substrate is used to homogeneously epitaxially grow an epitaxial layer, and the epitaxial layer is bonded to a low-quality second silicon carbide substrate, and the epitaxial defect layer formed in the epitaxial layer is used to peel off part of the device structure including the high-quality first silicon carbide substrate, and then the peeled device structure is transferred to the silicon substrate, and the doped well region is separated from the gate oxide layer and the metal layer to form a semiconductor device including a silicon substrate and a silicon carbide epitaxial layer. Therefore, the preparation process provided by the present application solves the problem of epitaxially growing silicon carbide on a silicon substrate. In addition, the prepared semiconductor device contains a part of the peeled silicon carbide epitaxial layer, which is conducive to exerting the excellent performance of the silicon carbide material itself and improving the performance of the semiconductor device. In addition, by first transferring the epitaxial silicon carbide film to a low-cost second silicon carbide substrate, and then transferring it to the silicon substrate through heterogeneous bonding, on the basis of overcoming the difficulties in preparing silicon carbide materials on a silicon basis, the cost of silicon carbide monolithic wafers is reduced, and the wafer size can be further expanded to 8 inches following the progress of the industry, while ensuring its compatibility with the existing silicon-based integrated circuit process. Furthermore, the prepared semiconductor device does not contain a high-quality first silicon carbide substrate, and only uses a high-quality first silicon carbide substrate to grow an epitaxial silicon carbide epitaxial layer, which reduces the dependence on high-quality silicon carbide materials, reduces device costs, and is conducive to increasing the widespread application of silicon carbide in the semiconductor field.

[0110] In some embodiments, the method further includes: recycling the first silicon carbide substrate after stripping.

[0111] In some embodiments, the recycling step may include: first performing thermal oxidation treatment on the peeled first silicon carbide substrate, then removing the oxide layer with hydrofluoric acid, and finally polishing the remaining surface of the first silicon carbide substrate after the hydrofluoric acid treatment, so as to obtain the recycled first silicon carbide substrate. The recycled first silicon carbide substrate can continue to be used in the preparation of semiconductor devices to achieve the recycling of the first silicon carbide substrate. This recycling method is different from the conventional grinding and polishing process. It can maximize the number of times the substrate is used while ensuring the wafer morphology of the substrate, thereby reducing the production cost of the prepared semiconductor device while taking into account the performance of silicon carbide.

[0112] In a specific embodiment, the recycling step may specifically include: firstly thermally oxidizing the peeled first silicon carbide substrate, wet oxidizing it in a 1300°C pure oxygen environment for 2 to 5 hours; then using hydrofluoric acid wet etching to remove the oxide layer, and finally fine polishing the remaining surface of the first silicon carbide substrate after the hydrofluoric acid treatment, wherein the thickness of the thin film removed does not exceed 500nm, thereby obtaining the recycled first silicon carbide substrate.

[0113] Since the ion implantation energy is large and the defect layer is deep, it is difficult to solve it with a simple chemical mechanical polishing process. Since the defect layer after implantation is more easily oxidized, a high-temperature thermal oxidation treatment is proposed, especially a thermal oxidation temperature higher than the silicon oxidation temperature, such as a thermal oxidation temperature of 1300°C, which is higher than the Si oxidation temperature to improve efficiency. After the defect layer is completely oxidized, the intact lattice below is better preserved due to the dual effects of the single crystal and the top oxide layer protection. Through hydrofluoric acid wet etching and a small amount of removal, the surface defect layer can be completely removed while ensuring the wafer morphology. Finally, only a small amount of polishing removal is required to retain the high-quality silicon carbide substrate to the maximum extent, ensure the wafer morphology of the substrate, and maximize the number of times the substrate is used.

[0114] It should be noted that the first silicon carbide substrate used in the above step may be a silicon carbide substrate obtained through the above recycling process.

[0115] An embodiment of the present application also provides a semiconductor device, which is prepared by any of the above-mentioned methods for preparing a semiconductor device.

[0116] In some embodiments, continuing as Figure 8 As shown, the semiconductor device includes a silicon substrate 250, a stripped epitaxial layer 220a disposed on the silicon substrate 250, a gate oxide layer 260 and a metal layer 280. The silicon substrate 250 and the stripped epitaxial layer 220a are made of different materials.

[0117] A conductive layer 226 is provided in a portion of the stripped epitaxial layer 220a close to the silicon substrate 250, and an activated doped well region is provided in the stripped epitaxial layer 220a. The doped well region includes a first well region and a second well region arranged side by side and at intervals, and a first doped region and a second doped region of opposite conductivity types respectively arranged in the first well region and the second well region. The first well region and the second well region may be arranged at two corner regions of the epitaxial layer, and the upper surface of the first doped region and the upper surface of the second doped region may be flush with the upper surface of the stripped epitaxial layer, respectively.

[0118] In some embodiments, the gate oxide layer 260 may include a gate 264 and an interlayer dielectric layer 262 . The interlayer dielectric layer 262 is disposed on a top surface of the third intermediate device structure, and the gate 264 is disposed inside the interlayer dielectric layer 262 .

[0119] The metal layer 280 includes a first metal layer 282 disposed on the back of the third intermediate device structure and used to form a drain, and a second metal layer 284 disposed on the top surface of the third intermediate device structure and used to form a source. The first metal layer 282 is disposed on the back of the silicon substrate in the third intermediate device structure. The middle portion of the second metal layer 284 covers the gate oxide, and the two side portions of the second metal layer 284 cover the top surface of the third intermediate device structure and are flush with the side surfaces of the third intermediate device structure. Specifically, a second metal layer 284 is deposited on the upper surface of the third intermediate device structure and the upper surface of the gate oxide layer, and a source is formed by an annealing process. The material of the deposited metal includes but is not limited to Al, AlCu (aluminum-copper alloy), and AlSiCu (aluminum-silicon-copper alloy), and the thickness of the formed second metal layer can be 1 to 10 μm.

[0120] The semiconductor device formed here may refer to a planar MOSFET (Metal-Oxide-SemiconductorField-Effect Transistor) device, or a trench MOSFET device. It should be noted that when forming a trench MOSFET device, a trench may be first formed in the third intermediate device structure, and then a gate oxide and a metal layer may be prepared on the third intermediate device structure after the trench is formed to obtain the trench MOSFET device.

[0121] In some embodiments, the first silicon carbide substrate used in the preparation process of the semiconductor device may be a silicon carbide substrate obtained after a stripping and recycling process.

[0122] In some embodiments, the recycling step may include: first performing thermal oxidation treatment on the peeled first silicon carbide substrate, then removing the oxide layer with hydrofluoric acid, and finally polishing the remaining surface of the first silicon carbide substrate after the hydrofluoric acid treatment, so as to obtain the recycled first silicon carbide substrate. The recycled first silicon carbide substrate can continue to be used in the preparation of semiconductor devices to achieve the recycling of the first silicon carbide substrate. This recycling method is different from the conventional grinding and polishing process, and can maximize the number of times the substrate is used while ensuring the wafer morphology of the substrate.

[0123] In a specific embodiment, the recycling process may specifically include: firstly subjecting the peeled first silicon carbide substrate to thermal oxidation treatment, wet oxidation in a 1300°C pure oxygen environment for 2 to 5 hours; then using hydrofluoric acid wet etching to remove the oxide layer, and finally fine polishing the remaining surface of the first silicon carbide substrate after hydrofluoric acid treatment, with the film removal thickness not exceeding 500nm, to obtain the recycled first silicon carbide substrate. This recycling method is different from the conventional grinding and polishing process, and can maximize the number of times the substrate is used while ensuring the wafer morphology of the substrate, thereby greatly reducing the production cost of the prepared semiconductor device while taking into account the performance of silicon carbide.

[0124] It should be noted that the specific details and beneficial effects of the above-mentioned device embodiment can be found in the above-mentioned method embodiment, which will not be repeated here.

[0125] The above description has fully disclosed the specific implementation methods of the present application. It should be pointed out that any changes made by technicians familiar with the field to the specific implementation methods of the present application do not deviate from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not limited to the above specific implementation methods.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a first silicon carbide substrate, and homoepitaxially growing an epitaxial layer on the first silicon carbide substrate; Performing a first ion implantation on the exposed first surface of the epitaxial layer to form an epitaxial defect layer in the epitaxial layer; the implantation energy of the first ions in the epitaxial layer is 5 to 15 times the conventional ion implantation energy, and the distance between the epitaxial defect layer and the exposed first surface of the epitaxial layer is greater than the distance between the epitaxial defect layer and the lower edge of the epitaxial layer; A doped well region is formed between the first surface and the epitaxial defect layer to form a first intermediate device structure that does not include a gate; in a process between the step of forming the first intermediate device structure and the step of performing a subsequent conductive treatment, the doped well region does not need to be annealed for doping activation; Providing a second silicon carbide substrate, and bonding the second silicon carbide substrate to the first intermediate device structure based on the first surface; The substrate quality of the first silicon carbide substrate is higher than the substrate quality of the second silicon carbide substrate; Along the layer direction of the epitaxial defect layer, a portion of the device structure including the first silicon carbide substrate is peeled off, and a peeled surface of the peeled device structure is post-processed to expose the second surface of the peeled epitaxial layer; the peeled device structure does not include the first silicon carbide substrate; Performing a conductive treatment on the second surface to form a conductive layer, and performing an annealing treatment on the conductive layer and the doped well region to form a second intermediate device structure; the annealing treatment is used to activate dopants in the doped well region, and the annealing treatment is performed after the step of stripping off the first silicon carbide substrate; the second intermediate device structure does not include the first silicon carbide substrate; Providing a silicon substrate, and bonding the inverted second intermediate device structure based on the second surface; removing the second silicon carbide substrate and activating the bonding interface to form a third intermediate device structure; Preparing a gate oxide layer and a metal layer on the third intermediate device structure to form a semiconductor device; Wherein, after forming the second intermediate device structure, the method further comprises: Recycling the first silicon carbide substrate after stripping to obtain a recycled first silicon carbide substrate; the recycled first silicon carbide substrate is used to prepare the semiconductor device; The recycling step includes: firstly performing thermal oxidation treatment on the peeled first silicon carbide substrate, wet oxidation in a 1300°C pure oxygen environment for 2 to 5 hours; then using hydrofluoric acid to remove the oxide layer obtained by the thermal oxidation treatment, and finally polishing the remaining surface of the first silicon carbide substrate after the hydrofluoric acid treatment, wherein the thickness of the film removed after polishing does not exceed 500nm, thereby obtaining the recycled first silicon carbide substrate.

2. The method according to claim 1, characterized in that: The implantation parameters of the first ion include at least one of the following: The implanted element of the first ion includes one or more of hydrogen ions and helium ions; The implantation dose of the first ion is in the range of 1E17 / cm 2 ~1E20 / cm 2 ; The implantation energy of the first ions ranges from 2 MeV to 10 MeV.

3. The method according to claim 1, characterized in that The doping elements of the epitaxial layer include one or more of nitrogen and phosphorus, and the doping concentration range is 1E12-1E15 / cm 3 ; The measurement dimensions of the substrate quality include one or more of the substrate crystal type quantity, substrate crystal type, and substrate defect density.

4. The method according to claim 1, characterized in that: The post-processing of the peeled surface to expose the second surface of the peeled epitaxial layer comprises: Based on a preset thinning thickness, the peeling surface is thinned; Using the exposed peeled surface after the thinning process as the second surface in the peeled epitaxial layer; The preset thinning thickness is any value between 1.5 and 3 μm.

5. The method according to any one of claims 1 to 4, characterized in that: The forming of the second intermediate device structure comprises: Performing a second ion implantation on the second surface to form a conductive layer in the stripped epitaxial layer; the type of the second ions is different from the type of the first ions; and the upper edge of the conductive layer is flush with the second surface; The conductive layer and the doped well region are subjected to an annealing process to form the second intermediate device structure.

6. The method according to claim 5, characterized in that The treatment conditions of the primary annealing treatment include at least one of the following: The annealing environment is vacuum, nitrogen atmosphere, or argon atmosphere; The annealing temperature is 1500-1800°C, the annealing time is 0.5-5 hours, and the annealing time is inversely proportional to the annealing temperature; A carbon film is applied for protection before annealing. The thickness of the carbon film is 100-1000 nanometers. The thickness of the carbon film is proportional to the annealing temperature and inversely proportional to the annealing pressure.

7. The method according to any one of claims 1 to 4, characterized in that: The activating the bonding interface to form a third intermediate device structure comprises: A secondary annealing process is performed on the device structure with the second silicon carbide substrate removed to activate the bonding interface between the silicon substrate and the inverted second intermediate device structure to form the third intermediate device structure.

8. The method according to claim 7, characterized in that The processing conditions of the secondary annealing treatment include at least one of the following: The annealing environment is vacuum or nitrogen atmosphere; The annealing temperature is 1300-1370°C, and the annealing time is 3-5 hours. The annealing time is inversely proportional to the annealing temperature. A carbon film is protected before annealing. The thickness of the carbon film is 100-500 nanometers. The thickness of the carbon film is proportional to the annealing temperature and inversely proportional to the annealing pressure.

9. The method according to any one of claims 1 to 4, characterized in that: The first silicon carbide substrate is a single crystal silicon carbide substrate; The second silicon carbide substrate includes at least one of a mixed crystal silicon carbide substrate and a polycrystalline silicon carbide substrate; The resistance of the silicon substrate is lower than or equal to 10 ohms, and the conductivity type of the silicon substrate is the same as the conductivity type of the first silicon carbide substrate.

10. A semiconductor device, characterized in that: The semiconductor device is prepared by the method according to any one of claims 1-9.

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