IO interface replacement circuit and interface circuit thereof

Abstract

The application provides an IO interface replacement circuit and an IO interface circuit comprising the same. The IO interface replacement circuit comprises: a first IO port and a second IO port configured to receive one of a serial data SDATA signal and a serial clock SCLK signal respectively; a first data selector and a second data selector configured to output first IO port data and second IO port data to their output terminals according to a second selection signal and a first selection signal respectively; a first pulse expansion circuit and a second pulse expansion circuit configured to perform signal expansion on the output of the first data selector and the second data selector; a first latch and a second latch configured to receive the output of the first pulse expansion circuit and the first pulse expansion circuit respectively, and perform latching according to a control signal to output the first selection signal and the second selection signal; and a counter configured to output the control signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of analog integrated circuit design, more particularly, to an IO interface replacement circuit and an IO interface circuit comprising the same. BACKGROUND

[0002] Mobile Industry Processor Interface (MIPI) is a non-profit organization composed of mobile device manufacturers, which is committed to providing a series of standardized interfaces and specifications for mobile devices, including hardware interfaces, software interfaces, communication protocols, etc. MIPI circuits are commonly used in mobile device fields, such as smartphones, tablets, smartwatches, in-vehicle entertainment, etc. The characteristics of MIPI circuits are high speed, low power consumption, high reliability, and excellent anti-interference performance. RF Front-End (RFFE) is a protocol in MIPI, which is an interface protocol for controlling RF front-end components. RF front-end refers to the front-end circuit part used for wireless communication in a mobile phone, including filters, amplifiers, switches, antennas, etc. The RFFE protocol is mainly used to control the switching, gain, frequency selection, etc. of these components, to realize the control and adjustment of RF signals. In the RFFE MIPI protocol, Master and Slave are two different devices, Figure 1 is a schematic diagram showing the relationship between Master and Slave in MIPI RFFE. As Figure 1As shown, the master device is usually a controller or processor, which sends control commands to the slave device through the RFFE bus to control the operation of the slave device. The slave device can be various types of devices, such as RF front-end modules, power amplifier devices (PA), etc. In the RFFE MIPI system, the Master and Slave are in a master-slave relationship, that is, the Master controls the Slave through the RFFE bus, and the Slave can only work under the control of the Master. The communication between Master and Slave adopts MIPI protocol, Master controls the operation of Slave by sending specific command and data packet, Slave returns response result to Master by sending response data packet. In this way, Master can control multiple Slave devices through RFFE bus, thereby realizing the control of the entire RFFE system. In general, Master and Slave are in a master-slave relationship in the RFFE MIPI system, Master controls the operation of the entire system, and Slave passively accepts the control of Master and executes corresponding commands and operations.

[0003] In the RFFE MIPI protocol, VIO, SDATA and SCLK are three signal lines on the RFFE bus, which respectively represent: voltage input / output signal (VIO, Voltage Input / Output), used to connect the power voltage of the RFFE bus and the Master device; serial data signal (SDATA, Serial Data), used to transmit control commands and data information between Master and Slave; serial clock signal (SCLK, Serial Clock), used to synchronize data transmission between Master and Slave, to ensure the correctness and stability of data transmission. These three signal lines are very important components in the RFFE MIPI protocol, which together constitute the RFFE bus and realize the communication and control between Master and Slave. SDATA and SCLK signal lines are closely related, and their relationship is synchronous. Specifically, when Master sends data to Slave, it will generate corresponding data bits according to the clock pulse of SCLK and transmit them through SDATA. When Slave receives data, it will also determine the data transmission rate and transmission timing according to the clock pulse of SCLK, and receive data through SDATA. Therefore, the synchronous relationship between SDATA and SCLK signal lines is a very important part of the RFFE MIPI protocol, which ensures the correctness and reliability of data transmission between Master and Slave. Figure 2is a schematic diagram showing the MIPI circuit. Referring to Figure 2 , the MIPI circuit includes three parts of IO interface circuit, digital circuit and analog circuit. The unique slave identifier (USID) is an identifier in the MIPI protocol, used to identify the slave device in the MIPI system. Each slave device needs a unique USID, and the master device can select a specific slave device for communication through the USID. In MIPI, the USID is an identifier for configuring and controlling the slave device, including information such as hardware interface, transmission protocol, register mapping, etc. In the circuit, USID<3:0> = SA<3:0>, and the slave address (SA) is used to uniquely identify each slave device on the RFFE bus. In the RFFE protocol, each slave device must have a unique SA. Therefore, when the master device needs to communicate with the slave device, the correct SA must be used to address the required slave device.

[0004] In today's 5G mobile phone radio frequency system, multiple main antennas and auxiliary antennas are needed to support multiple frequency bands and multiple antenna combination communication. Therefore, in order to realize such antenna switching, multiple antenna switch devices with MIPI control function are needed, such as single-pole four-throw (SP4T) switch devices. These switch devices communicate with the mobile phone processor through the MIPI bus interface to control different antennas or filters to switch signals between the antenna input and output. This antenna switching technology is crucial for efficient 5G communication and optimizing signal strength. A general SP4T switch has a package size of 1.1x1.1mm, with 9 pins. Figure 3 is a pin diagram of the SP4T switch chip. As shown in Figure 3 , the 9 pins include 5 RF pins

[0005] RF1 / RF2 / RF3 / RF4 / RFC, a GND pin and a set of MIPI signal pins. In order to realize the demand for multiple SP4T antenna switch devices on a mobile phone motherboard, each device needs to have a unique USID, so the manufacturer needs to provide chips with different USIDs. The general practice of manufacturers is to design multiple chips, each of which is configured with different USIDs for mobile phone manufacturers to use. For chip design manufacturers, this approach increases product models and design costs. For mobile phone manufacturers, this approach increases the bill of materials (BOM), which is not conducive to inventory and stock management. SUMMARY

[0006] One aspect of the present application provides an IO interface replacement circuit, comprising a data selector (MUX), a pulse extension circuit (Pulse Extended), a D latch (D Latch) and a counter (Counter). The application of the IO interface replacement circuit according to the embodiment of the present application in the MIPI IO interface circuit can realize the position replacement of SDATA and SCLK, and automatically modify the USID of the chip according to the IO port replacement information, and further can realize the application of two same chips on a mobile phone motherboard. This method can bring many benefits to chip design manufacturers, such as reducing product model quantity and design cost; for mobile phone manufacturers, this method helps to optimize the bill of materials (BOM) to improve the efficiency of inventory and stock management.

[0007] One aspect of the present application provides an IO interface replacement circuit, comprising: a first IO port and a second IO port, the first IO port is configured to receive one of a serial data SDATA signal and a serial clock SCLK signal, and the second IO port is configured to receive the other of the serial data SDATA signal and the serial clock SCLK signal; a first data selector and a second data selector, the first data selector is configured to take the first IO port as one of the inputs of the first data selector and select one of its inputs as the output of the first data selector according to a second selection signal, and the second data selector is configured to take the second IO port as one of the inputs of the second data selector and select one of its inputs as the output of the second data selector according to a first selection signal; a first pulse extension circuit and a second pulse extension circuit, the first pulse extension circuit is configured to be connected to the output of the first data selector, and the second pulse extension circuit is configured to be connected to the output of the second data selector, and the first pulse extension circuit and the second pulse extension circuit are configured to respectively extend the pulse duration of the input signals of the first pulse extension circuit and the second pulse extension circuit; a first latch and a second latch, the first latch is configured to receive the output of the first pulse extension circuit and perform latching according to a control signal to output the first selection signal, and the second latch is configured to receive the output of the second pulse extension circuit and perform latching according to a control signal to output the second selection signal; and a counter, the counter is configured to count a clock signal, and output the control signal according to the countdown time of the counter.

[0008] Another aspect of the present application proposes an IO interface replacement circuit, wherein the first data selector is configured such that a first IO port is connected to a 0th input of the first data selector, and a 1st input of the first data selector is grounded; the second data selector is configured such that a second IO port is connected to a 0th input of the second data selector, and a 1st input of the second data selector is grounded, and wherein when the first selection signal is equal to 0, the 0th input data of the first data selector is passed to an output of the first data selector, and when the first selection signal is equal to 1, the 1st input data of the first data selector is passed to the output of the first data selector; when the second selection signal is equal to 0, the 0th input data of the second data selector is passed to an output of the second data selector, and when the second selection signal is equal to 1, the 1st input data of the second data selector is passed to the output of the second data selector.

[0009] Another aspect of the present application proposes an IO interface replacement circuit, wherein the first pulse expansion circuit and the second pulse expansion circuit are configured to expand the pulse duration of their input signals to be greater than the countdown time of the counter.

[0010] Another aspect of the present application proposes an IO interface replacement circuit, wherein the first latch and the second latch are configured as D-latches, wherein an output of the first pulse expansion circuit is connected to a D-input of the first latch, and the control signal is connected to an E-input of the first latch to output the first selection signal, and wherein an output of the second pulse expansion circuit is connected to a D-input of the second latch, and the control signal is connected to an E-input of the second latch to output the second selection signal.

[0011] Another aspect of the present application proposes an IO interface replacement circuit, wherein the serial data SDATA signal is configured to include a start of sequence condition SSC instruction for indicating the start of a data frame of the SDATA signal.

[0012] Another aspect of the present application proposes an IO interface circuit comprising the IO interface replacement circuit of any one of the above aspects, comprising: the IO interface replacement circuit configured to receive signals from the first IO port and the second IO port and provide the first selection signal and the second selection signal; a third data selector and a fourth data selector, the third data selector configured to take the first IO port as an input of the third data selector and output the input of the third data selector through a 0th output or a 1st output of the third data selector according to the first selection signal, and the fourth data selector configured to take the second IO port as an input of the fourth data selector and output the input of the fourth data selector through a 0th output or a 1st output of the fourth data selector according to the second selection signal; and a first buffer and a second buffer, the first buffer configured to receive signals from the 0th outputs of the third data selector and the fourth data selector and output a buffered serial clock SCLK signal, and the second buffer configured to receive signals from the 1st outputs of the third data selector and the fourth data selector and output a buffered serial data SDATA signal.

[0013] Another aspect of the present application proposes an IO interface circuit, wherein the first buffer is a first buffer configured to receive signals from the 0th outputs of the third data selector and the fourth data selector and output a buffered serial clock SCLK signal.

[0014] Another aspect of the present application proposes an IO interface circuit, wherein the second buffer comprises a second buffer and a third buffer, wherein an input of the second buffer is connected to an output of the third buffer and an output of the second buffer is connected to an input of the third buffer, and wherein signals output from the 1st outputs of the third data selector and the fourth data selector are provided to the input of the third buffer and a buffered serial clock SCLK signal is output from the output of the third buffer.

[0015] Another aspect of the present application proposes an IO interface circuit, further comprising a fifth data selector configured to: a first slave unique identifier USID is provided to a 0th input of the fifth data selector, a second slave unique identifier USID is provided to a 1st input of the fifth data selector, and one of the 0th input and the 1st input of the fifth data selector is selected as a slave unique identifier USID output according to a second selection signal.

[0016] Another aspect of the present application proposes an IO interface circuit, wherein the IO interface replacement circuit is configured to receive a buffered serial clock SCLK signal from the first buffer. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a schematic diagram showing the relationship between a master and a slave in MIPI RFFE;

[0018] Figure 2 is a schematic diagram showing a MIPI circuit;

[0019] Figure 3 is a pin diagram of the SP4T switch chip of

[0020] Figure 4 is a schematic diagram showing an IO interface replacement circuit according to an embodiment of the present application;

[0021] Figure 5 is a schematic diagram showing the instruction format of a write register in RFFE MIPI protocol;

[0022] Figure 6 is a schematic diagram showing an IO interface circuit of MIPI including an IO interface replacement circuit according to an embodiment of the present application;

[0023] Figure 7 is a schematic diagram showing the timing relationship of MIPI circuit signals when IO1 signal is configured as SDATA and IO2 signal is configured as SCLK according to an embodiment of the present application; and

[0024] Figure 8 is a schematic diagram showing the timing relationship of MIPI circuit signals when IO2 signal is configured as SDATA and IO1 signal is configured as SCLK according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] Before undertaking a detailed description of the foregoing, it can be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The term “coupled” and variations thereof, means any direct or indirect communication or interaction between two or more elements, regardless of the type of physical connection or physical contact between them. The terms “transmit,” “receive,” and “communicate,” as well as variations thereof, encompass direct and indirect communication. The terms “include” and “comprise,” as well as variations thereof, mean “including but not limited to.” The term “or” is inclusive, meaning and / or. The phrase “associated with,” as well as variations thereof, means includes, is included within, interconnects with, contains, is contained within, connects or is connected with, couples or is coupled with, communicates or is in communication with, cooperates or is cooperative with, interleafs with, is proximate to, is attached to, or is attached with, has a property, has a relationship or is related to, or the like. The term “controller” means any device, system or part thereof that controls at least one operation. Such a controller can be implemented in hardware or as a combination of hardware and software and / or firmware. The functionality associated with any particular controller can be centralized or distributed, whether locally or remotely. The phrase “at least one of,” when used with respect to a list of items, means that different combinations of one or more of the listed items can be used and only one item from the list can be needed. For example, “at least one of A, B, and C” includes any of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0026] Definitions for other certain words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many if not most instances, such definitions apply to prior as well as future uses of such defined words and phrases.

[0027] In this patent document, the application combination of modules and the division level of sub-modules are for illustration only, and the application combination of modules and the division level of sub-modules can have different ways without departing from the scope of the disclosure.

[0028] Figure 4 A schematic diagram of an IO interface replacement circuit according to an embodiment of the present application is shown. Referring to Figure 4 , the IO interface replacement circuit according to an embodiment of the present application includes port IO1, IO2, SCLK_OUT, SEL_1 and SEL_2 signals. Among them, the IO1 port and the IO2 port respectively represent the SDATA and SCLK signals in the RFFE MIPI protocol, which are configured to be interchangeable. The port SCLK_OUT is configured as the SCLK signal output by the buffer in the RFFE MIPI interface circuit. The IO interface replacement circuit further includes data selector 1 (MUX1), data selector 2 (MUX2), and data selector 3 (MUX3). The IO interface replacement circuit further includes a control signal IO1_SEL, IO2_SEL, SCLK_OUT_SEL, SEL_1 and SEL_2.

[0029] (MUX2), pulse extended circuit 1, pulse extended circuit 2, D latch 1, D latch 2 and counter. Port IO1 signal connects the 0th input end of data selector 1, the 1st input end of data selector 1 is grounded, data selector 1 is controlled by signal SEL_2 signal, the output of data selector 1 is connected to the input end of pulse extended circuit 1, the output of pulse extended circuit 1 is connected to the input end D of D latch 1, the output end Q of D latch 1 is connected to port SEL_1. Port IO2 signal connects the 0th input end of data selector 2, the 1st input end of data selector 2 is grounded, data selector 2 is controlled by signal SEL_1 signal, the output of data selector 2 is connected to the input end of pulse extended circuit 2, the output of pulse extended circuit 2 is connected to the input end D of D latch 2, the output end Q of D latch 2 is connected to port SEL_2. Port SCLK_OUT signal is connected to the input end of counter, the output end of counter is connected to control signal Done, control signal Done is connected to the E input end of D latch 1 and D latch 2 to control the operation of D latch 1 and D latch 2. The IO interface replacement circuit according to the embodiment of the application can conveniently replace the positions of SDATA and SCLK in the MIPI IO interface circuit, and automatically modify the USID of the chip according to the IO port replacement information. This method is not only beneficial to the chip design manufacturer, but also can reduce the bill of materials (BOM) of the mobile phone manufacturer, which is beneficial to the inventory management and stock management.

[0030] According to the embodiment of the application, an IO interface replacement circuit is provided, which comprises a data selector (MUX), a pulse extended circuit (Pulse Extended), a D latch (D Latch) and a counter (Counter). Through the IO interface replacement circuit according to the embodiment of the application, the positions of SDATA and SCLK can be replaced in the MIPI IO interface circuit, and the USID of the chip can be automatically modified according to the IO port replacement information, so that two same chips can be applied to one mobile phone mainboard.

[0031] Figure 5 is a schematic diagram of the instruction format of writing register in RFFE MIPI protocol. Refer to Figure 5which shows the timing diagram of SDATA and SCLK in RFFE MIPI protocol. In which, the sequence start condition (SSC, Sequence Start Condition) instruction is used to indicate the start of SDATA data frame. Before data transmission, the Master sends the SSC signal by controlling the edge of SCLK signal to indicate the start of data transmission. Before the SSC signal, the SCLK signal does not send any data. Because in the MIPI RFFE protocol, the data communication is mainly based on the SDATA data line, and the SCLK clock line is only used to control the transmission speed of the data. Before the SDATA data line sends the SSC signal, the SCLK signal does not send any data.

[0032] Referring back to Figure 4 , assuming that the IO1 signal is the SDATA signal, and the IO2 signal is the SCLK signal,

[0033] at the initial moment, SDATA and SCLK are both 0, the outputs of the pulse expansion circuit 1 and the pulse expansion circuit 2 are 0, the SCLK_OUT signal is 0, the counter does not work, and the Done signal is 0, the outputs of the D latch 1 and the D latch 2 are 0, that is, SEL_1 = SEL_2 = 0. It is assumed that when SEL_1 = 0, the 0 input data of the data selector 2 is transmitted to the output; and when SEL_1 = 1, the 1 input data of the data selector 2 is transmitted to the output. It is assumed that when SEL_2 = 0, the 0 input data of the data selector 1 is transmitted to the output; and when SEL_2 = 1, the 1 input data of the data selector 1 is transmitted to the output. As Figure 5 shown in the timing diagram of data transmission, the IO1 signal is SDATA, and first sends an SSC instruction of "010". This pulse square wave signal is input into the pulse expansion circuit 1, the pulse square wave is expanded, enters the D latch 1, and outputs a high level "1" control signal SEL_1 from the output Q of the D latch 1, which controls the data selector 2 so that the 1 input signal of the data selector 2, that is, the ground "0", is output to the pulse expansion circuit 2, which is further input into the D latch 2 and output to SEL_2. Thus, SEL_1 = 1 and SEL2_ = 0 are temporarily obtained, and the duration of the above two signals is determined by the expansion time of the pulse expansion circuit. Alternatively, it is configured to be greater than the countdown time of the counter.

[0034] Figure 6 is a schematic diagram showing the IO interface circuit of MIPI including the IO interface replacement circuit according to an embodiment of the present application. Referring to Figure 6 , the IO1 port and the IO2 port respectively represent the SDATA and SCLK signals in the RFFE MIPI protocol, and the IO1 port is connected to the data selector 3

[0035] The input terminal of MUX3 is connected to the input terminal of data selector 4 (MUX4). The 0 output terminal of data selector 3 (MUX3) is connected to the input terminal of buffer 1, and the 1 output terminal of data selector 3 (MUX3) is connected to the output terminal of buffer 2 and the input terminal of buffer 3; and the 0 output terminal of data selector 4 (MUX4) is connected to the input terminal of buffer 1 (Buffer1), and the 1 output terminal of data selector 4 (MUX4) is connected to the output terminal of buffer 2 (Buffer2) and the input terminal of buffer 3 (Buffer3). The output terminal of buffer 1 outputs the clock signal SCLK_OUT, and the input terminal of buffer 2 and the output terminal of buffer 3 are connected to provide the data signal SDATA_OUT. The clock signal SCLK_OUT is input to the IO interface replacement circuit according to the embodiment of the present invention and is used as the input of the counter. And through the IO interface replacement circuit according to the embodiment of the present invention, the signal SEL_1 controls data selector 3 (MUX3), and the signal SEL_2 controls data selector 4 (MUX4). In addition, MIPI's IO interface circuit also includes a data selector 5 (MUX5), in which USID1<3:0> is connected to the 0 input of selector 5 (MUX5) and USID2<3:0> is connected to the 1 input of selector 5 (MUX5). The data selector 5 (MUX5) is controlled by the signal SEL_2 to output the corresponding USID.

[0036] refer to Figure 6 When SEL_1 = 1 and SEL_2 = 0, the data from port IO1 is temporarily transferred to buffer 3, and the data from port IO2 is temporarily transferred to buffer 1. At this time, port SCLK_OUT starts outputting the clock signal SCLK. Figure 4 After receiving the SCLK_OUT signal, the counter in the system starts counting down. When the counting cycle time is reached, the Done signal outputs a control signal. At this time, D latch 1 and D latch 2 are configured to enter the holding state, that is, to hold SEL_1 = 1 and SEL_2 = 0.

[0037] Figure 7 This is a schematic diagram illustrating the timing relationship of the MIPI circuit signals when the IO1 signal is configured as SDATA and the IO2 signal is configured as SCLK according to an embodiment of the present invention. Figure 7 As shown, SEL_2 = 0 at this time. Figure 6 The data selector MUX5 is configured to output the data of USID1<3:0> to the MIPI digital core circuit, where the USID is defined as USID1<3:0>.

[0038] When the IO1 signal is assumed to be the SCLK signal and the IO2 signal is the SDATA signal, refer back to Figure 4 At the initial moment, SDATA and SCLK are both 0, the outputs of the pulse expansion circuit 1 and the pulse expansion circuit 2 are 0, the SCLK_OUT signal is 0, the counter is not working, and the Done signal is 0. The D-latch 1 and the D-latch 2 outputs are 0, that is, SEL_1 = SEL_2 = 0. It is assumed that when SEL_1 = 0, the 0 input end data of the data selector 1 is transmitted to the output end; and when SEL_1 = 1, the 1 input end data of the data selector 1 is transmitted to the output end. It is assumed that when SEL_2 = 0, the 0 input end data of the data selector 2 is transmitted to the output end; and when SEL_2 = 1, the 1 input end data of the data selector 2 is transmitted to the output end.

[0039] Refer back to Figure 5 In the timing diagram of the data transmission, the port IO2 signal is the SDATA signal, and an SSC command of "010" is first sent. The pulse square wave signal is input into the pulse expansion circuit 2, the pulse square wave is expanded and then enters the D-latch 2, and a high level "1" control signal SEL_2 is output from the output end Q of the D-latch 2. The control signal SEL_2 controls the data selector 1, so that the 1 input end signal of the data selector 1, that is, the ground "0", is output to the pulse expansion circuit 1, which further enters the D-latch 1 and is output to SEL_1. Thus, SEL_1 = 0 and SEL2_ = 1 are temporarily obtained. The duration of the above two signals is determined by the expansion time of the pulse expansion circuit, and can be selected to be greater than the count time of the counter.

[0040] Refer back to Figure 6 According to the above description, when SEL_1 = 0 and SEL_2 = 1, the data of the port IO1 is temporarily transmitted to the buffer 1, and the data of the port IO2 is temporarily transmitted to the buffer 3. At this time, the port SCLK_OUT starts to output the clock signal SCLK.

[0041] Refer Figure 4 After the counter in the Figure 4 receives the SCLK_OUT signal, it starts to count down. When the count period time is reached, the Done signal outputs a control signal. At this time, the D-latch 1 and the D-latch 2 are configured to enter a holding state, that is, SEL_1 = 0 and SEL_2 = 1 are held.

[0042] Figure 8 is a schematic diagram showing the timing relationship of the MIPI circuit signals when the IO2 signal is configured as the SDATA and the IO1 signal is configured as the SCLK according to an embodiment of the present application. As shown in Figure 8 SEL_2 = 1, Figure 6The data selector MUX5 in the above-mentioned embodiment is configured to output the data of USID2<3:0> to the MIPI digital core circuit, and the USID in the MIPI circuit is defined as USID2<3:0>.

[0043] By the above-mentioned implementation steps, the application circuit can replace the positions of SDATA and SCLK, and automatically modify the USID of the chip according to the IO port replacement information. In the use process, only the positions of the SDATA and SCLK ports need to be exchanged, and then the application of two same chips on a mobile phone mainboard can be realized. This method can simplify the circuit design and production process, reduce the cost, and improve the production efficiency.

[0044] Although the present disclosure has been described with an example embodiment, various changes and modifications can be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.

[0045] None of the description in the present application should be understood to imply that any particular element, step, or function is essential to the patentable subject matter. The scope of the patent subject matter is defined only by the claims.

Claims

1. An IO interface replacement circuit, comprising: a first IO port and a second IO port, the first IO port configured to receive one of a serial data (SDATA) signal and a serial clock (SCLK) signal, and the second IO port configured to receive the other of the serial data (SDATA) signal and the serial clock (SCLK) signal; a first data selector and a second data selector, the first data selector configured to have the first IO port as one of the first data selector inputs and to select one of its inputs as the output of the first data selector according to a second select signal, the second data selector configured to have the second IO port as one of the second data selector inputs and to select one of its inputs as the output of the second data selector according to a first select signal; a first pulse expansion circuit and a second pulse expansion circuit, the first pulse expansion circuit configured to be connected to the output of the first data selector, and the second pulse expansion circuit configured to be connected to the output of the second data selector, the first pulse expansion circuit and the second pulse expansion circuit configured to expand the pulse duration of their input signals; a first latch and a second latch, the first latch configured to receive the output of the first pulse expansion circuit and to perform a latch according to a control signal to output the first select signal, the second latch configured to receive the output of the second pulse expansion circuit and to perform a latch according to a control signal to output the second select signal; and a counter configured to count a clock signal and to output the control signal according to the countdown time of the counter.

2. The IO interface replacement circuit of claim 1, the first data selector configured such that the first IO port is connected to the 0th input of the first data selector, and the 1st input of the first data selector is grounded; wherein the second data selector configured such that the second IO port is connected to the 0th input of the second data selector, and the 1st input of the second data selector is grounded, and wherein when the first select signal is equal to 0, the 0th input data of the first data selector is passed to the output of the first data selector, and when the first select signal is equal to 1, the 1st input data of the first data selector is passed to the output of the first data selector; when the second select signal is equal to 0, the 0th input data of the second data selector is passed to the output of the second data selector, and when the second select signal is equal to 1, the 1st input data of the second data selector is passed to the output of the second data selector. the first pulse expansion circuit and the second pulse expansion circuit configured to expand the pulse duration of their input signals to be greater than the countdown time of the counter.

3. The IO interface replacement circuit of claim 1, wherein, the first latch and the second latch configured to be D-latches, 4. The IO interface replacement circuit of claim 1, wherein, ​ wherein an output of the first pulse expansion circuit is connected to a D input of the first latch, and the control signal is connected to an E input of the first latch, to output a first selection signal, and wherein an output of the second pulse expansion circuit is connected to a D input of the second latch, and the control signal is connected to an E input of the second latch, to output a second selection signal.

5. The IO interface replacement circuit of claim 1, wherein, The serial data SDATA signal is configured to include a start of sequence condition SSC instruction to indicate a start of a data frame of the SDATA signal.

6. An IO interface circuit comprising the IO interface permutation circuit of any one of claims 1-5, comprising: an IO interface permutation circuit configured to receive signals from a first IO port and a second IO port, and to provide a first selection signal and a second selection signal; a third data selector and a fourth data selector, the third data selector configured to have the first IO port as an input of the third data selector and to output the input of the third data selector through a 0th output or a 1st output of the third data selector according to the first selection signal, and the fourth data selector configured to have the second IO port as an input of the fourth data selector and to output the input of the fourth data selector through a 0th output or a 1st output of the fourth data selector according to the second selection signal; and a first buffer configured to receive signals from the 0th outputs of the third data selector and the fourth data selector, and to output a buffered serial clock SCLK signal, and a second buffer configured to receive signals from the 1st outputs of the third data selector and the fourth data selector, and to output a buffered serial data SDATA signal. The first buffer is a first buffer configured to receive signals from the 0th outputs of the third data selector and the fourth data selector, and to output a buffered serial clock SCLK signal.

7. The IO interface circuit of claim 6, wherein, The second buffer comprises a second buffer and a third buffer, wherein 8. The IO interface circuit of claim 6, wherein, an input of the second buffer is connected to an output of the third buffer, and an output of the second buffer is connected to an input of the third buffer, and wherein signals output from the 1st outputs of the third data selector and the fourth data selector are provided to the input of the third buffer, and a buffered serial clock SCLK signal is output from the output of the third buffer.

9. The IO interface circuit of claim 6, further comprising a fifth data selector configured such that a first slave unique identifier USID is provided to a 0th input of the fifth data selector, a second slave unique identifier USID is provided to a 1st input of the fifth data selector, and one of the 0th input and the 1st input of the fifth data selector is selected as a slave unique identifier USID output according to the second selection signal. ​ 10. The IO interface circuit of claim 6, wherein, The IO interface replacement circuit is configured to receive a buffered serial clock (SCLK) signal from the first buffer.

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