Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, the method for manufacturing a semiconductor structure includes providing a substrate; forming a word line groove in the substrate; forming a gate oxide layer on the groove wall of the word line groove; forming a gate conductive layer in the word line groove, the gate conductive layer covers part of the gate oxide layer, and the top surface of the gate conductive layer forms a convex surface. In the semiconductor structure formed by the method for manufacturing a semiconductor structure provided by the present disclosure, the top surface of the gate conductive layer is a convex surface, which increases the cross-sectional area of ​​the gate conductive layer and reduces the resistance of the gate conductive layer; and the edge of the top surface of the gate conductive layer is the farthest from the top surface of the substrate, which reduces the gate-drain overlap area of ​​the transistor formed with the gate conductive layer as the gate, so as to avoid or reduce the gate induced drain leakage current, improve the reliability of the transistor and reduce the power of the transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) has the advantages of small size, high integration and low power consumption. As the integration of DRAM increases, the characteristic size of word line (WL) keeps decreasing, even to below 10nm. The reduction of word line width directly leads to a sharp increase of word line resistance. Meanwhile, the reduction of word line width will also lead to an increase of gate induced drain leakage (GIDL), which affects the reliability of word line transistors. Summary of the invention

[0003] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] A first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0006] providing a substrate;

[0007] forming a word line trench in the substrate;

[0008] forming a gate oxide layer on the wall of the word line trench;

[0009] A gate conductive layer is formed in the word line trench, the gate conductive layer covers a portion of the gate oxide layer, and a top surface of the gate conductive layer forms a convex surface.

[0010] According to some embodiments of the present disclosure, the word line trench includes a first trench and a second trench formed at the bottom of the first trench;

[0011] The thickness of the gate oxide layer formed on the sidewall of the first trench is greater than the thickness of the gate oxide layer formed on the groove wall of the second trench.

[0012] According to some embodiments of the present disclosure, inner wall surfaces of the gate oxide layer on the sidewall of the first trench and the gate oxide layer on the sidewall of the second trench are flush.

[0013] According to some embodiments of the present disclosure, forming a word line trench in the substrate includes:

[0014] removing a portion of the substrate to form a first trench;

[0015] A portion of the substrate is etched based on the first groove to form the second groove below the first groove, and the groove width of the first groove is greater than the groove width of the second groove.

[0016] According to some embodiments of the present disclosure, forming a gate oxide layer on the wall of the word line trench includes:

[0017] forming a first oxide layer, wherein the first oxide layer at least covers a sidewall of the first trench;

[0018] A second oxide layer is formed, the second oxide layer covers the groove wall of the second groove and the first oxide layer located on the side wall of the first groove, and the second oxide layer and the first oxide layer located on the side wall of the first groove jointly form the gate oxide layer.

[0019] According to some embodiments of the present disclosure, forming a gate conductive layer in the word line trench includes:

[0020] forming an initial gate conductive layer, wherein the initial gate conductive layer partially fills the word line trench, and a top surface of the initial gate conductive layer is lower than a top surface of the substrate;

[0021] Under predetermined conditions, the top surface of the initial gate conductive layer is etched to remove a portion of the initial gate conductive layer to form the convex surface, and the retained initial gate conductive layer forms the gate conductive layer.

[0022] According to some embodiments of the present disclosure, along the thickness direction of the substrate, the lowest point of the convex surface is higher than the second groove, and the highest point of the convex surface is lower than the top surface of the substrate.

[0023] According to some embodiments of the present disclosure, the manufacturing method includes:

[0024] When etching the initial gate conductive layer, an etching rate at an edge of a top surface of the initial gate conductive layer is greater than an etching rate at a center of the top surface of the initial gate conductive layer.

[0025] According to some embodiments of the present disclosure, the convex surface is a curved surface, and the etching rate gradually decreases from the edge of the curved surface to the center of the curved surface.

[0026] According to some embodiments of the present disclosure, the manufacturing method further includes:

[0027] A barrier layer is formed, wherein the barrier layer covers a portion of the gate oxide layer, and the barrier layer is located between the side wall of the gate conductive layer and the gate oxide layer, and between the bottom wall of the gate conductive layer and the gate oxide layer.

[0028] According to some embodiments of the present disclosure, the forming of the barrier layer further includes:

[0029] forming an initial barrier layer, wherein the initial barrier layer covers the gate oxide layer;

[0030] The initial barrier layer located above the lowest point of the convex surface is removed along the thickness direction of the substrate, and the retained initial barrier layer forms a barrier layer.

[0031] According to some embodiments of the present disclosure, the further comprising:

[0032] An isolation layer is formed, wherein the isolation layer covers a top surface of the gate conductive layer and fills an unfilled region of the word line trench, and a top surface of the isolation layer is flush with a top surface of the substrate.

[0033] A second aspect of the present disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0034] substrate;

[0035] A word line groove, wherein the word line groove is arranged in the substrate, and a gate oxide layer is arranged on a groove wall of the word line groove;

[0036] A gate conductive layer covers a portion of the gate oxide layer, and a top surface of the gate conductive layer is configured to be a convex surface.

[0037] According to some embodiments of the present disclosure, the word line trench includes a first trench and a second trench disposed at the bottom of the first trench;

[0038] The thickness of the gate oxide layer covering the sidewall of the first trench is greater than the thickness of the gate oxide layer covering the groove wall of the second trench.

[0039] According to some embodiments of the present disclosure, inner wall surfaces of the gate oxide layer on the sidewall of the first trench and the gate oxide layer on the sidewall of the second trench are flush.

[0040] According to some embodiments of the present disclosure, along the thickness direction of the substrate, the lowest point of the convex surface is higher than the second groove, and the highest point of the convex surface is lower than the top surface of the substrate.

[0041] According to some embodiments of the present disclosure, the semiconductor structure further includes:

[0042] A barrier layer, the barrier layer covers a portion of the gate oxide layer, the barrier layer is located between the side wall of the gate conductive layer and the gate oxide layer, and between the bottom wall of the gate conductive layer and the gate oxide layer;

[0043] An isolation layer covers a top surface of the gate conductive layer and fills an unfilled region of the word line trench, wherein a top surface of the isolation layer is flush with a top surface of the substrate.

[0044] In the manufacturing method of the semiconductor structure and the semiconductor structure provided by the embodiments of the present disclosure, the top surface of the gate conductive layer is convex, which increases the cross-sectional area of ​​the gate conductive layer and reduces the resistance of the gate conductive layer; and the edge of the top surface of the gate conductive layer is farthest from the top surface of the substrate, which reduces the gate-drain overlap area of ​​the transistor formed with the gate conductive layer as the gate, thereby avoiding or reducing gate-induced drain leakage current, improving the reliability of the transistor and reducing the power of the transistor.

[0045] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings incorporated into the specification and constituting a part of the specification illustrate embodiments of the present disclosure and are used together with the description to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, rather than all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 The present invention is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0048] Figure 2 FIG. 4 is a flow chart showing a process of forming a gate conductive layer according to an exemplary embodiment.

[0049] Figure 3 The present invention is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0050] Figure 4 is a schematic diagram of a substrate according to an exemplary embodiment.

[0051] Figure 5 is a schematic diagram showing the formation of a word line trench according to an exemplary embodiment.

[0052] Figure 6 FIG. 4 is a schematic diagram showing the formation of a gate oxide layer according to an exemplary embodiment.

[0053] Figure 7 is a schematic diagram showing the deposition of a conductive material according to an exemplary embodiment.

[0054] Figure 8 FIG. 4 is a schematic diagram showing the formation of an initial gate conductive layer according to an exemplary embodiment.

[0055] Fig. 9 FIG. 4 is a schematic diagram showing the formation of a gate conductive layer according to an exemplary embodiment.

[0056] Fig.10 is a schematic diagram showing the formation of an isolation layer according to an exemplary embodiment.

[0057] Fig.11 is a schematic diagram showing the formation of a first mask according to an exemplary embodiment.

[0058] Fig.12 is a schematic diagram showing the formation of a first trench according to an exemplary embodiment.

[0059] Fig.13 FIG. 4 is a schematic diagram showing forming a first oxide layer according to an exemplary embodiment.

[0060] Fig.14 is a schematic diagram showing the formation of a second trench according to an exemplary embodiment.

[0061] Fig.15 FIG. 4 is a schematic diagram showing forming a second oxide layer according to an exemplary embodiment.

[0062] Fig.16 FIG. 4 is a schematic diagram showing the formation of an initial barrier layer according to an exemplary embodiment.

[0063] Fig.17 FIG. 4 is a schematic diagram showing the formation of an initial gate conductive layer according to an exemplary embodiment.

[0064] Fig.18 is a schematic diagram showing a method for forming a gate conductive layer according to an exemplary embodiment

[0065] Fig.19 is a schematic diagram showing the formation of a barrier layer according to an exemplary embodiment.

[0066] Fig. 20 is a schematic diagram showing the formation of an isolation layer according to an exemplary embodiment.

[0067] Reference numerals:

[0068] 10. Substrate; 20. Word line trench; 21. First trench; 22. Second trench; 30. Gate oxide layer; 31. First oxide layer; 32. Second oxide layer; 40. Gate conductive layer; 41. Initial gate conductive layer; 42. Convex surface; 50. Blocking layer; 51. Initial blocking layer; 60. Isolation layer; 71. First mask; 72. Second mask. DETAILED DESCRIPTION

[0069] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other without conflict.

[0070] The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, wherein the top surface of a gate conductive layer is a convex surface, thereby increasing the cross-sectional area of ​​the gate conductive layer and reducing the resistance of the gate conductive layer; and the edge of the top surface of the gate conductive layer is farthest from the top surface of a substrate, thereby reducing the gate-drain overlap area of ​​a transistor formed with the gate conductive layer as a gate, thereby avoiding or reducing gate-induced drain leakage current, improving the reliability of the transistor and reducing the power of the transistor.

[0071] In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. Figure 1 As shown, Figure 1 A flowchart of a method for manufacturing a semiconductor structure provided according to an exemplary embodiment of the present disclosure is shown. Figure 4-Figure 10 The schematic diagram of each stage of the semiconductor structure manufacturing method is shown below. Figure 4-Figure 10 The method of manufacturing semiconductor structures is introduced.

[0072] The present embodiment does not limit the semiconductor structure. The semiconductor structure will be described below by taking a dynamic random access memory (DRAM) as an example, but the present embodiment is not limited thereto. The semiconductor structure in the present embodiment may also be other structures.

[0073] like Figure 1 As shown, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0074] Step S110: providing a substrate.

[0075] like Figure 4 As shown, the substrate 10 may be a semiconductor substrate, and the material of the semiconductor substrate may include one or more of silicon (Si), germanium (Ge), silicon germanium (GeSi), and silicon carbide (SiC); it may also be silicon on insulator (SOI), germanium on insulator (GOI); or, it may also include other materials, such as III-V group compounds such as gallium arsenide, etc. As required, some impurity ions may be doped in the semiconductor substrate, and the impurity ions may be n-type impurity ions or p-type impurity ions.

[0076] Step S120: forming word line trenches in the substrate.

[0077] like Figure 5 As shown, refer to Figure 4 , forming a word line trench 20 in the substrate 10, including: removing a portion of the substrate 10, forming the word line trench 20 in the substrate 10, wherein the word line trench 20 extends in a direction parallel to the top surface of the substrate 10. In some examples, referring to Figure 5 , along the thickness direction of the substrate 10, the word line groove 20 may include a plurality of connected parts, each of which may have the same or different sizes. For example, along the thickness direction of the substrate 10, the word line groove 20 may include two or more grooves of different sizes. In other examples, along the thickness direction of the substrate 10, the word line groove 20 may be a structure with a wide top and a narrow bottom, a structure with equal widths at the top and the bottom, or a structure with a narrow top and a wide bottom.

[0078] Step S130: forming a gate oxide layer on the wall of the word line trench.

[0079] like Figure 6 As shown, refer to Figure 5 A gate oxide layer 30 is formed by an atomic layer deposition process (ALD) or a chemical vapor deposition process (CVD), and the gate oxide layer 30 covers the sidewalls and bottom walls of the word line trench 20, wherein the material of the gate oxide layer 30 may include at least one of silicon oxide or silicon oxynitride.

[0080] In this embodiment, along the thickness direction of the substrate 10 , the thickness of the gate oxide layer 30 covering the sidewalls of the word line trench 20 can be thick at the top and thin at the bottom, equal thickness at the top and bottom, or thin at the top and thick at the bottom.

[0081] Step S140: forming a gate conductive layer in the word line trench, the gate conductive layer covers a portion of the gate oxide layer, and a top surface of the gate conductive layer forms a convex surface.

[0082] like Fig. 9 As shown, refer to Figure 6A gate conductive layer 40 is formed by deposition through any one of an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process (PVD), and the gate conductive layer 40 covers a portion of the gate oxide layer 30 and fills a portion of the word line trench 20. The material of the gate conductive layer 40 may include a doped semiconductor material, such as doped polysilicon; the material of the gate conductive layer 40 may also include at least one of a metal, a conductive metal oxide or other conductive materials, for example, the material of the gate conductive layer 40 may include one of metal titanium (Ti), metal tungsten (W), metal ruthenium (Ru) or a conductive metal oxide thereof.

[0083] According to the law of resistance, the resistance of a conductor is proportional to its length and resistivity, and inversely proportional to its cross-sectional area. The gate conductive layer is the main conductive structure of the word line. When the material, line width, and length of the gate conductive layer are the same, the larger the cross-sectional area of ​​the gate conductive layer, the smaller the resistance of the word line. In the cross section perpendicular to the extension direction of the word line, the top surface of the gate conductive layer is formed into a convex surface in this embodiment, which increases the cross-sectional area of ​​the gate conductive layer and reduces the resistance of the word line.

[0084] The top surface of the gate conductive layer formed in this embodiment is a convex surface. That is, the lowest point of the convex surface of the gate conductive layer is the edge of the top surface of the gate conductive layer. In other words, the edge of the top surface of the gate conductive layer is farthest from the top surface of the substrate. In the manufacturing process of the transistor (Ttransistor), the source region and the drain region are formed by ion implantation from the top surface of the substrate into the substrate. Therefore, for a transistor formed with the gate conductive layer formed in this embodiment as the gate, the gate-drain overlap region formed by the gate and the drain is smaller in range, so the possibility of the occurrence of gate induced drain leakage current (i.e., GIDL current) is lower. While increasing the cross-sectional area of ​​the gate conductive layer, this embodiment improves the reliability of the transistor and reduces the power of the transistor.

[0085] According to an exemplary embodiment, this embodiment is an explanation of the above embodiment. Figure 5 As shown, the word line trench 20 includes a first trench 21 and a second trench 22 formed at the bottom of the first trench 21. The width of the first trench 21 can be greater than the width of the second trench 22, the width of the first trench 21 and the width of the second trench 22 can also be equal, or the width of the first trench 21 can also be smaller than the width of the second trench 22.

[0086] like Figure 6 As shown, refer to Figure 5 The thickness of the gate oxide layer 30 formed on the sidewall of the first trench 21 is greater than the thickness of the gate oxide layer 30 formed on the sidewall of the second trench 22 .

[0087] like Fig. 9 As shown, along the thickness direction of the substrate 10, the lowest point of the convex surface 42 is higher than the second groove 22, and the highest point of the convex surface 42 is lower than the top surface of the substrate 10, that is, the top surface of the gate conductive layer 40 is located in the first groove 21, and the gate oxide layer 30 arranged between the top surface of the gate conductive layer 40 and the groove wall of the first groove 21 is thicker.

[0088] In the transistor formed with the gate conductive layer formed in this embodiment as the gate, the gate and the drain are separated by a thicker gate oxide layer, which reduces the flow of carriers between the gate and the drain of the transistor, thereby avoiding or reducing gate induced drain leakage current. The transistor formed with the gate conductive layer formed in this embodiment as the gate has better reliability and lower power consumption.

[0089] According to an exemplary embodiment, this embodiment is an explanation of the above embodiment. Figure 6 As shown, refer to Figure 5 The width of the first trench 21 is greater than the width of the second trench 22 , and the inner wall surface of the gate oxide layer 30 on the side wall of the first trench 21 is flush with the inner wall surface of the gate oxide layer 30 on the side wall of the second trench 22 .

[0090] In the present embodiment, the space used to form the gate conductive layer is of equal width at the top and bottom, that is, the present embodiment increases the thickness of the gate oxide layer covering the side wall of the first groove, but does not sacrifice the space for forming the gate conductive layer, thereby ensuring that the word line groove has enough space to form the gate conductive layer, thereby avoiding the problem of the top surface line width of the gate conductive layer being too narrow.

[0091] According to an exemplary embodiment, this embodiment is an explanation of step S140 in the above embodiment. Figure 2 As shown, forming a gate conductive layer in a word line trench includes the following steps:

[0092] Step S141: forming an initial gate conductive layer, wherein the initial gate conductive layer partially fills the word line trench, and the top surface of the initial gate conductive layer is lower than the top surface of the substrate.

[0093] Forming the initial gate conductive layer 41 includes: first, Figure 7 As shown, refer to Figure 6 , a conductive material is deposited by any deposition process of an atomic layer deposition process, a chemical vapor deposition process or a physical vapor deposition process (PVD), and the conductive material fills the unfilled portion of the word line trench 20 and covers the top surface of the substrate 10. Then, as Figure 8 As shown, refer to Figure 7The conductive material covering the top surface of the substrate 10 is removed by an etch-back process, and part of the conductive material in the word line groove 20 is etched back to remove the conductive material. The retained conductive material forms an initial gate conductive layer 41, which is a predetermined distance below the top surface of the substrate 10.

[0094] Step S142: under predetermined conditions, etching the top surface of the initial gate conductive layer to remove a portion of the initial gate conductive layer to form a convex surface, and the retained initial gate conductive layer forms a gate conductive layer.

[0095] In this embodiment, when etching the initial gate conductive layer 41 , the etching process is controlled so that the etching rates of different regions on the top surface of the initial gate conductive layer 41 are different, so that a convex surface 42 is formed on the top surface of the gate conductive layer 40 .

[0096] In some embodiments, when etching the initial gate conductive layer 41 , the etching process is controlled so that the etching rate at the edge of the top surface of the initial gate conductive layer 41 is greater than the etching rate at the center of the top surface of the initial gate conductive layer 41 .

[0097] In this embodiment, by controlling the etching parameters of the etching process so that the etching rate gradually decreases from the edge to the center of the initial gate conductive layer 41, the convex surface 42 formed on the top surface of the gate conductive layer 40 formed by etching is an arc surface, and the highest point of the arc surface is the center of the top surface of the gate conductive layer 40.

[0098] The manufacturing method of this embodiment has a lower process difficulty in making the top surface of the gate conductive layer a curved surface, and the process precision is easier to control. The qualified rate of the formed gate conductive layer is higher, which can improve the final yield rate of the semiconductor structure.

[0099] like Fig.10 As shown, refer to Fig. 9 This embodiment may further include the step of forming an isolation layer 60 , the isolation layer 60 covers the top surface of the gate conductive layer 40 and fills the unfilled area of ​​the word line trench 20 , and the top surface of the isolation layer 60 is flush with the top surface of the substrate 10 .

[0100] In some embodiments, the present embodiment may further include the following steps: in multiple cross sections perpendicular to the extension direction of the word line groove 20, a plurality of groups of symmetrically arranged source regions and drain regions may be formed on both sides of the word line groove 20 through an ion implantation process, each group of symmetrical source regions and drain regions having a gate conductive layer 40 located therebetween as a gate to form a transistor, that is, a plurality of transistors connected in series are formed along the extension direction of the word line groove 20.

[0101] In the semiconductor structure formed in this embodiment, the gate conductive layer 40, the barrier layer 50, the gate oxide layer 30 and the isolation layer 60 together form a word line. The word line is located in the word line groove 20 and extends in a direction parallel to the top surface of the substrate 10. The gate conductive layer 40 of each word line is connected to the gates of multiple transistors.

[0102] like Figure 3 As shown, a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

[0103] Step S210: providing a substrate.

[0104] like Fig.11 As shown, the substrate 10 provided in this embodiment is the same as the substrate 10 provided in step S110 of the above embodiment.

[0105] Step S220: removing a portion of the substrate to form a first trench.

[0106] like Fig.12 As shown, refer to Fig.11 Forming the first trench 21 includes: forming a first mask 71 on the top surface of the substrate 10 , etching the substrate 10 according to the first mask 71 , transferring the pattern of the first mask 71 to the substrate 10 , and forming the first trench 21 in the substrate 10 .

[0107] Exemplarily, the process of etching to form the first groove 21 is dry etching, using boron trichloride (BCl3) or chlorine (Cl2) as etching gas, applying a radio frequency bias of 100 watts to 700 watts to the etching gas, an etching pressure of 5mTorr to 20mTorr, and an etching temperature of 20°C to 100°C.

[0108] Reference Fig.12 The width of the first trench 21 formed by etching is 30 nm to 100 nm, and the depth of the first trench 21 is 50 nm to 100 nm.

[0109] In this embodiment, after the first groove 21 is formed, a disodium hydrogen phosphate solution is injected into the first groove 21 to clean the groove wall of the first groove 21 to remove etching byproducts and particles remaining in the etching process, so as to make the groove wall of the first groove 21 smooth, so as to subsequently form a first oxide layer 31 in the first groove 21.

[0110] Step S230: forming a first oxide layer, wherein the first oxide layer at least covers the sidewall of the first trench.

[0111] like Fig.13As shown, the first oxide layer 31 is formed by an atomic layer deposition process combined with an in-situ steam growth (ISSG) process. The first oxide layer 31 covers the sidewalls and bottom wall of the first trench 21. The material of the first oxide layer 31 may include at least one of silicon oxide or silicon oxynitride. The thickness of the first oxide layer 31 is 5nm to 15nm.

[0112] Step S240: etching the first oxide layer and a portion of the substrate based on the first trench to form a second trench below the first trench, wherein the width of the first trench is greater than the width of the second trench.

[0113] like Fig.14 As shown, refer to Fig.13 , etching a portion of the substrate 10 based on the first trench 21, including: forming a second mask 72, the second mask 72 covers the top surface of the substrate 10 and the top surface of the first oxide layer 31 located on the side wall of the first trench 21, etching and removing the first oxide layer 31 located on the bottom wall of the first trench 21 based on the second mask 72, exposing a portion of the substrate 10, and then continuing to etch and remove the portion of the substrate 10 exposed by the bottom wall of the first trench 21, forming a second trench 22 at the bottom of the first trench 21, so that the groove width of the first trench 21 is greater than the groove width of the second trench 22.

[0114] In this embodiment, the second trench 22 is formed by dry etching, and the etching gas and etching parameters are the same as those used to form the first trench 21. In this embodiment, the second trench 22 has a depth of 50 nm to 100 nm.

[0115] In this embodiment, after the second groove 22 is formed, a disodium hydrogen phosphate solution is injected into the second groove 22 to clean the groove wall of the second groove 22 to remove etching byproducts and particles remaining in the etching process, so as to make the groove wall of the second groove 22 smooth, so as to subsequently form a second oxide layer 32 in the second groove 22.

[0116] Step S250: forming a second oxide layer, where the second oxide layer covers the groove wall of the second groove and the first oxide layer located on the side wall of the first groove.

[0117] like Fig.15 As shown, refer to Fig.14 The second oxide layer 32 and the first oxide layer 31 located on the sidewall of the first trench 21 together form a gate oxide layer 30, that is, the gate oxide layer 30 located on the sidewall of the first trench 21 includes the first oxide layer 31 and the second oxide layer 32, while the gate oxide layer 30 covering the sidewall of the second trench 22 only includes the second oxide layer 32.

[0118] In this embodiment, the second oxide layer 32 can be formed by an atomic layer deposition process combined with an in-situ water vapor growth process. The material of the second oxide layer 32 may include at least one of silicon oxide or silicon oxynitride. The materials of the first oxide layer 31 and the second oxide layer 32 may be the same or different. In this embodiment, the materials of the first oxide layer 31 and the second oxide layer 32 are both silicon dioxide, and the thickness of the second oxide layer 32 is 5nm to 15nm.

[0119] Step S260: forming an initial barrier layer, wherein the initial barrier layer covers the gate oxide layer.

[0120] like Fig.16 As shown, refer to Fig.15 The barrier material may be deposited by an atomic layer deposition process or a chemical vapor deposition process, and the barrier material covers the gate oxide layer 30 to form an initial barrier layer 51 . The material of the initial barrier layer 51 may include at least one of silicon nitride or silicon oxynitride.

[0121] In an exemplary embodiment, forming the initial barrier layer 51 includes: introducing titanium tetrachloride (TiCl4) gas into a reaction chamber, and at least one of ammonia (NH3) or nitrogen (N2) into the reaction chamber, and forming the initial barrier layer 51 by chemical reaction growth on the surface of the gate oxide layer 30 through a chemical vapor deposition process, wherein the material of the initial barrier layer 51 includes titanium nitride, and the thickness of the initial barrier layer 51 is 2nm to 10nm. Then, the initial barrier layer 51 is subjected to thermal annealing to improve the barrier capability of titanium nitride.

[0122] Step S270: forming a gate conductive layer in the word line trench, wherein the gate conductive layer covers a portion of the gate oxide layer, and a top surface of the gate conductive layer forms a convex surface.

[0123] Similarly, in the present embodiment, the process of forming the gate conductive layer 40 is to first form the initial gate conductive layer 41, and then etch the top surface of the initial gate conductive layer 41 to form the gate conductive layer 40, and the top surface of the gate conductive layer 40 is a convex surface 42. The process of forming the initial gate conductive layer 41 in the present embodiment is the same as the process of forming step S141 in the above embodiment, and will not be repeated here.

[0124] In this embodiment, Fig.17 , Fig.18As shown, the material of the gate conductive layer 40 includes metal tungsten or a conductive metal oxide of tungsten. In this embodiment, when forming the convex surface 42, the semiconductor structure is placed in a reaction chamber, and high-density plasma dry etching is used to generate high-density, high-energy plasma and free radicals to perform high-rate, anisotropic etching on the tungsten material of the initial gate conductive layer 41. Exemplarily, the high-density plasma used in this embodiment can be an etching process such as inductively coupled plasma (ICP), transformer coupled plasma (TCP), etc.

[0125] For example, in this embodiment, transformer coupled plasma etching can be used to form the convex surface 42, and the etching parameters are: the chamber temperature is 20°C to 50°C; the etching gas pressure is 3mTorr to 50mTorr; the flat panel power used to increase the plasma energy is greater than 150 watts; the RF bias power is between 200 watts and 700 watts; the temperature of the electrode tray is less than 5°C; and the etching gas includes at least one of sulfur hexafluoride, chlorine or methane. Under these parameters, the etching rate of the edge of the top surface of the initial gate conductive layer 41 can be increased, while the etching rate of the center of the top surface of the initial gate conductive layer 41 is close to zero, that is, the center of the top surface of the initial gate conductive layer 41 is almost not etched. Refer to Fig.18 The curvature of the top surface of the gate conductive layer 40 formed in this embodiment is the largest, the cross-sectional area of ​​the gate conductive layer 40 is the smallest, and the resistance of the gate conductive layer 40 is the smallest. In other embodiments, some chlorine gas may be added to the etching gas, and the chlorine gas flow rate is 150ml / min to 300ml / min.

[0126] The top surface of the gate conductive layer 40 formed in this embodiment is an arc surface, the lowest point of the arc surface is the edge of the top surface of the gate conductive layer 40, the highest point of the arc surface is the center of the top surface of the gate conductive layer 40, the center of the arc surface is 5nm to 10nm away from the top surface of the substrate 10, and the height difference between the center of the arc surface and the edge of the arc surface is 5nm to 10nm.

[0127] Step S280: forming a barrier layer.

[0128] like Fig.19 As shown, refer to Fig.18 The barrier layer 50 is formed by removing the initial barrier layer 51 located above the lowest point of the convex surface 42 along the thickness direction of the substrate 10, and the retained initial barrier layer 51 forms the barrier layer 50. The barrier layer 50 covers a portion of the gate oxide layer 30, and the barrier layer 50 is located between the side wall of the gate conductive layer 40 and the gate oxide layer 30, and between the bottom wall of the gate conductive layer 40 and the gate oxide layer 30.

[0129] In this embodiment, an acid solution at 25°C to 50°C may be injected into the word line groove 20, for example, a mixed solution of dilute sulfuric acid or sulfuric acid and hydrogen peroxide, to dissolve the initial barrier layer 51 exposed in the word line groove 20 through the acid solution, and then the acid solution that has dissolved the initial barrier layer 51 is removed, and the retained initial barrier layer 51 forms a barrier layer 50, and the top surface of the barrier layer 50 is flush with the edge of the top surface of the gate conductive layer 40.

[0130] Step S290: forming an isolation layer, the isolation layer covers the top surface of the gate conductive layer and fills the unfilled area of ​​the word line trench, and the top surface of the isolation layer is flush with the top surface of the substrate.

[0131] In this embodiment, if Fig. 20 As shown, forming the isolation layer 60 includes: first, using silicon tetrachloride (SiCl4) gas and ammonia (NH3) as gas sources, depositing silicon nitride through a physical vapor deposition process (PVD), the silicon nitride filling the unfilled portion of the word line groove 20 and covering the top surface of the substrate 10, removing the silicon nitride covering the top surface of the substrate 10 through chemical mechanical polishing (CMP), retaining the silicon nitride located in the word line groove 20 to form the isolation layer 60, the height of the isolation layer 60 is 15nm ~ 30nm.

[0132] In the manufacturing method of the present embodiment, a first trench and a first oxide layer are first formed, and then a second trench and a second oxide layer are formed. An etching mask is formed using a pattern formed in the first trench by the first oxide layer, thereby reducing the difficulty of forming the second trench. In the present embodiment, the gate oxide layer located on the side wall of the first trench includes two layers, the first oxide layer and the second oxide layer, while the gate oxide layer located on the side wall of the second trench includes only a single layer of the second oxide layer, thereby ensuring that the thickness of the gate oxide layer located on the side wall of the first trench is greater, thereby avoiding the transistor from generating GIDL current.

[0133] like Fig.10 or Fig. 20 As shown, an exemplary embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure comprising: a substrate 10, a word line trench 20 disposed in the substrate 10, and a gate oxide layer 30 disposed on the trench wall of the word line trench 20. The semiconductor structure further comprises a gate conductive layer 40, the gate conductive layer 40 is disposed in the word line trench 20, the gate conductive layer 40 covers a portion of the gate oxide layer 30, and the top surface of the gate conductive layer 40 is configured as a convex surface 42.

[0134] like Fig.10 or Fig. 20 As shown, refer to Figure 5In some embodiments, the word line trench 20 includes a first trench 21 and a second trench 22 disposed at the bottom of the first trench 21 , and the thickness of the gate oxide layer 30 covering the sidewall of the first trench 21 is greater than the thickness of the gate oxide layer 30 covering the groove wall of the second trench 22 .

[0135] like Fig.10 or Fig. 20 As shown, refer to Figure 5 , Figure 6 , Fig.15 The inner wall surface of the gate oxide layer 30 on the side wall of the first trench 21 and the inner wall surface of the gate oxide layer 30 on the side wall of the second trench 22 are flush.

[0136] Along the thickness direction of the substrate 10 , the lowest point of the convex surface 42 is higher than the second groove 22 , and the highest point of the convex surface 42 is lower than the top surface of the substrate 10 .

[0137] like Fig. 20 As shown, in some embodiments, the semiconductor structure further includes a barrier layer 50 , which covers a portion of the gate oxide layer 30 , and is located between the sidewall of the gate conductive layer 40 and the gate oxide layer 30 , and between the bottom wall of the gate conductive layer 40 and the gate oxide layer 30 .

[0138] like Fig.10 or Fig. 20 As shown, in some embodiments, the semiconductor structure further includes an isolation layer 60 , which covers the top surface of the gate conductive layer 40 and fills the unfilled area of ​​the word line trench 20 , and the top surface of the isolation layer 60 is flush with the top surface of the substrate 10 .

[0139] In the semiconductor structure of this embodiment, the cross-sectional area of ​​the gate conductive layer is large, which reduces the resistance of the gate conductive layer and improves the electrical performance of the semiconductor device; and the edge of the top surface of the gate conductive layer is far away from the top surface of the substrate, which reduces the gate-drain overlap area of ​​the transistor using the gate conductive layer as the gate, and a thicker gate oxide layer is arranged between the top surface of the gate conductive layer and the substrate, thereby improving the reliability of the transistor and reducing the power of the transistor.

[0140] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0141] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0142] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0143] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0144] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0145] In one or more of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Many specific details of the present disclosure, such as the structure, materials, dimensions, processing technology and technology of the device are described below to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: providing a substrate; forming a word line trench in the substrate; forming a gate oxide layer on the wall of the word line trench; forming a gate conductive layer in the word line trench, wherein the gate conductive layer covers a portion of the gate oxide layer, and a top surface of the gate conductive layer forms a convex surface; The word line trench comprises a first trench and a second trench formed at the bottom of the first trench; The thickness of the gate oxide layer formed on the sidewall of the first trench is greater than the thickness of the gate oxide layer formed on the groove wall of the second trench; The inner wall surface of the gate oxide layer on the side wall of the first trench is flush with the inner wall surface of the gate oxide layer on the side wall of the second trench; The forming of a word line trench in the substrate comprises: removing a portion of the substrate to form a first trench; Etching a portion of the substrate based on the first groove to form the second groove below the first groove, wherein the groove width of the first groove is greater than the groove width of the second groove; The forming of a gate oxide layer on the wall of the word line trench comprises: forming a first oxide layer, wherein the first oxide layer at least covers a sidewall of the first trench; A second oxide layer is formed, the second oxide layer covers the groove wall of the second groove and the first oxide layer located on the side wall of the first groove, and the second oxide layer and the first oxide layer located on the side wall of the first groove jointly form the gate oxide layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The forming of a gate conductive layer in the word line trench comprises: forming an initial gate conductive layer, wherein the initial gate conductive layer partially fills the word line trench, and a top surface of the initial gate conductive layer is lower than a top surface of the substrate; Under predetermined conditions, the top surface of the initial gate conductive layer is etched to remove a portion of the initial gate conductive layer to form the convex surface, and the retained initial gate conductive layer forms the gate conductive layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Along the thickness direction of the substrate, the lowest point of the convex surface is higher than the second groove, and the highest point of the convex surface is lower than the top surface of the substrate.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The production method comprises: When etching the initial gate conductive layer, an etching rate at an edge of a top surface of the initial gate conductive layer is greater than an etching rate at a center of the top surface of the initial gate conductive layer.

5. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The convex surface is a curved surface, and the etching rate gradually decreases from the edge of the curved surface to the center of the curved surface.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The production method further comprises: A barrier layer is formed, wherein the barrier layer covers a portion of the gate oxide layer, and the barrier layer is located between the side wall of the gate conductive layer and the gate oxide layer, and between the bottom wall of the gate conductive layer and the gate oxide layer.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The forming of the barrier layer further comprises: forming an initial barrier layer, wherein the initial barrier layer covers the gate oxide layer; The initial barrier layer located above the lowest point of the convex surface is removed along the thickness direction of the substrate, and the retained initial barrier layer forms a barrier layer.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The production method further comprises: An isolation layer is formed, wherein the isolation layer covers a top surface of the gate conductive layer and fills an unfilled region of the word line trench, and a top surface of the isolation layer is flush with a top surface of the substrate.

9. A semiconductor structure, characterized in that: The semiconductor structure comprises: substrate; A word line groove, wherein the word line groove is arranged in the substrate, and a gate oxide layer is arranged on a groove wall of the word line groove; A gate conductive layer, the gate conductive layer covers a portion of the gate oxide layer, and the top surface of the gate conductive layer is configured to be a convex surface; The word line trench comprises a first trench and a second trench disposed at the bottom of the first trench; The thickness of the gate oxide layer covering the sidewall of the first trench is greater than the thickness of the gate oxide layer covering the groove wall of the second trench; The inner wall surfaces of the gate oxide layer on the sidewall of the first trench and the gate oxide layer on the sidewall of the second trench are flush.

10. The semiconductor structure according to claim 9, characterized in that: Along the thickness direction of the substrate, the lowest point of the convex surface is higher than the second groove, and the highest point of the convex surface is lower than the top surface of the substrate.

11. The semiconductor structure according to claim 9, characterized in that: The semiconductor structure further comprises: A barrier layer, the barrier layer covers a portion of the gate oxide layer, the barrier layer is located between the side wall of the gate conductive layer and the gate oxide layer, and between the bottom wall of the gate conductive layer and the gate oxide layer; An isolation layer covers a top surface of the gate conductive layer and fills an unfilled region of the word line trench, wherein a top surface of the isolation layer is flush with a top surface of the substrate.

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