Substrate end identification method and apparatus for semiconductor devices

Abstract

This disclosure provides a method and apparatus for identifying the substrate end of a semiconductor device. Based on the substrate effect of the semiconductor device, the method compares the threshold voltage and drain current obtained under two test conditions: one with a bias voltage applied and the other without. The method determines whether the semiconductor device exhibits a substrate effect, thereby identifying the substrate end that causes the semiconductor device to exhibit a substrate effect as the substrate end of the semiconductor device. This improves the accuracy of substrate end identification of semiconductor devices and ensures the effectiveness of subsequent electrical tests on the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and apparatus for identifying the substrate end of a semiconductor device. Background Technology

[0002] In the process of testing semiconductor devices, it is necessary to first determine the ports of the semiconductor device, and then conduct further electrical tests on the semiconductor device based on the determined ports.

[0003] In the prior art, since the drain or source terminals of a semiconductor device can form PN junctions with the substrate, once the drain or source terminals of the semiconductor device are determined, the substrate to be identified can be determined as the substrate of the semiconductor device by determining the PN junction characteristics between the drain or source terminals and the substrate to be identified.

[0004] However, using existing technology, when two semiconductor devices are placed adjacent to each other, the drain or source terminal of one semiconductor device can form a PN junction with the substrate terminal of the other semiconductor device. When determining the substrate terminal of a semiconductor device using the characteristics of the PN junction, the substrate terminal of one semiconductor device may be incorrectly identified as the substrate terminal of the other, thus affecting the results of subsequent electrical tests. Therefore, how to more accurately identify the substrate terminal of a semiconductor device is a technical problem that needs to be solved in this field. Summary of the Invention

[0005] This disclosure provides a method for identifying the substrate end of a semiconductor device, which solves the problem of inaccurate identification of the substrate end of a semiconductor device in the prior art.

[0006] This disclosure provides a method for identifying the substrate end of a semiconductor device, comprising: when a first voltage is input to the drain end of the semiconductor device, the source end is grounded, a second voltage is input to the gate end, and a third voltage is input to the substrate end to be identified, determining a first threshold voltage of the semiconductor device, and a first drain current at the drain end of the semiconductor device when the second voltage varies within a preset range; when the first voltage is input to the drain end of the semiconductor device, the source end is grounded, the second voltage is input to the gate end, and a fourth voltage is input to the substrate end to be identified, determining a second threshold voltage of the semiconductor device, and a second drain current at the drain end of the semiconductor device when the second voltage varies within the preset range; and determining the substrate end to be identified as the substrate end of the semiconductor device when the first threshold voltage, the second threshold voltage, the first drain current, and the second drain current satisfy a first preset condition.

[0007] In one embodiment of the first aspect of this disclosure, the first preset condition includes: the first threshold voltage is different from the second threshold voltage; when the second voltage varies within the linear region of the semiconductor device, the first drain current is different from the second drain current.

[0008] In one embodiment of the first aspect of this disclosure, the first preset condition includes: the difference between the first threshold voltage and the second threshold voltage is greater than a first threshold; when the second voltage changes within the linear region of the semiconductor device, the difference between the first drain current and the second drain current is greater than a second threshold.

[0009] In one embodiment of the first aspect of this disclosure, the third voltage is 0V; the absolute value of the fourth voltage is greater than the third voltage and less than 1V.

[0010] In one embodiment of the first aspect of this disclosure, the semiconductor device includes: a metal-oxide-semiconductor field-effect transistor (MOSFET) with a substrate of the first type.

[0011] In one embodiment of the first aspect of this disclosure, the method further includes: acquiring an image of a semiconductor layout, the semiconductor layout including the semiconductor device; determining, based on the image, a drain terminal, a source terminal, a gate terminal, and a plurality of substrate terminals to be identified of the semiconductor device; and sequentially determining whether each of the substrate terminals is a substrate terminal of the semiconductor device.

[0012] In one embodiment of the first aspect of this disclosure, it further includes: when a device in the region between two substrate ends in the image meets a second preset condition, determining that the region between the two substrate ends includes a second type of well.

[0013] In one embodiment of the first aspect of this disclosure, the second preset condition includes: the region between the two substrate ends includes at least one row of devices, and each row of devices includes at least two devices of the same type.

[0014] A second aspect of this disclosure provides a substrate identification device for a semiconductor device, comprising: an acquisition module, configured to determine a first threshold voltage of the semiconductor device and a first drain current at the drain terminal of the semiconductor device when a first voltage is input to the drain terminal, the source terminal is grounded, a second voltage is input to the gate terminal, and a third voltage is input to the substrate terminal to be identified; and to determine a second threshold voltage of the semiconductor device and a second drain current at the drain terminal of the semiconductor device when the second voltage varies within the preset range when the first voltage is input to the drain terminal, the source terminal is grounded, the second voltage is input to the gate terminal, and a fourth voltage is input to the substrate terminal to be identified; and an identification module, configured to determine whether the first threshold voltage, the second threshold voltage, the first drain current, and the second drain current satisfy preset conditions, and to determine the substrate terminal to be identified as the substrate terminal of the semiconductor device when the first threshold voltage, the second threshold voltage, the first drain current, and the second drain current satisfy the preset conditions.

[0015] In one embodiment of the second aspect of this disclosure, the first preset condition includes: the first threshold voltage is different from the second threshold voltage; when the second voltage varies within the linear region of the semiconductor device, the first drain current is different from the second drain current.

[0016] In one embodiment of the second aspect of this disclosure, the first preset condition includes: the difference between the first threshold voltage and the second threshold voltage is greater than a first threshold; when the second voltage changes within the linear region of the semiconductor device, the difference between the first drain current and the second drain current is greater than a second threshold.

[0017] In one embodiment of the second aspect of this disclosure, the third voltage is 0V; the absolute value of the fourth voltage is greater than the third voltage and less than 1V.

[0018] In one embodiment of the second aspect of this disclosure, the semiconductor device includes: a metal-oxide-semiconductor field-effect transistor (MOSFET) with a substrate of the first type.

[0019] In one embodiment of the second aspect of this disclosure, it further includes: an image acquisition module, configured to acquire an image of a semiconductor layout, the semiconductor layout including the semiconductor device; an image recognition module, configured to determine, based on the image, a drain terminal, a source terminal, a gate terminal, and a plurality of substrate terminals to be identified of the semiconductor device; the recognition module is further configured to sequentially determine whether each of the substrate terminals is a substrate terminal of the semiconductor device.

[0020] In one embodiment of the second aspect of this disclosure, the identification module is further configured to determine that the region between the two substrate ends includes a second type of well when the device in the region between the two substrate ends in the image meets a second preset condition.

[0021] In one embodiment of the second aspect of this disclosure, the second preset condition includes: the region between the two substrate ends includes at least one row of devices, each row of devices includes at least two devices, and the at least two devices are of the same type.

[0022] In summary, the semiconductor device substrate identification method and apparatus provided in this disclosure, based on the substrate effect of semiconductor devices, compares the obtained threshold voltage and drain current under two test conditions: applying a bias voltage to the substrate to be identified and not applying a bias voltage. It then determines whether the semiconductor device exhibits a substrate effect, thereby identifying the substrate to be identified that causes the substrate effect as the substrate of the semiconductor device. This eliminates potential misidentification that may occur when using PN junction characteristics to determine the substrate of a semiconductor device in related technologies, improves the accuracy of semiconductor device substrate identification, and ensures the effectiveness of subsequent electrical testing of the semiconductor device. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the circuit structure of a semiconductor device;

[0025] Figure 2 This is a schematic diagram of the structure of a semiconductor device;

[0026] Figure 3 This is a schematic diagram of the layout structure of a semiconductor device;

[0027] Figure 4 This is a schematic diagram of a method for identifying the substrate end of a semiconductor device in the related art;

[0028] Figure 5 This is a schematic diagram of another method for identifying the substrate end of a semiconductor device in the related technology;

[0029] Figure 6 The voltage and current variation curves when identifying the substrate end in related technologies;

[0030] Figure 7This is a voltage-current variation curve of a semiconductor device in related technologies;

[0031] Figure 8 This is a schematic flowchart of an embodiment of the semiconductor device substrate identification method provided in this disclosure;

[0032] Figure 9 This is a schematic diagram of the substrate end identification method for semiconductor devices provided in this disclosure;

[0033] Figure 10 A schematic diagram of voltage and current curve changes that can be obtained from the semiconductor device identification method provided in this disclosure;

[0034] Figure 11 Another schematic diagram of voltage and current curve changes that can be obtained from the semiconductor device identification method provided in this disclosure;

[0035] Figure 12 This is a schematic diagram illustrating the determination of a trap in a semiconductor device as provided in this disclosure;

[0036] Figure 13 This is a schematic diagram of the structure of a substrate end identification device for a semiconductor device provided in this disclosure. Detailed Implementation

[0037] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0038] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0039] Figure 1 This is a schematic diagram of the circuit structure of a semiconductor device, such as... Figure 1As shown, taking an N-type metal-oxide-semiconductor field-effect transistor (MOS transistor) as an example, the N-type MOS transistor includes a gate (G), a source (S), a drain (D), and a substrate (B).

[0040] Figure 2 This is a schematic diagram of the structure of a semiconductor device, such as... Figure 2 It shows Figure 1 A specific implementation of an N-type MOSFET in a circuit diagram. Figure 3 This is a schematic diagram of the layout structure of a semiconductor device, such as... Figure 3 It shows Figure 2 The layout structure of the N-type MOSFET from the A-direction view. Figure 2 and Figure 3 As can be seen from the diagram, on the layout of an N-type MOS transistor, the substrate (B), source (S), gate (G), and drain (D) are arranged in sequence.

[0041] When semiconductor device manufacturers, suppliers, etc. are concerned about, Figure 1-3 When analyzing and testing the semiconductor device shown, it is first necessary to determine the four ports of the semiconductor device, and then perform electrical tests on the semiconductor device by applying corresponding voltages to different ports.

[0042] In related technologies, it is possible to obtain information from, for example... Figure 3 The semiconductor device is photographed from the A-direction viewpoint, and the source terminal S, gate terminal G, and drain terminal D of the semiconductor device are determined by image recognition of the photographed image.

[0043] In related technologies, after determining the source terminal S and drain terminal D of a semiconductor device, the substrate terminal B of the semiconductor device can be further identified based on the PN junction characteristics between the source terminal S and the substrate terminal B, or between the drain terminal D and the substrate terminal B.

[0044] For example, when the semiconductor device is an N-type MOSFET, both the drain (D) and source (D) terminals are N-type doped, and the substrate (B) terminal is P-type doped. Therefore, a PN junction can be formed between the substrate (B) and drain (D), and also between the substrate (B) and source (D). Based on the forward conduction and negative cutoff characteristics of a PN junction, a varying DC voltage from -1V to 1V can be applied to one end of the PN junction while the other end is grounded. The voltage-current change curves of the PN junction can then be measured to determine if it exhibits the characteristics of a PN junction.

[0045] Figure 4 This is a schematic diagram of a method for identifying the substrate end of a semiconductor device in related technologies. A probe labeled ① is connected to the substrate end B1 to be identified, and a probe labeled ② is connected to the source end S of the semiconductor device, which has already been identified. Then, probe ① is grounded, and probe ② inputs a voltage to the source end S of the semiconductor device. Finally, the current on the source end S is detected, and the change in the detected current determines whether substrate end B1 is the substrate end of the semiconductor device. Alternatively, Figure 5 This is a schematic diagram of another method for identifying the substrate end of a semiconductor device in the related art. In this method, the probe labeled ① is connected to the substrate end B1 to be identified, and the probe labeled ② is connected to the drain end D of the semiconductor device that has been identified. Then, the probe ① is grounded, and the probe ② is used to input a voltage to the drain end D of the semiconductor device. Finally, the current on the drain end D is detected, and the substrate end B1 is determined to be the substrate end of the semiconductor device based on the change in the detected current.

[0046] Figure 6 To identify the voltage and current change curves at the substrate end in related technologies, in order to Figure 4 Taking the substrate end identification method shown as an example, such as Figure 6 The horizontal axis of the graph shows the voltage Vs input by probe ② to the source terminal S of the semiconductor device, and the vertical axis shows the current generated at the source terminal S of the semiconductor device under different input voltages Vs. It can be seen that as the voltage Vs gradually decreases from 0V, the PN junction between the substrate B1 and the source terminal S opens at voltage Vs-1, and is fully conducting at voltage Vs-2, with the current reaching the 1uA limit current. Therefore, according to... Figure 6 The voltage and current variation curves of the source terminal S of the semiconductor device shown indicate that the substrate terminal B1 to be tested is the substrate terminal of the semiconductor device.

[0047] Understandably, if probe ① is connected to the substrate terminal B2 to be identified, and probe ② is connected to the drain terminal D of the already identified semiconductor device, then following the same testing method described above will not yield the desired result. Figure 6 The voltage and current variation curves shown indicate that the substrate B2 being tested is not the substrate of the semiconductor device.

[0048] However, the above-mentioned Figure 4-6The method of identifying the substrate terminal of a semiconductor device by using PN junction characteristics can lead to inaccurate identification in some cases. For example, when two semiconductor devices are placed adjacent to each other, the drain terminal (D) or source terminal (S) of one semiconductor device can form a PN junction with the substrate terminal (B) of the other semiconductor device. When determining the substrate terminal (B) of a semiconductor device by using PN junction characteristics, the substrate terminal (B) of one semiconductor device may be incorrectly identified as the substrate terminal of the other semiconductor device, thus affecting the results of subsequent electrical tests on the semiconductor devices.

[0049] For example, Figure 7 This is a voltage and current variation curve of a semiconductor device in related technologies, such as... Figure 7 This diagram illustrates that when two semiconductor devices are placed adjacent to each other, probe ① is connected to the substrate terminal B of one semiconductor device, and probe ② is connected to the source terminal S of the other semiconductor device. A voltage Vs is input to the source terminal S of one semiconductor device through probe ②. When the voltage is Vs-3, the PN junction between the source terminal S and the substrate terminal B opens, allowing the source terminal S of the other semiconductor device to also generate current under the influence of the input voltage Vs, conforming to... Figure 6 The PN junction characteristics shown lead to the incorrect identification of the substrate B of one semiconductor device as the substrate of another semiconductor device.

[0050] Therefore, this disclosure provides a method based on the substrate effect principle of semiconductor devices, which can more accurately identify the substrate end of semiconductor devices. The technical solution of this disclosure will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0051] Figure 8 This is a schematic flowchart of an embodiment of the semiconductor device substrate identification method provided in this disclosure, as shown below. Figure 8 The identification method shown can be used to identify, for example, Figure 1-3 The substrate B of the N-type MOS transistor and other semiconductor devices shown in the figure can be executed by any electronic device with relevant data processing and computing capabilities, such as a computer, server, or workstation. Figure 8 The substrate identification method for the semiconductor device shown specifically includes:

[0052] S101: Input a first voltage to the drain terminal D of the semiconductor device, ground the source terminal S, input a second voltage to the gate terminal G, and input a third voltage to the substrate terminal to be identified. When the second voltage changes within a preset range, determine the first threshold voltage Vt1 of the semiconductor device and the first drain current Id1 of the drain terminal D. Thus, the first curve L1 reflecting the voltage-current change of the first drain current Id1 when the second voltage changes can be obtained.

[0053] Figure 9 This is a schematic diagram of the substrate end identification method for semiconductor devices provided in this disclosure, as shown below. Figure 9 As shown, in order to obtain the first threshold voltage Vt1 and the first drain current Id1 of the semiconductor device, after determining the source terminal S, drain terminal D, and gate terminal G of the semiconductor device, the source terminal S can be grounded through probe ②, a second voltage can be input to the gate terminal G through probe ③, and a third voltage can be input to the drain terminal D through probe ④. At the same time, the third voltage is input to the substrate terminal B1 to be identified through probe ①.

[0054] In some embodiments, perform as follows Figure 8 Prior to the identification method shown, the source terminal S, gate terminal G, and drain terminal D of the semiconductor device can be determined by taking a picture of the semiconductor device and performing image recognition on the image. Multiple substrate terminals to be identified in the image can also be determined through image recognition, such as... Figure 9 The example shown includes two substrate terminals, B1 and B2, to be identified. Alternatively, multiple substrate terminals to be identified can be determined by relevant test personnel through other means. The electronic device performing the identification method then uses probe ① to perform subsequent identification processing on the substrate terminal indicated by the test personnel.

[0055] S102: Input a first voltage to the drain terminal D of the semiconductor device, ground the source terminal S, input a second voltage to the gate terminal G, and input a fourth voltage to the substrate terminal to be identified. When the second voltage changes within a preset range, determine the second threshold voltage Vt2 of the semiconductor device and the second drain current Id2 of the drain terminal D. Thus, the second curve L2 reflecting the voltage-current change when the second voltage changes can be obtained.

[0056] Specifically, in S102, in order to obtain the second threshold voltage Vt2 and the second drain current Id2, it can also be done according to... Figure 9 The probes ①-④ are set up as shown, and a first voltage is input to the drain terminal D, the source terminal S is grounded, and a second voltage is input to the gate terminal, respectively. The difference from S101 is that in S102, a fourth voltage is input to the substrate terminal B1 to be identified, and the third voltage is different from the fourth voltage.

[0057] In some embodiments, the first voltage may be a fixed voltage of 1.1V, the second voltage may be a varying voltage of 0-1.2V, and the third voltage may be 0V obtained from grounding.

[0058] S103: Compare the first threshold voltage Vt1 obtained in S101 with the second threshold voltage Vt2 obtained in S102, and determine whether the substrate terminal B1 to be identified is the substrate terminal of the semiconductor device based on the first drain current Id1 obtained in S101 and the second drain current Id2 obtained in S102.

[0059] This disclosure utilizes the principle of the substrate effect present in semiconductor devices such as MOSFETs to determine whether the substrate terminal to be identified is the corresponding substrate terminal of the semiconductor device. The substrate effect refers to the phenomenon that when a bias voltage Vbs is applied to the substrate terminal B of a MOSFET, the quasi-electronic Fermi level (Efn) of substrate terminal B shifts from the quasi-electronic Fermi level (Efp) by the magnitude of Vbs. This causes a change in the threshold voltage (VT) of the MOSFET, resulting in changes in the voltage and current curves between the drain current Id and the gate voltage.

[0060] In some embodiments, to determine whether a substrate effect exists in a semiconductor device, in S101 and S102, the voltage value input to the substrate terminal B1 to be identified can be changed to create two test cases: one with bias voltage Vbs and the other without. For example, in S101, a third voltage of 0V can be input to the substrate terminal B1 to be identified, or the substrate terminal B1 can be grounded to set the voltage of the substrate terminal B1 to 0V, forming a test case where no bias voltage Vbs is applied to the substrate terminal B1. In S102, a fourth voltage of -0.7V can be input to the substrate terminal B1 to be identified, forming a test case where a bias voltage Vbs is applied to the substrate terminal B1. The voltage value of the fourth voltage can also be set according to the characteristics of the MOSFET; for example, its absolute value can be other values ​​greater than the third voltage but less than 1V.

[0061] Figure 10 The semiconductor device identification method provided in this disclosure can obtain a schematic diagram of voltage and current curve changes, such as... Figure 10As shown, when the semiconductor device is an N-type MOS transistor, if the substrate B1 to be tested is the substrate corresponding to the semiconductor device, it can be seen that in the test case S101, when no bias voltage is applied to substrate B1, and a first voltage is input to the drain terminal D of the semiconductor device, the source terminal S is grounded, and a second voltage is input to the gate terminal G, the first curve L1 obtained is not the same as the second curve L2 obtained in the test case S102, when a bias voltage is applied to substrate B1, and a first voltage is input to the drain terminal D of the semiconductor device, the source terminal S is grounded, and a second voltage is input to the gate terminal G. This difference is particularly evident in the linear region where the gate voltage of the semiconductor device is from Vg-1 to Vg-2. Figure 10 When all other conditions are the same as seen in the curve, the first drain current Id1 and the second drain current Id2 are not the same. This difference is caused by the substrate effect of the semiconductor device. Therefore, it can be determined that the substrate end B1 being tested is the substrate end corresponding to the semiconductor device.

[0062] Figure 11 Another schematic diagram of voltage and current curve changes that can be obtained from the semiconductor device identification method provided in this disclosure, such as... Figure 11 As shown, if the substrate B2 to be tested is not the substrate corresponding to the semiconductor device, in the test case of S101, when no bias voltage is applied to substrate B2, and a first voltage is applied to the drain terminal D of the semiconductor device, the source terminal S is grounded, and a second voltage is applied to the gate terminal G, the resulting first curve L1 is the same as the resulting second curve L2 in the test case of S102, when a bias voltage is applied to substrate B2, and a first voltage is applied to the drain terminal D of the semiconductor device, the source terminal S is grounded, and a second voltage is applied to the gate terminal G. The curves change similarly, especially within the linear region of the semiconductor device's gate voltage from Vg-1 to Vg-2. Figure 11 When all other conditions observed in the curves are the same, the first drain current Id1 and the second drain current Id2 are exactly the same, and the first curve L1 and the second curve L2 overlap. This means that there is no substrate effect between the semiconductor device and the currently detected substrate B2, so the two curves will not show the same pattern. Figure 10 The difference shown indicates that the substrate B2 being tested is not the substrate corresponding to the semiconductor device.

[0063] Therefore, it can be done Figure 10 and Figure 11 The method of comparing the first curve L1 of the first drain current Id1 and the second curve L2 of the second drain current Id2 obtained in the previous step determines whether the substrate terminal to be identified is the substrate terminal of the semiconductor device.

[0064] Meanwhile, due to the substrate effect of semiconductor devices, the threshold voltage of semiconductor devices changes differently under test conditions with a bias voltage Vbs applied to the substrate and without a bias voltage Vbs applied to the substrate.

[0065] In the test case S101, if the substrate B1 being tested is the substrate corresponding to the semiconductor device, the first threshold voltage Vt1 obtained when no bias voltage is applied to the substrate B1, the first voltage is applied to the drain terminal D of the semiconductor device, the source terminal S is grounded, and the second voltage is applied to the gate terminal G. This is different from the second threshold voltage Vt2 obtained in the test case S102, when a bias voltage is applied to the substrate B1, the first voltage is applied to the drain terminal D of the semiconductor device, the source terminal S is grounded, and the second voltage is applied to the gate terminal G. Vt1 ≠ Vt2. The difference between the two threshold voltages is caused by the substrate effect of the semiconductor device. Therefore, it can be determined that the substrate B1 being tested is the substrate corresponding to the semiconductor device.

[0066] If the substrate B2 being tested is not the substrate corresponding to the semiconductor device, under the test conditions of S101 (when no bias voltage is applied to substrate B2), the first threshold voltage Vt1 obtained when a first voltage is applied to the drain terminal D of the semiconductor device, the source terminal S is grounded, and the gate terminal G is input with a second voltage is compared with the second threshold voltage Vt2 obtained under the test conditions of S102 (when a bias voltage is applied to substrate B2, and a first voltage is applied to the drain terminal D of the semiconductor device, the source terminal S is grounded, and the gate terminal G is input with a second voltage), Vt1 = Vt2. This indicates that there is no substrate effect between the semiconductor device and the currently tested substrate B2, therefore it can be determined that the currently tested substrate B2 is not the substrate corresponding to the semiconductor device.

[0067] Therefore, it is also possible to determine whether the substrate to be identified is the substrate of a semiconductor device by comparing the first threshold voltage Vt1 and the second threshold voltage Vt2.

[0068] In summary, in S103, the conditions for simultaneously satisfying the first threshold voltage Vt1 and the second threshold voltage Vt2, as well as... Figure 10 The first drain current Id1 and the second drain current Id2 are different, which is denoted as the first preset condition. When the first threshold voltage Vt1, the second threshold voltage Vt2, the first drain current Id1, and the second drain current Id2 obtained in S101-S102 satisfy the above-mentioned first preset condition, it can be determined that the semiconductor device has a substrate effect, and thus the substrate end to be identified under test is determined to be the substrate end of the semiconductor device; otherwise, the substrate end to be identified under test is not the substrate end of the semiconductor device.

[0069] Alternatively, in some embodiments, due to errors in the specific implementation process, a first threshold and a second threshold can be defined, such that the first preset condition includes: the difference between the first threshold voltage Vt1 and the second threshold voltage Vt2 is greater than the first threshold, that is, only after satisfying the first threshold can it be determined that the two are different; and the difference between the first drain current Id1 and the second drain current Id2 is greater than the second threshold in the linear region of the semiconductor device, that is, only after satisfying the second threshold can it be determined that the two are different. Thus, after satisfying the above first preset condition, it can be determined that the semiconductor device has a substrate effect, so the substrate end to be identified in the current test is the substrate end of the semiconductor device.

[0070] Furthermore, the substrate identification method for semiconductor devices provided in this embodiment is based on the substrate effect of semiconductor devices, and is similar to... Figure 6-7 Compared to related technologies that determine the substrate end of a semiconductor device based on the PN junction principle illustrated, even in related technologies, there are scenarios where adjacent semiconductor devices may form a PN junction, leading to misidentification. However, in such scenarios, for adjacent semiconductors, after applying a bias voltage to the substrate end of one semiconductor device, the other semiconductor device will not experience substrate effects because it does not have a bias voltage.

[0071] In summary, the semiconductor device substrate identification method provided in this embodiment, based on the substrate effect of semiconductor devices, compares the obtained threshold voltage and drain current under two test conditions: one with a bias voltage applied and the other without. It then determines whether the semiconductor device exhibits a substrate effect, thereby identifying the substrate terminal that causes the substrate effect as the substrate terminal of the semiconductor device. This eliminates potential misidentification that may occur when using PN junction characteristics to determine the substrate terminal of a semiconductor device in related technologies, improving the accuracy of semiconductor device substrate identification and ensuring the effectiveness of subsequent electrical testing of the semiconductor device.

[0072] This disclosure does not limit the testing of the semiconductor device after the substrate end of the semiconductor device is determined. For example, the semiconductor device can be subjected to failure analysis (FA). When the substrate end of the semiconductor device can be identified more accurately, the completion rate of the FA analysis of the semiconductor device is higher.

[0073] One embodiment of this disclosure also provides a method for determining the well of a semiconductor device based on a determined substrate end, for example... Figure 12 This is a schematic diagram of a well for a semiconductor device provided in this disclosure, wherein, for example... Figure 12The semiconductor layout shown includes multiple substrate terminals. When, according to the aforementioned method of this disclosure, an image of the semiconductor layout is acquired, the gate terminal, source terminal, and multiple substrate terminals to be identified are determined, and it is sequentially determined whether the multiple substrate terminals to be identified are substrate terminals of the semiconductor device, and finally, substrate terminals B1-1 and B1-2 are determined to be substrate terminals of the semiconductor device, it can be further determined whether the device included in the region between the two substrate terminals meets a second preset condition. Specifically, when the substrate of the semiconductor device is of the first type, if the second preset condition is met, it can be determined that a second type well is included between the two substrate terminals B1-1 and B1-2. For example, the first type is N-type and the second type is P-type; or, the first type is P-type and the second type is N-type, etc.

[0074] In some embodiments, the second preset condition includes: at least one row of devices is included in the region between the two substrate ends, and each row includes at least two devices of the same type. For example, in Figure 12 In the example shown, between substrate ends B1-1 and B1-2, there are three rows of devices, denoted as D1, D2, and D3, with each row containing at least two devices of the same type. Devices in different rows can be different. Since multiple semiconductor devices can share one or two substrate ends, when two substrate ends include one or more rows of devices of the same type, and testing reveals that these devices share the same substrate end, it indicates that the devices between the two substrate ends are in the same well. For example, when the devices between two substrate ends include N-type MOS transistors, the presence of a Pwell well between the two substrate ends can be determined based on the shared devices.

[0075] In summary, this embodiment can determine the position and type of the well between substrate ends by whether there are devices of the same type between the substrate ends in the semiconductor layout. This allows for more accurate detection of parameters such as the resistance of the well, thereby improving the efficiency of testing semiconductor devices in the semiconductor layout.

[0076] One embodiment of this disclosure also provides a method for determining the region where a semiconductor device is located based on the number of substrate terminals of the semiconductor device, thereby determining the function of the semiconductor device and whether the layout of the semiconductor device conforms to design rules, etc. Specifically, after determining the substrate terminals of the semiconductor device according to the aforementioned method of this disclosure, when the number of ligands in the semiconductor device is small and they share a row of substrate terminals, for example, when the number is 2-8, the current semiconductor device is determined to be in the sense amplifier region. When the number of ligands in the semiconductor device is large and they share three rows of substrate terminals, for example, when the number is greater than 10 or in the tens, the current semiconductor device is determined to be in the electrostatic discharge (ESD) region. Here, ligands can also be referred to as peripheral contacts (PCs), etc., and are the contact metal between the peripheral gate (PG) layer and the MO metal layer.

[0077] In the foregoing embodiments, a method for identifying the substrate end of a semiconductor device provided by this disclosure has been described. To implement the functions of the methods provided by this disclosure, the electronic device serving as the execution entity may include hardware structures and / or software modules, implementing the aforementioned functions in the form of hardware structures, software modules, or a combination of hardware structures and software modules. Whether a particular function is executed in the form of hardware structures, software modules, or a combination of hardware structures and software modules depends on the specific application and design constraints of the technical solution.

[0078] For example, Figure 13This is a schematic diagram of a substrate identification device for a semiconductor device provided in this disclosure. The device 100 includes an acquisition module 1001 and an identification module 1002. The acquisition module 1001 is used to determine a first threshold voltage of the semiconductor device and a first drain current at the drain terminal when the second voltage varies within a preset range, when a first voltage is input to the drain terminal of the semiconductor device, the source terminal is grounded, a second voltage is input to the gate terminal, and a third voltage is input to the substrate terminal to be identified; and to determine a second threshold voltage of the semiconductor device and a second drain current at the drain terminal when the second voltage varies within a preset range, when the first voltage is input to the drain terminal, the source terminal is grounded, the gate terminal is input, and a fourth voltage is input to the substrate terminal to be identified. The identification module 1002 is used to determine whether the first threshold voltage, the second threshold voltage, the first drain current, and the second drain current meet preset conditions. When the first threshold voltage, the second threshold voltage, the first drain current, and the second drain current meet the preset conditions, the substrate terminal to be identified is determined to be the substrate terminal of the semiconductor device.

[0079] In some embodiments, the device further includes: an image acquisition module for acquiring an image of a semiconductor layout, the semiconductor layout including a semiconductor device; an image recognition module for determining, based on the image, the drain terminal, source terminal, gate terminal and a plurality of substrate terminals to be identified of the semiconductor device; the recognition module is further configured to sequentially determine whether each substrate terminal is a substrate terminal of the semiconductor device.

[0080] The specific implementation and principle of the semiconductor device substrate end identification device in various embodiments of this disclosure can be referred to the semiconductor device substrate end identification method provided in the foregoing embodiments of this disclosure. The specific implementation and principle are the same and will not be repeated here.

[0081] It should be noted that the division of the various modules in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. These modules can be implemented entirely in software via processing element calls; they can be fully implemented in hardware; or some modules can be implemented by processing element calls to software, while others are implemented in hardware. They can be separate processing elements, integrated into a chip within the device, or stored as program code in the device's memory, invoked and executed by a processing element. The implementation of other modules is similar. Furthermore, these modules can be fully or partially integrated together, or implemented independently. The processing element described here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules can be completed through integrated logic circuits in the hardware of the processor element or through software instructions.

[0082] For example, these modules can be one or more integrated circuits configured to implement the above methods, such as one or more application-specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs). As another example, when a module is implemented using processing element scheduler code, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor capable of calling program code. Furthermore, these modules can be integrated together to implement a system-on-a-chip (SOC).

[0083] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this disclosure are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0084] This application also provides an electronic device, including: a processor and a memory; wherein the memory stores a computer program, and when the processor executes the computer program, the processor can be used to perform a substrate identification method for a semiconductor device as described in any of the foregoing embodiments of this disclosure.

[0085] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed, can be used to perform a substrate identification method for a semiconductor device as described in any of the foregoing embodiments of this disclosure.

[0086] This disclosure also provides a chip for executing instructions, the chip being used to perform a substrate identification method for any of the semiconductor devices described above.

[0087] This disclosure also provides a program product including a computer program stored in a storage medium. At least one processor can read the computer program from the storage medium. When the at least one processor executes the computer program, it can implement a substrate end identification method for a semiconductor device as described above in this disclosure.

[0088] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for identifying the substrate end of a semiconductor device, characterized in that, include: When a first voltage is applied to the drain terminal of the semiconductor device, the source terminal is grounded, a second voltage is applied to the gate terminal, and a third voltage is applied to the substrate terminal to be identified, a first threshold voltage of the semiconductor device is determined, and a first drain current at the drain terminal of the semiconductor device is determined when the second voltage varies within a preset range. When the first voltage is applied to the drain terminal of the semiconductor device, the source terminal is grounded, the second voltage is applied to the gate terminal, and the fourth voltage is applied to the substrate terminal to be identified, the second threshold voltage of the semiconductor device is determined, and the second drain current at the drain terminal of the semiconductor device is determined when the second voltage varies within the preset range. When the first threshold voltage, the second threshold voltage, the first drain current, and the second drain current meet the first preset condition, the substrate terminal to be identified is determined to be the substrate terminal of the semiconductor device.

2. The method according to claim 1, characterized in that, The first preset conditions include: The first threshold voltage is different from the second threshold voltage; When the second voltage varies within the linear region of the semiconductor device, the first drain current is different from the second drain current.

3. The method according to claim 1, characterized in that, The first preset conditions include: The difference between the first threshold voltage and the second threshold voltage is greater than the first threshold value; When the second voltage varies within the linear region of the semiconductor device, the difference between the first drain current and the second drain current is greater than the second threshold.

4. The method according to claim 2 or 3, characterized in that, The third voltage is 0V; The absolute value of the fourth voltage is greater than the third voltage but less than 1V.

5. The method according to claim 1, characterized in that, The semiconductor device includes a MOSFET with a substrate of type 1.

6. The method according to claim 1, characterized in that, Also includes: Acquire an image of a semiconductor layout, wherein the semiconductor layout includes the semiconductor device; Based on the image, the drain terminal, source terminal, gate terminal, and multiple substrate terminals to be identified of the semiconductor device are determined; In sequence, determine whether each of the substrate ends is a substrate end of the semiconductor device.

7. The method according to claim 6, characterized in that, Also includes: When the device in the region between the two substrate ends in the image meets the second preset condition, it is determined that the region between the two substrate ends includes a second type of well.

8. The method according to claim 7, characterized in that, The second preset condition includes: The region between the two substrate ends includes at least one row of devices, and each row of devices includes at least two devices of the same type.

9. A substrate end identification device for a semiconductor device, characterized in that, include: The acquisition module is configured to: determine a first threshold voltage of the semiconductor device and a first drain current at the drain terminal of the semiconductor device when a first voltage is input to the drain terminal, the source terminal is grounded, the gate terminal is input to the gate terminal, and a third voltage is input to the substrate terminal to be identified; and determine a second threshold voltage of the semiconductor device and a second drain current at the drain terminal of the semiconductor device when the second voltage varies within a preset range when the first voltage is input to the drain terminal, the source terminal is grounded, the gate terminal is input to the gate terminal, and a fourth voltage is input to the substrate terminal to be identified. The identification module is used to determine whether the first threshold voltage, the second threshold voltage, the first drain current and the second drain current meet the first preset condition. When the first threshold voltage, the second threshold voltage, the first drain current and the second drain current meet the first preset condition, the substrate terminal to be identified is determined to be the substrate terminal of the semiconductor device.

10. The apparatus according to claim 9, characterized in that, The first preset conditions include: The first threshold voltage is different from the second threshold voltage; When the second voltage varies within the linear region of the semiconductor device, the first drain current is different from the second drain current.

11. The apparatus according to claim 9, characterized in that, The first preset conditions include: The difference between the first threshold voltage and the second threshold voltage is greater than the first threshold value; When the second voltage varies within the linear region of the semiconductor device, the difference between the first drain current and the second drain current is greater than the second threshold.

12. The apparatus according to claim 10 or 11, characterized in that, The third voltage is 0V; The absolute value of the fourth voltage is greater than the third voltage but less than 1V.

13. The apparatus according to claim 9, characterized in that, The semiconductor device includes a MOSFET with a substrate of type 1.

14. The apparatus according to claim 9, characterized in that, Also includes: Image acquisition module, used to acquire images of a semiconductor layout, the semiconductor layout including the semiconductor device; An image recognition module is used to determine the drain terminal, source terminal, gate terminal, and multiple substrate terminals to be identified of the semiconductor device based on the image. The identification module is also used to sequentially determine whether each of the substrate ends is a substrate end of the semiconductor device.

15. The apparatus according to claim 14, characterized in that, The identification module is also used for, When the device in the region between the two substrate ends in the image meets the second preset condition, it is determined that the region between the two substrate ends includes a second type of well.

16. The apparatus according to claim 15, characterized in that, The second preset condition includes: The region between the two substrate ends includes at least one row of devices, each row of devices includes at least two devices, and the at least two devices are of the same type.

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