Chip testing method and system

Abstract

The application relates to a chip testing method and system, which comprises the following steps: providing a reference frequency, constructing a weighted frequency difference model based on the reference frequency, calculating a weighted frequency difference through the weighted frequency difference model according to the working temperature and working voltage of chip testing, and dividing the chip grade according to the weighted frequency difference, wherein the working temperature is a temperature value obtained by temperature compensation of the actually measured temperature. The application constructs the weighted frequency difference model, calculates the weighted frequency difference of chip testing by using the working temperature after temperature compensation, replaces the test result of the traditional constant temperature testing machine, and overcomes the technical defects of low test result accuracy caused by the difficulty in temperature control in the test process of the large current calculation type chip by the weighted frequency difference and temperature compensation under the premise of significantly reducing the test cost.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to a chip testing method and system. Background Technology

[0002] Due to differences in manufacturing processes, computing chips produced by different wafer packaging plants and using different processes can exhibit varying performance characteristics. Even within the same wafer packaging plant, significant differences can occur between different batches. This necessitates chip testing equipment capable of classifying chip performance into grades, typically based on the highest operating frequency the chip can achieve. The highest operating frequency of such chips is usually highly dependent on the chip's temperature.

[0003] In reality, these types of chips often consume relatively high power due to their high-speed mathematical calculation capabilities, generating a significant amount of heat during testing. Since ordinary testing equipment typically lacks temperature control, this heat cannot dissipate quickly enough, causing the chip's temperature to rise during testing. Therefore, both ambient temperature variations and temperature increases during testing can alter chip performance, thus affecting the accuracy and consistency of test results.

[0004] Currently, the common approach to solving this problem is to use temperature-controlled testing equipment. This involves using cooling devices to keep the chip at a relatively constant temperature during testing. However, this solution has drawbacks: high cost, the need for an additional temperature control system, and the time lag between detecting a temperature change and effectively cooling the chip during testing, making it difficult to maintain a constant internal chip temperature. Therefore, even disregarding cost, existing temperature-controlled testing equipment still suffers from low test accuracy. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is to overcome the technical defects of the existing high current calculation chips, which have low accuracy of test results due to the difficulty of temperature control during the testing process.

[0006] To address the aforementioned technical problems, this invention provides a chip testing method, comprising:

[0007] A reference frequency is provided, and a weighted frequency difference model is constructed based on the reference frequency;

[0008] Based on the chip's operating temperature and operating voltage, a weighted frequency difference is calculated using the weighted frequency difference model, and the chip is classified according to the weighted frequency difference. The operating temperature is the measured temperature value obtained after temperature compensation.

[0009] In one embodiment of the present invention, a weighted frequency difference model is constructed based on the reference frequency, including:

[0010] The weighted frequency difference model is constructed based on the operating voltage, operating temperature, and reference frequency as follows:

[0011] ΔF=m*V / T work +cF base

[0012] In the formula, ΔF represents the weighted frequency difference, V represents the operating voltage, and T represents the operating voltage. work Indicates operating temperature, F base represents the reference frequency, m represents the gain, and c represents the bias.

[0013] In one embodiment of the present invention, when constructing the weighted frequency difference model, the operating temperature is the measured temperature obtained after temperature compensation, and the temperature compensation formula is:

[0014] T work =T0+β*ΔT

[0015] In the formula, T work T represents the operating temperature, T0 represents the reference temperature, ΔT represents the temperature rise, and β represents the influence coefficient of the temperature rise on the operating temperature.

[0016] In one embodiment of the present invention, after constructing the weighted frequency difference model, multiple sets of chips are tested using a constant temperature system to obtain multiple sets of candidate gains and biases, and the gain and bias of the weighted frequency difference model are determined based on the multiple sets of candidate gains and biases.

[0017] In one embodiment of the present invention, solving for multiple sets of candidate gains and biases includes:

[0018] Substitute each preset operating voltage and operating temperature into the formula ΔF+F base =m*V / T work +c, we obtain multiple sets of equations concerning gain and bias;

[0019] By combining each set of equations, the solution to each set of equations is calculated, resulting in multiple candidate gains and biases.

[0020] In one embodiment of the present invention, determining the gain and bias of the weighted frequency difference model based on multiple sets of candidate gains and biases includes:

[0021] The average gain of multiple candidate gains is calculated to obtain the gain of the weighted frequency difference model, and the average bias of multiple candidate biases is calculated to obtain the bias of the weighted frequency difference model.

[0022] In one embodiment of the present invention, the weighted frequency difference is calculated using the weighted frequency difference model based on the chip's operating temperature and operating voltage during testing, including:

[0023] The actual temperature of the chip is collected during testing, and the operating temperature is obtained after temperature compensation.

[0024] Substituting the temperature-compensated operating temperature and the actual operating voltage into the formula ΔF=m*V / T work +cF base In the solution, the weighted frequency difference is obtained.

[0025] Furthermore, the present invention also provides a chip testing system, comprising:

[0026] The model building module provides a reference frequency, and the model building module is used to build a weighted frequency difference model based on the reference frequency;

[0027] The chip testing module is used to calculate a weighted frequency difference based on the chip's operating temperature and operating voltage using the weighted frequency difference model, and to classify the chip according to the weighted frequency difference. The operating temperature is the measured temperature value obtained after temperature compensation.

[0028] In one embodiment of the present invention, a weighted frequency difference model is constructed based on the reference frequency, including:

[0029] The weighted frequency difference model is constructed based on the operating voltage, operating temperature, and reference frequency as follows:

[0030] ΔF=m*V / T work +cF base

[0031] In the formula, ΔF represents the weighted frequency difference, V represents the operating voltage, and T represents the operating voltage. work Indicates operating temperature, F base represents the reference frequency, m represents the gain, and c represents the bias.

[0032] In one embodiment of the present invention, after constructing the weighted frequency difference model, multiple sets of chips are tested using a constant temperature system to obtain multiple sets of candidate gains and biases, and the gain and bias of the weighted frequency difference model are determined based on the multiple sets of candidate gains and biases.

[0033] The technical solution of the present invention has the following advantages compared with the prior art:

[0034] The chip testing method and system described in this invention constructs a weighted frequency difference model and calculates the weighted frequency difference of the chip test using the operating temperature after temperature compensation. This replaces the test results of the traditional constant temperature tester. Under the premise of significantly reducing the test cost, the method overcomes the technical defects of low test results caused by the difficulty of temperature control in the test process of high current computing chips through weighted frequency difference and temperature compensation. Attached Figure Description

[0035] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein...

[0036] Figure 1 This is a flowchart illustrating a chip testing method proposed in this invention.

[0037] Figure 2 The results are from tests conducted using a traditional constant temperature testing machine.

[0038] Figure 3 These are test results obtained using the method of this invention. Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0040] This invention provides a chip testing method and system. By constructing a weighted frequency difference model, the weighted frequency difference of the chip test is calculated using the temperature-compensated operating temperature, replacing the test results of the traditional constant temperature tester. Under the premise of significantly reducing the test cost, the method overcomes the technical defects of low test results caused by the difficulty of temperature control in the testing process of high current computing chips through weighted frequency difference and temperature compensation.

[0041] This invention provides a chip testing method and system to address the problem of temperature control difficulties affecting chip grade testing results in high-current computing chips. The testing system model is as follows: the DPS module of the testing machine outputs voltage to power the chip; a set of digital test channels of the testing machine provides a continuous waveform excitation at a certain frequency; and the internal state of the chip is read back through the digital test channels to determine whether it is normal or malfunctioning, thus classifying the chip under test into a higher grade. The conventional definition is that, under a certain operating temperature and based on the same operating frequency, a chip that can accept a lower supply voltage and operate normally will be classified as a higher-grade product. For example, two chips, A and B, operating at the same temperature and voltage, chip A can operate at 500MHz, but chip B can only operate at 450MHz. Therefore, chip A is classified as superior, and chip B is classified as ordinary.

[0042] Chip operating temperature is usually easily read from within the chip via the digital channel of the test machine or from the temperature sensor on the test load board. Based on this, please refer to... Figure 1 As shown in the figure, an embodiment of the present invention provides a chip testing method, which includes the following steps:

[0043] Step S1: Provide a reference frequency, and construct a weighted frequency difference model based on the reference frequency;

[0044] Step S2: Based on the chip's operating temperature and operating voltage, calculate the weighted frequency difference using the weighted frequency difference model, and classify the chip according to the weighted frequency difference. The operating temperature is the measured temperature value obtained after temperature compensation.

[0045] In step S1, constructing a weighted frequency difference model based on the reference frequency includes: constructing a weighted frequency difference model based on the operating voltage, operating temperature, and reference frequency as follows: ΔF = m * V / T work +cF base In the formula, ΔF represents the weighted frequency difference, V represents the operating voltage, and T represents the operating voltage. work Indicates operating temperature, F base represents the reference frequency, m represents the gain, and c represents the bias.

[0046] As an example, for a specific chip, the highest clock frequency that the system can operate at, which is also the highest frequency at which the digital channel excites the chip, is F=F. base +ΔF, where F in the formula base The reference frequency is given in the test, and ΔF is the weighted frequency difference between the actual ambient temperature and the temperature rise generated during the test. F=m*V / T work +c, for the testing method of this invention, means that it is necessary to determine the operating voltage V and operating temperature T.work To calculate the weighted frequency difference ΔF = m * V / T under the current environment work +cF base .

[0047] Further, in step S1, after constructing the weighted frequency difference model, multiple sets of chips are tested using a constant temperature system to obtain multiple sets of candidate gains and biases, and the gain and bias of the weighted frequency difference model are determined based on the multiple sets of candidate gains and biases.

[0048] Specifically, each preset operating voltage and operating temperature is substituted into the formula ΔF+F base =m*V / T work +c, to obtain multiple sets of equations about gain and bias; solve each set of equations simultaneously, and calculate the solution of each set of equations to obtain multiple sets of candidate gains and biases; calculate the average value of the gains of multiple candidate gains to obtain the gain of the weighted frequency difference model, and calculate the average value of the biases of multiple candidate biases to obtain the bias of the weighted frequency difference model.

[0049] As an example, the same chip was first tested using a constant temperature testing machine, with two different operating temperatures T set. work 'and T work Using a fixed operating voltage V, the operating temperature T can be obtained separately. work 'and T work The operating frequency is ''. For the formula ΔF=m*V / T work +cF base In the middle, V, T work All are known quantities, T work 'and T work '' Corresponding ΔF+F base Alternatively, these quantities can be measured using a constant temperature testing machine. Substituting these known quantities into the formula ΔF=m*V / T work +cF base This process yields a set of equations for gain and bias. By solving these equations simultaneously, we can obtain the candidate gain and bias values. Repeating this process with a different chip yields another set of candidate gain and bias values. After small-batch verification testing of a batch of chips, multiple candidate gain and bias values ​​are obtained. The average value of these multiple candidate gains and bias values ​​is then calculated to obtain the final gain and bias of the weighted frequency difference model. This completes the acquisition of a weighted frequency difference model with definite gain and bias values, which is then used in the mass production testing of the chips.

[0050] In step S2, the weighted frequency difference is calculated using the weighted frequency difference model based on the chip's operating temperature and voltage during testing. This includes: acquiring the measured temperature of the chip during testing; obtaining the operating temperature after temperature compensation from the measured temperature; and substituting the temperature-compensated operating temperature and the actual operating voltage into the formula ΔF=m*V / T. work +cF base In the solution, the weighted frequency difference is obtained.

[0051] The test results are primarily affected by two temperature values: the ambient reference temperature T0 of the chip's environment, and the temperature rise ΔT during the test. T0 can vary significantly between different testing facilities, and even different working areas within the same testing facility can exhibit noticeable temperature differences. ΔT is mainly related to the test program. The principle of this invention is to calculate the difference in the maximum clock frequency caused by temperature based on the current temperature and voltage. The aforementioned temperature compensation formula is: T work =T0+β*ΔT, where T work T0 represents the operating temperature, ΔT represents the reference temperature, β represents the temperature rise, and β represents the influence coefficient of the temperature rise on the operating temperature. Preferably, in this embodiment, β = 0.5 is selected.

[0052] Figure 2 and Figure 3 These are the results of a comparative test on a batch of chips. Figure 2 The results are from chip grading using a traditional constant temperature testing machine. Figure 3 The test results obtained using the method of this invention show that the two results are similar, thus proving the effectiveness of the method of this invention. This allows the mass production of computing chips to use ordinary testing machines instead of expensive constant temperature testing machines. Under the premise of significantly reducing testing costs, the method overcomes the technical defects of low test results caused by the difficulty in temperature control during the testing of high-current computing chips by using weighted frequency difference and temperature compensation.

[0053] The following describes a chip testing system disclosed in an embodiment of the present invention. The chip testing system described below can be referred to in correspondence with the chip testing method described above.

[0054] This invention provides a chip testing system, comprising:

[0055] The model building module provides a reference frequency, and the model building module is used to build a weighted frequency difference model based on the reference frequency;

[0056] The chip testing module is used to calculate a weighted frequency difference based on the chip testing operating temperature and operating voltage using the weighted frequency difference model, and to calculate the chip testing operating frequency based on the weighted frequency difference and the reference frequency, wherein the operating temperature is the measured temperature value obtained after temperature compensation.

[0057] In one embodiment of the present invention, constructing a weighted frequency difference model based on the reference frequency includes: constructing the weighted frequency difference model according to the operating voltage, operating temperature, and reference frequency as follows:

[0058] ΔF=m*V / T work +cF base

[0059] In the formula, ΔF represents the weighted frequency difference, V represents the operating voltage, and T represents the operating voltage. work Indicates operating temperature, F base represents the reference frequency, m represents the gain, and c represents the bias.

[0060] As an example, for a specific chip, the highest clock frequency that the system can operate at, which is also the highest frequency at which the digital channel excites the chip, is F=F. base +ΔF, where F in the formula base The reference frequency is given in the test, and ΔF is the weighted frequency difference between the actual ambient temperature and the temperature rise generated during the test. F=m*V / T work +c, for the testing method of this invention, means that it is necessary to determine the operating voltage V and operating temperature T. work To calculate the weighted frequency difference ΔF = m * V / T under the current environment work +cF base .

[0061] In one embodiment of the present invention, after constructing the weighted frequency difference model, multiple sets of chips are tested using a constant temperature system to obtain multiple sets of candidate gains and biases, and the gain and bias of the weighted frequency difference model are determined based on the multiple sets of candidate gains and biases.

[0062] Specifically, each preset operating voltage and operating temperature is substituted into the formula ΔF+F base =m*V / T work +c, to obtain multiple sets of equations about gain and bias; solve each set of equations simultaneously, and calculate the solution of each set of equations to obtain multiple sets of candidate gains and biases; calculate the average value of the gains of multiple candidate gains to obtain the gain of the weighted frequency difference model, and calculate the average value of the biases of multiple candidate biases to obtain the bias of the weighted frequency difference model.

[0063] As an example, the same chip was first tested using a constant temperature testing machine, with two different operating temperatures T set. work 'and T work Using a fixed operating voltage V, the operating temperature T can be obtained separately. work 'and T work The operating frequency is ''. For the formula ΔF=m*V / T work +cF base In the middle, V,T work All are known quantities, T work 'and T work '' Corresponding ΔF+F base Alternatively, these quantities can be measured using a constant temperature testing machine. Substituting these known quantities into the formula ΔF=m*V / T work +cF base This process yields a set of equations for gain and bias. By solving these equations simultaneously, we can obtain the candidate gain and bias values. Repeating this process with a different chip yields another set of candidate gain and bias values. After small-batch verification testing of a batch of chips, multiple candidate gain and bias values ​​are obtained. The average value of these multiple candidate gains and bias values ​​is then calculated to obtain the final gain and bias of the weighted frequency difference model. This completes the acquisition of a weighted frequency difference model with definite gain and bias values, which is then used in the mass production testing of the chips.

[0064] The chip testing system of this embodiment is used to implement the aforementioned chip testing method. Therefore, the specific implementation of this system can be found in the embodiment section of the chip testing method above. Thus, its specific implementation can be referred to the description of the corresponding embodiments, and will not be elaborated here.

[0065] Furthermore, since the chip testing system in this embodiment is used to implement the aforementioned chip testing method, its function corresponds to that of the method described above, and will not be repeated here.

[0066] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0067] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0068] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0069] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0070] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A chip testing method, characterized in that: include: A reference frequency is provided, and a weighted frequency difference model is constructed based on the reference frequency, including: The weighted frequency difference model is constructed based on the operating voltage, operating temperature, and reference frequency as follows: ΔF=m*V / T work +c-F base In the formula, ΔF represents the weighted frequency difference, V represents the operating voltage, and T represents the operating voltage. work Indicates operating temperature, F base This represents the reference frequency, m represents the gain, and c represents the bias. The operating temperature mentioned above is the measured temperature value obtained after temperature compensation, and the temperature compensation formula is as follows: T work =T0+β*ΔT In the formula, T work T0 represents the reference temperature, ΔT represents the temperature rise, and β represents the influence coefficient of the temperature rise on the operating temperature. Based on the chip's operating temperature and operating voltage, a weighted frequency difference is calculated using the weighted frequency difference model, and the chip is classified according to the weighted frequency difference. The operating temperature is the measured temperature value obtained after temperature compensation. The step of calculating the weighted frequency difference based on the chip's operating temperature and voltage using the weighted frequency difference model includes: The actual temperature of the chip is collected during testing, and the operating temperature is obtained after temperature compensation. Substituting the temperature-compensated operating temperature and the actual operating voltage into the formula ΔF=m*V / T work +cF base In the solution, the weighted frequency difference is obtained.

2. The chip testing method according to claim 1, characterized in that: After constructing the weighted frequency difference model, multiple sets of chips are tested using a constant temperature system to obtain multiple sets of candidate gains and biases. Based on the multiple sets of candidate gains and biases, the gain and bias of the weighted frequency difference model are determined.

3. The chip testing method according to claim 2, characterized in that: The solution yields multiple sets of candidate gains and biases, including: Substitute each preset operating voltage and operating temperature into the formula ΔF+F base =m*V / T work +c, we obtain multiple sets of equations concerning gain and bias; By combining each set of equations, the solution to each set of equations is calculated, resulting in multiple candidate gains and biases.

4. The chip testing method according to claim 3, characterized in that: Determining the gain and bias of the weighted frequency difference model based on multiple sets of candidate gains and biases includes: The average gain of multiple candidate gains is calculated to obtain the gain of the weighted frequency difference model, and the average bias of multiple candidate biases is calculated to obtain the bias of the weighted frequency difference model.

5. A chip testing system, characterized in that: The system is used to implement a chip testing method according to any one of claims 1 to 4, comprising: The model building module provides a reference frequency, and the model building module is used to build a weighted frequency difference model based on the reference frequency; The chip testing module is used to calculate a weighted frequency difference based on the chip's operating temperature and operating voltage using the weighted frequency difference model, and to classify the chip according to the weighted frequency difference. The operating temperature is the measured temperature value obtained after temperature compensation.

6. The chip testing system according to claim 5, characterized in that: A weighted frequency difference model is constructed based on the reference frequency, including: The weighted frequency difference model is constructed based on the operating voltage, operating temperature, and reference frequency as follows: ΔF=m*V / T work +c-F base In the formula, ΔF represents the weighted frequency difference, V represents the operating voltage, and T represents the operating voltage. work Indicates operating temperature, F base represents the reference frequency, m represents the gain, and c represents the bias.

7. A chip testing system according to claim 6, characterized in that: After constructing the weighted frequency difference model, multiple sets of chips are tested using a constant temperature system to obtain multiple sets of candidate gains and biases. Based on the multiple sets of candidate gains and biases, the gain and bias of the weighted frequency difference model are determined.

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