Memory control system and method

Abstract

The application provides a memory control system and method, comprising: a memory, including a main storage module and a built-in EEPROM; a memory controller, in a normal mode, reading a program in the main storage module based on an instruction of a processor, and performing read-write control on the built-in EEPROM; in a test mode, performing read-write control on the main storage module or the built-in EEPROM based on a configuration of a test control signal, or completing self-test based on an instruction of the test control signal; and the processor. The application greatly reduces resource loss; eliminates the logic of hardware control reading part after hibernation, and the time consumed during hibernation and wake-up, and has simple flow and high efficiency; only one counter is used to realize the control of the whole system timing, effectively reducing the area and power consumption of the whole system.

Description

Technical Field

[0001] This invention relates to the field of memory, and in particular to a memory control system and method. Background Technology

[0002] Current processors often employ a program memory + independent EEPROM memory architecture. This architecture presents three main problems in digital design:

[0003] 1. This architecture uses separate program memory and EEPROM, which results in higher costs.

[0004] 2. This architecture requires separate controller designs for the program memory and EEPROM, which increases the chip area.

[0005] 3. The separate controller design for the program memory and EEPROM in this architecture leads to an increase in the number of logic gates, which in turn increases power consumption.

[0006] Therefore, how to simplify the processor's memory architecture and control logic, thereby reducing cost, chip area and power consumption, has become one of the problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a memory control system and method to solve the problems of high cost, large chip area, and high power consumption in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a memory control system, the memory control system comprising at least:

[0009] Memory, memory controller, and processor;

[0010] The memory includes a main storage module and a built-in EEPROM;

[0011] The storage controller connects to the memory and the processor, and receives test control signals. In normal mode, it reads the program in the main storage module based on the instructions of the processor and performs read and write control on the built-in EEPROM. In test mode, it performs read and write control on the main storage module or the built-in EEPROM based on the configuration of the test control signals, or completes self-test based on the instructions of the test control signals.

[0012] Optionally, the storage controller includes a control register group, a state machine, a timing control unit, a data address processing unit, and a built-in self-test control unit;

[0013] The built-in self-test control unit receives the test control signal and generates a self-test configuration signal;

[0014] The control register group obtains configuration instructions from the processor, the built-in self-test control unit, and the test control signal, and receives, stores, and parses the configuration instructions;

[0015] The state machine is connected to the control register group and controls the transition of the working state based on the output signal of the control register group;

[0016] The timing control unit is connected to the state machine and the memory, and generates timing control signals that satisfy the operation of the memory based on the working state determined by the state machine.

[0017] The data address processing unit is connected to the state machine, the control register group, and the memory. It controls the operation address of the memory based on the state machine and the control register group, and processes the data read from or written to the memory.

[0018] Alternatively, the timing control unit includes a timing information array and a counter; the timing information array includes a target count value corresponding to each working state, a count value corresponding to the rising edge of each timing signal, and a count value corresponding to the falling edge; the counter counts each working state based on the timing information array, and is reset to zero after reaching the target count value corresponding to each working state.

[0019] Alternatively, the storage controller may further include a trimming register group connected to the output of the data address processing unit, which reads the trimming value in the memory upon power-up and performs registration and parsing.

[0020] Alternatively, the state machine is in an idle state by default. After power-on, it switches to the trim value reading state, and returns to the idle state after reading. Upon receiving a read instruction from the main storage module, the state machine switches from the idle state to the main storage module reading state, and returns to the idle state after reading. Upon receiving a read instruction from the built-in EEPROM, the state machine switches from the idle state to the built-in EEPROM reading state, and returns to the idle state after reading. Upon receiving a write instruction from the main storage module, the state machine switches from the idle state to the main storage module erase state, and switches to the main storage module write state after erasing, and returns to the idle state after writing. Upon receiving a write instruction from the built-in EEPROM, the state machine switches from the idle state to the built-in EEPROM erase state, and switches to the built-in EEPROM write state after erasing, and returns to the idle state after writing.

[0021] Optionally, the processor is a CPU or an MCU.

[0022] Alternatively, the memory control system further includes an I2C slave and a test mode controller; the I2C slave receives external I2C signals; the test mode controller is connected to the I2C slave, sets the test mode based on the output signal of the I2C slave, and outputs the test control signal.

[0023] To achieve the above and other related objectives, the present invention provides a memory control method, implemented based on the aforementioned memory control system, wherein the memory control method includes at least:

[0024] In normal mode, the storage controller reads the program in the main storage module based on the processor's instructions and performs read and write operations on the built-in EEPROM.

[0025] In test mode, the storage controller performs read and write operations on the main storage module or the built-in EEPROM based on the configuration of the test control signal; or completes self-test based on the instructions of the test control signal.

[0026] Optionally, when performing a write operation on the built-in EEPROM in normal mode, the processor executes a program and enters a sleep state after configuring the control register group, writes data to the built-in EEPROM, and wakes up and continues to execute the program after the write operation is completed; when performing a read operation on the built-in EEPROM in normal mode, the processor executes the read operation program during the entire reading process, reads data from the built-in EEPROM and reports it to the processor.

[0027] Alternatively, the memory control method further includes: reading the adjustment value in the main memory module after power-on, entering a window period to wait after the adjustment value is read, and determining whether to work in normal mode or test mode within the window period.

[0028] As described above, the memory control system and method of the present invention have the following beneficial effects:

[0029] 1. The memory control system and method of the present invention eliminates the use of RAM when performing read and write operations on EEPROM, and only a small number of registers are needed to replace it, which greatly reduces the consumption of resources.

[0030] 2. When performing read operations on the EEPROM, the memory control system and method of the present invention directly obtain the EEPROM data through the processor without performing sleep / wake-up operations; it eliminates the logic of hardware control for reading after sleep, as well as the time consumed during sleep and wake-up, making the process simple and efficient.

[0031] 3. The memory control system and method of the present invention uses only one timing control unit and only one counter to control the timing of the entire system, which effectively reduces the area and power consumption of the entire system. Attached Figure Description

[0032] Figure 1 The diagram shows a memory architecture with built-in EEPROM.

[0033] Figure 2 The diagram shown is an architectural schematic of the memory control system of the present invention.

[0034] Figure 3 The diagram shown is a schematic representation of the memory control system of the present invention.

[0035] Figure 4 The diagram shown is a schematic representation of the state transitions of the state machine of this invention.

[0036] Figure 5 The diagram shown illustrates the principle of timing control in this invention.

[0037] Figure 6 The diagram shown is a flowchart of the memory control method of the present invention.

[0038] Figure 7 The diagram shows the normal mode EEPROM writing timing diagram of the present invention.

[0039] Figure 8 The diagram shows the normal mode EEPROM read timing diagram of the present invention.

[0040] Component designation explanation

[0041] 11. Memory

[0042] 111 Main Storage Module

[0043] 112 Built-in EEPROM

[0044] 12 Selectors

[0045] 13 Storage Controller

[0046] 14 CPU

[0047] 15 RAM

[0048] 16 RAM controller

[0049] 17 Built-in self-test controller

[0050] 18 Test Mode Controller

[0051] 19 I2C Slave

[0052] 2. Memory Control System

[0053] 21. Memory

[0054] 211 Main Storage Module

[0055] 212 Built-in EEPROM

[0056] 22 Storage Controller

[0057] 221 Control Register Group

[0058] 222 State Machine

[0059] 223 Timing Control Unit

[0060] 224 Data Address Processing Unit

[0061] 225 Built-in self-test control unit

[0062] 226 Adjustment Register Set

[0063] 23 Processors

[0064] 24 I2C Slave

[0065] 25 Test Mode Controller

[0066] 26 Modules to be Repaired Detailed Implementation

[0067] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0068] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0069] like Figure 1As shown, a memory scheme with built-in EEPROM is proposed, including a memory 11, a selector 12, a memory controller 13, a CPU 14, RAM 15, a RAM controller 16, a built-in self-test controller 17, a test mode controller 18, and an I2C slave 19. The memory 11 includes a main memory module 111 and a built-in EEPROM 112; the memory controller 13 includes a state machine, a timing control unit, a data address processing unit, a test register group, and a trim register group; the RAM controller 16 includes a RAM register group; and the built-in self-test controller 17 includes a state machine, a timing control unit, and a data address processing unit. The functions implemented by this scheme include: reading the power-on trim value in normal mode; reading the internal program of the memory by the CPU in normal mode; reading and writing the EEPROM in normal mode; writing and reading the MTP (Multiple Programming Port) via I2C in test mode; writing and reading the EEPROM via I2C in test mode; and built-in self-test of the memory in test mode.

[0070] In normal mode, the power-on trim value is read after power-on. The timing is controlled by the storage controller 13 to perform a read operation on the trim value stored at a fixed address inside the memory 11. The read trim value is then stored in the internal trim register group and reported to other modules.

[0071] In normal mode, the CPU14 reads the program inside the memory by the memory controller 13 issuing a read timing signal to the memory 11 according to the address specified by the CPU, and then reporting the read data to the CPU14.

[0072] In normal mode, EEPROM read and write operations cannot be performed simultaneously on the main storage module 111 and the built-in EEPROM 112, so they must be indirectly performed through RAM 15. The specific steps for writing to the EEPROM are as follows: first, write data to RAM 15 and configure the RAM register group for EEPROM write operations; then, configure CPU 14 to enter sleep mode to prevent CPU 14 from continuing to read data from the MTP program area; finally, after CPU 14 enters sleep mode, the hardware automatically switches to select the EEPROM region and maps the data in RAM 15 to the EEPROM. After completion, CPU 14 is automatically woken up to continue executing the program. The specific steps for reading from the EEPROM are as follows: first, configure the RAM register group for EEPROM read operations; then, configure CPU 14 to enter sleep mode to prevent CPU 14 from continuing to read data from the MTP program area; finally, after CPU 14 enters sleep mode, the hardware automatically switches to select the EEPROM region and maps the data in the EEPROM to RAM 15. After completion, CPU 14 is automatically woken up to continue executing the program. The user indirectly reads EEPROM data by reading from RAM 15.

[0073] In test mode, read and write operations on memory 11 are performed by sending instructions through an external I2C host. The internal I2C slave 19 parses the received instructions and enters the corresponding mode, and completes the configuration of the test register group in the memory controller 13. Thus, the memory controller 13 generates read and write timing control for memory 11.

[0074] In test mode, the built-in self-test of memory 11 is performed by sending instructions through an external I2C host. The internal I2C slave 19 parses the received instructions and enters the corresponding mode. The built-in self-test controller 17 is enabled to generate timing signals, which are selected by selector 12 and then take over memory 11 to complete the self-test of the entire memory 11.

[0075] Therefore, it is evident that EEPROM operations, which involve interaction via RAM 15, consume significant resources; EEPROM read or write operations require CPU 14 to perform sleep / wake-up operations, resulting in a complex and inefficient process; both the memory controller 13 and the built-in self-test controller 16 include timing control units, and using too many timing control units, i.e., extensive use of counters, will lead to increased area and power consumption. Based on the above reasons, this invention proposes a new memory control system to solve these problems, the specific solution of which is as follows.

[0076] like Figure 2 and Figure 3 As shown, this embodiment provides a memory control system 2, which includes:

[0077] Memory 21, memory controller 22 and processor 23.

[0078] like Figure 2 and Figure 3 As shown, the memory 21 includes a main memory module 211 and a built-in EEPROM 212.

[0079] Specifically, the address of the memory 21 is divided into two parts: one part serves as the main memory module 211, and the other part serves as the built-in EEPROM 212. As an example, addresses 0x0000 to (0xXXXX-1) are allocated to the main memory module 211 for storing programs and adjustment values; addresses from 0xXXXX onwards are allocated to the built-in EEPROM 212 for storing data.

[0080] like Figure 2 and Figure 3As shown, the storage controller 22 is connected to the memory 21 and the processor 23, and receives test control signals. In normal mode, it reads the program in the main storage module 211 based on the instructions of the processor 23, and performs read and write control on the built-in EEPROM 212. In test mode, it performs read and write control on the main storage module 211 or the built-in EEPROM 212 based on the configuration of the test control signals, or completes self-test based on the instructions of the test control signals.

[0081] Specifically, such as Figure 2 and Figure 3 As shown, the storage controller 22 includes a control register group 221, a state machine 222, a timing control unit 223, a data address processing unit 224, and a built-in self-test control unit 225.

[0082] More specifically, the built-in self-test control unit 225 receives the test control signal, generates a self-test configuration signal, automatically configures the control register group 221, and thus controls the entire test process.

[0083] More specifically, the control register group 221 obtains configuration instructions from the processor 23, the built-in self-test control unit 225 and the test control signal, and receives, stores and parses the configuration instructions.

[0084] More specifically, the state machine 222 is connected to the control register group 221, and controls the transition of the working state based on the output signal of the control register group 221. As an example, the state machine 222 includes eight states: IDLE (idle), TRIM_RD (TRIM trimming value read), MAIN_RD (main memory module read), MAIN_WR (main memory module write), MAIN_ER (main memory module erase), EE_RD (internal EEPROM read), EE_WR (internal EEPROM write), and EE_ER (internal EEPROM erase). Figure 4As shown, the state machine 222 is in the idle state (IDLE) by default. After power-on, it switches to the trim value reading state (TRIM_RD), and returns to the idle state (IDLE) after completing the read. Upon receiving a read instruction from the main storage module 211, the state machine 222 switches from the idle state (IDLE) to the main storage module reading state (MAIN_RD), and returns to the idle state (IDLE) after completing the read. Upon receiving a read instruction from the built-in EEPROM, the state machine 222 switches from the idle state (IDLE) to the built-in EEPROM reading state (EE_RD), and returns to the idle state after completing the read. Upon receiving a write instruction from the main storage module 211, the state machine 222 switches from the idle state IDLE to the main storage module erase state MAIN_ER, and after completing the erase, switches to the main storage module write state MAIN_WR, and after completing the write, returns to the idle state IDLE; upon receiving a write instruction from the built-in EEPROM, the state machine 222 switches from the idle state IDLE to the built-in EEPROM erase state EE_ER, and after completing the erase, switches to the built-in EEPROM write state EE_WR, and after completing the write, returns to the idle state IDLE.

[0085] More specifically, the timing control unit 223 is connected to the state machine 222 and the memory 21, and generates timing control signals that satisfy the operation of the memory 21 based on the working state determined by the state machine 222. In this embodiment, the timing control unit 223 includes a timing information array and a counter; the timing information array includes at least the target count value corresponding to each working state, the count value corresponding to the rising edge of each timing signal, and the count value corresponding to the falling edge, which will not be described in detail here and can be set as needed; the counter counts each working state based on the timing information array and is reset to zero after reaching the target count value corresponding to each working state. As an example, the erase state and the programming state (i.e., the write state) are shown in the table below:

[0086]

[0087] In erase mode, the target count value `counter` is 9. The rising edge of the erase operation (`er_rise`) corresponds to a count value of 0, the falling edge of the erase operation (`er_fall`) corresponds to a count value of 8, the rising edge of the enable signal (`pep_rise`) corresponds to a count value of 1, and the falling edge of the enable signal (`pep_fall`) corresponds to a count value of 7. In programming mode, the target count value `counter` is 7. The rising edge of the programming operation (`pg_rise`) corresponds to a count value of 1, the falling edge of the programming operation (`pg_fall`) corresponds to a count value of 6, the rising edge of the enable signal (`pep_rise`) corresponds to a count value of 2, and the falling edge of the enable signal (`pep_fall`) corresponds to a count value of 5. For example... Figure 5As shown, the counter generates an erase timing signal ER, a programming timing signal PG, and an enable signal PEP based on the timing information array. In practical applications, corresponding timing control signals can be set as needed, which will not be elaborated here.

[0088] More specifically, the data address processing unit 224 is connected to the state machine 222, the control register group 221, and the memory 21. Based on the state machine 222 and the control register group 221, it controls the operation address of the memory 21 and processes the data read from or written to the memory 21. The structure of the data address processing unit 224 is not limited; any circuit structure capable of selecting a specified address in the memory 21 based on instructions is applicable to this invention, and will not be elaborated upon here.

[0089] More specifically, as another implementation of the present invention, the storage controller 22 further includes a trimming register group 226, which is connected to the output of the data address processing unit 224. Upon power-up, the trimming value in the memory 21 is read, stored, and parsed. The memory control system 2 further includes a trimming module 26, which is connected to the output of the trimming register group 226 and performs trimming based on the trimming data output by the trimming register group 226.

[0090] It should be noted that, as an example, the storage controller 22 is an embedded storage controller.

[0091] like Figure 2 and Figure 3 As shown, the processor 23 is connected to the storage controller 22.

[0092] Specifically, in this embodiment, the processor 23 obtains a program from the memory 21 through the storage controller 22, and performs data read and write operations on the memory 21 based on the program. The processor 23 includes, but is not limited to, a CPU (Central Processing Unit) or an MCU (Micro Control Unit). Any device with information processing and program execution functions is applicable to this invention, and will not be described in detail here.

[0093] like Figure 2 and Figure 3As shown, in another implementation of the present invention, the memory control system 2 further includes an I2C slave device 24 and a test mode controller 25. The I2C slave device 24 receives I2C signals from an external I2C host; the test mode controller 25 is connected to the I2C slave device 24, sets the test mode based on the output signals of the I2C slave device 24, and outputs the test control signal. In practical use, the test control signal can be directly input from the outside through a transmission line, and is not limited to this embodiment.

[0094] The memory control method implemented by the memory control system 1 is as follows:

[0095] In normal mode, the storage controller reads the program in the main storage module based on the processor's instructions and performs read and write operations on the built-in EEPROM.

[0096] In test mode, the storage controller performs read and write operations on the main storage module or the built-in EEPROM based on the configuration of the test control signal; or completes self-test based on the instructions of the test control signal.

[0097] Specifically, the memory control method further includes: reading the adjustment value in the main memory module after power-on, entering a window period to wait after the adjustment value is read, and determining whether to work in normal mode or test mode within the window period.

[0098] like Figure 6 As shown, the operation flow of the storage controller 22 includes: the storage controller 22 is in an idle state by default, and begins reading adjustment data after power-on. After the adjustment data is read, it enters a window period waiting period. During the window period, it can enter the test mode by sending a command through an external I2C host. After entering the test mode, it can continue to enter the programming mode or self-test mode by sending commands through I2C. In programming mode, the control register group 221 inside the storage controller 22 is configured by the external I2C host to complete the read and write operations of the main storage module 211 or EEPROM 212 area. In self-test mode, the built-in self-test control unit 225 inside the storage controller 22 will automatically configure the control register group 221 to complete the read and write operations of the main storage module 211 or EEPROM 212 area. If no command to enter the test mode is received within the window period waiting time, it will automatically enter the normal mode. In normal mode, the CPU will read the program stored in the main storage module 211 area and configure the control register group 221 through the CPU to complete the read and write operations of EEPROM 212 in normal mode.

[0099] Specifically, in normal mode, write operations to the built-in EEPROM are performed using a register + EEPROM approach. The processor 23 retrieves the program from the main memory module 211, runs the program to write data into the control register group 221, and enters a sleep state after configuring the control register group 221. The hardware circuit automatically writes the data in the control register group 221 into the built-in EEPROM 212. After the write operation is completed, the processor 23 is woken up and continues to execute the program. When the operation reaches the EEPROM area, the port signal EE_SEL of the control memory 21 will be automatically enabled (i.e., the EEPROM area is selected), and data will be written into the EEPROM area. Figure 7 The following is the timing sequence for writing to the EEPROM in normal mode. Here, EE_SEL is the EEPROM select signal, PG is the programming signal, AD[12:0] are the address signals for memory operations, D[7:0] are the memory input data signals, eg1[7:0] are the external configuration register signals that determine the memory input data, and cpu_clk is the processor clock signal. During the write process, the clock cpu_clk enters sleep mode, the EE_SEL signal is pulled high to select the EEPROM region, the write signal PG is pulled high, and the register data 8'bb is written to the EEPROM. After the write is complete, the EE_SEL and PG signals are pulled low, and cpu_clk wakes the program to continue running.

[0100] Specifically, in normal mode, the read operation on the built-in EEPROM is performed by the CPU directly reading the program area data. Throughout the reading process, the processor 23 executes the read operation program, reading data from the built-in EEPROM and reporting it to the processor 23. Figure 8 The timing sequence for reading EEPROM in normal mode is as follows: RE is the read signal, and Q[7:0] is the memory output data signal. When operating on the EEPROM area, the EE_SEL signal is pulled high, the data is read and reported to the CPU. During this process, the processor clock cpu_clk does not need to enter the sleep state, and the read operation can be completed in two clock cycles.

[0101] The memory control system and method of this invention are implemented based on a memory controller with built-in EEPROM, resulting in a simpler structure. In terms of resource utilization, it eliminates the dependence of EEPROM operations on RAM. Simultaneously, the memory controller and the built-in self-test control module are designed in a coordinated and integrated manner, maximizing the reuse of logic such as the state machine, timing control unit, and data address processing unit, effectively reducing logic gates and further lowering area and power consumption. This invention uses the memory controller as its core. In normal mode, the processor reads the program stored inside the main memory module and accesses the built-in EEPROM by configuring the control register group. In test mode, the I2C slave sends an instruction to enter the programming mode and configures the internal control register group of the memory controller to access the main memory module or EEPROM area. The I2C slave can also send an instruction to enter the self-test mode to complete the self-test.

[0102] In summary, this invention provides a memory control system and method, comprising: a memory, a memory controller, and a processor; the memory includes a main memory module and a built-in EEPROM; the memory controller connects to the memory and the processor, and receives test control signals. In normal mode, it reads the program in the main memory module based on the instructions of the processor, and performs read / write control on the built-in EEPROM; in test mode, it performs read / write control on the main memory module or the built-in EEPROM based on the configuration of the test control signals, or completes self-testing based on the instructions of the test control signals. When performing read / write operations on the EEPROM, the memory control system and method of this invention eliminates the use of RAM, requiring only a small number of registers instead, greatly reducing resource consumption; when performing read operations on the EEPROM, the EEPROM data is directly obtained through the processor, eliminating the need for sleep / wake-up operations, saving the logic of hardware control for reading after sleep, as well as the time consumed during sleep and wake-up, resulting in a simple process and high efficiency; only one timing control unit and only one counter are used to control the timing of the entire system, effectively reducing the overall system area and power consumption. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A memory control system, characterized in that, The memory control system includes at least: Memory, memory controller, and processor; The memory includes a main memory module and a built-in EEPROM; The storage controller is connected to the memory and the processor, and receives test control signals. In normal mode, it reads the program in the main storage module based on the instructions of the processor and performs read and write control on the built-in EEPROM. In test mode, it performs read and write control on the main storage module or the built-in EEPROM based on the configuration of the test control signals, or completes self-test based on the instructions of the test control signals. The storage controller includes a control register group, a state machine, a timing control unit, a data address processing unit, and a built-in self-test control unit. The built-in self-test control unit receives the test control signal and generates a self-test configuration signal; The control register group obtains configuration instructions from the processor, the built-in self-test control unit, and the test control signal, and receives, stores, and parses the configuration instructions; The state machine is connected to the control register group and controls the transition of the working state based on the output signal of the control register group; The timing control unit is connected to the state machine and the memory, and generates timing control signals that satisfy the operation of the memory based on the working state determined by the state machine. The data address processing unit is connected to the state machine, the control register group, and the memory. It controls the operation address of the memory based on the state machine and the control register group, and processes the data read from or written to the memory.

2. The memory control system according to claim 1, characterized in that: The timing control unit includes a timing information array and a counter; the timing information array includes a target count value corresponding to each working state, a count value corresponding to the rising edge of each timing signal, and a count value corresponding to the falling edge of each timing signal. The counter counts each working state based on the timing information array, and resets to zero after reaching the target count value corresponding to each working state.

3. The memory control system according to claim 1, characterized in that: The storage controller also includes a trimming register group, which is connected to the output of the data address processing unit. Upon power-up, the trimming value in the memory is read, stored, and parsed.

4. The memory control system according to claim 3, characterized in that: The state machine is in an idle state by default. After power-on, it switches to the trim value reading state and returns to the idle state after reading. Upon receiving a read instruction from the main storage module, the state machine switches from the idle state to the main storage module read state, and returns to the idle state after completing the read. Upon receiving a read instruction from the built-in EEPROM, the state machine switches from the idle state to the built-in EEPROM read state, and returns to the idle state after completing the read. Upon receiving a write instruction from the main storage module, the state machine switches from the idle state to the main storage module erase state. After erasing, it switches to the main storage module write state. After writing, it returns to the idle state. Upon receiving a write command for the built-in EEPROM, the state machine switches from the idle state to the built-in EEPROM erase state. After erasing, it switches to the built-in EEPROM write state. After writing, it returns to the idle state.

5. The memory control system according to claim 1, characterized in that: The processor is either a CPU or an MCU.

6. The memory control system according to any one of claims 1-5, characterized in that: The memory control system also includes an I2C slave device and a test mode controller; the I2C slave device receives external I2C signals; the test mode controller is connected to the I2C slave device, sets the test mode based on the output signal of the I2C slave device, and outputs the test control signal.

7. A memory control method, implemented based on the memory control system as described in any one of claims 1-6, characterized in that, The memory control method includes at least: In normal mode, the storage controller reads the program in the main storage module based on the processor's instructions and performs read and write operations on the built-in EEPROM. In test mode, the storage controller performs read and write operations on the main storage module or the built-in EEPROM based on the configuration of the test control signal; or completes self-test based on the instructions of the test control signal.

8. The memory control method according to claim 7, characterized in that: When performing a write operation on the built-in EEPROM in normal mode, the processor executes a program and enters a sleep state after configuring the control register group. Data is written to the built-in EEPROM. After the write operation is completed, the processor is woken up and continues to execute the program. When performing a read operation on the built-in EEPROM in normal mode, the processor executes the read operation program throughout the reading process, reads data from the built-in EEPROM, and reports it to the processor.

9. The memory control method according to claim 7 or 8, characterized in that: The memory control method further includes: reading the adjustment value in the main memory module after power-on, entering a window period to wait after the adjustment value is read, and determining whether to work in normal mode or test mode within the window period.

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