transfer circuit

Abstract

A transfer circuit includes a high voltage level transfer circuit and a latch circuit. The high voltage level transfer circuit has a first input terminal and a second input terminal, and a first output terminal and a second output terminal. The latch circuit receives the first output terminal and the second output terminal of the high voltage level transfer circuit, and outputs a signal. When the first input terminal receives a first pulse signal, the high voltage level transfer circuit outputs a low pulse signal at the first output terminal to the latch circuit, so that the latch circuit outputs a signal latched as high. When the second input terminal receives a second pulse signal, the high voltage level transfer circuit outputs a low pulse signal at the second output terminal to the latch circuit, so that the latch circuit outputs a signal latched as low.

Description

Technical Field

[0001] This application belongs to the field of circuits, and relates to driving circuits, and in particular to level shifting circuits. Background Technology

[0002] The drive circuit of an electric motor or motor typically includes a high-side voltage domain and a low-side voltage domain, as well as level shifting or transfer circuits and amplifiers. Level shifting circuits are electrical components that convert digital signals from the low-side voltage domain to the high-side voltage domain. The input signal is referenced to the low-side voltage domain, and the output signal is referenced to the high-side voltage domain. The high-side voltage domain and the low-side voltage domain should be separate and electrically isolated from each other.

[0003] In the applications described above, it is often necessary to shift the voltage level from 0V to a high-side voltage domain of 200V or higher. The output current of the driver circuit can be sensitive to rapidly changing common-mode voltage transients. The high-side voltage domain generates significant common-mode noise at the moment of transition, which may be caused by parasitic capacitance between the gate and drain of the driver circuit's output transistor. Traditional level shifting circuits may produce erroneous switching signals when common-mode noise occurs. If this results in the transistors on both the high-side and low-side voltage domains being connected simultaneously, disastrous consequences will ensue.

[0004] Therefore, there is an urgent need for a transient-resistant level shifting circuit that can still output a stable signal under common-mode noise interference, which can avoid generating erroneous switching signals and prevent the transistors on both sides of the high-side voltage domain and the low-side voltage domain from being connected together. Summary of the Invention

[0005] This application proposes a transfer circuit to address the shortcomings of the prior art, aiming to provide a transient-resistant level transfer circuit that can stably output signals even under common-mode noise interference.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] According to one embodiment of this application, a transfer circuit is provided, comprising a high-voltage level transfer circuit and a latching circuit. The high-voltage level transfer circuit has a first input terminal and a second input terminal, and a first output terminal and a second output terminal. The latching circuit receives the first output terminal and the second output terminal of the high-voltage level transfer circuit and outputs a signal. When the first input terminal receives a first pulse signal, the high-voltage level transfer circuit outputs a low-level pulse signal at its first output terminal to the latching circuit, causing the latching circuit to output a latched high-level signal. When the second input terminal receives a second pulse signal, the high-voltage level transfer circuit outputs a low-level pulse signal at its second output terminal to the latching circuit, causing the latching circuit to output a latched low-level signal.

[0008] Preferably, the transfer circuit operates in the voltage domain between the high level and the low level, and the difference between the high level and the low level is less than 2V.

[0009] Preferably, for latching the output, the latching circuit includes a first NAND gate, a second NAND gate, and an inverting gate. The first output terminal of the high-voltage level transfer circuit is connected to the first input terminal of the first NAND gate, the output terminal of the second NAND gate, and the input terminal of the inverting gate. The second output terminal of the high-voltage level transfer circuit is connected to the first input terminal of the second NAND gate and the output terminal of the first NAND gate. The output terminal of the inverting gate is used for output latching of the transfer circuit.

[0010] Preferably, in order to design a symmetrical circuit to cancel out instantaneous coupling current, the above-mentioned high-voltage level transfer circuit includes a first side circuit and a second side circuit with the same side circuit design. The input terminal of the first side circuit is the first input terminal of the above-mentioned high-voltage level transfer circuit, the input terminal of the second side circuit is the second input terminal of the above-mentioned high-voltage level transfer circuit, the first output terminal of the first side circuit and the second output terminal of the second side circuit are the second output terminal of the high-voltage level transfer circuit, and the first output terminal of the second side circuit and the second output terminal of the first side circuit are the first output terminal of the high-voltage level transfer circuit.

[0011] Preferably, in order to offset the instantaneous coupling current, the aforementioned side circuit includes a first current replication circuit and a second current replication circuit connected to each other. The input terminal of the first current replication circuit is the input terminal of the side circuit, the output terminal of the first current replication circuit is the first output terminal of the side circuit, and the output terminal of the second current replication circuit is the second output terminal of the side circuit.

[0012] Preferably, the first current replication circuit includes a first transistor, a second transistor, a third transistor, and a capacitor. The sources of the first transistor, the second transistor, and the third transistor and the first terminal of the capacitor are connected to each other to the high level. The gates of the first transistor, the second transistor, and the third transistor are connected to each other to the second terminal of the capacitor. The drain of the first transistor is the input terminal of the first current replication circuit. The drain of the second transistor is connected to the second current replication circuit. The drain of the third transistor is the output terminal of the first current replication circuit.

[0013] Preferably, the second current replication circuit includes a fourth transistor and a fifth transistor, the gate and drain of the fourth transistor and the gate of the fifth transistor are connected to each other in the first current replication circuit, the sources of the fourth transistor and the fifth transistor are connected to each other in the low level, and the drain of the fifth transistor is the output terminal of the second current replication circuit.

[0014] Preferably, the transfer circuit further includes a first high-voltage circuit and a second high-voltage circuit with the same high-voltage circuit design, wherein the output terminal of the first high-voltage circuit is connected to the first input terminal of the high-voltage level transfer circuit, and the output terminal of the second high-voltage circuit is connected to the second input terminal of the high-voltage level transfer circuit.

[0015] Preferably, the high-voltage circuit described above includes a high-voltage transistor and a first capacitor and a second capacitor connected in parallel. The input terminal of the high-voltage circuit is connected to the gate of the high-voltage transistor and the first terminal of the first capacitor and the second capacitor. The source of the high-voltage transistor is connected to the second terminal of the first capacitor and the second capacitor. The drain of the high-voltage transistor is the output terminal of the high-voltage circuit.

[0016] Preferably, the first input terminal and the second input terminal of the high-voltage level transfer circuit are respectively connected to the preamplifier circuit. When the input signal of the preamplifier circuit is a rising edge, the preamplifier circuit outputs the first pulse signal to the first input terminal of the high-voltage level transfer circuit. When the input signal of the preamplifier circuit is a falling edge, the preamplifier circuit outputs the second pulse signal to the second input terminal of the high-voltage level transfer circuit.

[0017] Due to the adoption of the above scheme, the beneficial effect of this application is that it can avoid the transfer circuit from generating incorrect flip signals, thereby preventing the transistors on both sides of the high-side voltage domain and the low-side voltage domain from being connected together. Attached Figure Description

[0018] Figure 1 This is a block diagram of a transfer circuit 100 according to an embodiment of the present application.

[0019] Figure 2 This is a circuit diagram of a latch circuit 120 according to an embodiment of this application.

[0020] Figure 3 This is a block diagram of a high-voltage level transfer circuit 110 according to an embodiment of this application.

[0021] Figure 4 This is a block diagram of a high-voltage level transfer side circuit 310 according to an embodiment of this application.

[0022] Figure 5 This is a block diagram of a first current replication circuit 410 according to an embodiment of this application.

[0023] Figure 6 This is a block diagram of a second current replication circuit 420 according to an embodiment of this application.

[0024] Figure 7 This is a block diagram of a transfer circuit 700 according to another embodiment of this application.

[0025] Figure 8 This is a circuit diagram of a high-voltage circuit 710 according to an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] The terms “first,” “second,” “third,” etc. (if present) in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the objects described herein may be used interchangeably where appropriate. In the description of this application, “plural” means two or more, unless otherwise expressly and specifically defined. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. Such functional entities may be implemented in software, in one or more hardware circuits or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0028] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0029] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or connections that allow for communication; they can refer to direct connections or indirect connections via an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the aforementioned terms in this application according to the specific circumstances.

[0030] To make the objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the drawings and specific embodiments.

[0031] Please refer to Figure 1 The diagram shown is a block illustration of a transfer circuit 100 according to an embodiment of this application. The transfer circuit 100 includes a high-voltage level transfer circuit 110 and a latching circuit 120. The transfer circuit 100 can operate in the voltage range between the BS voltage and the SW voltage. In other words, the high-voltage level transfer circuit 110 and the latching circuit 120 operate in the voltage range between the BS voltage and the SW voltage. The BS voltage is higher than the SW voltage. In one embodiment, the BS voltage and the SW voltage can differ by less than 2V, and the transfer circuit 100 can still operate normally.

[0032] like Figure 1 As shown, the transfer circuit 100 has two input terminals 112 and 114. Input terminal 112 is used to receive a first narrow pulse signal transmitted by the preceding circuit (e.g., a pulse generator). This first narrow pulse signal is transmitted when the input signal is at its rising edge. Input terminal 114 is used to receive a second narrow pulse signal transmitted by the preceding circuit (e.g., a pulse generator). This second narrow pulse signal is transmitted when the input signal is at its falling edge. In other words, when the input signal changes from low to high, the transfer circuit 100 receives the first narrow pulse signal from input terminal 112. Conversely, when the input signal changes from high to low, the transfer circuit 100 receives the second narrow pulse signal from input terminal 114. The aforementioned input terminals 112 and 114 can be referred to as the first input terminal 112 and the second input terminal 114, respectively.

[0033] like Figure 1 As shown, the first input terminal 112 and the second input terminal 114 are respectively input to the high-voltage level transfer circuit 110. Between the high-voltage level transfer circuit 110 and the latch circuit 120, there are two circuits, namely circuit A and circuit B. The latch circuit 120 has input terminals for circuit A and circuit B, and an output terminal 122 for outputting signals.

[0034] The transfer circuit 100 can work in conjunction with the high-voltage undervoltage protection circuit. The main function of the transfer circuit 100 is to prevent changes in the output signal of the output terminal 122 when the voltage of SW changes instantaneously, thereby ensuring the safety of the system under such changing conditions.

[0035] Please refer to Figure 2The diagram shown is a circuit schematic of a latch circuit 120 according to an embodiment of this application. The latch circuit 120 has input terminals A and B to receive output signals from a high-voltage level transfer circuit 110. The latch circuit 120 includes a first NAND gate 210, a second NAND gate 220, and an inverter 230. As previously described, the latch circuit 120 operates in the voltage domain between the BS voltage and the SW voltage. The first NAND gate 210, the second NAND gate 220, and the inverter 230 also operate in the voltage domain between the BS voltage and the SW voltage.

[0036] One input terminal of the first NAND gate 210 is connected to input terminal A of the latch circuit 120 and the output terminal of the second NAND gate 220. Similarly, one input terminal of the second NAND gate 220 is connected to input terminal B of the latch circuit 120 and the output terminal of the first NAND gate 210.

[0037] The input of the inverter 230 is connected to one input of the first NAND gate 210, input A of the latch circuit 120, and the output of the second NAND gate 220. The output of the inverter 230 is the output 122 of the latch circuit 120.

[0038] When the input terminal A of the latch circuit 120 receives a low-level pulse from the high-voltage level transfer circuit 110, and the low level of the low-level pulse is close to the SW voltage, the output terminal 122 of the latch circuit 120 will be the BS voltage, which is the high level in the BS / SW voltage domain.

[0039] Similarly, when the input B of the latch circuit 120 receives a low-level pulse from the high-voltage level transfer circuit 110, and the low level of the low-level pulse is close to the SW voltage, the output 122 of the latch circuit 120 will be the SW voltage, that is, the low level in the BS / SW voltage domain.

[0040] Please refer to Figure 3 The diagram shown is a block schematic of a high-voltage level shifting circuit 110 according to an embodiment of this application. As previously described, the high-voltage level shifting circuit 110 operates in the voltage domain between the BS voltage and the SW voltage. The high-voltage level shifting circuit 110 includes opposing circuits 310 on both sides. For convenience, in Figure 3 The one on the left is called the first-side circuit 310A. Figure 3 The circuit on the right is called the second-side circuit 310B. The first-side circuit 310A and the second-side circuit 310B also operate in the voltage domain between the BS voltage and the SW voltage. To compensate for the instantaneous change in the SW voltage, the first-side circuit 310A and the second-side circuit 310B are designed symmetrically.

[0041] Each side of the circuit 310 includes one input terminal 320 and two output terminals 330 and 340. For example... Figure 3 As shown, the input terminal 320A of the first side circuit 310A is the first input terminal 112 of the transfer circuit 100. Symmetrically, the input terminal 320B of the second side circuit 310B is the second input terminal 114 of the transfer circuit 100.

[0042] The first output terminal 330A of the first-side circuit 310A and the second output terminal 340B of the second-side circuit 310B are coupled to the input terminal B of the latch circuit 120. Symmetrically, the second output terminal 340A of the first-side circuit 310A and the first output terminal 330B of the second-side circuit 310B are coupled to the input terminal A of the latch circuit 120.

[0043] Because the first-side circuit 310A and the second-side circuit 310B are designed symmetrically, the output of the high-voltage level transfer circuit 110 is also symmetrical. When the input terminal 320A of the first-side circuit 310A receives a narrow pulse signal, a low-level pulse close to the SW voltage is generated at the input terminal A of the latch circuit 120. Symmetrically, when the input terminal 320B of the second-side circuit 310B receives a narrow pulse signal, a low-level pulse close to the SW voltage is generated at the input terminal B of the latch circuit 120.

[0044] Please refer to Figure 4 The diagram shown is a block schematic of a high-voltage level shifting side circuit 310 according to an embodiment of this application. The side circuit 310 operates in the voltage domain between the BS voltage and the SW voltage. The side circuit 310 includes a first current replication circuit 410 and a second current replication circuit 420. The first current replication circuit 410 is connected to the BS voltage, and the second current replication circuit 420 is connected to the SW voltage. The first current replication circuit 410 has a first contact 412 connected to a second contact 422 of the second current replication circuit 420.

[0045] The first current replication circuit 410 has an input terminal 320 and a first output terminal 330 of the side circuit 310. The second current replication circuit 420 has a second output terminal 340 of the side circuit 310. As previously described, the first output terminal 330 is connected to the second output terminal 340 of the second current replication circuit 420 on the other side of the circuit. The second output terminal 340 is connected to the first output terminal 340 of the first current replication circuit 410 on the other side of the circuit.

[0046] In one embodiment, the first current replication circuit 410 and the second current replication circuit 420 may be designed identically, each including a current mirror circuit as understood by those skilled in the art. In another embodiment, the first current replication circuit 410 and the second current replication circuit 420 may be designed with different current mirror circuits.

[0047] For ease of design, the transistors included in the first current replication circuit 410 can be of the same type. For example, all P-type transistors or all N-type transistors. Similarly, the transistors included in the second current replication circuit 420 can be of the same type. For example, all P-type transistors or all N-type transistors.

[0048] In one embodiment, the first current replication circuit 410 and the second current replication circuit 420 may be designed to include the same type of transistors, for example, all P-type transistors or all N-type transistors. In another embodiment, the first current replication circuit 410 and the second current replication circuit 420 may be designed to include different types of transistors. For example, the first current replication circuit 410 may include all P-type transistors, and the second current replication circuit 420 may include all N-type transistors. In another example, the first current replication circuit 410 may include all N-type transistors, and the second current replication circuit 420 may include all P-type transistors.

[0049] Please refer to Figure 5 The diagram shown is a block illustration of a first current replication circuit 410 according to an embodiment of this application. The first current replication circuit 410 may include a first transistor 510, a second transistor 520, a third transistor 530, and a capacitor 540. Figure 5 As shown, the first transistor 510, the second transistor 520, and the third transistor 530 are all N-type field-effect transistors. Those skilled in the art will understand that this application can be applied to different types of transistors depending on the application.

[0050] The sources of the first transistor 510, the second transistor 520, and the third transistor 530 are all connected to the BS voltage, and their gates are connected to each other. The first terminal of capacitor 540 is connected to the BS voltage, and the second terminal is connected to the gates of the three transistors 510. The drain of the first transistor 510 is the input terminal 320 of the first current replication circuit 410, and the drain 412 of the second transistor 520 is connected to the second current replication circuit 420. The drain of the third transistor 530 is the first output terminal 330 of this circuit 310.

[0051] Please refer to Figure 6 The diagram shown is a block illustration of a second current replication circuit 420 according to an embodiment of this application. The second current replication circuit 420 may include a fourth transistor 610 and a fifth transistor 620. The sources of the fourth transistor 610 and the fifth transistor 620 are connected to the SW voltage. The drain 412 of the second transistor 620 is connected to the drain 422 and gate of the fourth transistor 610, and to the gate of the fifth transistor 620. The drain of the fifth transistor 620 is the second output terminal 340 of the circuit 310 on this side.

[0052] Combination Figure 3 , Figure 5 and Figure 6 In one embodiment, the drain of the third transistor 530 in the first-side circuit 310A is connected to the drain of the fifth transistor 620 in the second-side circuit 310B, serving as the input terminal B of the latch circuit 120. Similarly, the drain of the third transistor 530 in the second-side circuit 310B is connected to the drain of the fifth transistor 620 in the first-side circuit 310A, serving as the input terminal A of the latch circuit 120.

[0053] When the input terminal 320A of the first-side circuit 310A receives a narrow pulse signal, a low-level pulse close to the SW voltage will be generated at the input terminal A of the latch circuit 120. When the input terminal A of the latch circuit 120 receives a low-level pulse from the high-voltage level transfer circuit 110, and the low level of the low-level pulse is close to the SW voltage, the output terminal 122 of the latch circuit 120 will be the BS voltage, which is the high level in the BS / SW voltage domain.

[0054] Symmetrically, when the input terminal 320B of the second-side circuit 310B receives a narrow pulse signal, a low-level pulse close to the SW voltage will be generated at the input terminal B of the latch circuit 120. When the input terminal B of the latch circuit 120 receives a low-level pulse from the high-voltage level transfer circuit 110, and the low level of this low-level pulse is close to the SW voltage, the output terminal 122 of the latch circuit 120 will be the SW voltage, that is, the low level in the BS / SW voltage domain.

[0055] Please refer to Figure 7 As shown, it is a block diagram of a transfer circuit 700 according to another embodiment of this application. Figure 1 Compared to the transfer circuit 100 shown, the transfer circuit 700 further includes two high-voltage circuits 710A and 710B. The first high-voltage circuit 710A is connected to the first input terminal 112 and the high-voltage level transfer circuit 110, respectively. The second high-voltage circuit 710B is connected to the second input terminal 114 and the high-voltage level transfer circuit 110, respectively.

[0056] In one embodiment, for the sake of symmetry and design convenience, the first high-voltage circuit 710A and the second high-voltage circuit 710B are designed identically. Please refer to... Figure 8 The diagram shown is a circuit schematic of a high-voltage circuit 710 according to an embodiment of this application. This high-voltage circuit 710 can be applied to a first high-voltage circuit 710A and a second high-voltage circuit 710B.

[0057] The high-voltage circuit 710 includes a high-voltage transistor 730 and two parallel capacitors, a first capacitor 740A and a second capacitor 740B. For example... Figure 8 As shown, the input terminal 720 of the high-voltage circuit 710 is connected to the gate of the high-voltage transistor 730 and the first terminals of the first capacitor 740A and the second capacitor 740B, respectively. The second terminals of the first capacitor 740A and the second capacitor 740B, as well as the source of the high-voltage transistor 730, are connected to the same voltage AVSS. The drain of the high-voltage transistor 730 is connected to the high-voltage level transfer circuit 110. When the input terminal 720 receives a narrow pulse signal, the drain of the high-voltage transistor 730 generates a pulse current, which is transmitted to the high-voltage level transfer circuit 110.

[0058] In one embodiment, for the sake of symmetry and design convenience, the capacitance designs of the first capacitor 740A and the second capacitor 740B are identical. Those skilled in the art will understand that, although... Figure 8 Two capacitors, 740A and 740B, are shown, but one or more parallel capacitors can be used instead.

[0059] According to one embodiment of this application, a transfer circuit is provided, comprising a high-voltage level transfer circuit and a latching circuit. The high-voltage level transfer circuit has a first input terminal and a second input terminal, and a first output terminal and a second output terminal. The latching circuit receives the first output terminal and the second output terminal of the high-voltage level transfer circuit and outputs a signal. When the first input terminal receives a first pulse signal, the high-voltage level transfer circuit outputs a low-level pulse signal at its first output terminal to the latching circuit, causing the latching circuit to output a latched high-level signal. When the second input terminal receives a second pulse signal, the high-voltage level transfer circuit outputs a low-level pulse signal at its second output terminal to the latching circuit, causing the latching circuit to output a latched low-level signal.

[0060] Preferably, the transfer circuit operates in the voltage domain between the high level and the low level, and the difference between the high level and the low level is less than 2V.

[0061] Preferably, for latching the output, the latching circuit includes a first NAND gate, a second NAND gate, and an inverting gate. The first output terminal of the high-voltage level transfer circuit is connected to the first input terminal of the first NAND gate, the output terminal of the second NAND gate, and the input terminal of the inverting gate. The second output terminal of the high-voltage level transfer circuit is connected to the first input terminal of the second NAND gate and the output terminal of the first NAND gate. The output terminal of the inverting gate is used for output latching of the transfer circuit.

[0062] Preferably, in order to design a symmetrical circuit to cancel out instantaneous coupling current, the above-mentioned high-voltage level transfer circuit includes a first side circuit and a second side circuit with the same side circuit design. The input terminal of the first side circuit is the first input terminal of the above-mentioned high-voltage level transfer circuit, the input terminal of the second side circuit is the second input terminal of the above-mentioned high-voltage level transfer circuit, the first output terminal of the first side circuit and the second output terminal of the second side circuit are the second output terminal of the high-voltage level transfer circuit, and the first output terminal of the second side circuit and the second output terminal of the first side circuit are the first output terminal of the high-voltage level transfer circuit.

[0063] Preferably, in order to offset the instantaneous coupling current, the aforementioned side circuit includes a first current replication circuit and a second current replication circuit connected to each other. The input terminal of the first current replication circuit is the input terminal of the side circuit, the output terminal of the first current replication circuit is the first output terminal of the side circuit, and the output terminal of the second current replication circuit is the second output terminal of the side circuit.

[0064] Preferably, the first current replication circuit includes a first transistor, a second transistor, a third transistor, and a capacitor. The sources of the first transistor, the second transistor, and the third transistor and the first terminal of the capacitor are connected to each other to the high level. The gates of the first transistor, the second transistor, and the third transistor are connected to each other to the second terminal of the capacitor. The drain of the first transistor is the input terminal of the first current replication circuit. The drain of the second transistor is connected to the second current replication circuit. The drain of the third transistor is the output terminal of the first current replication circuit.

[0065] Preferably, the second current replication circuit includes a fourth transistor and a fifth transistor, the gate and drain of the fourth transistor and the gate of the fifth transistor are connected to each other in the first current replication circuit, the sources of the fourth transistor and the fifth transistor are connected to each other in the low level, and the drain of the fifth transistor is the output terminal of the second current replication circuit.

[0066] Preferably, the transfer circuit further includes a first high-voltage circuit and a second high-voltage circuit with the same high-voltage circuit design, wherein the output terminal of the first high-voltage circuit is connected to the first input terminal of the high-voltage level transfer circuit, and the output terminal of the second high-voltage circuit is connected to the second input terminal of the high-voltage level transfer circuit.

[0067] Preferably, the high-voltage circuit described above includes a high-voltage transistor and a first capacitor and a second capacitor connected in parallel. The input terminal of the high-voltage circuit is connected to the gate of the high-voltage transistor and the first terminal of the first capacitor and the second capacitor. The source of the high-voltage transistor is connected to the second terminal of the first capacitor and the second capacitor. The drain of the high-voltage transistor is the output terminal of the high-voltage circuit.

[0068] Preferably, the first input terminal and the second input terminal of the high-voltage level transfer circuit are respectively connected to the preamplifier circuit. When the input signal of the preamplifier circuit is a rising edge, the preamplifier circuit outputs the first pulse signal to the first input terminal of the high-voltage level transfer circuit. When the input signal of the preamplifier circuit is a falling edge, the preamplifier circuit outputs the second pulse signal to the second input terminal of the high-voltage level transfer circuit.

[0069] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in this application, based on the technical solution and application concept of this application, should be included within the scope of protection of this application.

Claims

1. A transfer circuit, characterized in that, Include: A high-voltage level transfer circuit has a first input terminal and a second input terminal, and a first output terminal and a second output terminal; the first input terminal is used to receive a first narrow pulse signal transmitted by the preceding circuit, which is transmitted when the input signal is a rising edge. The second input terminal is used to receive the second narrow pulse signal transmitted by the preceding circuit. This second narrow pulse signal is transmitted when the input signal is at a falling edge. as well as A latching circuit receives the first output terminal and the second output terminal of the high-voltage level transfer circuit, and outputs a signal. When the first input terminal receives the first pulse signal, the high-voltage level transfer circuit outputs a low-level pulse signal to the latch circuit at the first output terminal, causing the latch circuit to output a latched high-level signal. When the second input terminal receives the second pulse signal, the high-voltage level transfer circuit outputs a low-level pulse signal to the latching circuit at the second output terminal, so that the latching circuit outputs a latched low-level signal. The aforementioned high-voltage level transfer circuit includes a first side circuit and a second side circuit with the same side circuit design. The input terminal of the first side circuit is the first input terminal of the aforementioned high-voltage level transfer circuit, and the input terminal of the second side circuit is the second input terminal of the aforementioned high-voltage level transfer circuit. The first output terminal of the first side circuit and the second output terminal of the second side circuit are the second output terminal of the high-voltage level transfer circuit, and the first output terminal of the second side circuit and the second output terminal of the first side circuit are the first output terminal of the high-voltage level transfer circuit. The aforementioned side circuit includes a first current replication circuit and a second current replication circuit connected to each other. The input terminal of the first current replication circuit is the input terminal of the side circuit, the output terminal of the first current replication circuit is the first output terminal of the side circuit, and the output terminal of the second current replication circuit is the second output terminal of the side circuit. The aforementioned first current replication circuit includes a first transistor, a second transistor, a third transistor, and a capacitor. The sources of the first transistor, the second transistor, and the third transistor and the first terminal of the capacitor are connected to each other at the high level. The gates of the first transistor, the second transistor, and the third transistor are connected to each other at the second terminal of the capacitor. The drain of the first transistor is the input terminal of the first current replication circuit. The drain of the second transistor is connected to the second current replication circuit. The drain of the third transistor is the output terminal of the first current replication circuit. The second current replication circuit mentioned above includes a fourth transistor and a fifth transistor. The gate and drain of the fourth transistor and the gate of the fifth transistor are connected to each other in the first current replication circuit. The sources of the fourth transistor and the fifth transistor are connected to each other in the low level. The drain of the fifth transistor is the output terminal of the second current replication circuit.

2. The transfer circuit as described in claim 1, characterized in that, The transfer circuit operates in the voltage range between the high and low levels, where the difference between the high and low levels is less than 2V.

3. The transfer circuit as described in claim 1, characterized in that, The latching circuit includes a first NAND gate, a second NAND gate, and an inverting gate. The first output terminal of the high-voltage level transfer circuit is connected to the first input terminal of the first NAND gate, the output terminal of the second NAND gate, and the input terminal of the inverting gate. The second output terminal of the high-voltage level transfer circuit is connected to the first input terminal of the second NAND gate and the output terminal of the first NAND gate. The output terminal of the inverting gate is the output latch of the transfer circuit.

4. The transfer circuit as described in claim 1, characterized in that, It also includes a first high-voltage circuit and a second high-voltage circuit with the same high-voltage circuit design, wherein the output terminal of the first high-voltage circuit is connected to the first input terminal of the high-voltage level transfer circuit, and the output terminal of the second high-voltage circuit is connected to the second input terminal of the high-voltage level transfer circuit.

5. The transfer circuit as described in claim 4, characterized in that, The high-voltage circuit described above includes a high-voltage transistor and a first capacitor and a second capacitor connected in parallel. The input terminal of the high-voltage circuit is connected to the gate of the high-voltage transistor and the first terminal of the first capacitor and the second capacitor. The source of the high-voltage transistor is connected to the second terminal of the first capacitor and the second capacitor. The drain of the high-voltage transistor is the output terminal of the high-voltage circuit.

6. The transfer circuit as described in claim 1, characterized in that, The first and second input terminals of the high-voltage level transfer circuit are respectively connected to the pre-amplifier circuit. When the input signal of the pre-amplifier circuit is a rising edge, the pre-amplifier circuit outputs the first pulse signal to the first input terminal of the high-voltage level transfer circuit. When the input signal of the pre-amplifier circuit is a falling edge, the pre-amplifier circuit outputs the second pulse signal to the second input terminal of the high-voltage level transfer circuit.

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